Lines Matching refs:instruction

486      instruction; the barrier can be considered to draw a line in that CPU's
1162 got to that point in the instruction execution flow yet.  This permits the
1163 actual load instruction to potentially complete immediately because the CPU
1567      with a single memory-reference instruction, prevents "load tearing"
2354 instruction itself is complete.
2614 This means that it must be considered that the CPU will execute its instruction
2616 instruction in the stream depends on an earlier instruction, then that
2617 earlier instruction must be sufficiently complete[*] before the later
2618 instruction may proceed; in other words: provided that the appearance of
2625 A CPU may also discard any instruction sequence that winds up having no
2630 Similarly, it has to be assumed that compiler might reorder the instruction
2680 it wishes, and continue execution until it is forced to wait for an instruction
2881 instruction before moving on to the next one, leading to a definite sequence of