1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [hw|sw|cache|tracepoint|pmu|event_glob]
12
13DESCRIPTION
14-----------
15This command displays the symbolic event types which can be selected in the
16various perf commands with the -e option.
17
18[[EVENT_MODIFIERS]]
19EVENT MODIFIERS
20---------------
21
22Events can optionally have a modifier by appending a colon and one or
23more modifiers. Modifiers allow the user to restrict the events to be
24counted. The following modifiers exist:
25
26 u - user-space counting
27 k - kernel counting
28 h - hypervisor counting
29 I - non idle counting
30 G - guest counting (in KVM guests)
31 H - host counting (not in KVM guests)
32 p - precise level
33 S - read sample value (PERF_SAMPLE_READ)
34 D - pin the event to the PMU
35
36The 'p' modifier can be used for specifying how precise the instruction
37address should be. The 'p' modifier can be specified multiple times:
38
39 0 - SAMPLE_IP can have arbitrary skid
40 1 - SAMPLE_IP must have constant skid
41 2 - SAMPLE_IP requested to have 0 skid
42 3 - SAMPLE_IP must have 0 skid
43
44For Intel systems precise event sampling is implemented with PEBS
45which supports up to precise-level 2.
46
47On AMD systems it is implemented using IBS (up to precise-level 2).
48The precise modifier works with event types 0x76 (cpu-cycles, CPU
49clocks not halted) and 0xC1 (micro-ops retired). Both events map to
50IBS execution sampling (IBS op) with the IBS Op Counter Control bit
51(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
52Manual Volume 2: System Programming, 13.3 Instruction-Based
53Sampling). Examples to use IBS:
54
55 perf record -a -e cpu-cycles:p ...    # use ibs op counting cycles
56 perf record -a -e r076:p ...          # same as -e cpu-cycles:p
57 perf record -a -e r0C1:p ...          # use ibs op counting micro-ops
58
59RAW HARDWARE EVENT DESCRIPTOR
60-----------------------------
61Even when an event is not available in a symbolic form within perf right now,
62it can be encoded in a per processor specific way.
63
64For instance For x86 CPUs NNN represents the raw register encoding with the
65layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
66of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
67Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
68
69Note: Only the following bit fields can be set in x86 counter
70registers: event, umask, edge, inv, cmask. Esp. guest/host only and
71OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
72MODIFIERS>>.
73
74Example:
75
76If the Intel docs for a QM720 Core i7 describe an event as:
77
78  Event  Umask  Event Mask
79  Num.   Value  Mnemonic    Description                        Comment
80
81  A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
82                            delivered by loop stream detector  invert to count
83                                                               cycles
84
85raw encoding of 0x1A8 can be used:
86
87 perf stat -e r1a8 -a sleep 1
88 perf record -e r1a8 ...
89
90You should refer to the processor specific documentation for getting these
91details. Some of them are referenced in the SEE ALSO section below.
92
93PARAMETERIZED EVENTS
94--------------------
95
96Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
97example:
98
99  hv_gpci/dtbp_ptitc,phys_processor_idx=?/
100
101This means that when provided as an event, a value for '?' must
102also be supplied. For example:
103
104  perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
105
106OPTIONS
107-------
108
109Without options all known events will be listed.
110
111To limit the list use:
112
113. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
114
115. 'sw' or 'software' to list software events such as context switches, etc.
116
117. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
118
119. 'tracepoint' to list all tracepoint events, alternatively use
120  'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
121  block, etc.
122
123. 'pmu' to print the kernel supplied PMU events.
124
125. If none of the above is matched, it will apply the supplied glob to all
126  events, printing the ones that match.
127
128One or more types can be used at the same time, listing the events for the
129types specified.
130
131Support raw format:
132
133. '--raw-dump', shows the raw-dump of all the events.
134. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
135  a certain kind of events.
136
137SEE ALSO
138--------
139linkperf:perf-stat[1], linkperf:perf-top[1],
140linkperf:perf-record[1],
141http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
142http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
143