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Searched refs:__raw_writel (Results 1 – 200 of 639) sorted by relevance

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/linux-4.1.27/arch/arm/mach-iop13xx/
Dpci.c250 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR, in iop13xx_atux_pci_status()
286 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atux_read_config()
315 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
317 __raw_writel(addr, IOP13XX_ATUX_OCCAR); in iop13xx_atux_write_config()
318 __raw_writel(value, IOP13XX_ATUX_OCCDR); in iop13xx_atux_write_config()
382 __raw_writel(status, IOP13XX_ATUE_PIE_STS); in iop13xx_atue_pci_status()
407 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_read()
429 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, in iop13xx_atue_read_config()
462 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR); in iop13xx_atue_write_config()
464 __raw_writel(addr, IOP13XX_ATUE_OCCAR); in iop13xx_atue_write_config()
[all …]
/linux-4.1.27/arch/mips/kernel/
Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
65 __raw_writel(TIMER_CCD, &tmrptr->ccdr); in txx9_clocksource_init()
66 __raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr); in txx9_clocksource_init()
67 __raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra); in txx9_clocksource_init()
68 __raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr); in txx9_clocksource_init()
83 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9tmr_stop_and_clear()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
98 __raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE, in txx9tmr_set_mode()
101 __raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >> in txx9tmr_set_mode()
[all …]
Dirq_txx9.c72 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_unmask()
77 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_unmask()
78 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_unmask()
88 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_mask()
93 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_mask()
94 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_mask()
109 __raw_writel(TXx9_IRSCR_EIClrE | irq_nr, &txx9_ircptr->scr); in txx9_irq_mask_ack()
135 __raw_writel(cr, crp); in txx9_irq_set_type()
162 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
164 __raw_writel(0, &txx9_ircptr->ilr[i]); in txx9_irq_init()
[all …]
Dgpio_txx9.c35 __raw_writel(val, &txx9_pioptr->dout); in txx9_gpio_set_raw()
52 __raw_writel(__raw_readl(&txx9_pioptr->dir) & ~(1 << offset), in txx9_gpio_dir_in()
65 __raw_writel(__raw_readl(&txx9_pioptr->dir) | (1 << offset), in txx9_gpio_dir_out()
/linux-4.1.27/arch/mips/alchemy/common/
Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask()
303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask()
304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask()
313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask()
314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask()
323 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic1_mask()
324 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic1_mask()
337 __raw_writel(1 << bit, base + IC_FALLINGCLR); in au1x_ic0_ack()
338 __raw_writel(1 << bit, base + IC_RISINGCLR); in au1x_ic0_ack()
[all …]
Dvss.c26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset */ in __enable_block()
29 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
33 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
35 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
37 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
39 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
42 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
45 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
48 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
57 __raw_writel(0x0f, base + VSS_FTR); /* disable isolation cells */ in __disable_block()
[all …]
Dusb.c111 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
117 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
127 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock */ in __au1300_ohci_control()
133 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
140 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
144 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
149 __raw_writel(r, base + USB_INT_ENABLE); in __au1300_ohci_control()
155 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
169 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
174 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
[all …]
Ddbdma.c1004 __raw_writel(alchemy_dbdma_pm_data[i][0] & ~1, addr + 0x00); in alchemy_dbdma_suspend()
1013 __raw_writel(0, addr + 0x0c); in alchemy_dbdma_suspend()
1025 __raw_writel(alchemy_dbdma_pm_data[0][0], addr + 0x00); in alchemy_dbdma_resume()
1026 __raw_writel(alchemy_dbdma_pm_data[0][1], addr + 0x04); in alchemy_dbdma_resume()
1027 __raw_writel(alchemy_dbdma_pm_data[0][2], addr + 0x08); in alchemy_dbdma_resume()
1028 __raw_writel(alchemy_dbdma_pm_data[0][3], addr + 0x0c); in alchemy_dbdma_resume()
1033 __raw_writel(alchemy_dbdma_pm_data[i][0], addr + 0x00); in alchemy_dbdma_resume()
1034 __raw_writel(alchemy_dbdma_pm_data[i][1], addr + 0x04); in alchemy_dbdma_resume()
1035 __raw_writel(alchemy_dbdma_pm_data[i][2], addr + 0x08); in alchemy_dbdma_resume()
1036 __raw_writel(alchemy_dbdma_pm_data[i][3], addr + 0x0c); in alchemy_dbdma_resume()
[all …]
/linux-4.1.27/arch/mips/sgi-ip22/
Dip22-nvram.c35 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
36 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
39 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
44 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
46 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
63 __raw_writel(__raw_readl(ctrl) | EEPROM_DATO, ctrl); in eeprom_cmd()
[all …]
/linux-4.1.27/arch/arm/mach-mmp/
Dtime.c62 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
82 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
87 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
104 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
109 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
110 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
115 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0)); in timer_set_next_event()
120 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
138 __raw_writel(0x00, mmp_timer_base + TMR_IER(0)); in timer_set_mode()
172 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */ in timer_config()
[all …]
Dpm-mmp2.c50 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
55 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
66 __raw_writel(0x0, CIU_REG(0x64)); in pm_scu_clk_disable()
67 __raw_writel(0x0, CIU_REG(0x68)); in pm_scu_clk_disable()
72 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_disable()
82 __raw_writel(0x03003003, CIU_REG(0x64)); in pm_scu_clk_enable()
83 __raw_writel(0x00303030, CIU_REG(0x68)); in pm_scu_clk_enable()
88 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_enable()
99 __raw_writel(0x0000a010, MPMU_CGR_PJ); in pm_mpmu_clk_disable()
106 __raw_writel(0xdffefffe, MPMU_CGR_PJ); in pm_mpmu_clk_enable()
[all …]
Dpm-pxa910.c114 __raw_writel(awucrm, MPMU_AWUCRM); in pxa910_set_wake()
118 __raw_writel(apcr, MPMU_APCR); in pxa910_set_wake()
123 __raw_writel(awucrm, MPMU_AWUCRM); in pxa910_set_wake()
127 __raw_writel(apcr, MPMU_APCR); in pxa910_set_wake()
173 __raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */ in pxa910_pm_enter_lowpower_mode()
183 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode()
184 __raw_writel(apcr, MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
200 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
219 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
263 __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), in pxa910_pm_init()
[all …]
Dclock.c24 __raw_writel(clk_rst, clk->clk_rst); in apbc_clk_enable()
29 __raw_writel(0, clk->clk_rst); in apbc_clk_disable()
39 __raw_writel(clk->enable_val, clk->clk_rst); in apmu_clk_enable()
44 __raw_writel(0, clk->clk_rst); in apmu_clk_disable()
Dmmp2.c93 __raw_writel(data | (1 << 6), mfpr_pmic); in mmp2_clear_pmic_int()
94 __raw_writel(data, mfpr_pmic); in mmp2_clear_pmic_int()
127 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); in mmp2_timer_init()
134 __raw_writel(clk_rst, APBC_TIMERS); in mmp2_timer_init()
Dpxa168.c76 __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); in pxa168_timer_init()
79 __raw_writel(TIMER_CLK_RST, APBC_TIMERS); in pxa168_timer_init()
91 __raw_writel(val | mask, APMU_WAKE_CLR); in pxa168_clear_keypad_wakeup()
/linux-4.1.27/arch/arm/mach-lpc32xx/
Dtimer.c37 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, in lpc32xx_clkevt_next_event()
39 __raw_writel(delta, LPC32XX_TIMER_PR(LPC32XX_TIMER0_BASE)); in lpc32xx_clkevt_next_event()
40 __raw_writel(LPC32XX_TIMER_CNTR_TCR_EN, in lpc32xx_clkevt_next_event()
61 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); in lpc32xx_clkevt_mode()
83 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), in lpc32xx_timer_interrupt()
107 __raw_writel(LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN | in lpc32xx_timer_init()
130 __raw_writel(0, LPC32XX_TIMER_TCR(LPC32XX_TIMER0_BASE)); in lpc32xx_timer_init()
131 __raw_writel(LPC32XX_TIMER_CNTR_MTCH_BIT(0), in lpc32xx_timer_init()
133 __raw_writel(1, LPC32XX_TIMER_MR0(LPC32XX_TIMER0_BASE)); in lpc32xx_timer_init()
134 __raw_writel(LPC32XX_TIMER_CNTR_MCR_MTCH(0) | in lpc32xx_timer_init()
[all …]
Dirq.c217 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); in lpc32xx_mask_irq()
227 __raw_writel(reg, LPC32XX_INTC_MASK(ctrl)); in lpc32xx_unmask_irq()
236 __raw_writel(mask, LPC32XX_INTC_RAW_STAT(ctrl)); in lpc32xx_ack_irq()
240 __raw_writel(lpc32xx_events[d->hwirq].mask, in lpc32xx_ack_irq()
257 __raw_writel(reg, LPC32XX_INTC_POLAR(ctrl)); in __lpc32xx_set_irq_type()
265 __raw_writel(reg, LPC32XX_INTC_ACT_TYPE(ctrl)); in __lpc32xx_set_irq_type()
276 __raw_writel(reg, lpc32xx_events[irq].event_group->edge_reg); in __lpc32xx_set_irq_type()
332 __raw_writel(lpc32xx_events[d->hwirq].mask, in lpc32xx_irq_wake()
337 __raw_writel(eventreg, in lpc32xx_irq_wake()
344 __raw_writel(lpc32xx_events[d->hwirq].mask, in lpc32xx_irq_wake()
[all …]
Dserial.c80 __raw_writel(0, LPC32XX_CLKPWR_UART_CLK_CTRL); in lpc32xx_serial_init()
92 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
99 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
100 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
105 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
109 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
113 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
114 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
118 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
124 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
[all …]
Dclock.c141 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL); in local_pll397_enable()
145 __raw_writel(reg, LPC32XX_CLKPWR_PLL397_CTRL); in local_pll397_enable()
170 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL); in local_oscmain_enable()
174 __raw_writel(reg, LPC32XX_CLKPWR_MAIN_OSC_CTRL); in local_oscmain_enable()
381 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); in local_clk_usbpll_setup()
395 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 | in local_usbpll_enable()
398 __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1, in local_usbpll_enable()
413 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); in local_usbpll_enable()
419 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); in local_usbpll_enable()
436 __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2, in local_usbpll_enable()
[all …]
Dcommon.c76 __raw_writel(savedval2 + 1, iramptr2); in lpc32xx_return_iram_size()
81 __raw_writel(savedval2, iramptr2); in lpc32xx_return_iram_size()
200 __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN, in lpc23xx_restart()
204 __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18)); in lpc23xx_restart()
205 __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC)); in lpc23xx_restart()
/linux-4.1.27/arch/arm/mach-s3c24xx/
Dmach-n30.c408 __raw_writel(0x007fffff, S3C2410_GPACON); in n30_hwinit()
410 __raw_writel(0x007fefff, S3C2410_GPACON); in n30_hwinit()
411 __raw_writel(0x00000000, S3C2410_GPADAT); in n30_hwinit()
426 __raw_writel(0x00154556, S3C2410_GPBCON); in n30_hwinit()
427 __raw_writel(0x00000750, S3C2410_GPBDAT); in n30_hwinit()
428 __raw_writel(0x00000073, S3C2410_GPBUP); in n30_hwinit()
445 __raw_writel(0xaaa80618, S3C2410_GPCCON); in n30_hwinit()
446 __raw_writel(0x0000014c, S3C2410_GPCDAT); in n30_hwinit()
447 __raw_writel(0x0000fef2, S3C2410_GPCUP); in n30_hwinit()
457 __raw_writel(0xaa95aaa4, S3C2410_GPDCON); in n30_hwinit()
[all …]
Dpm-s3c2416.c32 __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG); in s3c2416_cpu_suspend()
35 __raw_writel(0x2BED, S3C2443_PWRMODE); in s3c2416_cpu_suspend()
50 __raw_writel(0x2BED, S3C2412_INFORM0); in s3c2416_pm_prepare()
51 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); in s3c2416_pm_prepare()
79 __raw_writel(0x0, S3C2443_PWRMODE); in s3c2416_pm_resume()
80 __raw_writel(0x0, S3C2412_INFORM0); in s3c2416_pm_resume()
81 __raw_writel(0x0, S3C2412_INFORM1); in s3c2416_pm_resume()
Diotiming-s3c2412.c191 __raw_writel(bt->smbidcyr, regs + SMBIDCYR); in s3c2412_iotiming_set()
192 __raw_writel(bt->smbwstrd, regs + SMBWSTRDR); in s3c2412_iotiming_set()
193 __raw_writel(bt->smbwstwr, regs + SMBWSTWRR); in s3c2412_iotiming_set()
194 __raw_writel(bt->smbwstoen, regs + SMBWSTOENR); in s3c2412_iotiming_set()
195 __raw_writel(bt->smbwstwen, regs + SMBWSTWENR); in s3c2412_iotiming_set()
196 __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR); in s3c2412_iotiming_set()
283 __raw_writel(refresh, S3C2412_REFRESH); in s3c2412_cpufreq_setrefresh()
Dpm-s3c2410.c48 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); in s3c2410_pm_prepare()
63 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); in s3c2410_pm_prepare()
79 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); in s3c2410_pm_prepare()
108 __raw_writel(tmp, S3C2410_GSTATUS2); in s3c2410_pm_resume()
Dmach-jive.c485 __raw_writel(0x2BED, S3C2412_INFORM0); in jive_pm_suspend()
486 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); in jive_pm_suspend()
493 __raw_writel(0x0, S3C2412_INFORM0); in jive_pm_resume()
539 __raw_writel(S3C2412_SLPCON_IN(0) | in jive_machine_init()
553 __raw_writel(S3C2412_SLPCON_PULL(0) | in jive_machine_init()
573 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON); in jive_machine_init()
577 __raw_writel(S3C2412_SLPCON_LOW(0) | in jive_machine_init()
588 __raw_writel(S3C2412_SLPCON_IN(0) | in jive_machine_init()
607 __raw_writel(S3C2412_SLPCON_PULL(0) | in jive_machine_init()
Dirq-pm.c94 __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); in s3c24xx_irq_resume()
97 __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); in s3c24xx_irq_resume()
100 __raw_writel(save_eintmask, S3C24XX_EINTMASK); in s3c24xx_irq_resume()
Dpm-s3c2412.c47 __raw_writel(tmp, S3C2412_PWRCFG); in s3c2412_cpu_suspend()
123 __raw_writel(tmp, S3C2412_PWRCFG); in s3c2412_pm_resume()
/linux-4.1.27/drivers/clocksource/
Dtcb_clksrc.c101 __raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR)); in tc_mode()
102 __raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR)); in tc_mode()
115 __raw_writel(timer_clock in tc_mode()
118 __raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC)); in tc_mode()
121 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); in tc_mode()
124 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, in tc_mode()
132 __raw_writel(timer_clock | ATMEL_TC_CPCSTOP in tc_mode()
135 __raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER)); in tc_mode()
147 __raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC)); in tc_next_event()
150 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, in tc_next_event()
[all …]
Dvf_pit_timer.c42 __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); in pit_timer_enable()
47 __raw_writel(0, clkevt_base + PITTCTRL); in pit_timer_disable()
52 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); in pit_irq_acknowledge()
63 __raw_writel(0, clksrc_base + PITTCTRL); in pit_clocksource_init()
64 __raw_writel(~0UL, clksrc_base + PITLDVAL); in pit_clocksource_init()
65 __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); in pit_clocksource_init()
83 __raw_writel(delta - 1, clkevt_base + PITLDVAL); in pit_set_next_event()
142 __raw_writel(0, clkevt_base + PITTCTRL); in pit_clockevent_init()
143 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); in pit_clockevent_init()
192 __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); in pit_timer_init()
Dmxs_timer.c87 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + in timrot_irq_disable()
93 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base + in timrot_irq_enable()
99 __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base + in timrot_irq_acknowledge()
113 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0)); in timrotv1_set_next_event()
122 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0)); in timrotv2_set_next_event()
162 __raw_writel(0xffff, in mxs_set_mode()
165 __raw_writel(0xffffffff, in mxs_set_mode()
274 __raw_writel((timrot_is_v1() ? in mxs_timer_init()
282 __raw_writel((timrot_is_v1() ? in mxs_timer_init()
290 __raw_writel(0xffff, in mxs_timer_init()
[all …]
/linux-4.1.27/arch/arm/mach-pxa/
Dsmemc.c35 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
36 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
37 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
38 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
39 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
40 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
44 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
63 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
Dirq.c74 __raw_writel(icmr, base + ICMR); in pxa_mask_irq()
84 __raw_writel(icmr, base + ICMR); in pxa_unmask_irq()
131 __raw_writel(hw | IPR_VALID, pxa_irq_base + IPR(hw)); in pxa_irq_map()
163 __raw_writel(0, base + ICMR); /* disable all IRQs */ in pxa_init_irq_common()
164 __raw_writel(0, base + ICLR); /* all IRQs are IRQ, not FIQ */ in pxa_init_irq_common()
167 __raw_writel(1, irq_base(0) + ICCR); in pxa_init_irq_common()
193 __raw_writel(0, base + ICMR); in pxa_irq_suspend()
211 __raw_writel(saved_icmr[i], base + ICMR); in pxa_irq_resume()
212 __raw_writel(0, base + ICLR); in pxa_irq_resume()
217 __raw_writel(saved_ipr[i], pxa_irq_base + IPR(i)); in pxa_irq_resume()
[all …]
Dcm-x2xx-pci.c63 __raw_writel((0), IT8152_INTC_PDCNIRR); in __cmx2xx_pci_suspend()
64 __raw_writel((0), IT8152_INTC_LPCNIRR); in __cmx2xx_pci_suspend()
70 __raw_writel((sleep_save_ite[0]), IT8152_INTC_PDCNIMR); in __cmx2xx_pci_resume()
71 __raw_writel((sleep_save_ite[1]), IT8152_INTC_LPCNIMR); in __cmx2xx_pci_resume()
72 __raw_writel((sleep_save_ite[2]), IT8152_INTC_LPNIAR); in __cmx2xx_pci_resume()
131 __raw_writel(0x800, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit()
Dh5000.c177 __raw_writel(0x129c24f2, MSC0); in fix_msc()
178 __raw_writel(0x7ff424fa, MSC1); in fix_msc()
179 __raw_writel(0x7ff47ff4, MSC2); in fix_msc()
181 __raw_writel(__raw_readl(MDREFR) | 0x02080000, MDREFR); in fix_msc()
/linux-4.1.27/arch/mips/pci/
Dops-tx4927.c68 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
73 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in mkaddr()
88 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff) in check_abort()
134 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
243 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
251 __raw_writel((channel->io_resource->end - channel->io_resource->start) in tx4927_pcic_setup()
265 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
270 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
285 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */ in tx4927_pcic_setup()
288 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
[all …]
Dpci-ar71xx.c127 __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); in ar71xx_pci_check_error()
141 __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); in ar71xx_pci_check_error()
158 __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); in ar71xx_pci_local_write()
159 __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); in ar71xx_pci_local_write()
172 __raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD); in ar71xx_pci_set_cfgaddr()
173 __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), in ar71xx_pci_set_cfgaddr()
219 __raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA); in ar71xx_pci_write_config()
267 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
284 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
302 __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_init()
[all …]
Dpci-alchemy.c115 __raw_writel(r, ctx->regs + PCI_REG_STATCMD); in config_access()
154 __raw_writel(*data, ctx->pci_cfg_vm->addr + offset); in config_access()
174 __raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); in config_access()
334 __raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); in alchemy_pci_resume()
335 __raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); in alchemy_pci_resume()
336 __raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); in alchemy_pci_resume()
337 __raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); in alchemy_pci_resume()
338 __raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); in alchemy_pci_resume()
339 __raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); in alchemy_pci_resume()
340 __raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); in alchemy_pci_resume()
[all …]
Dpci-ar724x.c105 __raw_writel(data, base + (where & ~3)); in ar724x_pci_local_write()
216 __raw_writel(data, base + (where & ~3)); in ar724x_pci_write()
261 __raw_writel(t | AR724X_PCI_INT_DEV0, in ar724x_pci_irq_unmask()
282 __raw_writel(t & ~AR724X_PCI_INT_DEV0, in ar724x_pci_irq_mask()
289 __raw_writel(t | AR724X_PCI_INT_DEV0, in ar724x_pci_irq_mask()
312 __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_init()
313 __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); in ar724x_pci_irq_init()
/linux-4.1.27/arch/sh/drivers/pci/
Dpci-sh7780.c130 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
143 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
157 __raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM); in sh7780_pci_serr_irq()
172 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
203 __raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \ in sh7780_pci_setup_irqs()
208 __raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \ in sh7780_pci_setup_irqs()
234 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
244 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
261 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
264 __raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS, in sh7780_pci_init()
[all …]
/linux-4.1.27/sound/soc/au1x/
Dpsc-ac97.c82 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
89 __raw_writel(PSC_AC97CDC_RD | PSC_AC97CDC_INDX(reg), in au1xpsc_ac97_read()
102 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
122 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_write()
129 __raw_writel(PSC_AC97CDC_INDX(reg) | (val & 0xffff), in au1xpsc_ac97_write()
140 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_write()
152 __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
155 __raw_writel(0, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
165 __raw_writel(0, AC97_CFG(au1xpsc_ac97_workdata)); in au1xpsc_ac97_cold_reset()
167 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(pscdata)); in au1xpsc_ac97_cold_reset()
[all …]
Dpsc-i2s.c152 __raw_writel(PSC_CTRL_ENABLE, PSC_CTRL(pscdata)); in au1xpsc_i2s_configure()
162 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
164 __raw_writel(pscdata->cfg | PSC_I2SCFG_DE_ENABLE, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
176 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
177 __raw_writel(PSC_CTRL_SUSPEND, PSC_CTRL(pscdata)); in au1xpsc_i2s_configure()
197 __raw_writel(I2SPCR_CLRFIFO(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
199 __raw_writel(I2SPCR_START(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
208 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_start()
220 __raw_writel(I2SPCR_STOP(stype), I2S_PCR(pscdata)); in au1xpsc_i2s_stop()
231 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_stop()
[all …]
/linux-4.1.27/arch/sh/mm/
Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
Dtlb-sh4.c31 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
43 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
49 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA); in __update_tlb()
59 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
79 __raw_writel(data, addr); in local_flush_tlb_one()
101 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
104 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
Dcache-sh4.c80 __raw_writel(0, icacheaddr + (j * PAGE_SIZE)); in sh4_flush_icache_range()
138 __raw_writel(ccr, SH_CCR); in flush_icache_all()
161 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
162 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
163 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
164 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
165 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
166 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
167 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
168 __raw_writel(0, addr); addr += entry_offset; in flush_dcache_all()
Dtlb-sh3.c43 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
50 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
77 __raw_writel(data, addr + (i << 8)); in local_flush_tlb_one()
94 __raw_writel(status, MMUCR); in local_flush_tlb_all()
Dcache-sh2.c34 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
50 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2__flush_purge_region()
68 __raw_writel(ccr, SH_CCR); in sh2__flush_invalidate_region()
81 __raw_writel((v & CACHE_PHYSADDR_MASK), in sh2__flush_invalidate_region()
Dcache-sh2a.c35 __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr); in sh2a_flush_oc_line()
44 __raw_writel((addr & CACHE_PHYSADDR_MASK), cache_addr | addr); in sh2a_invalidate_line()
74 __raw_writel(data & ~SH_CACHE_UPDATED, v); in sh2a__flush_wback_region()
137 __raw_writel(__raw_readl(SH_CCR) | CCR_OCACHE_INVALIDATE, in sh2a__flush_invalidate_region()
171 __raw_writel(__raw_readl(SH_CCR) | CCR_ICACHE_INVALIDATE, in sh2a_flush_icache_range()
Dtlb-urb.c43 __raw_writel(status, MMUCR); in tlb_wire_entry()
55 __raw_writel(status, MMUCR); in tlb_wire_entry()
89 __raw_writel(status, MMUCR); in tlb_unwire_entry()
/linux-4.1.27/arch/sh/kernel/cpu/sh4a/
Dubc.c37 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
38 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
43 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
44 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
53 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
62 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
85 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
115 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
118 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
119 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
Dsmp-shx3.c39 __raw_writel(x, 0xfe410080 + offs); /* C0INTICICLR..CnINTICICLR */ in ipi_interrupt_handler()
54 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
91 __raw_writel(entry_point, RESET_REG(cpu)); in shx3_start_cpu()
93 __raw_writel(virt_to_phys(entry_point), RESET_REG(cpu)); in shx3_start_cpu()
96 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_start_cpu()
102 __raw_writel(STBCR_RESET | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_start_cpu()
116 __raw_writel(1 << (message << 2), addr); /* C0INTICI..CnINTICI */ in shx3_send_ipi()
121 __raw_writel(STBCR_MSTP, STBCR_REG(cpu)); in shx3_update_boot_vector()
124 __raw_writel(STBCR_RESET, STBCR_REG(cpu)); in shx3_update_boot_vector()
Dsetup-sh7780.c463 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
466 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
467 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
470 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
473 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
483 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); in plat_irq_setup_pins()
488 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
489 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
493 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
494 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
[all …]
Dperf_event.c241 __raw_writel(tmp, PPC_CCBR(idx)); in sh4a_pmu_disable()
251 __raw_writel(tmp, PPC_PMCAT); in sh4a_pmu_enable()
255 __raw_writel(tmp, PPC_CCBR(idx)); in sh4a_pmu_enable()
257 __raw_writel(__raw_readl(PPC_CCBR(idx)) | CCBR_DUC, PPC_CCBR(idx)); in sh4a_pmu_enable()
265 __raw_writel(__raw_readl(PPC_CCBR(i)) & ~CCBR_DUC, PPC_CCBR(i)); in sh4a_pmu_disable_all()
273 __raw_writel(__raw_readl(PPC_CCBR(i)) | CCBR_DUC, PPC_CCBR(i)); in sh4a_pmu_enable_all()
Dsetup-sh7786.c421 __raw_writel(val | EXT_CLOCK_MODE, USBCTL0); in sh7786_usb_use_exclock()
448 __raw_writel(USBINITVAL1, USBINITREG1); in sh7786_usb_setup()
449 __raw_writel(USBINITVAL2, USBINITREG2); in sh7786_usb_setup()
454 __raw_writel(PHY_ENB | PLL_ENB, USBPCTL1); in sh7786_usb_setup()
458 __raw_writel(PHY_ENB | PLL_ENB | PHY_RST, USBPCTL1); in sh7786_usb_setup()
757 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
760 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
761 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
764 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
774 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); in plat_irq_setup_pins()
[all …]
Dsetup-sh7785.c559 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
562 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
563 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
566 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
569 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
579 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0); in plat_irq_setup_pins()
584 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); in plat_irq_setup_pins()
589 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
590 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
594 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
[all …]
Dsetup-sh7763.c420 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
423 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
424 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
434 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); in plat_irq_setup_pins()
439 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
440 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
444 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
445 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
449 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
454 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
Dsetup-sh7770.c537 __raw_writel(0xff000000, INTC_INTMSK0); in plat_irq_setup()
540 __raw_writel(0xc0000000, INTC_INTMSK1); in plat_irq_setup()
541 __raw_writel(0xfffefffe, INTC_INTMSK2); in plat_irq_setup()
544 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); in plat_irq_setup()
547 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
557 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); in plat_irq_setup_pins()
562 __raw_writel(0x40000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
563 __raw_writel(0x0000fffe, INTC_INTMSKCLR2); in plat_irq_setup_pins()
567 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
568 __raw_writel(0xfffe0000, INTC_INTMSKCLR2); in plat_irq_setup_pins()
[all …]
Dsetup-sh7724.c862 __raw_writel(L2_CACHE_ENABLE, RAMCR); in l2_cache_init()
1234 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */ in sh7724_post_sleep_notifier_call()
1235 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */ in sh7724_post_sleep_notifier_call()
1236 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */ in sh7724_post_sleep_notifier_call()
1237 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */ in sh7724_post_sleep_notifier_call()
1238 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */ in sh7724_post_sleep_notifier_call()
1239 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */ in sh7724_post_sleep_notifier_call()
1240 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */ in sh7724_post_sleep_notifier_call()
1241 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */ in sh7724_post_sleep_notifier_call()
1242 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */ in sh7724_post_sleep_notifier_call()
[all …]
Dsetup-sh7734.c594 __raw_writel(0xF0000000, INTC_INTMSK0); in plat_irq_setup()
597 __raw_writel(0x80000000, INTC_INTMSK1); in plat_irq_setup()
600 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00800000, INTC_ICR0); in plat_irq_setup()
603 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); in plat_irq_setup()
613 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0); in plat_irq_setup_pins()
618 __raw_writel(0x80000000, INTC_INTMSKCLR1); in plat_irq_setup_pins()
619 __raw_writel(0xf0000000, INTC_INTMSKCLR0); in plat_irq_setup_pins()
623 __raw_writel(0x80000000, INTC_INTMSKCLR0); in plat_irq_setup_pins()
/linux-4.1.27/drivers/mailbox/
Dpl320-ipc.c61 __raw_writel(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox)); in set_destination()
62 __raw_writel(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox)); in set_destination()
67 __raw_writel(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox)); in clear_destination()
68 __raw_writel(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox)); in clear_destination()
75 __raw_writel(data[i], ipc_base + IPCMxDR(mbox, i)); in __ipc_send()
76 __raw_writel(0x1, ipc_base + IPCMxSEND(mbox)); in __ipc_send()
117 __raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX)); in ipc_handler()
123 __raw_writel(2, ipc_base + IPCMxSEND(IPC_RX_MBOX)); in ipc_handler()
149 __raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX)); in pl320_probe()
157 __raw_writel(CHAN_MASK(A9_SOURCE), in pl320_probe()
[all …]
/linux-4.1.27/arch/m68k/coldfire/
Dpci.c89 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
105 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
121 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
132 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
137 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
204 __raw_writel(cpu_to_le32(v), iospace + (addr & PCI_IO_MASK)); in mcf_pci_outl()
264 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
265 __raw_writel(0, PCITCR); in mcf_pci_init()
271 __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | in mcf_pci_init()
279 __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | in mcf_pci_init()
[all …]
Dsltimers.c46 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR)); in mcfslt_profile_tick()
66 __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT)); in mcfslt_profile_init()
67 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, in mcfslt_profile_init()
89 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR)); in mcfslt_tick()
135 __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT)); in hw_timer_init()
136 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN, in hw_timer_init()
Dintc-2.c65 __raw_writel(val | imrbit, imraddr); in intc_irq_mask()
87 __raw_writel(val & ~imrbit, imraddr); in intc_irq_unmask()
198 __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL); in init_IRQ()
200 __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL); in init_IRQ()
Dm54xx.c72 __raw_writel(0, MCF_GPT_GMS0); in mcf54xx_reset()
73 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0); in mcf54xx_reset()
74 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4), in mcf54xx_reset()
Dintc.c73 __raw_writel(imr | (0x1 << index), MCFSIM_IMR); in mcf_setimr()
80 __raw_writel(imr & ~(0x1 << index), MCFSIM_IMR); in mcf_clrimr()
88 __raw_writel(imr, MCFSIM_IMR); in mcf_maskimr()
/linux-4.1.27/arch/arm/common/
Dit8152.c40 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) | in it8152_mask_irq()
44 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) | in it8152_mask_irq()
48 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) | in it8152_mask_irq()
59 __raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) & in it8152_unmask_irq()
63 __raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) & in it8152_unmask_irq()
67 __raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) & in it8152_unmask_irq()
84 __raw_writel((0xffff), IT8152_INTC_PDCNIMR); in it8152_init_irq()
85 __raw_writel((0), IT8152_INTC_PDCNIRR); in it8152_init_irq()
86 __raw_writel((0xffff), IT8152_INTC_LPCNIMR); in it8152_init_irq()
87 __raw_writel((0), IT8152_INTC_LPCNIRR); in it8152_init_irq()
[all …]
/linux-4.1.27/arch/arm/mach-ks8695/
Dpci.c53 __raw_writel(pbca, KS8695_PCI_VA + KS8695_PBCA); in ks8695_pci_setupconfig()
56 __raw_writel(pbca | PBCA_TYPE1, KS8695_PCI_VA + KS8695_PBCA); in ks8695_pci_setupconfig()
70 __raw_writel(value, KS8695_PCI_VA + KS8695_PBCD); in ks8695_local_writeconfig()
144 __raw_writel(cmdstat, KS8695_PCI_VA + KS8695_CRCFCS); in ks8695_pci_fault()
178 __raw_writel(0x80000000, KS8695_PCI_VA + KS8695_PBCS); in ks8695_pci_preinit()
181 __raw_writel(0x00010001, KS8695_PCI_VA + KS8695_CRCSID); in ks8695_pci_preinit()
185 __raw_writel(0x40000000, KS8695_PCI_VA + KS8695_PBCS); in ks8695_pci_preinit()
188 __raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBA); in ks8695_pci_preinit()
189 __raw_writel(size_mask(KS8695_PCIMEM_SIZE), KS8695_PCI_VA + KS8695_PMBAM); in ks8695_pci_preinit()
190 __raw_writel(KS8695_PCIMEM_PA, KS8695_PCI_VA + KS8695_PMBAT); in ks8695_pci_preinit()
[all …]
Dirq.c44 __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); in ks8695_irq_mask()
54 __raw_writel(inten, KS8695_IRQ_VA + KS8695_INTEN); in ks8695_irq_unmask()
59 __raw_writel((1 << d->irq), KS8695_IRQ_VA + KS8695_INTST); in ks8695_irq_ack()
126 __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); in ks8695_irq_set_type()
149 __raw_writel(0, KS8695_IRQ_VA + KS8695_INTMC); in ks8695_init_irq()
150 __raw_writel(0, KS8695_IRQ_VA + KS8695_INTEN); in ks8695_init_irq()
/linux-4.1.27/arch/arm/mach-w90x900/
Dtime.c61 __raw_writel(timer0_load, REG_TICR0); in nuc900_clockevent_setmode()
75 __raw_writel(val, REG_TCSR0); in nuc900_clockevent_setmode()
83 __raw_writel(evt, REG_TICR0); in nuc900_clockevent_setnextevent()
87 __raw_writel(val, REG_TCSR0); in nuc900_clockevent_setnextevent()
106 __raw_writel(0x01, REG_TISR); /* clear TIF0 */ in nuc900_timer0_interrupt()
125 __raw_writel(0x00, REG_TCSR0); in nuc900_clockevents_init()
132 __raw_writel(RESETINT, REG_TISR); in nuc900_clockevents_init()
149 __raw_writel(0x00, REG_TCSR1); in nuc900_clocksource_init()
154 __raw_writel(0xffffffff, REG_TICR1); in nuc900_clocksource_init()
158 __raw_writel(val, REG_TCSR1); in nuc900_clocksource_init()
Dirq.c94 __raw_writel(regval, REG_AIC_GEN); in nuc900_group_enable()
103 __raw_writel(1 << d->irq, REG_AIC_MDCR); in nuc900_irq_mask()
150 __raw_writel(0x01, REG_AIC_EOSCR); in nuc900_irq_ack()
159 __raw_writel(1 << d->irq, REG_AIC_MECR); in nuc900_irq_unmask()
209 __raw_writel(0xFFFFFFFE, REG_AIC_MDCR); in nuc900_init_irq()
Dmfp.c69 __raw_writel(mfpen, REG_MFSEL); in mfp_set_groupf()
99 __raw_writel(mfpen, REG_MFSEL); in mfp_set_groupc()
127 __raw_writel(mfpen, REG_MFSEL); in mfp_set_groupi()
168 __raw_writel(mfpen, REG_MFSEL); in mfp_set_groupg()
196 __raw_writel(mfpen, REG_MFSEL); in mfp_set_groupd()
Dgpio.c82 __raw_writel(regval, pio); in nuc900_gpio_set()
98 __raw_writel(regval, pio); in nuc900_dir_input()
117 __raw_writel(regval, pio); in nuc900_dir_output()
126 __raw_writel(regval, outreg); in nuc900_dir_output()
Dcpu.c165 __raw_writel(pllclk, REG_PLLCON0); in nuc900_set_clkval()
170 __raw_writel(val, REG_CLKDIV); in nuc900_set_clkval()
193 __raw_writel(val, REG_CKSKEW); in nuc900_set_cpufreq()
240 __raw_writel(WTE | WTRE | WTCLK, WTCR); in nuc9xx_restart()
Dclock.c76 __raw_writel(clken, W90X900_VA_CLKPWR); in nuc900_clk_enable()
91 __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK); in nuc900_subclk_enable()
/linux-4.1.27/arch/mips/txx9/generic/
Dirq_tx4939.c66 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_unmask()
84 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_mask()
98 __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf)) in tx4939_irq_mask_ack()
141 __raw_writel(cr, crp); in tx4939_irq_set_type()
172 __raw_writel(0, &tx4939_ircptr->den.r); in tx4939_irq_init()
173 __raw_writel(0, &tx4939_ircptr->maskint.r); in tx4939_irq_init()
174 __raw_writel(0, &tx4939_ircptr->maskext.r); in tx4939_irq_init()
184 __raw_writel(0, &tx4939_ircptr->msk.r); in tx4939_irq_init()
186 __raw_writel(0, &tx4939_ircptr->lvl[i].r); in tx4939_irq_init()
189 __raw_writel(0, &tx4939_ircptr->dm[i].r); in tx4939_irq_init()
[all …]
/linux-4.1.27/arch/mips/include/asm/mach-au1x00/
Dau1000_dma.h160 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
169 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
177 __raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffers()
186 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
198 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
218 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
242 __raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR); in init_dma()
248 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); in init_dma()
249 __raw_writel(mode, chan->io + DMA_MODE_SET); in init_dma()
307 __raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR); in set_dma_fifo_addr()
[all …]
Dgpio-au1000.h283 __raw_writel(d, base + AU1000_GPIO2_DIR); in __alchemy_gpio2_mod_dir()
292 __raw_writel(mask, base + AU1000_GPIO2_OUTPUT); in alchemy_gpio2_set_value()
356 __raw_writel(r, base + AU1000_GPIO2_INTENABLE); in __alchemy_gpio2_mod_int()
433 __raw_writel(3, base + AU1000_GPIO2_ENABLE); /* reset, clock enabled */ in alchemy_gpio2_enable()
435 __raw_writel(1, base + AU1000_GPIO2_ENABLE); /* clock enabled */ in alchemy_gpio2_enable()
447 __raw_writel(2, base + AU1000_GPIO2_ENABLE); /* reset, clock disabled */ in alchemy_gpio2_disable()
/linux-4.1.27/arch/arm/mach-davinci/
Dtime.c136 __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, in timer32_config()
143 __raw_writel(tcr, t->base + TCR); in timer32_config()
146 __raw_writel(0, t->base + t->tim_off); in timer32_config()
147 __raw_writel(t->period, t->base + t->prd_off); in timer32_config()
155 __raw_writel(tcr, t->base + TCR); in timer32_config()
215 __raw_writel(0, base[i] + TCR); in timer_init()
219 __raw_writel(tgcr, base[i] + TGCR); in timer_init()
223 __raw_writel(tgcr, base[i] + TGCR); in timer_init()
228 __raw_writel(tgcr, base[i] + TGCR); in timer_init()
231 __raw_writel(0, base[i] + TIM12); in timer_init()
[all …]
Dpm.c49 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
56 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
63 __raw_writel(val, pdata->deepsleep_reg); in davinci_pm_suspend()
73 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
78 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
86 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
95 __raw_writel(val, pdata->cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
Dpsc.c105 __raw_writel(mdctl, psc_base + MDCTL + 4 * id); in davinci_psc_config()
111 __raw_writel(pdctl, psc_base + PDCTL + 4 * domain); in davinci_psc_config()
114 __raw_writel(ptcmd, psc_base + PTCMD); in davinci_psc_config()
122 __raw_writel(pdctl, psc_base + PDCTL + 4 * domain); in davinci_psc_config()
125 __raw_writel(ptcmd, psc_base + PTCMD); in davinci_psc_config()
Dclock.c380 __raw_writel(v, pll->base + clk->div_reg); in davinci_set_sysclk_rate()
384 __raw_writel(v, pll->base + PLLCMD); in davinci_set_sysclk_rate()
512 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
518 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
521 __raw_writel(prediv, pll->base + PREDIV); in davinci_set_pllrate()
523 __raw_writel(mult, pll->base + PLLM); in davinci_set_pllrate()
526 __raw_writel(postdiv, pll->base + POSTDIV); in davinci_set_pllrate()
532 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
538 __raw_writel(ctrl, pll->base + PLLCTL); in davinci_set_pllrate()
/linux-4.1.27/arch/arm/mach-imx/
Dtime.c92 __raw_writel(0, timer_base + V2_IR); in gpt_irq_disable()
95 __raw_writel(tmp & ~MX1_2_TCTL_IRQEN, timer_base + MXC_TCTL); in gpt_irq_disable()
102 __raw_writel(1<<0, timer_base + V2_IR); in gpt_irq_enable()
104 __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN, in gpt_irq_enable()
113 __raw_writel(0, timer_base + MX1_2_TSTAT); in gpt_irq_acknowledge()
115 __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, in gpt_irq_acknowledge()
118 __raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT); in gpt_irq_acknowledge()
160 __raw_writel(tcmp, timer_base + MX1_2_TCMP); in mx1_2_set_next_event()
173 __raw_writel(tcmp, timer_base + V2_TCMP); in v2_set_next_event()
207 __raw_writel(__raw_readl(timer_base + V2_TCN) - 3, in mxc_set_mode()
[all …]
Davic.c70 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL); in avic_set_irq_fiq()
74 __raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH); in avic_set_irq_fiq()
98 __raw_writel(gc->wake_active, avic_base + ct->regs.mask); in avic_irq_suspend()
107 __raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask); in avic_irq_resume()
167 __raw_writel(0, avic_base + AVIC_INTCNTL); in mxc_init_irq()
168 __raw_writel(0x1f, avic_base + AVIC_NIMASK); in mxc_init_irq()
171 __raw_writel(0, avic_base + AVIC_INTENABLEH); in mxc_init_irq()
172 __raw_writel(0, avic_base + AVIC_INTENABLEL); in mxc_init_irq()
175 __raw_writel(0, avic_base + AVIC_INTTYPEH); in mxc_init_irq()
176 __raw_writel(0, avic_base + AVIC_INTTYPEL); in mxc_init_irq()
[all …]
Dtzic.c71 __raw_writel(value, tzic_base + TZIC_INTSEC0(index)); in tzic_set_irq_fiq()
85 __raw_writel(gc->wake_active, tzic_base + TZIC_WAKEUP0(idx)); in tzic_irq_suspend()
92 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(idx)), in tzic_irq_resume()
171 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL); in tzic_init_irq()
172 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK); in tzic_init_irq()
173 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL); in tzic_init_irq()
176 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i)); in tzic_init_irq()
180 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i)); in tzic_init_irq()
217 __raw_writel(1, tzic_base + TZIC_DSMINT); in tzic_enable_wake()
222 __raw_writel(__raw_readl(tzic_base + TZIC_ENSET0(i)), in tzic_enable_wake()
Dcpu.c48 __raw_writel(0x77777777, base + 0x0); in imx_set_aips()
49 __raw_writel(0x77777777, base + 0x4); in imx_set_aips()
56 __raw_writel(0x0, base + 0x40); in imx_set_aips()
57 __raw_writel(0x0, base + 0x44); in imx_set_aips()
58 __raw_writel(0x0, base + 0x48); in imx_set_aips()
59 __raw_writel(0x0, base + 0x4C); in imx_set_aips()
61 __raw_writel(reg, base + 0x50); in imx_set_aips()
Dpm-imx5.c130 __raw_writel(plat_lpc, cortex_base + MXC_CORTEXA8_PLAT_LPC); in mx5_cpu_lp_set()
131 __raw_writel(ccm_clpcr, ccm_base + MXC_CCM_CLPCR); in mx5_cpu_lp_set()
132 __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_ARM_SRPGCR); in mx5_cpu_lp_set()
133 __raw_writel(arm_srpgcr, gpc_base + MXC_SRPG_NEON_SRPGCR); in mx5_cpu_lp_set()
139 __raw_writel(empgc0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_cpu_lp_set()
140 __raw_writel(empgc1, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_cpu_lp_set()
162 __raw_writel(0, gpc_base + MXC_SRPG_EMPGC0_SRPGCR); in mx5_suspend_enter()
163 __raw_writel(0, gpc_base + MXC_SRPG_EMPGC1_SRPGCR); in mx5_suspend_enter()
Depit.c70 __raw_writel(val, timer_base + EPITCR); in epit_irq_disable()
79 __raw_writel(val, timer_base + EPITCR); in epit_irq_enable()
84 __raw_writel(EPITSR_OCIF, timer_base + EPITSR); in epit_irq_acknowledge()
104 __raw_writel(tcmp - evt, timer_base + EPITCMPR); in epit_set_next_event()
213 __raw_writel(0x0, timer_base + EPITCR); in epit_timer_init()
215 __raw_writel(0xffffffff, timer_base + EPITLR); in epit_timer_init()
216 __raw_writel(EPITCR_EN | EPITCR_CLKSRC_REF_HIGH | EPITCR_WAITEN, in epit_timer_init()
Diomux-v3.c48 __raw_writel(mux_mode, base + mux_ctrl_ofs); in mxc_iomux_v3_setup_pad()
51 __raw_writel(sel_input, base + sel_input_ofs); in mxc_iomux_v3_setup_pad()
54 __raw_writel(pad_ctrl, base + pad_ctrl_ofs); in mxc_iomux_v3_setup_pad()
Dclk-pllv2.c174 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); in clk_pllv2_set_rate()
176 __raw_writel(dp_op, pllbase + MXC_PLL_DP_OP); in clk_pllv2_set_rate()
177 __raw_writel(dp_mfd, pllbase + MXC_PLL_DP_MFD); in clk_pllv2_set_rate()
178 __raw_writel(dp_mfn, pllbase + MXC_PLL_DP_MFN); in clk_pllv2_set_rate()
202 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); in clk_pllv2_prepare()
229 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); in clk_pllv2_unprepare()
Dmach-imx51.c43 __raw_writel(0xf00, hsc_addr); in imx51_ipu_mipi_setup()
46 __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff, in imx51_ipu_mipi_setup()
Diomux-imx31.c63 __raw_writel(l, reg); in mxc_iomux_mode()
88 __raw_writel(l, reg); in mxc_iomux_set_pad()
172 __raw_writel(l, IOMUXGPR); in mxc_iomux_set_gpr()
/linux-4.1.27/arch/arm/mach-s3c24xx/include/mach/
Dpm-core.h28 __raw_writel(tmp, S3C2410_CLKCON); in s3c_pm_debug_init_uart()
34 __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK); in s3c_pm_arch_prepare_irqs()
35 __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK); in s3c_pm_arch_prepare_irqs()
39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
47 __raw_writel(0x00, S3C2410_CLKCON); /* turn off clocks over sleep */ in s3c_pm_arch_stop_clocks()
/linux-4.1.27/sound/soc/txx9/
Dtxx9aclc-ac97.c59 __raw_writel(dat, base + ACREGACC); in txx9aclc_ac97_read()
60 __raw_writel(ACINT_REGACCRDY, base + ACINTEN); in txx9aclc_ac97_read()
62 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); in txx9aclc_ac97_read()
76 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); in txx9aclc_ac97_read()
87 __raw_writel(((reg | (ac97->num << 7)) << ACREGACC_REG_SHIFT) | in txx9aclc_ac97_write()
90 __raw_writel(ACINT_REGACCRDY, base + ACINTEN); in txx9aclc_ac97_write()
95 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); in txx9aclc_ac97_write()
104 __raw_writel(ACCTL_ENLINK, base + ACCTLDIS); in txx9aclc_ac97_cold_reset()
107 __raw_writel(ACCTL_ENLINK, base + ACCTLEN); in txx9aclc_ac97_cold_reset()
109 __raw_writel(ready, base + ACINTEN); in txx9aclc_ac97_cold_reset()
[all …]
/linux-4.1.27/arch/arm/mach-versatile/
Dpci.c161 __raw_writel(val, addr); in versatile_write_config()
283 __raw_writel(myslot, PCI_SELFID); in pci_versatile_setup()
288 __raw_writel(val, local_pci_cfg_base + CSR_OFFSET); in pci_versatile_setup()
293 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); in pci_versatile_setup()
294 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); in pci_versatile_setup()
295 __raw_writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); in pci_versatile_setup()
308 __raw_writel(0, VERSATILE_PCI_VIRT_BASE+PCI_INTERRUPT_LINE); in pci_versatile_setup()
325 __raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0); in pci_versatile_preinit()
326 __raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1); in pci_versatile_preinit()
327 __raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2); in pci_versatile_preinit()
[all …]
/linux-4.1.27/arch/arm/mach-ixp4xx/
Dixp4xx_qmgr.c40 __raw_writel((__raw_readl(reg) & ~(7 << bit)) | (src << bit), in qmgr_set_irq()
58 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[0]); in qmgr_irq1_a0()
83 __raw_writel(0xFFFFFFFF, &qmgr_regs->irqstat[1]); in qmgr_irq2_a0()
103 __raw_writel(req_bitmap, &qmgr_regs->irqstat[half]); /* ACK */ in qmgr_irq()
122 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) | mask, in qmgr_enable_irq()
134 __raw_writel(__raw_readl(&qmgr_regs->irqen[half]) & ~mask, in qmgr_disable_irq()
136 __raw_writel(mask, &qmgr_regs->irqstat[half]); /* clear */ in qmgr_disable_irq()
223 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]); in qmgr_request_queue()
273 __raw_writel(0, &qmgr_regs->sram[queue]); in qmgr_release_queue()
298 __raw_writel(0x33333333, &qmgr_regs->stat1[i]); in qmgr_init()
[all …]
Dixp4xx_npe.c176 __raw_writel(data, &npe->regs->exec_data); in npe_cmd_write()
177 __raw_writel(addr, &npe->regs->exec_addr); in npe_cmd_write()
178 __raw_writel(cmd, &npe->regs->exec_status_cmd); in npe_cmd_write()
183 __raw_writel(addr, &npe->regs->exec_addr); in npe_cmd_read()
184 __raw_writel(cmd, &npe->regs->exec_status_cmd); in npe_cmd_read()
206 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); in npe_start()
207 __raw_writel(CMD_NPE_START, &npe->regs->exec_status_cmd); in npe_start()
212 __raw_writel(CMD_NPE_STOP, &npe->regs->exec_status_cmd); in npe_stop()
213 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); /*FIXME?*/ in npe_stop()
236 __raw_writel(CMD_NPE_CLR_PIPE, &npe->regs->exec_status_cmd); in npe_debug_instr()
[all …]
/linux-4.1.27/arch/mips/ath79/
Dgpio.c37 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); in __ath79_gpio_set_value()
39 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); in __ath79_gpio_set_value()
66 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), in ath79_gpio_direction_input()
83 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); in ath79_gpio_direction_output()
85 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); in ath79_gpio_direction_output()
87 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), in ath79_gpio_direction_output()
102 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) | (1 << offset), in ar934x_gpio_direction_input()
119 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); in ar934x_gpio_direction_output()
121 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); in ar934x_gpio_direction_output()
123 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), in ar934x_gpio_direction_output()
[all …]
Dirq.c58 __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
71 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
84 __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
101 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_init()
102 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); in ath79_misc_irq_init()
/linux-4.1.27/arch/sh/kernel/cpu/sh3/
Dprobe.c34 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); in cpu_probe()
36 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); in cpu_probe()
41 __raw_writel(data0, addr0); in cpu_probe()
44 __raw_writel(data2, addr1); in cpu_probe()
48 __raw_writel(data0&~SH_CACHE_VALID, addr0); in cpu_probe()
49 __raw_writel(data2&~SH_CACHE_VALID, addr1); in cpu_probe()
97 __raw_writel(CCR_CACHE_32KB, CCR3_REG); in cpu_probe()
99 __raw_writel(CCR_CACHE_16KB, CCR3_REG); in cpu_probe()
/linux-4.1.27/arch/sh/boards/mach-sh7763rdp/
Dirq.c31 __raw_writel(1 << 25, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
34 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, in init_sh7763rdp_IRQ()
38 __raw_writel(1 << 17, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
41 __raw_writel(1 << 16, INTC_INT2MSKCR1); in init_sh7763rdp_IRQ()
44 __raw_writel(1 << 8, INTC_INT2MSKCR); in init_sh7763rdp_IRQ()
/linux-4.1.27/arch/mips/loongson1/common/
Dirq.c32 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
41 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
50 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
52 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
61 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
124 __raw_writel(0x0, LS1X_INTC_INTIEN(n)); in ls1x_irq_init()
125 __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); in ls1x_irq_init()
126 __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); in ls1x_irq_init()
128 __raw_writel(n ? 0x0 : 0xe000, LS1X_INTC_INTEDGE(n)); in ls1x_irq_init()
Dtime.c43 __raw_writel(period, timer_base + PWM_HRC); in ls1x_pwmtimer_set_period()
44 __raw_writel(period, timer_base + PWM_LRC); in ls1x_pwmtimer_set_period()
49 __raw_writel(0x0, timer_base + PWM_CNT); in ls1x_pwmtimer_restart()
50 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); in ls1x_pwmtimer_restart()
138 __raw_writel(INT_EN | CNT_EN, timer_base + PWM_CTRL); in ls1x_clockevent_set_mode()
142 __raw_writel(__raw_readl(timer_base + PWM_CTRL) & ~CNT_EN, in ls1x_clockevent_set_mode()
Dreset.c29 __raw_writel(0x1, wdt_base + WDT_EN); in ls1x_restart()
30 __raw_writel(0x1, wdt_base + WDT_TIMER); in ls1x_restart()
31 __raw_writel(0x1, wdt_base + WDT_SET); in ls1x_restart()
/linux-4.1.27/arch/arm/mach-gemini/
Dgpio.c55 __raw_writel(reg, base + GPIO_INT_EN); in _set_gpio_irqenable()
63 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); in gpio_ack_irq()
120 __raw_writel(reg_type, base + GPIO_INT_TYPE); in gpio_set_irq_type()
121 __raw_writel(reg_level, base + GPIO_INT_LEVEL); in gpio_set_irq_type()
122 __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE); in gpio_set_irq_type()
165 __raw_writel(reg, base + GPIO_DIR); in _set_gpio_direction()
173 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET); in gemini_gpio_set()
175 __raw_writel(1 << (offset % 32), base + GPIO_DATA_CLR); in gemini_gpio_set()
215 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_EN); in gemini_gpio_init()
216 __raw_writel(0x0, GPIO_BASE(i) + GPIO_INT_MASK); in gemini_gpio_init()
[all …]
Dirq.c40 __raw_writel(1 << d->irq, IRQ_CLEAR(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_ack_irq()
49 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_mask_irq()
58 __raw_writel(mask, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_unmask_irq()
99 __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
100 __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
103 __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
104 __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); in gemini_init_irq()
/linux-4.1.27/arch/arm/mach-s5pv210/
Dpm.c68 __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK); in s5pv210_pm_prepare()
69 __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK); in s5pv210_pm_prepare()
72 __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0); in s5pv210_pm_prepare()
76 __raw_writel(tmp, S5P_SLEEP_CFG); in s5pv210_pm_prepare()
82 __raw_writel(tmp, S5P_PWR_CFG); in s5pv210_pm_prepare()
87 __raw_writel(tmp, S5P_OTHERS); in s5pv210_pm_prepare()
163 __raw_writel(tmp , S5P_OTHERS); in s5pv210_pm_resume()
/linux-4.1.27/arch/arm/include/asm/
Dcti.h91 __raw_writel(val, base + CTIINEN + trig_in * 4); in cti_map_trigger()
95 __raw_writel(val, base + CTIOUTEN + trig_out * 4); in cti_map_trigger()
106 __raw_writel(0x1, cti->base + CTICONTROL); in cti_enable()
117 __raw_writel(0, cti->base + CTICONTROL); in cti_disable()
133 __raw_writel(val, base + CTIINTACK); in cti_irq_ack()
145 __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS); in cti_unlock()
157 __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS); in cti_lock()
Dio.h99 #define __raw_writel __raw_writel macro
100 static inline void __raw_writel(u32 val, volatile void __iomem *addr) in __raw_writel() function
258 #define outl(v,p) ({ __iowmb(); __raw_writel((__force __u32) \
304 #define writel_relaxed(v,c) __raw_writel((__force u32) cpu_to_le32(v),c)
348 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
/linux-4.1.27/arch/sh/boards/
Dboard-magicpanelr2.c69 __raw_writel(0x36db0400, CS2BCR); in setup_chip_select()
71 __raw_writel(0x000003c0, CS2WCR); in setup_chip_select()
75 __raw_writel(0x00000200, CS4BCR); in setup_chip_select()
77 __raw_writel(0x00100981, CS4WCR); in setup_chip_select()
81 __raw_writel(0x00000200, CS5ABCR); in setup_chip_select()
83 __raw_writel(0x00100981, CS5AWCR); in setup_chip_select()
87 __raw_writel(0x00000200, CS5BBCR); in setup_chip_select()
89 __raw_writel(0x00100981, CS5BWCR); in setup_chip_select()
93 __raw_writel(0x00000200, CS6ABCR); in setup_chip_select()
95 __raw_writel(0x001009C1, CS6AWCR); in setup_chip_select()
Dboard-sh2007.c131 __raw_writel(CS5BCR_D, CS5BCR); in sh2007_setup()
132 __raw_writel(CS5WCR_D, CS5WCR); in sh2007_setup()
133 __raw_writel(CS5PCR_D, CS5PCR); in sh2007_setup()
/linux-4.1.27/arch/score/kernel/
Dirq.c60 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \ in score_mask()
63 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) | \ in score_mask()
72 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \ in score_unmask()
75 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKH) & \ in score_unmask()
104 __raw_writel(0xffffffff, SCORE_PIC + INT_MASKL); in init_IRQ()
105 __raw_writel(0xffffffff, SCORE_PIC + INT_MASKH); in init_IRQ()
/linux-4.1.27/drivers/video/fbdev/
Dtgafb.c671 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
672 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
690 __raw_writel((is8bpp
704 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
717 __raw_writel(mask << shift, fb_base + pos);
723 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
746 __raw_writel(mask, fb_base + pos + j*bincr);
755 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
766 __raw_writel(mask, fb_base + pos);
771 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
[all …]
Dgrvga.c155 __raw_writel(((info->var.yres - 1) << 16) | (info->var.xres - 1), in grvga_set_par()
158 __raw_writel((info->var.lower_margin << 16) | (info->var.right_margin), in grvga_set_par()
161 __raw_writel((info->var.vsync_len << 16) | (info->var.hsync_len), in grvga_set_par()
164 …__raw_writel(((info->var.yres + info->var.lower_margin + info->var.upper_margin + info->var.vsync_… in grvga_set_par()
186 __raw_writel((par->clk_sel << 6) | (func << 4) | 1, in grvga_set_par()
219 __raw_writel((regno << 24) | (red << 16) | (green << 8) | blue, in grvga_setcolreg()
253 __raw_writel(base_addr, in grvga_pan_display()
492 __raw_writel(physical_start, &par->regs->fb_pos); in grvga_probe()
493 __raw_writel(__raw_readl(&par->regs->status) | 1, /* Enable framebuffer */ in grvga_probe()
/linux-4.1.27/arch/sh/kernel/cpu/irq/
Dintc-sh5.c98 __raw_writel(bitmask, reg); in enable_intc_irq()
115 __raw_writel(bitmask, reg); in disable_intc_irq()
142 __raw_writel(-1, INTC_INTDSB_0); in plat_irq_setup()
143 __raw_writel(-1, INTC_INTDSB_1); in plat_irq_setup()
146 __raw_writel( NO_PRIORITY, reg); in plat_irq_setup()
171 __raw_writel(INTC_ICR_IRLM, reg); in plat_irq_setup()
179 __raw_writel(data, reg); in plat_irq_setup()
/linux-4.1.27/arch/mips/include/asm/mach-rc32434/
Ddma_v.h29 __raw_writel(0, &ch->dmac); in rc32434_halt_dma()
32 __raw_writel(0, &ch->dmas); in rc32434_halt_dma()
43 __raw_writel(0, &ch->dmandptr); in rc32434_start_dma()
44 __raw_writel(dma_addr, &ch->dmadptr); in rc32434_start_dma()
49 __raw_writel(dma_addr, &ch->dmandptr); in rc32434_chain_dma()
/linux-4.1.27/arch/arm/plat-samsung/
Dpm-gpio.c54 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
58 __raw_writel(gps_gpdat, base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
59 __raw_writel(gps_gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
138 __raw_writel(chip->pm_save[2], base + OFFS_UP); in samsung_gpio_pm_2bit_resume()
181 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
185 __raw_writel(gps_gpdat, base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
186 __raw_writel(gps_gpcon, base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
259 __raw_writel(gpcon, con); in samsung_gpio_pm_4bit_con()
282 __raw_writel(chip->pm_save[2], base + OFFS_DAT); in samsung_gpio_pm_4bit_resume()
283 __raw_writel(chip->pm_save[1], base + OFFS_CON); in samsung_gpio_pm_4bit_resume()
[all …]
Dpm-debug.c91 __raw_writel(save->ulcon, regs + S3C2410_ULCON); in s3c_pm_restore_uarts()
92 __raw_writel(save->ucon, regs + S3C2410_UCON); in s3c_pm_restore_uarts()
93 __raw_writel(save->ufcon, regs + S3C2410_UFCON); in s3c_pm_restore_uarts()
94 __raw_writel(save->umcon, regs + S3C2410_UMCON); in s3c_pm_restore_uarts()
95 __raw_writel(save->ubrdiv, regs + S3C2410_UBRDIV); in s3c_pm_restore_uarts()
98 __raw_writel(save->udivslot, regs + S3C2443_DIVSLOT); in s3c_pm_restore_uarts()
Dwatchdog-reset.c47 __raw_writel(0, wdt_base + S3C2410_WTCON); in samsung_wdt_reset()
50 __raw_writel(0x80, wdt_base + S3C2410_WTCNT); in samsung_wdt_reset()
51 __raw_writel(0x80, wdt_base + S3C2410_WTDAT); in samsung_wdt_reset()
54 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV16 | in samsung_wdt_reset()
Dpm-common.c56 __raw_writel(ptr->val, ptr->reg); in s3c_pm_do_restore()
74 __raw_writel(ptr->val, ptr->reg); in s3c_pm_do_restore_core()
/linux-4.1.27/arch/sh/drivers/dma/
Ddmabrg.c91 __raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ in dmabrg_irq()
115 __raw_writel(dcr, DMABRGCR); in dmabrg_disable_irq()
123 __raw_writel(dcr, DMABRGCR); in dmabrg_enable_irq()
169 __raw_writel(0, DMABRGCR); in dmabrg_init()
170 __raw_writel(0, DMACHCR0); in dmabrg_init()
171 __raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */ in dmabrg_init()
175 __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR); in dmabrg_init()
Ddma-pvr2.c46 __raw_writel(0, PVR2_DMA_LMMODE0); in pvr2_request_dma()
63 __raw_writel(chan->dar, PVR2_DMA_ADDR); in pvr2_xfer_dma()
64 __raw_writel(chan->count, PVR2_DMA_COUNT); in pvr2_xfer_dma()
65 __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE); in pvr2_xfer_dma()
Ddma-sh.c120 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); in dma_tei()
154 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); in sh_dmac_configure_channel()
171 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); in sh_dmac_enable_dma()
191 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); in sh_dmac_disable_dma()
222 __raw_writel(chan->sar, (dma_base_addr(chan->chan) + SAR)); in sh_dmac_xfer_dma()
225 __raw_writel(chan->dar, (dma_base_addr(chan->chan) + DAR)); in sh_dmac_xfer_dma()
227 __raw_writel(chan->count >> calc_xmit_shift(chan), in sh_dmac_xfer_dma()
/linux-4.1.27/arch/arm/mach-cns3xxx/
Dpm.c23 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
32 __raw_writel(reg, PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
41 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
54 __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down()
70 __raw_writel(reg, PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force()
74 __raw_writel(reg, PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force()
Ddevices.c60 __raw_writel(tmp, MISC_SATA_POWER_MODE); in cns3xxx_ahci_init()
105 __raw_writel(gpioa_pins, gpioa); in cns3xxx_sdhci_init()
/linux-4.1.27/drivers/watchdog/
Dtxx9wdt.c49 __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); in txx9wdt_ping()
57 __raw_writel(WD_TIMER_CLK * wdt_dev->timeout, &txx9wdt_reg->cpra); in txx9wdt_start()
58 __raw_writel(WD_TIMER_CCD, &txx9wdt_reg->ccdr); in txx9wdt_start()
59 __raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */ in txx9wdt_start()
60 __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG, in txx9wdt_start()
62 __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); in txx9wdt_start()
70 __raw_writel(TXx9_TMWTMR_WDIS, &txx9wdt_reg->wtmr); in txx9wdt_stop()
71 __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, in txx9wdt_stop()
Dks8695_wdt.c73 __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_stop()
88 __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_start()
91 __raw_writel(tval | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC); in ks8695_wdt_start()
95 __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_start()
109 __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_reload()
110 __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); in ks8695_wdt_reload()
Dm54xx_wdt.c55 __raw_writel(gms0, MCF_GPT_GMS0); in wdt_enable()
56 __raw_writel(MCF_GPT_GCIR_PRE(heartbeat*(MCF_BUSCLK/0xffff)) | in wdt_enable()
59 __raw_writel(gms0, MCF_GPT_GMS0); in wdt_enable()
69 __raw_writel(gms0, MCF_GPT_GMS0); in wdt_disable()
78 __raw_writel(gms0, MCF_GPT_GMS0); in wdt_keepalive()
/linux-4.1.27/drivers/spi/
Dspi-bcm63xx-hsspi.c120 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_cs()
131 __raw_writel(CLK_CTRL_ACCUM_RST_ON_LOOP | reg, in bcm63xx_hsspi_set_clk()
139 __raw_writel(reg, bs->regs + HSSPI_PROFILE_SIGNAL_CTRL_REG(profile)); in bcm63xx_hsspi_set_clk()
147 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_set_clk()
174 __raw_writel(0 << MODE_CTRL_PREPENDBYTE_CNT_SHIFT | in bcm63xx_hsspi_do_txrx()
191 __raw_writel(HSSPI_PINGx_CMD_DONE(0), in bcm63xx_hsspi_do_txrx()
195 __raw_writel(!chip_select << PINGPONG_CMD_SS_SHIFT | in bcm63xx_hsspi_do_txrx()
228 __raw_writel(reg, bs->regs + in bcm63xx_hsspi_setup()
240 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_setup()
298 __raw_writel(reg, bs->regs + HSSPI_GLOBAL_CTRL_REG); in bcm63xx_hsspi_transfer_one()
[all …]
Dspi-nuc900.c92 __raw_writel(val, hw->regs + USI_SSR); in nuc900_slave_select()
101 __raw_writel(val, hw->regs + USI_CNT); in nuc900_slave_select()
131 __raw_writel(val, hw->regs + USI_CNT); in nuc900_spi_setup_txnum()
149 __raw_writel(val, hw->regs + USI_CNT); in nuc900_spi_setup_txbitlen()
165 __raw_writel(val, hw->regs + USI_CNT); in nuc900_spi_gobusy()
184 __raw_writel(hw_txbyte(hw, 0x0), hw->regs + USI_TX0); in nuc900_spi_txrx()
200 __raw_writel(status, hw->regs + USI_CNT); in nuc900_spi_irq()
210 __raw_writel(hw_txbyte(hw, count), hw->regs + USI_TX0); in nuc900_spi_irq()
236 __raw_writel(val, hw->regs + USI_CNT); in nuc900_tx_edge()
254 __raw_writel(val, hw->regs + USI_CNT); in nuc900_rx_edge()
[all …]
/linux-4.1.27/drivers/rtc/
Drtc-nuc900.c71 __raw_writel(rtc_irq, rtc->rtc_reg + REG_RTC_RIIR); in nuc900_rtc_interrupt()
77 __raw_writel(rtc_irq, rtc->rtc_reg + REG_RTC_RIIR); in nuc900_rtc_interrupt()
89 __raw_writel(INIRRESET, nuc900_rtc->rtc_reg + REG_RTC_INIR); in check_rtc_access_enable()
93 __raw_writel(AERPOWERON, nuc900_rtc->rtc_reg + REG_RTC_AER); in check_rtc_access_enable()
142 __raw_writel(__raw_readl(rtc->rtc_reg + REG_RTC_RIER)| in nuc900_alarm_irq_enable()
145 __raw_writel(__raw_readl(rtc->rtc_reg + REG_RTC_RIER)& in nuc900_alarm_irq_enable()
176 __raw_writel(val, rtc->rtc_reg + REG_RTC_CLR); in nuc900_rtc_set_time()
179 __raw_writel(val, rtc->rtc_reg + REG_RTC_TLR); in nuc900_rtc_set_time()
209 __raw_writel(val, rtc->rtc_reg + REG_RTC_CAR); in nuc900_rtc_set_alarm()
212 __raw_writel(val, rtc->rtc_reg + REG_RTC_TAR); in nuc900_rtc_set_alarm()
[all …]
Drtc-tx4939.c34 __raw_writel(cmd, &rtcreg->ctl); in tx4939_rtc_cmd()
59 __raw_writel(0, &rtcreg->adr); in tx4939_rtc_set_mmss()
61 __raw_writel(buf[i], &rtcreg->dat); in tx4939_rtc_set_mmss()
85 __raw_writel(2, &rtcreg->adr); in tx4939_rtc_read_time()
117 __raw_writel(0, &rtcreg->adr); in tx4939_rtc_set_alarm()
119 __raw_writel(buf[i], &rtcreg->dat); in tx4939_rtc_set_alarm()
143 __raw_writel(2, &rtcreg->adr); in tx4939_rtc_read_alarm()
204 __raw_writel(pos++, &rtcreg->adr); in tx4939_rtc_nvram_read()
223 __raw_writel(pos++, &rtcreg->adr); in tx4939_rtc_nvram_write()
224 __raw_writel(*buf++, &rtcreg->dat); in tx4939_rtc_nvram_write()
Drtc-imxdi.c140 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr, in di_int_enable()
153 __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr, in di_int_disable()
172 __raw_writel(DSR_WEF, imxdi->ioaddr + DSR); in clear_write_error()
204 __raw_writel(val, imxdi->ioaddr + reg); in di_write_wait()
449 __raw_writel(0, imxdi->ioaddr + DIER); in dryice_rtc_probe()
519 __raw_writel(0, imxdi->ioaddr + DIER); in dryice_rtc_remove()
/linux-4.1.27/sound/soc/mxs/
Dmxs-saif.c155 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
197 __raw_writel(scr, master_saif->base + SAIF_CTRL); in mxs_saif_set_clk()
222 __raw_writel(BM_SAIF_CTRL_CLKGATE, in mxs_saif_put_mclk()
224 __raw_writel(BM_SAIF_CTRL_RUN, in mxs_saif_put_mclk()
250 __raw_writel(BM_SAIF_CTRL_SFTRST, in mxs_saif_get_mclk()
254 __raw_writel(BM_SAIF_CTRL_CLKGATE, in mxs_saif_get_mclk()
279 __raw_writel(BM_SAIF_CTRL_RUN, in mxs_saif_get_mclk()
358 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); in mxs_saif_set_dai_fmt()
377 __raw_writel(BM_SAIF_CTRL_SFTRST, in mxs_saif_startup()
381 __raw_writel(BM_SAIF_CTRL_CLKGATE, in mxs_saif_startup()
[all …]
/linux-4.1.27/drivers/mmc/host/
Dau1xmmc.c169 __raw_writel(val, HOST_CONFIG(host)); in IRQ_ON()
177 __raw_writel(val | SD_CONFIG2_FF, HOST_CONFIG2(host)); in FLUSH_FIFO()
184 __raw_writel(val, HOST_CONFIG2(host)); in FLUSH_FIFO()
192 __raw_writel(val, HOST_CONFIG(host)); in IRQ_OFF()
204 __raw_writel(config2 | SD_CONFIG2_DF, HOST_CONFIG2(host)); in SEND_STOP()
208 __raw_writel(STOP_CMD, HOST_CMD(host)); in SEND_STOP()
303 __raw_writel(cmd->arg, HOST_CMDARG(host)); in au1xmmc_send_command()
309 __raw_writel((mmccmd | SD_CMD_GO), HOST_CMD(host)); in au1xmmc_send_command()
324 __raw_writel(SD_STATUS_CR, HOST_STATUS(host)); in au1xmmc_send_command()
364 __raw_writel(SD_STATUS_WC | SD_STATUS_RC, HOST_STATUS(host)); in au1xmmc_data_complete()
[all …]
/linux-4.1.27/drivers/input/touchscreen/
Dw90p910_ts.c78 __raw_writel(ADC_TSC_X, w90p910_ts->ts_reg + 0x04); in w90p910_prepare_x_reading()
82 __raw_writel(ctlreg, w90p910_ts->ts_reg); in w90p910_prepare_x_reading()
91 __raw_writel(ADC_TSC_Y, w90p910_ts->ts_reg + 0x04); in w90p910_prepare_y_reading()
95 __raw_writel(ctlreg, w90p910_ts->ts_reg); in w90p910_prepare_y_reading()
107 __raw_writel(ctlreg, w90p910_ts->ts_reg); in w90p910_prepare_next_packet()
173 __raw_writel(ADC_RST1, w90p910_ts->ts_reg); in w90p910_open()
175 __raw_writel(ADC_RST0, w90p910_ts->ts_reg); in w90p910_open()
180 __raw_writel(val & TSC_FOURWIRE, w90p910_ts->ts_reg + 0x04); in w90p910_open()
181 __raw_writel(ADC_DELAY, w90p910_ts->ts_reg + 0x08); in w90p910_open()
189 __raw_writel(val, w90p910_ts->ts_reg); in w90p910_open()
[all …]
/linux-4.1.27/drivers/parisc/
Ddino.c187 __raw_writel(v, base_addr + DINO_PCI_ADDR); in dino_cfg_read()
222 __raw_writel(v & 0xffffff00, base_addr + DINO_PCI_ADDR); in dino_cfg_write()
226 __raw_writel(v, base_addr + DINO_PCI_ADDR); in dino_cfg_write()
262 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
279 __raw_writel((u32) addr, d->base_addr + DINO_PCI_ADDR); \
307 __raw_writel(dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); in dino_mask_irq()
328 __raw_writel( dino_dev->imr, dino_dev->hba.base_addr+DINO_IMR); in dino_unmask_irq()
501 __raw_writel(1 << i, base_addr + DINO_IO_ADDR_EN); in dino_card_setup()
660 __raw_writel(0x00000005, in dino_card_init()
665 __raw_writel(0x00000000, dino_dev->hba.base_addr+DINO_GMASK); in dino_card_init()
[all …]
/linux-4.1.27/arch/arm/mach-shmobile/
Dsmp-sh73a0.c49 __raw_writel(1 << lcpu, WUPCR); /* wake up */ in sh73a0_boot_secondary()
51 __raw_writel(1 << lcpu, SRESCR); /* reset */ in sh73a0_boot_secondary()
59 __raw_writel(0, APARMBAREA); /* 4k */ in sh73a0_smp_prepare_cpus()
60 __raw_writel(__pa(shmobile_boot_vector), SBAR); in sh73a0_smp_prepare_cpus()
/linux-4.1.27/drivers/cpufreq/
Ds5pv210-cpufreq.c221 __raw_writel(tmp1, reg); in s5pv210_set_refresh()
306 __raw_writel(reg, S5P_CLK_DIV2); in s5pv210_target()
321 __raw_writel(reg, S5P_CLK_SRC2); in s5pv210_target()
339 __raw_writel(reg, S5P_CLK_SRC0); in s5pv210_target()
364 __raw_writel(reg, S5P_CLK_DIV0); in s5pv210_target()
378 __raw_writel(reg, S5P_ARM_MCS_CON); in s5pv210_target()
382 __raw_writel(0x2cf, S5P_APLL_LOCK); in s5pv210_target()
390 __raw_writel(APLL_VAL_1000, S5P_APLL_CON); in s5pv210_target()
392 __raw_writel(APLL_VAL_800, S5P_APLL_CON); in s5pv210_target()
407 __raw_writel(reg, S5P_CLK_SRC2); in s5pv210_target()
[all …]
Dexynos5440-cpufreq.c158 __raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * in init_div_table()
172 __raw_writel(0, dvfs_info->base + XMU_DVFS_CTRL); in exynos_enable_dvfs()
177 __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN); in exynos_enable_dvfs()
182 __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN); in exynos_enable_dvfs()
203 __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4); in exynos_enable_dvfs()
207 __raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT, in exynos_enable_dvfs()
230 __raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4); in exynos_target()
275 __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ); in exynos_cpufreq_irq()
/linux-4.1.27/drivers/i2c/busses/
Di2c-iop3xx.c65 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_reset()
66 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET); in iop3xx_i2c_reset()
67 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_reset()
96 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_enable()
107 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_transaction_cleanup()
121 __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET); in iop3xx_i2c_irq_handler()
249 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); in iop3xx_i2c_send_target_addr()
254 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_send_target_addr()
268 __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET); in iop3xx_i2c_write_byte()
276 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); in iop3xx_i2c_write_byte()
[all …]
/linux-4.1.27/drivers/input/keyboard/
Ddavinci_keyscan.c87 __raw_writel(DAVINCI_KEYSCAN_INT_ALL, in davinci_ks_initialize()
91 __raw_writel(DAVINCI_KEYSCAN_INT_ALL, in davinci_ks_initialize()
95 __raw_writel(pdata->strobe, in davinci_ks_initialize()
97 __raw_writel(pdata->interval, in davinci_ks_initialize()
99 __raw_writel(0x01, in davinci_ks_initialize()
116 __raw_writel(DAVINCI_KEYSCAN_AUTODET | DAVINCI_KEYSCAN_KEYEN | in davinci_ks_initialize()
134 __raw_writel(0x0, davinci_ks->base + DAVINCI_KEYSCAN_INTENA); in davinci_ks_interrupt()
159 __raw_writel(DAVINCI_KEYSCAN_INT_ALL, in davinci_ks_interrupt()
164 __raw_writel(0x1, davinci_ks->base + DAVINCI_KEYSCAN_INTENA); in davinci_ks_interrupt()
/linux-4.1.27/arch/arm/mach-s3c64xx/include/mach/
Dpm-core.h37 __raw_writel(tmp, S3C_PCLK_GATE); in s3c_pm_debug_init_uart()
46 __raw_writel(__raw_readl(S3C64XX_EINT0PEND), S3C64XX_EINT0PEND); in s3c_pm_arch_prepare_irqs()
109 __raw_writel(0, S3C64XX_SLPEN); in s3c_pm_restored_gpios()
119 __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN); in samsung_pm_saved_gpios()
/linux-4.1.27/drivers/net/ethernet/xilinx/
Dxilinx_emaclite.c162 __raw_writel(reg_data | XEL_TSR_XMIT_IE_MASK, in xemaclite_enable_interrupts()
166 __raw_writel(XEL_RSR_RECV_IE_MASK, drvdata->base_addr + XEL_RSR_OFFSET); in xemaclite_enable_interrupts()
169 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); in xemaclite_enable_interrupts()
184 __raw_writel(XEL_GIER_GIE_MASK, drvdata->base_addr + XEL_GIER_OFFSET); in xemaclite_disable_interrupts()
188 __raw_writel(reg_data & (~XEL_TSR_XMIT_IE_MASK), in xemaclite_disable_interrupts()
193 __raw_writel(reg_data & (~XEL_RSR_RECV_IE_MASK), in xemaclite_disable_interrupts()
350 __raw_writel((byte_count & XEL_TPLR_LENGTH_MASK), in xemaclite_send_data()
359 __raw_writel(reg_data, addr + XEL_TSR_OFFSET); in xemaclite_send_data()
441 __raw_writel(reg_data, addr + XEL_RSR_OFFSET); in xemaclite_recv_data()
468 __raw_writel(ETH_ALEN, addr + XEL_TPLR_OFFSET); in xemaclite_update_address()
[all …]
/linux-4.1.27/arch/arm/mach-s3c64xx/
Dpm.c54 __raw_writel(val, S3C64XX_NORMAL_CFG); in s3c64xx_pd_off()
69 __raw_writel(val, S3C64XX_NORMAL_CFG); in s3c64xx_pd_on()
224 __raw_writel(s3c_irqwake_eintmask, S3C64XX_EINT_MASK); in s3c_pm_configure_extint()
229 __raw_writel(0, S3C64XX_EINT_MASK); in s3c_pm_restore_core()
258 __raw_writel(tmp, S3C64XX_PWR_CFG); in s3c64xx_cpu_suspend()
262 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), in s3c64xx_cpu_suspend()
306 __raw_writel(virt_to_phys(s3c_cpu_resume), S3C64XX_INFORM0); in s3c64xx_pm_prepare()
309 __raw_writel(__raw_readl(S3C64XX_WAKEUP_STAT), S3C64XX_WAKEUP_STAT); in s3c64xx_pm_prepare()
Dmach-anw6410.c97 __raw_writel(tmp, S3C64XX_SPCON); in anw6410_lcd_mode_set()
102 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); in anw6410_lcd_mode_set()
113 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV); in anw6410_lcd_power_set()
119 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV); in anw6410_lcd_power_set()
167 __raw_writel(anw6410_extdev_status, ANW6410_VA_EXTDEV); in anw6410_dm9000_enable()
Dirq-pm.c97 __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); in s3c64xx_irq_pm_resume()
100 __raw_writel(grp->con, S3C64XX_EINT12CON + (i * 4)); in s3c64xx_irq_pm_resume()
101 __raw_writel(grp->mask, S3C64XX_EINT12MASK + (i * 4)); in s3c64xx_irq_pm_resume()
102 __raw_writel(grp->fltcon, S3C64XX_EINT12FLTCON + (i * 4)); in s3c64xx_irq_pm_resume()
Dmach-real6410.c222 __raw_writel(tmp, S3C64XX_SPCON); in real6410_map_io()
227 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); in real6410_map_io()
314 __raw_writel(cs1, S3C64XX_SROM_BW); in real6410_machine_init()
318 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | in real6410_machine_init()
Dmach-mini6410.c252 __raw_writel(tmp, S3C64XX_SPCON); in mini6410_map_io()
257 __raw_writel(tmp, S3C64XX_MODEM_MIFPCON); in mini6410_map_io()
345 __raw_writel(cs1, S3C64XX_SROM_BW); in mini6410_machine_init()
349 __raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) | in mini6410_machine_init()
/linux-4.1.27/drivers/devfreq/exynos/
Dexynos_ppmu.c20 __raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base); in exynos_ppmu_reset()
21 __raw_writel(PPMU_ENABLE_CYCLE | in exynos_ppmu_reset()
32 __raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch)); in exynos_ppmu_setevent()
37 __raw_writel(PPMU_ENABLE, ppmu_base); in exynos_ppmu_start()
42 __raw_writel(PPMU_DISABLE, ppmu_base); in exynos_ppmu_stop()
Dexynos4_bus.c306 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); in exynos4210_set_busclk()
315 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); in exynos4210_set_busclk()
331 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); in exynos4210_set_busclk()
347 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); in exynos4210_set_busclk()
372 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); in exynos4x12_set_busclk()
392 __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); in exynos4x12_set_busclk()
418 __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); in exynos4x12_set_busclk()
434 __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); in exynos4x12_set_busclk()
450 __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); in exynos4x12_set_busclk()
464 __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); in exynos4x12_set_busclk()
[all …]
/linux-4.1.27/drivers/gpio/
Dgpio-samsung.c53 __raw_writel(pup, reg); in samsung_gpio_setpull_updown()
125 __raw_writel(pup, reg); in s3c24xx_gpio_setpull_1()
196 __raw_writel(con, reg); in samsung_gpio_setcfg_2bit()
259 __raw_writel(con, reg); in samsung_gpio_setcfg_4bit()
327 __raw_writel(con, reg); in s3c24xx_gpio_setcfg_abank()
443 __raw_writel(con, base + 0x00); in samsung_gpiolib_2bit_input()
464 __raw_writel(dat, base + 0x04); in samsung_gpiolib_2bit_output()
470 __raw_writel(con, base + 0x00); in samsung_gpiolib_2bit_output()
471 __raw_writel(dat, base + 0x04); in samsung_gpiolib_2bit_output()
505 __raw_writel(con, base + GPIOCON_OFF); in samsung_gpiolib_4bit_input()
[all …]
Dgpio-ks8695.c55 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPC); in ks8695_gpio_mode()
78 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_interrupt()
114 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_direction_input()
144 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD); in ks8695_gpio_direction_output()
149 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPM); in ks8695_gpio_direction_output()
176 __raw_writel(x, KS8695_GPIO_VA + KS8695_IOPD); in ks8695_gpio_set_value()
Dgpio-lpc32xx.c178 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
181 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_dir_p012()
191 __raw_writel(u, group->gpio_grp->dir_clr); in __set_gpio_dir_p3()
193 __raw_writel(u, group->gpio_grp->dir_set); in __set_gpio_dir_p3()
200 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_level_p012()
203 __raw_writel(GPIO012_PIN_TO_BIT(pin), in __set_gpio_level_p012()
213 __raw_writel(u, group->gpio_grp->outp_set); in __set_gpio_level_p3()
215 __raw_writel(u, group->gpio_grp->outp_clr); in __set_gpio_level_p3()
222 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); in __set_gpo_level_p3()
224 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); in __set_gpo_level_p3()
/linux-4.1.27/drivers/irqchip/
Dirq-mxs.c53 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, in icoll_ack_irq()
59 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, in icoll_mask_irq()
65 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE, in icoll_unmask_irq()
80 __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR); in icoll_handle_irq()
/linux-4.1.27/drivers/tty/serial/
Dapbuart.h53 #define UART_PUT_CHAR(port, v) (__raw_writel(v, APBBASE_DATA_P(port)))
55 #define UART_PUT_STATUS(port, v)(__raw_writel(v, APBBASE_STATUS_P(port)))
57 #define UART_PUT_CTRL(port, v) (__raw_writel(v, APBBASE_CTRL_P(port)))
59 #define UART_PUT_SCAL(port, v) (__raw_writel(v, APBBASE_SCALAR_P(port)))
/linux-4.1.27/drivers/infiniband/hw/mthca/
Dmthca_doorbell.h84 __raw_writel(((__force u32 *) &val)[0], dest); in mthca_write64_raw()
85 __raw_writel(((__force u32 *) &val)[1], dest + 4); in mthca_write64_raw()
97 __raw_writel(hi, dest); in mthca_write64()
98 __raw_writel(lo, dest + 4); in mthca_write64()
/linux-4.1.27/drivers/net/ethernet/xscale/
Dixp4xx_eth.c323 __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event); in ixp_rx_timestamp()
369 __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event); in ixp_tx_timestamp()
397 __raw_writel(0, &regs->channel[ch].ch_control); in hwtstamp_set()
401 __raw_writel(MASTER_MODE, &regs->channel[ch].ch_control); in hwtstamp_set()
410 __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED, in hwtstamp_set()
453 __raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]); in ixp4xx_mdio_cmd()
454 __raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]); in ixp4xx_mdio_cmd()
456 __raw_writel(((phy_id << 5) | location) & 0xFF, in ixp4xx_mdio_cmd()
458 __raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */, in ixp4xx_mdio_cmd()
543 __raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control); in ixp4xx_mdio_register()
[all …]
/linux-4.1.27/arch/arm/mach-exynos/
Dfirmware.c48 __raw_writel(virt_to_phys(exynos_cpu_resume_ns), in exynos_do_idle()
50 __raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20); in exynos_do_idle()
103 __raw_writel(boot_addr, boot_reg); in exynos_set_cpu_boot_addr()
229 __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); in exynos_set_boot_flag()
238 __raw_writel(tmp, REG_CPU_STATE_ADDR + cpu * 4); in exynos_clear_boot_flag()
Dpm.c136 __raw_writel(virt_to_phys(exynos_cpu_resume), in exynos_cpu_set_boot_vector()
138 __raw_writel(flags, exynos_boot_vector_flag()); in exynos_cpu_set_boot_vector()
239 __raw_writel(virt_to_phys(exynos_cpu_resume), in exynos_cpu0_enter_aftr()
254 __raw_writel(virt_to_phys(exynos_cpu_resume), in exynos_cpu0_enter_aftr()
302 __raw_writel(virt_to_phys(exynos_cpu_resume), cpu_boot_reg_base()); in exynos_pre_enter_aftr()
Dmcpm-exynos.c222 __raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ in exynos_mcpm_setup_entry_point()
223 __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ in exynos_mcpm_setup_entry_point()
224 __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8); in exynos_mcpm_setup_entry_point()
/linux-4.1.27/drivers/ata/
Dpata_imx.c60 __raw_writel(val, priv->host_regs + PATA_IMX_ATA_CONTROL); in pata_imx_set_mode()
153 __raw_writel(PATA_IMX_ATA_CTRL_FIFO_RST_B | in pata_imx_probe()
157 __raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2, in pata_imx_probe()
181 __raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN); in pata_imx_remove()
197 __raw_writel(0, priv->host_regs + PATA_IMX_ATA_INT_EN); in pata_imx_suspend()
215 __raw_writel(priv->ata_ctl, priv->host_regs + PATA_IMX_ATA_CONTROL); in pata_imx_resume()
217 __raw_writel(PATA_IMX_ATA_INTR_ATA_INTRQ2, in pata_imx_resume()
/linux-4.1.27/arch/mips/include/asm/mach-ralink/
Dralink_regs.h21 __raw_writel(val, rt_sysc_membase + reg); in rt_sysc_w32()
33 __raw_writel(val | set, rt_sysc_membase + reg); in rt_sysc_m32()
38 __raw_writel(val, rt_memc_membase + reg); in rt_memc_w32()
/linux-4.1.27/drivers/ptp/
Dptp_ixp46x.c77 __raw_writel(lo, &regs->systime_lo); in ixp_systime_write()
78 __raw_writel(hi, &regs->systime_hi); in ixp_systime_write()
126 __raw_writel(ack, &regs->event); in isr()
155 __raw_writel(addend, &regs->addend); in ptp_ixp_adjfreq()
316 __raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend); in ptp_ixp_init()
317 __raw_writel(1, &ixp_clock.regs->trgt_lo); in ptp_ixp_init()
318 __raw_writel(0, &ixp_clock.regs->trgt_hi); in ptp_ixp_init()
319 __raw_writel(TTIPEND, &ixp_clock.regs->event); in ptp_ixp_init()
/linux-4.1.27/arch/mips/paravirt/
Dparavirt-irq.c177 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s); in irq_pci_enable()
184 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c); in irq_pci_disable()
195 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1c); in irq_pci_mask()
202 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_en_w1s); in irq_pci_unmask()
225 __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); in irq_mbox_all()
247 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1c + sizeof(u32)); in irq_mbox_ack()
258 __raw_writel(mask, mips_irq_chip + mips_irq_chip_reg_raw_w1s + sizeof(u32)); in irq_mbox_ipi()
270 __raw_writel(mask, base + (cpuid * mips_irq_cpu_stride)); in irq_mbox_cpu_onoffline()
/linux-4.1.27/arch/metag/include/asm/
Dio.h80 #define __raw_writel __raw_writel macro
81 static inline void __raw_writel(u32 b, volatile void __iomem *addr) in __raw_writel() function
129 #define metag_out32(b, addr) __raw_writel(b, (volatile void __iomem *)(addr))
/linux-4.1.27/arch/sh/include/asm/
Dwatchdog.h85 __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT); in sh_wdt_write_cnt()
97 __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST); in sh_wdt_write_bst()
118 __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR); in sh_wdt_write_csr()
Dmmu_context_32.h16 __raw_writel(asid, MMU_PTEAEX); in set_asid()
52 __raw_writel((unsigned long)pgd, MMU_TTB); in set_TTB()
/linux-4.1.27/drivers/clk/samsung/
Dclk-pll.c193 __raw_writel(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
199 __raw_writel(rate->pdiv * PLL35XX_LOCK_FACTOR, in samsung_pll35xx_set_rate()
209 __raw_writel(tmp, pll->con_reg); in samsung_pll35xx_set_rate()
302 __raw_writel(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
308 __raw_writel(rate->pdiv * PLL36XX_LOCK_FACTOR, pll->lock_reg); in samsung_pll36xx_set_rate()
317 __raw_writel(pll_con0, pll->con_reg); in samsung_pll36xx_set_rate()
321 __raw_writel(pll_con1, pll->con_reg + 4); in samsung_pll36xx_set_rate()
417 __raw_writel(con0, pll->con_reg); in samsung_pll45xx_set_rate()
438 __raw_writel(rate->pdiv * PLL4502_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
441 __raw_writel(rate->pdiv * PLL4508_LOCK_FACTOR, pll->lock_reg); in samsung_pll45xx_set_rate()
[all …]
/linux-4.1.27/arch/sh/boards/mach-microdev/
Dirq.c80 __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); in disable_microdev_irq()
103 __raw_writel(priorities, priorityReg); in enable_microdev_irq()
106 __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); in enable_microdev_irq()
128 __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG); in init_microdev_irq()
/linux-4.1.27/arch/sh/kernel/
Dftrace.c49 __raw_writel(ip + MCOUNT_INSN_SIZE, ftrace_nop); in ftrace_nop_replace()
56 __raw_writel(addr, ftrace_replaced_code); in ftrace_call_replace()
296 __raw_writel(new_addr, ip); in ftrace_mod()
389 __raw_writel(old, parent); in prepare_ftrace_return()
398 __raw_writel(old, parent); in prepare_ftrace_return()
/linux-4.1.27/drivers/pwm/
Dpwm-atmel-tcb.c113 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); in atmel_tcb_pwm_request()
172 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); in atmel_tcb_pwm_disable()
179 __raw_writel(ATMEL_TC_SWTRG | ATMEL_TC_CLKDIS, in atmel_tcb_pwm_disable()
182 __raw_writel(ATMEL_TC_SWTRG, regs + in atmel_tcb_pwm_disable()
254 __raw_writel(cmr, regs + ATMEL_TC_REG(group, CMR)); in atmel_tcb_pwm_enable()
257 __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RA)); in atmel_tcb_pwm_enable()
259 __raw_writel(tcbpwm->duty, regs + ATMEL_TC_REG(group, RB)); in atmel_tcb_pwm_enable()
261 __raw_writel(tcbpwm->period, regs + ATMEL_TC_REG(group, RC)); in atmel_tcb_pwm_enable()
264 __raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG, in atmel_tcb_pwm_enable()
/linux-4.1.27/drivers/usb/host/
Dohci-pxa27x.c167 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_ohci_select_pmm()
168 __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB); in pxa27x_ohci_select_pmm()
256 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_setup_hc()
257 __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA); in pxa27x_setup_hc()
264 __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); in pxa27x_reset_hc()
266 __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR); in pxa27x_reset_hc()
289 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_start_hc()
306 __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR); in pxa27x_start_hc()
307 __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE); in pxa27x_start_hc()
332 __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS); in pxa27x_stop_hc()
Dohci-nxp.c121 __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); in isp1301_configure_lpc32xx()
152 __raw_writel(tmp, USB_OTG_STAT_CONTROL); in ohci_nxp_start_hc()
161 __raw_writel(tmp, USB_OTG_STAT_CONTROL); in ohci_nxp_stop_hc()
196 __raw_writel(USB_SLAVE_HCLK_EN | PAD_CONTROL_LAST_DRIVEN, USB_CTRL); in ohci_hcd_nxp_probe()
240 __raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL); in ohci_hcd_nxp_probe()
/linux-4.1.27/arch/arm/mach-at91/
Dsam9_smc.c29 __raw_writel(config->mode in sam9_smc_cs_write_mode()
46 __raw_writel(AT91_SMC_NWESETUP_(config->nwe_setup) in sam9_smc_cs_configure()
53 __raw_writel(AT91_SMC_NWEPULSE_(config->nwe_pulse) in sam9_smc_cs_configure()
60 __raw_writel(AT91_SMC_NWECYCLE_(config->write_cycle) in sam9_smc_cs_configure()
/linux-4.1.27/drivers/net/ethernet/nuvoton/
Dw90p910_ether.c202 __raw_writel(val, ether->reg + REG_MCMDR); in update_linkspeed_register()
275 __raw_writel(lsw, ether->reg + REG_CAML_BASE + x * CAM_ENTRY_SIZE); in w90p910_write_cam()
276 __raw_writel(msw, ether->reg + REG_CAMM_BASE + x * CAM_ENTRY_SIZE); in w90p910_write_cam()
349 __raw_writel(val, ether->reg + REG_FFTCR); in w90p910_set_fifo_threshold()
359 __raw_writel(val, ether->reg + REG_MCMDR); in w90p910_return_default_idle()
366 __raw_writel(ENSTART, ether->reg + REG_RSDR); in w90p910_trigger_rx()
373 __raw_writel(ENSTART, ether->reg + REG_TSDR); in w90p910_trigger_tx()
384 __raw_writel(val, ether->reg + REG_MIEN); in w90p910_enable_mac_interrupt()
393 __raw_writel(*val, ether->reg + REG_MISTA); in w90p910_get_and_clear_int()
403 __raw_writel(val, ether->reg + REG_MCMDR); in w90p910_set_global_maccmd()
[all …]
/linux-4.1.27/drivers/mtd/nand/
Dnuc900_nand.c49 __raw_writel((val), (dev)->reg + REG_SMDATA)
52 __raw_writel((val), (dev)->reg + REG_SMCMD)
55 __raw_writel((val), (dev)->reg + REG_SMADDR)
223 __raw_writel(RESET_FMI, (nand->reg + REG_FMICSR)); in nuc900_nand_enable()
228 __raw_writel(val | NAND_EN, nand->reg + REG_FMICSR); in nuc900_nand_enable()
235 __raw_writel(val, nand->reg + REG_SMCSR); in nuc900_nand_enable()
/linux-4.1.27/drivers/char/hw_random/
Dbcm2835-rng.c65 __raw_writel(RNG_WARMUP_COUNT, rng_base + RNG_STATUS); in bcm2835_rng_probe()
66 __raw_writel(RNG_RBGEN, rng_base + RNG_CTRL); in bcm2835_rng_probe()
84 __raw_writel(0, rng_base + RNG_CTRL); in bcm2835_rng_remove()
Dmxc-rnga.c101 __raw_writel(ctrl | RNGA_CONTROL_CLEAR_INT, in mxc_rnga_data_read()
115 __raw_writel(ctrl & ~RNGA_CONTROL_SLEEP, mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
126 __raw_writel(ctrl | RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
139 __raw_writel(ctrl & ~RNGA_CONTROL_GO, mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_cleanup()
/linux-4.1.27/drivers/staging/iio/adc/
Dspear_adc.c93 __raw_writel(val, &st->adc_base_spear6xx->status); in spear_adc_set_status()
106 __raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high), in spear_adc_set_clk()
113 __raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]); in spear_adc_set_ctrl()
130 __raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate), in spear_adc_set_scanrate()
132 __raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate), in spear_adc_set_scanrate()
135 __raw_writel(rate, &st->adc_base_spear3xx->scan_rate); in spear_adc_set_scanrate()
244 __raw_writel(0, &st->adc_base_spear6xx->clk); in spear_adc_configure()
/linux-4.1.27/drivers/devfreq/event/
Dexynos-ppmu.c105 __raw_writel(PPMU_CCNT_MASK | in exynos_ppmu_disable()
115 __raw_writel(pmnc, info->ppmu.base + PPMU_PMNC); in exynos_ppmu_disable()
132 __raw_writel(cntens, info->ppmu.base + PPMU_CNTENS); in exynos_ppmu_set_event()
135 __raw_writel(PPMU_RO_DATA_CNT | PPMU_WO_DATA_CNT, in exynos_ppmu_set_event()
146 __raw_writel(pmnc, info->ppmu.base + PPMU_PMNC); in exynos_ppmu_set_event()
164 __raw_writel(pmnc, info->ppmu.base + PPMU_PMNC); in exynos_ppmu_get_event()
189 __raw_writel(cntenc, info->ppmu.base + PPMU_CNTENC); in exynos_ppmu_get_event()
/linux-4.1.27/arch/arc/include/asm/
Dio.h90 #define __raw_writel __raw_writel macro
91 static inline void __raw_writel(u32 w, volatile void __iomem *addr) in __raw_writel() function
/linux-4.1.27/drivers/input/mouse/
Dpxa930_trkball.c72 __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC); in pxa930_trkball_interrupt()
73 __raw_writel(0, trkball->mmio_base + TBSBC); in pxa930_trkball_interrupt()
83 __raw_writel(v, trkball->mmio_base + TBCR); in write_tbcr()
114 __raw_writel(TBSBC_TBSBC, trkball->mmio_base + TBSBC); in pxa930_trkball_config()
115 __raw_writel(0, trkball->mmio_base + TBSBC); in pxa930_trkball_config()
/linux-4.1.27/arch/arm/mach-ep93xx/
Dcore.c127 __raw_writel(1, EP93XX_TIMER1_CLEAR); in ep93xx_timer_interrupt()
170 __raw_writel(tmode, EP93XX_TIMER1_CONTROL); in ep93xx_timer_init()
171 __raw_writel(TIMER1_RELOAD, EP93XX_TIMER1_LOAD); in ep93xx_timer_init()
172 __raw_writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, in ep93xx_timer_init()
176 __raw_writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, in ep93xx_timer_init()
209 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); in ep93xx_syscon_swlocked_write()
210 __raw_writel(val, reg); in ep93xx_syscon_swlocked_write()
225 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); in ep93xx_devcfg_set_clear()
226 __raw_writel(val, EP93XX_SYSCON_DEVCFG); in ep93xx_devcfg_set_clear()
277 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET); in ep93xx_uart_set_mctrl()
[all …]
Dcrunch.c69 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK); in crunch_do()
70 __raw_writel(devcfg, EP93XX_SYSCON_DEVCFG); in crunch_do()
/linux-4.1.27/arch/mips/mti-sead3/
Dsead3-reset.c21 __raw_writel(GORESET, softres_reg); in mips_machine_restart()
29 __raw_writel(GORESET, softres_reg); in mips_machine_halt()
Dsead3-display.c57 __raw_writel((LCD_SETDDRAM | i), in mips_display_message()
60 __raw_writel(ch, display + DISPLAY_LCDDATA); in mips_display_message()
/linux-4.1.27/arch/mips/alchemy/devboards/
Ddb1550.c47 __raw_writel(PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE, in db1550_hw_setup()
49 __raw_writel(PSC_CTRL_DISABLE, base + PSC_CTRL_OFFSET); in db1550_hw_setup()
51 __raw_writel(PSC_AC97RST_RST, base + PSC_AC97RST_OFFSET); in db1550_hw_setup()
598 __raw_writel(PSC_SEL_CLK_SERCLK, in db1550_dev_setup()
601 __raw_writel(PSC_SEL_CLK_SERCLK, in db1550_dev_setup()
605 __raw_writel(PSC_SEL_CLK_INTCLK, in db1550_dev_setup()
608 __raw_writel(PSC_SEL_CLK_INTCLK, in db1550_dev_setup()
/linux-4.1.27/arch/arm64/include/asm/
Dio.h52 #define __raw_writel __raw_writel macro
53 static inline void __raw_writel(u32 val, volatile void __iomem *addr) in __raw_writel() function
127 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
182 #define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
/linux-4.1.27/arch/arm/mach-lpc32xx/include/mach/
Duncompress.h47 __raw_writel((u32) ch, _UARTREG(LPC32XX_UART_DLLFIFO_O)); in putc()
52 __raw_writel(__raw_readl(_UARTREG(LPC32XX_UART_IIRFCR_O)) | in flush()
/linux-4.1.27/arch/sh/kernel/cpu/
Dinit.c65 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); in speculative_execution_init()
94 __raw_writel(expmask, EXPMASK); in expmask_init()
159 __raw_writel(0, addr); in cache_init()
192 __raw_writel(flags, SH_CCR); in cache_init()
/linux-4.1.27/drivers/infiniband/hw/qib/
Dqib_pio_copy.c55 __raw_writel(*(const u32 *)src, dst); in qib_pio_copy()
62 __raw_writel(*src++, dst++); in qib_pio_copy()
/linux-4.1.27/arch/arm/mach-ep93xx/include/mach/
Duncompress.h29 static void __raw_writel(unsigned int value, unsigned int ptr) in __raw_writel() function
71 __raw_writel(v | ETH_SELF_CTL_RESET, PHYS_ETH_SELF_CTL); in ethernet_reset()
/linux-4.1.27/arch/mips/mti-malta/
Dmalta-display.c33 __raw_writel(*str++, display + i); in mips_display_message()
35 __raw_writel(' ', display + i); in mips_display_message()
/linux-4.1.27/arch/sh/boards/mach-dreamcast/
Drtc.c63 __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); in aica_rtc_settimeofday()
64 __raw_writel((adj & 0xffff), AICA_RTC_SECS_L); in aica_rtc_settimeofday()
/linux-4.1.27/arch/sh/boot/romimage/
Dmmcif-sh7724.c36 __raw_writel(__raw_readl(MSTPCR2) & ~0x20000000, MSTPCR2); in mmcif_loader()
69 __raw_writel(__raw_readl(MSTPCR2) | 0x20000000, MSTPCR2); in mmcif_loader()
/linux-4.1.27/include/linux/mlx4/
Ddoorbell.h79 __raw_writel((__force u32) val[0], dest); in mlx4_write64()
80 __raw_writel((__force u32) val[1], dest + 4); in mlx4_write64()
/linux-4.1.27/include/linux/mlx5/
Ddoorbell.h72 __raw_writel((__force u32) val[0], dest); in mlx5_write64()
73 __raw_writel((__force u32) val[1], dest + 4); in mlx5_write64()
/linux-4.1.27/arch/sparc/lib/
DPeeCeeI.c45 __raw_writel(*(u32 *)src, addr); in outsl()
54 __raw_writel(l, addr); in outsl()
66 __raw_writel(l, addr); in outsl()
78 __raw_writel(l, addr); in outsl()
/linux-4.1.27/arch/arm/mach-prima2/
Dplatsmp.c68 __raw_writel(virt_to_phys(sirfsoc_secondary_startup), in sirfsoc_boot_secondary()
72 __raw_writel(0x3CAF5D62, in sirfsoc_boot_secondary()
/linux-4.1.27/arch/sh/include/mach-common/mach/
Dmagicpanelr2.h24 #define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
27 #define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
/linux-4.1.27/arch/sparc/include/asm/
Dio_64.h83 #define __raw_writel __raw_writel macro
84 static inline void __raw_writel(u32 l, const volatile void __iomem *addr) in __raw_writel() function
314 __raw_writel(l, addr); in sbus_writel()
419 #define iowrite32be __raw_writel

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