101 		__raw_writel(0xff, regs + ATMEL_TC_REG(2, IDR));  in tc_mode()
102 		__raw_writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));  in tc_mode()
115 		__raw_writel(timer_clock  in tc_mode()
118 		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_mode()
121 		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_mode()
124 		__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,  in tc_mode()
132 		__raw_writel(timer_clock | ATMEL_TC_CPCSTOP  in tc_mode()
135 		__raw_writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));  in tc_mode()
147 	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));  in tc_next_event()
150 	__raw_writel(ATMEL_TC_CLKEN | ATMEL_TC_SWTRG,  in tc_next_event()
224 	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */  in tcb_setup_dual_chan()
230 	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));  in tcb_setup_dual_chan()
231 	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));  in tcb_setup_dual_chan()
232 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_dual_chan()
233 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_dual_chan()
236 	__raw_writel(ATMEL_TC_XC1			/* input: TIOA0 */  in tcb_setup_dual_chan()
240 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */  in tcb_setup_dual_chan()
241 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));  in tcb_setup_dual_chan()
244 	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);  in tcb_setup_dual_chan()
246 	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_dual_chan()
252 	__raw_writel(mck_divisor_idx			/* likely divide-by-8 */  in tcb_setup_single_chan()
256 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_single_chan()
257 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_single_chan()
260 	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_single_chan()