63 	__raw_writel(TCR_BASE, &tmrptr->tcr);  in txx9_clocksource_init()
64 	__raw_writel(0, &tmrptr->tisr);  in txx9_clocksource_init()
65 	__raw_writel(TIMER_CCD, &tmrptr->ccdr);  in txx9_clocksource_init()
66 	__raw_writel(TXx9_TMITMR_TZCE, &tmrptr->itmr);  in txx9_clocksource_init()
67 	__raw_writel(1 << TXX9_CLOCKSOURCE_BITS, &tmrptr->cpra);  in txx9_clocksource_init()
68 	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9_clocksource_init()
83 	__raw_writel(TCR_BASE, &tmrptr->tcr);  in txx9tmr_stop_and_clear()
85 	__raw_writel(0, &tmrptr->tisr);  in txx9tmr_stop_and_clear()
98 		__raw_writel(TXx9_TMITMR_TIIE | TXx9_TMITMR_TZCE,  in txx9tmr_set_mode()
101 		__raw_writel(((u64)(NSEC_PER_SEC / HZ) * evt->mult) >>  in txx9tmr_set_mode()
104 		__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9tmr_set_mode()
108 		__raw_writel(0, &tmrptr->itmr);  in txx9tmr_set_mode()
111 		__raw_writel(TXx9_TMITMR_TIIE, &tmrptr->itmr);  in txx9tmr_set_mode()
114 		__raw_writel(TIMER_CCD, &tmrptr->ccdr);  in txx9tmr_set_mode()
115 		__raw_writel(0, &tmrptr->itmr);  in txx9tmr_set_mode()
129 	__raw_writel(delta, &tmrptr->cpra);  in txx9tmr_set_next_event()
130 	__raw_writel(TCR_BASE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9tmr_set_next_event()
151 	__raw_writel(0, &tmrptr->tisr); /* ack interrupt */  in txx9tmr_interrupt()
171 	__raw_writel(TIMER_CCD, &tmrptr->ccdr);  in txx9_clockevent_init()
172 	__raw_writel(0, &tmrptr->itmr);  in txx9_clockevent_init()
193 	__raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr);  in txx9_tmr_init()
195 	__raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr);  in txx9_tmr_init()
196 	__raw_writel(0, &tmrptr->tisr);  in txx9_tmr_init()
197 	__raw_writel(0xffffffff, &tmrptr->cpra);  in txx9_tmr_init()
198 	__raw_writel(0, &tmrptr->itmr);  in txx9_tmr_init()
199 	__raw_writel(0, &tmrptr->ccdr);  in txx9_tmr_init()
200 	__raw_writel(0, &tmrptr->pgmr);  in txx9_tmr_init()