323 	__raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);  in ixp_rx_timestamp()
369 	__raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].ch_event);  in ixp_tx_timestamp()
397 		__raw_writel(0, &regs->channel[ch].ch_control);  in hwtstamp_set()
401 		__raw_writel(MASTER_MODE, &regs->channel[ch].ch_control);  in hwtstamp_set()
410 	__raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,  in hwtstamp_set()
453 		__raw_writel(cmd & 0xFF, &mdio_regs->mdio_command[0]);  in ixp4xx_mdio_cmd()
454 		__raw_writel(cmd >> 8, &mdio_regs->mdio_command[1]);  in ixp4xx_mdio_cmd()
456 	__raw_writel(((phy_id << 5) | location) & 0xFF,  in ixp4xx_mdio_cmd()
458 	__raw_writel((phy_id >> 3) | (write << 2) | 0x80 /* GO */,  in ixp4xx_mdio_cmd()
543 	__raw_writel(DEFAULT_CORE_CNTRL, &mdio_regs->core_control);  in ixp4xx_mdio_register()
582 		__raw_writel(DEFAULT_TX_CNTRL0 & ~TX_CNTRL0_HALFDUPLEX,  in ixp4xx_adjust_link()
585 		__raw_writel(DEFAULT_TX_CNTRL0 | TX_CNTRL0_HALFDUPLEX,  in ixp4xx_adjust_link()
943 			__raw_writel(allmulti[i], &port->regs->mcast_addr[i]);  in eth_set_mcast_list()
944 			__raw_writel(allmulti[i], &port->regs->mcast_mask[i]);  in eth_set_mcast_list()
946 		__raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,  in eth_set_mcast_list()
952 		__raw_writel(DEFAULT_RX_CNTRL0 & ~RX_CNTRL0_ADDR_FLTR_EN,  in eth_set_mcast_list()
968 		__raw_writel(addr[i], &port->regs->mcast_addr[i]);  in eth_set_mcast_list()
969 		__raw_writel(~diffs[i], &port->regs->mcast_mask[i]);  in eth_set_mcast_list()
972 	__raw_writel(DEFAULT_RX_CNTRL0 | RX_CNTRL0_ADDR_FLTR_EN,  in eth_set_mcast_list()
1265 		__raw_writel(dev->dev_addr[i], &port->regs->hw_addr[i]);  in eth_open()
1266 	__raw_writel(0x08, &port->regs->random_seed);  in eth_open()
1267 	__raw_writel(0x12, &port->regs->partial_empty_threshold);  in eth_open()
1268 	__raw_writel(0x30, &port->regs->partial_full_threshold);  in eth_open()
1269 	__raw_writel(0x08, &port->regs->tx_start_bytes);  in eth_open()
1270 	__raw_writel(0x15, &port->regs->tx_deferral);  in eth_open()
1271 	__raw_writel(0x08, &port->regs->tx_2part_deferral[0]);  in eth_open()
1272 	__raw_writel(0x07, &port->regs->tx_2part_deferral[1]);  in eth_open()
1273 	__raw_writel(0x80, &port->regs->slot_time);  in eth_open()
1274 	__raw_writel(0x01, &port->regs->int_clock_threshold);  in eth_open()
1285 	__raw_writel(TX_CNTRL1_RETRIES, &port->regs->tx_control[1]);  in eth_open()
1286 	__raw_writel(DEFAULT_TX_CNTRL0, &port->regs->tx_control[0]);  in eth_open()
1287 	__raw_writel(0, &port->regs->rx_control[1]);  in eth_open()
1288 	__raw_writel(DEFAULT_RX_CNTRL0, &port->regs->rx_control[0]);  in eth_open()
1461 	__raw_writel(DEFAULT_CORE_CNTRL | CORE_RESET,  in eth_init_one()
1464 	__raw_writel(DEFAULT_CORE_CNTRL, &port->regs->core_control);  in eth_init_one()