127 		__raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR);  in ar71xx_pci_check_error()
141 		__raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR);  in ar71xx_pci_check_error()
158 	__raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE);  in ar71xx_pci_local_write()
159 	__raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA);  in ar71xx_pci_local_write()
172 	__raw_writel(addr, base + AR71XX_PCI_REG_CFG_AD);  in ar71xx_pci_set_cfgaddr()
173 	__raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),  in ar71xx_pci_set_cfgaddr()
219 		__raw_writel(value, base + AR71XX_PCI_REG_CFG_WRDATA);  in ar71xx_pci_write_config()
267 	__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);  in ar71xx_pci_irq_unmask()
284 	__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);  in ar71xx_pci_irq_mask()
302 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);  in ar71xx_pci_irq_init()
303 	__raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);  in ar71xx_pci_irq_init()
329 	__raw_writel(AR71XX_PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);  in ar71xx_pci_reset()
330 	__raw_writel(AR71XX_PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);  in ar71xx_pci_reset()
331 	__raw_writel(AR71XX_PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);  in ar71xx_pci_reset()
332 	__raw_writel(AR71XX_PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);  in ar71xx_pci_reset()
333 	__raw_writel(AR71XX_PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);  in ar71xx_pci_reset()
334 	__raw_writel(AR71XX_PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);  in ar71xx_pci_reset()
335 	__raw_writel(AR71XX_PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);  in ar71xx_pci_reset()
336 	__raw_writel(AR71XX_PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);  in ar71xx_pci_reset()