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Searched refs:L1 (Results 1 – 117 of 117) sorted by relevance

/linux-4.1.27/arch/c6x/lib/
Dcsum_64plus.S54 || ADD .L1 A16,A9,A9
67 || MVK .L1 1,A2
77 ADD .L1 A16,A9,A9
80 || ADD .L1 A8,A9,A9
87 ZERO .L1 A7
119 || ZERO .L1 A7
207 || ADD .L1 A3,A5,A5
297 MV .L1 A0,A3
314 MVK .L1 2,A0
315 AND .L1 A4,A0,A0
[all …]
Dmemcpy_64plus.S16 AND .L1 0x1,A6,A0
/linux-4.1.27/scripts/rt-tester/
Dt4-l2-pi-deboost.tst63 # T1 lock L1
72 # T0 lock L1
77 # T1 unlock L1
87 # T2 lock L1 (T0 is boosted and pending owner !)
104 # Unlock L1 and let T2 get L1
Dt2-l2-2rt-deadlock.tst61 # T1 lock L1
65 # T0 lock L1
Dt5-l4-pi-boost-deboost.tst64 # T1 lock L1
77 # T2 lock L1
Dt5-l4-pi-boost-deboost-setsched.tst64 # T1 lock L1
77 # T2 lock L1
/linux-4.1.27/arch/arm/mm/
Dproc-xsc3.S71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
272 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
Dproc-macros.S257 mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
Dproc-v7.S78 ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
DKconfig242 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
980 Setting ARM L1 cache line size to 64 Bytes.
/linux-4.1.27/arch/blackfin/
DKconfig750 bool "Locate interrupt entry code in L1 Memory"
755 into L1 instruction memory. (less latency)
758 …bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memor…
763 (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
767 bool "Locate frequently called do_irq dispatcher function in L1 Memory"
772 into L1 instruction memory. (less latency)
775 bool "Locate frequently called timer_interrupt() function in L1 Memory"
780 into L1 instruction memory. (less latency)
783 bool "Locate frequently idle function in L1 Memory"
788 into L1 instruction memory. (less latency)
[all …]
/linux-4.1.27/arch/hexagon/lib/
Dmemset.S172 if (r2==#0) jump:nt .L1
199 if (p1) jump .L1
210 if (p0.new) jump:nt .L1
221 if (p0.new) jump:nt .L1
297 .L1: label
/linux-4.1.27/arch/c6x/kernel/
Dhead.S61 CMPEQ .L1 A10,A0,A0
84 L1: BNOP .S2 L1,5 label
/linux-4.1.27/drivers/pci/pcie/
DKconfig37 state L0/L0s/L1.
70 Enable PCI Express ASPM L0s and L1 where possible, even if the
77 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
/linux-4.1.27/drivers/net/ethernet/adi/
DKconfig36 bool "Use L1 memory for rx/tx packets"
40 To get maximum network performance, you should use L1 memory as rx/tx
41 buffers. Say N here if you want to reserve L1 memory for other uses.
/linux-4.1.27/arch/powerpc/boot/dts/
Dsbc8548-pre.dtsi38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
Dgef_sbc610.dts46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
Damigaone.dts31 d-cache-size = <32768>; // L1, 32K
32 i-cache-size = <32768>; // L1, 32K
Dgef_ppc9a.dts46 d-cache-size = <32768>; // L1, 32K
47 i-cache-size = <32768>; // L1, 32K
57 d-cache-size = <32768>; // L1, 32K
58 i-cache-size = <32768>; // L1, 32K
Dgef_sbc310.dts47 d-cache-size = <32768>; // L1, 32K
48 i-cache-size = <32768>; // L1, 32K
58 d-cache-size = <32768>; // L1, 32K
59 i-cache-size = <32768>; // L1, 32K
Dmpc866ads.dts30 d-cache-size = <0x2000>; // L1, 8K
31 i-cache-size = <0x4000>; // L1, 16K
Dtqm8xx.dts37 d-cache-size = <0x1000>; // L1, 4K
38 i-cache-size = <0x1000>; // L1, 4K
Dtqm5200.dts31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
Dcharon.dts34 d-cache-size = <0x4000>; // L1, 16K
35 i-cache-size = <0x4000>; // L1, 16K
Dmpc7448hpc2.dts40 d-cache-size = <0x8000>; // L1, 32K bytes
41 i-cache-size = <0x8000>; // L1, 32K bytes
Dmpc8641_hpcn_36b.dts40 d-cache-size = <32768>; // L1, 32K
41 i-cache-size = <32768>; // L1, 32K
51 d-cache-size = <32768>; // L1, 32K
52 i-cache-size = <32768>; // L1, 32K
Dlite5200.dts31 d-cache-size = <0x4000>; // L1, 16K
32 i-cache-size = <0x4000>; // L1, 16K
Dxpedite5370.dts37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
50 d-cache-size = <0x8000>; // L1, 32K
51 i-cache-size = <0x8000>; // L1, 32K
Dxpedite5301.dts39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
52 d-cache-size = <0x8000>; // L1, 32K
53 i-cache-size = <0x8000>; // L1, 32K
Dmpc5125twr.dts41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
Dxpedite5330.dts75 d-cache-size = <0x8000>; // L1, 32K
76 i-cache-size = <0x8000>; // L1, 32K
88 d-cache-size = <0x8000>; // L1, 32K
89 i-cache-size = <0x8000>; // L1, 32K
Dxcalibur1501.dts38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
51 d-cache-size = <0x8000>; // L1, 32K
52 i-cache-size = <0x8000>; // L1, 32K
Dsocrates.dts38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
Dksi8560.dts38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
Dmpc832x_rdb.dts37 d-cache-size = <16384>; // L1, 16K
38 i-cache-size = <16384>; // L1, 16K
Dmpc5200b.dtsi32 d-cache-size = <0x4000>; // L1, 16K
33 i-cache-size = <0x4000>; // L1, 16K
Dsbc8641d.dts44 d-cache-size = <32768>; // L1
45 i-cache-size = <32768>; // L1
Dxpedite5200.dts40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Dmpc8540ads.dts40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Dmpc8555cds.dts40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Dstxssa8555.dts39 d-cache-size = <0x8000>; // L1, 32K
40 i-cache-size = <0x8000>; // L1, 32K
Dmpc8541cds.dts40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
Dmpc8610_hpcd.dts36 d-cache-size = <32768>; // L1
37 i-cache-size = <32768>; // L1
Dmpc8560ads.dts41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
Dxpedite5200_xmon.dts44 d-cache-size = <0x8000>; // L1, 32K
45 i-cache-size = <0x8000>; // L1, 32K
Dtqm8548-bigflash.dts42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
Dmpc832x_mds.dts49 d-cache-size = <16384>; // L1, 16K
50 i-cache-size = <16384>; // L1, 16K
Dmpc836x_mds.dts42 d-cache-size = <32768>; // L1, 32K
43 i-cache-size = <32768>; // L1, 32K
Dtqm8548.dts42 d-cache-size = <0x8000>; // L1, 32K
43 i-cache-size = <0x8000>; // L1, 32K
Dkmeter1.dts40 d-cache-size = <32768>; // L1, 32K
41 i-cache-size = <32768>; // L1, 32K
Dmpc5121.dtsi37 d-cache-size = <0x8000>; /* L1, 32K */
38 i-cache-size = <0x8000>; /* L1, 32K */
Dmpc8641_hpcn.dts40 d-cache-size = <32768>; // L1
41 i-cache-size = <32768>; // L1
/linux-4.1.27/arch/m68k/fpsp040/
Dsetox.S104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
[all …]
/linux-4.1.27/tools/perf/util/
Dparse-events.l210 L1-dcache|l1-d|l1d|L1-data |
211 L1-icache|l1-i|l1i|L1-instruction |
/linux-4.1.27/arch/m68k/lib/
Ddivsi3.S93 jpl L1
100 L1: movel sp@(8), d0 /* d0 = dividend */ label
Dudivsi3.S144 L1: addl d0,d0 | shift reg pair (p,a) one bit left label
152 jcc L1
/linux-4.1.27/Documentation/devicetree/bindings/media/
Dst-rc.txt10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
13 - tx-mode: should be "infrared". This property specifies the L1
/linux-4.1.27/arch/alpha/boot/
Dmain.c59 #define L1 ((unsigned long *) 0x200802000) macro
71 pcb_va->ptbr = L1[1] >> 32; in pal_init()
Dbootp.c65 #define L1 ((unsigned long *) 0x200802000) macro
77 pcb_va->ptbr = L1[1] >> 32; in pal_init()
Dbootpz.c113 #define L1 ((unsigned long *) 0x200802000) macro
125 pcb_va->ptbr = L1[1] >> 32; in pal_init()
/linux-4.1.27/Documentation/zh_CN/arm64/
Dmemory.txt90 | | +---------------------> [38:30] L1 索引
105 | +-------------------------------> [47:42] L1 索引
/linux-4.1.27/arch/arm/mach-omap2/
Dsram243x.S53 str r3, [r2] @ go to L1-freq operation
56 mov r9, #0x1 @ set up for L1 voltage call
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ Force transition to L1
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ Force transition to L1
Dsram242x.S53 str r3, [r2] @ go to L1-freq operation
56 mov r9, #0x1 @ set up for L1 voltage call
115 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
119 str r5, [r4] @ Force transition to L1
210 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
214 str r8, [r10] @ Force transition to L1
Dsleep44xx.S75 mov r1, #0xFF @ clean seucre L1
/linux-4.1.27/arch/metag/tbx/
Dtbidspram.S43 $L1:
50 BR $L1
/linux-4.1.27/arch/blackfin/kernel/cplb-nompu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.1.27/arch/blackfin/kernel/cplb-mpu/
DMakefile8 -ffixed-L0 -ffixed-L1 -ffixed-L2 -ffixed-L3 \
/linux-4.1.27/arch/arc/kernel/
Dentry.S200 ; if L2 IRQ interrupted a L1 ISR, disable preemption
204 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
654 ; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
681 ; if L2 IRQ interrupted an L1 ISR, we'd disabled preemption earlier
682 ; so that sched doesn't move to new task, causing L1 to be delayed
688 bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
/linux-4.1.27/Documentation/arm64/
Dmemory.txt70 | | +---------------------> [38:30] L1 index
85 | +-------------------------------> [47:42] L1 index
/linux-4.1.27/drivers/net/ethernet/atheros/
DKconfig33 tristate "Atheros/Attansic L1 Gigabit Ethernet support"
38 This driver supports the Atheros/Attansic L1 gigabit ethernet
/linux-4.1.27/arch/blackfin/mach-common/
Darch_checks.c65 # error You need IFLUSH in L1 inst while Anomaly 05000491 applies
Dhead.S57 L1 = r6; define
/linux-4.1.27/drivers/cpufreq/
Ds5pv210-cpufreq.c111 L0, L1, L2, L3, L4, enumerator
127 {0, L1, 800*1000},
150 [L1] = {
Dexynos-cpufreq.h13 L0, L1, L2, L3, L4, enumerator
Dexynos4210-cpufreq.c36 {0, L1, 1000 * 1000},
Dexynos5250-cpufreq.c39 {0, L1, 1600 * 1000},
Dexynos4x12-cpufreq.c37 {0, L1, 1400 * 1000},
Dexynos5440-cpufreq.c93 L0, L1, L2, L3, L4, enumerator
/linux-4.1.27/Documentation/virtual/kvm/
Dnested-vmx.txt30 L0, the guest hypervisor, which we call L1, and its nested guest, which we
71 As a VMX implementation, nested VMX presents a VMCS structure to L1.
79 The name "vmcs12" refers to the VMCS that L1 builds for L2. In the code we
80 also have "vmcs01", the VMCS that L0 built for L1, and "vmcs02" is the VMCS
/linux-4.1.27/Documentation/ABI/testing/
Dsysfs-bus-usb161 L1 sleep state. The usb2_lpm_l1_timeout attribute allows
162 tuning the timeout for L1 inactivity timer (LPM timer), e.g.
163 needed inactivity time before host requests the device to go to L1 sleep.
172 L1 sleep state now use a best effort service latency value (BESL) to
/linux-4.1.27/Documentation/locking/
Drt-mutex-design.txt46 grab lock L1 (owned by C)
129 Mutexes: L1, L2, L3, L4
131 A owns: L1
132 B blocked on L1
142 E->L4->D->L3->C->L2->B->L1->A
149 F->L5->B->L1->A
158 +->B->L1->A
170 G->L2->B->L1->A
178 G-+ +->B->L1->A
239 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
[all …]
Dlockdep-design.txt86 <L1> -> <L2>
87 <L2> -> <L1>
/linux-4.1.27/arch/m68k/68360/
Dhead-rom.S235 L1: label
238 bhi L1
Dhead-ram.S225 L1: label
228 bhi L1
/linux-4.1.27/Documentation/
Dpercpu-rw-semaphore.txt9 is bouncing between L1 caches of the cores, causing performance
Dcrc32.txt127 more importantly, too much of the L1 cache.
167 be kept busy and make full use of its L1 cache.
Drobust-futexes.txt67 destroying the CPU's L1 and L2 caches!
Dedac.txt59 Some architectures have ECC detectors for L1, L2 and L3 caches, along with DMA
/linux-4.1.27/arch/alpha/lib/
Dev6-memset.S160 wh64 ($4) # L1 : memory subsystem write hint
337 wh64 ($4) # L1 : memory subsystem write hint
524 wh64 ($4) # L1 : memory subsystem write hint
Dev6-clear_user.S151 wh64 ($3) # .. .. .. L1 : memory subsystem hint
Dev6-memcpy.S84 wh64 ($7) # L1 : memory subsystem hint: 64 bytes at
/linux-4.1.27/arch/metag/lib/
Ddiv64.S11 $L1:
/linux-4.1.27/arch/blackfin/mach-bf561/
Dsecondary.S48 L1 = r6; define
/linux-4.1.27/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm7038-l1-intc.txt11 - Most onchip peripherals are wired directly to an L1 input
/linux-4.1.27/arch/sh/lib64/
Dmemcpy.S57 movi (L1-L0+63*32 + 1) & 0xffff,r1
75 L1: /* 0 byte memcpy */ label
Dcopy_user_memcpy.S72 movi (L1-L0+63*32 + 1) & 0xffff,r1
90 L1: /* 0 byte memcpy */ label
/linux-4.1.27/Documentation/devicetree/bindings/sound/
Dnvidia,tegra-audio-rt5677.txt48 "DMIC L1", "Internal Mic 1",
/linux-4.1.27/Documentation/networking/
Doperstates.txt53 Interface is unable to transfer data on L1, f.e. ethernet is not
61 Interface is L1 up, but waiting for an external event, f.e. for a
Dpktgen.txt36 than the CPU's L1/L2 cache, 2) because it allows more queueing in the
Ddecnet.txt74 set with a single digit, 0=EndNode, 1=L1 Router and 2=L2 Router.
Dscaling.txt56 share a particular memory level (L1, L2, NUMA node, etc.).
/linux-4.1.27/arch/mips/cavium-octeon/
DKconfig14 int "Number of L1 cache lines reserved for CVMSEG memory"
/linux-4.1.27/arch/x86/kernel/cpu/
Dperf_event_intel_ds.c56 OP_LH | P(LVL, L1) | P(SNOOP, NONE), /* 0x01: L1 local */
76 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2); in precise_store_data()
169 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2); in load_latency_data()
/linux-4.1.27/Documentation/devicetree/bindings/arm/
Dl2cc.txt23 maintenance operations on L1 are broadcasted to the L2 and L2
/linux-4.1.27/Documentation/devicetree/bindings/powerpc/fsl/
Dmpc5200.txt180 of three cells; <L1 L2 level>
182 L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
/linux-4.1.27/arch/blackfin/mach-bf609/
DKconfig21 bool "Enable L1 parity check"
24 Enable the L1 parity check in L1 sram. A fault event is raised
25 when L1 parity error is found.
/linux-4.1.27/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt44 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
/linux-4.1.27/tools/perf/Documentation/
Dperf-list.txt117 . 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
/linux-4.1.27/Documentation/devicetree/
Dbooting-without-of.txt893 - d-cache-block-size : one cell, L1 data cache block size in bytes (*)
894 - i-cache-block-size : one cell, L1 instruction cache block size in
896 - d-cache-size : one cell, size of L1 data cache in bytes
897 - i-cache-size : one cell, size of L1 instruction cache in bytes
918 - d-cache-line-size : one cell, L1 data cache line size in bytes
920 - i-cache-line-size : one cell, L1 instruction cache line size in
/linux-4.1.27/arch/m68k/ifpsp060/src/
Dfplsp.S6758 # 3.1 R := X + N*L1, #
6759 # where L1 := single-precision(-log2/64). #
6761 # L2 := extended-precision(-log2/64 - L1).#
6762 # Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
6764 # b) N*L1 is exact because N is no longer than 22 bits #
6765 # and L1 is no longer than 24 bits. #
6766 # c) The calculation X+N*L1 is also exact due to #
6767 # cancellation. Thus, R is practically X+N(L1+L2) to full #
7145 fmul.s &0xBC317218,%fp0 # N * L1, L1 = lead(-log2/64)
7146 fmul.x L2(%pc),%fp2 # N * L2, L1+L2 = -log2/64
[all …]
Dfpsp.S7010 # 3.1 R := X + N*L1, #
7011 # where L1 := single-precision(-log2/64). #
7013 # L2 := extended-precision(-log2/64 - L1).#
8959 # r := ((X - N*L1)-N*L2) * L10 #
8960 # where L1, L2 are the leading and trailing parts of #
/linux-4.1.27/Documentation/usb/
Dpower-management.txt521 lower power state(L1 for usb2.0 devices, or U1/U2 for usb3.0 devices),
534 enters L1 state and resume successfully and the host
/linux-4.1.27/Documentation/crypto/
Ddescore-readme.txt147 movement (in particular, his use of L1, R1, L2, R2), and it was full of
/linux-4.1.27/arch/powerpc/
DKconfig901 available and even more limited number that will fit in the L1 MMU.
/linux-4.1.27/drivers/platform/x86/
DKconfig640 If you have a legacy free Toshiba laptop (such as the Libretto L1
/linux-4.1.27/drivers/tty/serial/
DKconfig894 bool "SGI Altix L1 serial console support"
/linux-4.1.27/arch/arm/
DKconfig1063 the L1 caching of the NEON accesses and disables the PLD instruction