1/* 2 * base MPC5200b Device Tree Source 3 * 4 * Copyright (C) 2010 SecretLab 5 * Grant Likely <grant@secretlab.ca> 6 * John Bonesio <bones@secretlab.ca> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 */ 13 14/dts-v1/; 15 16/ { 17 model = "fsl,mpc5200b"; 18 compatible = "fsl,mpc5200b"; 19 #address-cells = <1>; 20 #size-cells = <1>; 21 interrupt-parent = <&mpc5200_pic>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 powerpc: PowerPC,5200@0 { 28 device_type = "cpu"; 29 reg = <0>; 30 d-cache-line-size = <32>; 31 i-cache-line-size = <32>; 32 d-cache-size = <0x4000>; // L1, 16K 33 i-cache-size = <0x4000>; // L1, 16K 34 timebase-frequency = <0>; // from bootloader 35 bus-frequency = <0>; // from bootloader 36 clock-frequency = <0>; // from bootloader 37 }; 38 }; 39 40 memory: memory { 41 device_type = "memory"; 42 reg = <0x00000000 0x04000000>; // 64MB 43 }; 44 45 soc: soc5200@f0000000 { 46 #address-cells = <1>; 47 #size-cells = <1>; 48 compatible = "fsl,mpc5200b-immr"; 49 ranges = <0 0xf0000000 0x0000c000>; 50 reg = <0xf0000000 0x00000100>; 51 bus-frequency = <0>; // from bootloader 52 system-frequency = <0>; // from bootloader 53 54 cdm@200 { 55 compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm"; 56 reg = <0x200 0x38>; 57 }; 58 59 mpc5200_pic: interrupt-controller@500 { 60 // 5200 interrupts are encoded into two levels; 61 interrupt-controller; 62 #interrupt-cells = <3>; 63 compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic"; 64 reg = <0x500 0x80>; 65 }; 66 67 gpt0: timer@600 { // General Purpose Timer 68 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 69 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 70 reg = <0x600 0x10>; 71 interrupts = <1 9 0>; 72 // add 'fsl,has-wdt' to enable watchdog 73 }; 74 75 gpt1: timer@610 { // General Purpose Timer 76 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 77 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 78 reg = <0x610 0x10>; 79 interrupts = <1 10 0>; 80 }; 81 82 gpt2: timer@620 { // General Purpose Timer 83 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 84 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 85 reg = <0x620 0x10>; 86 interrupts = <1 11 0>; 87 }; 88 89 gpt3: timer@630 { // General Purpose Timer 90 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 91 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 92 reg = <0x630 0x10>; 93 interrupts = <1 12 0>; 94 }; 95 96 gpt4: timer@640 { // General Purpose Timer 97 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 98 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 99 reg = <0x640 0x10>; 100 interrupts = <1 13 0>; 101 }; 102 103 gpt5: timer@650 { // General Purpose Timer 104 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 105 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 106 reg = <0x650 0x10>; 107 interrupts = <1 14 0>; 108 }; 109 110 gpt6: timer@660 { // General Purpose Timer 111 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 112 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 113 reg = <0x660 0x10>; 114 interrupts = <1 15 0>; 115 }; 116 117 gpt7: timer@670 { // General Purpose Timer 118 compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt"; 119 #gpio-cells = <2>; // Add 'gpio-controller;' to enable gpio mode 120 reg = <0x670 0x10>; 121 interrupts = <1 16 0>; 122 }; 123 124 rtc@800 { // Real time clock 125 compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc"; 126 reg = <0x800 0x100>; 127 interrupts = <1 5 0 1 6 0>; 128 }; 129 130 can@900 { 131 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 132 interrupts = <2 17 0>; 133 reg = <0x900 0x80>; 134 }; 135 136 can@980 { 137 compatible = "fsl,mpc5200b-mscan","fsl,mpc5200-mscan"; 138 interrupts = <2 18 0>; 139 reg = <0x980 0x80>; 140 }; 141 142 gpio_simple: gpio@b00 { 143 compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio"; 144 reg = <0xb00 0x40>; 145 interrupts = <1 7 0>; 146 gpio-controller; 147 #gpio-cells = <2>; 148 }; 149 150 gpio_wkup: gpio@c00 { 151 compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup"; 152 reg = <0xc00 0x40>; 153 interrupts = <1 8 0 0 3 0>; 154 gpio-controller; 155 #gpio-cells = <2>; 156 }; 157 158 spi@f00 { 159 #address-cells = <1>; 160 #size-cells = <0>; 161 compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; 162 reg = <0xf00 0x20>; 163 interrupts = <2 13 0 2 14 0>; 164 }; 165 166 usb: usb@1000 { 167 compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be"; 168 reg = <0x1000 0xff>; 169 interrupts = <2 6 0>; 170 }; 171 172 dma-controller@1200 { 173 compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm"; 174 reg = <0x1200 0x80>; 175 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0 176 3 4 0 3 5 0 3 6 0 3 7 0 177 3 8 0 3 9 0 3 10 0 3 11 0 178 3 12 0 3 13 0 3 14 0 3 15 0>; 179 }; 180 181 xlb@1f00 { 182 compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb"; 183 reg = <0x1f00 0x100>; 184 }; 185 186 psc1: psc@2000 { // PSC1 187 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; 188 reg = <0x2000 0x100>; 189 interrupts = <2 1 0>; 190 }; 191 192 psc2: psc@2200 { // PSC2 193 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; 194 reg = <0x2200 0x100>; 195 interrupts = <2 2 0>; 196 }; 197 198 psc3: psc@2400 { // PSC3 199 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; 200 reg = <0x2400 0x100>; 201 interrupts = <2 3 0>; 202 }; 203 204 psc4: psc@2600 { // PSC4 205 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; 206 reg = <0x2600 0x100>; 207 interrupts = <2 11 0>; 208 }; 209 210 psc5: psc@2800 { // PSC5 211 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; 212 reg = <0x2800 0x100>; 213 interrupts = <2 12 0>; 214 }; 215 216 psc6: psc@2c00 { // PSC6 217 compatible = "fsl,mpc5200b-psc","fsl,mpc5200-psc"; 218 reg = <0x2c00 0x100>; 219 interrupts = <2 4 0>; 220 }; 221 222 eth0: ethernet@3000 { 223 compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec"; 224 reg = <0x3000 0x400>; 225 local-mac-address = [ 00 00 00 00 00 00 ]; 226 interrupts = <2 5 0>; 227 }; 228 229 mdio@3000 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "fsl,mpc5200b-mdio","fsl,mpc5200-mdio"; 233 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts 234 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co. 235 }; 236 237 ata@3a00 { 238 compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata"; 239 reg = <0x3a00 0x100>; 240 interrupts = <2 7 0>; 241 }; 242 243 sclpc@3c00 { 244 compatible = "fsl,mpc5200-lpbfifo"; 245 reg = <0x3c00 0x60>; 246 interrupts = <2 23 0>; 247 }; 248 249 i2c@3d00 { 250 #address-cells = <1>; 251 #size-cells = <0>; 252 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 253 reg = <0x3d00 0x40>; 254 interrupts = <2 15 0>; 255 }; 256 257 i2c@3d40 { 258 #address-cells = <1>; 259 #size-cells = <0>; 260 compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 261 reg = <0x3d40 0x40>; 262 interrupts = <2 16 0>; 263 }; 264 265 sram@8000 { 266 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; 267 reg = <0x8000 0x4000>; 268 }; 269 }; 270 271 pci: pci@f0000d00 { 272 #interrupt-cells = <1>; 273 #size-cells = <2>; 274 #address-cells = <3>; 275 device_type = "pci"; 276 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci"; 277 reg = <0xf0000d00 0x100>; 278 // interrupt-map-mask = need to add 279 // interrupt-map = need to add 280 clock-frequency = <0>; // From boot loader 281 interrupts = <2 8 0 2 9 0 2 10 0>; 282 bus-range = <0 0>; 283 // ranges = need to add 284 }; 285 286 localbus: localbus { 287 compatible = "fsl,mpc5200b-lpb","fsl,mpc5200-lpb","simple-bus"; 288 #address-cells = <2>; 289 #size-cells = <1>; 290 ranges = <0 0 0xfc000000 0x2000000>; 291 }; 292}; 293