| /linux-4.4.14/drivers/clk/zte/ |
| H A D | Makefile | 1 obj-y := clk.o
2 obj-$(CONFIG_SOC_ZX296702) += clk-zx296702.o
|
| H A D | clk-zx296702.c | 10 #include <linux/clk-provider.h>
13 #include "clk.h"
21 static struct clk *topclk[ZX296702_TOPCLK_END];
22 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
23 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
199 static inline struct clk *zx_divtbl(const char *name, const char *parent, zx_divtbl()
207 static inline struct clk *zx_div(const char *name, const char *parent, zx_div()
214 static inline struct clk *zx_mux(const char *name, const char * const *parents, zx_mux()
221 static inline struct clk *zx_gate(const char *name, const char *parent, zx_gate()
230 struct clk **clk = topclk; zx296702_top_clocks_init() local
236 clk[ZX296702_OSC] = zx296702_top_clocks_init()
239 clk[ZX296702_PLL_A9] = zx296702_top_clocks_init()
245 clk[ZX296702_PLL_A9_350M] = zx296702_top_clocks_init()
248 clk[ZX296702_PLL_MAC_1000M] = zx296702_top_clocks_init()
251 clk[ZX296702_PLL_MAC_333M] = zx296702_top_clocks_init()
254 clk[ZX296702_PLL_MM0_1188M] = zx296702_top_clocks_init()
257 clk[ZX296702_PLL_MM0_396M] = zx296702_top_clocks_init()
260 clk[ZX296702_PLL_MM0_198M] = zx296702_top_clocks_init()
263 clk[ZX296702_PLL_MM1_108M] = zx296702_top_clocks_init()
266 clk[ZX296702_PLL_MM1_72M] = zx296702_top_clocks_init()
269 clk[ZX296702_PLL_MM1_54M] = zx296702_top_clocks_init()
272 clk[ZX296702_PLL_LSP_104M] = zx296702_top_clocks_init()
275 clk[ZX296702_PLL_LSP_26M] = zx296702_top_clocks_init()
278 clk[ZX296702_PLL_DDR_266M] = zx296702_top_clocks_init()
281 clk[ZX296702_PLL_AUDIO_294M912] = zx296702_top_clocks_init()
286 clk[ZX296702_MATRIX_ACLK] = zx296702_top_clocks_init()
289 clk[ZX296702_MAIN_HCLK] = zx296702_top_clocks_init()
292 clk[ZX296702_MAIN_PCLK] = zx296702_top_clocks_init()
297 clk[ZX296702_CLK_500] = zx296702_top_clocks_init()
300 clk[ZX296702_CLK_250] = zx296702_top_clocks_init()
303 clk[ZX296702_CLK_125] = zx296702_top_clocks_init()
305 clk[ZX296702_CLK_148M5] = zx296702_top_clocks_init()
308 clk[ZX296702_CLK_74M25] = zx296702_top_clocks_init()
311 clk[ZX296702_A9_WCLK] = zx296702_top_clocks_init()
314 clk[ZX296702_A9_AS1_ACLK_MUX] = zx296702_top_clocks_init()
317 clk[ZX296702_A9_TRACE_CLKIN_MUX] = zx296702_top_clocks_init()
320 clk[ZX296702_A9_AS1_ACLK_DIV] = zx296702_top_clocks_init()
325 clk[ZX296702_CLK_2] = zx296702_top_clocks_init()
328 clk[ZX296702_CLK_27] = zx296702_top_clocks_init()
331 clk[ZX296702_DECPPU_ACLK_MUX] = zx296702_top_clocks_init()
334 clk[ZX296702_PPU_ACLK_MUX] = zx296702_top_clocks_init()
337 clk[ZX296702_MALI400_ACLK_MUX] = zx296702_top_clocks_init()
340 clk[ZX296702_VOU_ACLK_MUX] = zx296702_top_clocks_init()
343 clk[ZX296702_VOU_MAIN_WCLK_MUX] = zx296702_top_clocks_init()
346 clk[ZX296702_VOU_AUX_WCLK_MUX] = zx296702_top_clocks_init()
349 clk[ZX296702_VOU_SCALER_WCLK_MUX] = zx296702_top_clocks_init()
353 clk[ZX296702_R2D_ACLK_MUX] = zx296702_top_clocks_init()
356 clk[ZX296702_R2D_WCLK_MUX] = zx296702_top_clocks_init()
361 clk[ZX296702_CLK_50] = zx296702_top_clocks_init()
364 clk[ZX296702_CLK_25] = zx296702_top_clocks_init()
367 clk[ZX296702_CLK_12] = zx296702_top_clocks_init()
370 clk[ZX296702_CLK_16M384] = zx296702_top_clocks_init()
373 clk[ZX296702_CLK_32K768] = zx296702_top_clocks_init()
376 clk[ZX296702_SEC_WCLK_DIV] = zx296702_top_clocks_init()
379 clk[ZX296702_DDR_WCLK_MUX] = zx296702_top_clocks_init()
382 clk[ZX296702_NAND_WCLK_MUX] = zx296702_top_clocks_init()
385 clk[ZX296702_LSP_26_WCLK_MUX] = zx296702_top_clocks_init()
390 clk[ZX296702_A9_AS0_ACLK] = zx296702_top_clocks_init()
392 clk[ZX296702_A9_AS1_ACLK] = zx296702_top_clocks_init()
394 clk[ZX296702_A9_TRACE_CLKIN] = zx296702_top_clocks_init()
396 clk[ZX296702_DECPPU_AXI_M_ACLK] = zx296702_top_clocks_init()
398 clk[ZX296702_DECPPU_AHB_S_HCLK] = zx296702_top_clocks_init()
400 clk[ZX296702_PPU_AXI_M_ACLK] = zx296702_top_clocks_init()
402 clk[ZX296702_PPU_AHB_S_HCLK] = zx296702_top_clocks_init()
404 clk[ZX296702_VOU_AXI_M_ACLK] = zx296702_top_clocks_init()
406 clk[ZX296702_VOU_APB_PCLK] = zx296702_top_clocks_init()
408 clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] = zx296702_top_clocks_init()
411 clk[ZX296702_VOU_AUX_CHANNEL_WCLK] = zx296702_top_clocks_init()
414 clk[ZX296702_VOU_HDMI_OSCLK_CEC] = zx296702_top_clocks_init()
416 clk[ZX296702_VOU_SCALER_WCLK] = zx296702_top_clocks_init()
418 clk[ZX296702_MALI400_AXI_M_ACLK] = zx296702_top_clocks_init()
420 clk[ZX296702_MALI400_APB_PCLK] = zx296702_top_clocks_init()
422 clk[ZX296702_R2D_WCLK] = zx296702_top_clocks_init()
424 clk[ZX296702_R2D_AXI_M_ACLK] = zx296702_top_clocks_init()
426 clk[ZX296702_R2D_AHB_HCLK] = zx296702_top_clocks_init()
428 clk[ZX296702_DDR3_AXI_S0_ACLK] = zx296702_top_clocks_init()
430 clk[ZX296702_DDR3_APB_PCLK] = zx296702_top_clocks_init()
432 clk[ZX296702_DDR3_WCLK] = zx296702_top_clocks_init()
434 clk[ZX296702_USB20_0_AHB_HCLK] = zx296702_top_clocks_init()
436 clk[ZX296702_USB20_0_EXTREFCLK] = zx296702_top_clocks_init()
438 clk[ZX296702_USB20_1_AHB_HCLK] = zx296702_top_clocks_init()
440 clk[ZX296702_USB20_1_EXTREFCLK] = zx296702_top_clocks_init()
442 clk[ZX296702_USB20_2_AHB_HCLK] = zx296702_top_clocks_init()
444 clk[ZX296702_USB20_2_EXTREFCLK] = zx296702_top_clocks_init()
446 clk[ZX296702_GMAC_AXI_M_ACLK] = zx296702_top_clocks_init()
448 clk[ZX296702_GMAC_APB_PCLK] = zx296702_top_clocks_init()
450 clk[ZX296702_GMAC_125_CLKIN] = zx296702_top_clocks_init()
452 clk[ZX296702_GMAC_RMII_CLKIN] = zx296702_top_clocks_init()
454 clk[ZX296702_GMAC_25M_CLK] = zx296702_top_clocks_init()
456 clk[ZX296702_NANDFLASH_AHB_HCLK] = zx296702_top_clocks_init()
458 clk[ZX296702_NANDFLASH_WCLK] = zx296702_top_clocks_init()
460 clk[ZX296702_LSP0_APB_PCLK] = zx296702_top_clocks_init()
462 clk[ZX296702_LSP0_AHB_HCLK] = zx296702_top_clocks_init()
464 clk[ZX296702_LSP0_26M_WCLK] = zx296702_top_clocks_init()
466 clk[ZX296702_LSP0_104M_WCLK] = zx296702_top_clocks_init()
468 clk[ZX296702_LSP0_16M384_WCLK] = zx296702_top_clocks_init()
470 clk[ZX296702_LSP1_APB_PCLK] = zx296702_top_clocks_init()
473 * UART does not work after parent clk is disabled/enabled */ zx296702_top_clocks_init()
474 clk[ZX296702_LSP1_26M_WCLK] = zx296702_top_clocks_init()
476 clk[ZX296702_LSP1_104M_WCLK] = zx296702_top_clocks_init()
478 clk[ZX296702_LSP1_32K_CLK] = zx296702_top_clocks_init()
480 clk[ZX296702_AON_HCLK] = zx296702_top_clocks_init()
482 clk[ZX296702_SYS_CTRL_PCLK] = zx296702_top_clocks_init()
484 clk[ZX296702_DMA_PCLK] = zx296702_top_clocks_init()
486 clk[ZX296702_DMA_ACLK] = zx296702_top_clocks_init()
488 clk[ZX296702_SEC_HCLK] = zx296702_top_clocks_init()
490 clk[ZX296702_AES_WCLK] = zx296702_top_clocks_init()
492 clk[ZX296702_DES_WCLK] = zx296702_top_clocks_init()
494 clk[ZX296702_IRAM_ACLK] = zx296702_top_clocks_init()
496 clk[ZX296702_IROM_ACLK] = zx296702_top_clocks_init()
498 clk[ZX296702_BOOT_CTRL_HCLK] = zx296702_top_clocks_init()
500 clk[ZX296702_EFUSE_CLK_30] = zx296702_top_clocks_init()
504 clk[ZX296702_VOU_MAIN_CHANNEL_DIV] = zx296702_top_clocks_init()
507 clk[ZX296702_VOU_AUX_CHANNEL_DIV] = zx296702_top_clocks_init()
510 clk[ZX296702_VOU_TV_ENC_HD_DIV] = zx296702_top_clocks_init()
513 clk[ZX296702_VOU_TV_ENC_SD_DIV] = zx296702_top_clocks_init()
516 clk[ZX296702_VL0_MUX] = zx296702_top_clocks_init()
519 clk[ZX296702_VL1_MUX] = zx296702_top_clocks_init()
522 clk[ZX296702_VL2_MUX] = zx296702_top_clocks_init()
525 clk[ZX296702_GL0_MUX] = zx296702_top_clocks_init()
528 clk[ZX296702_GL1_MUX] = zx296702_top_clocks_init()
531 clk[ZX296702_GL2_MUX] = zx296702_top_clocks_init()
534 clk[ZX296702_WB_MUX] = zx296702_top_clocks_init()
537 clk[ZX296702_HDMI_MUX] = zx296702_top_clocks_init()
540 clk[ZX296702_VOU_TV_ENC_HD_MUX] = zx296702_top_clocks_init()
543 clk[ZX296702_VOU_TV_ENC_SD_MUX] = zx296702_top_clocks_init()
546 clk[ZX296702_VL0_CLK] = zx296702_top_clocks_init()
548 clk[ZX296702_VL1_CLK] = zx296702_top_clocks_init()
550 clk[ZX296702_VL2_CLK] = zx296702_top_clocks_init()
552 clk[ZX296702_GL0_CLK] = zx296702_top_clocks_init()
554 clk[ZX296702_GL1_CLK] = zx296702_top_clocks_init()
556 clk[ZX296702_GL2_CLK] = zx296702_top_clocks_init()
558 clk[ZX296702_WB_CLK] = zx296702_top_clocks_init()
560 clk[ZX296702_CL_CLK] = zx296702_top_clocks_init()
562 clk[ZX296702_MAIN_MIX_CLK] = zx296702_top_clocks_init()
565 clk[ZX296702_AUX_MIX_CLK] = zx296702_top_clocks_init()
568 clk[ZX296702_HDMI_CLK] = zx296702_top_clocks_init()
570 clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] = zx296702_top_clocks_init()
573 clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] = zx296702_top_clocks_init()
578 clk[ZX296702_A9_PERIPHCLK] = zx296702_top_clocks_init()
583 if (IS_ERR(clk[i])) { zx296702_top_clocks_init()
584 pr_err("zx296702 clk %d: register failed with %ld\n", zx296702_top_clocks_init()
585 i, PTR_ERR(clk[i])); zx296702_top_clocks_init()
594 CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
599 struct clk **clk = lsp0clk; zx296702_lsp0_clocks_init() local
606 clk[ZX296702_SDMMC1_WCLK_MUX] = zx296702_lsp0_clocks_init()
609 clk[ZX296702_SDMMC1_WCLK_DIV] = zx296702_lsp0_clocks_init()
611 clk[ZX296702_SDMMC1_WCLK] = zx296702_lsp0_clocks_init()
613 clk[ZX296702_SDMMC1_PCLK] = zx296702_lsp0_clocks_init()
616 clk[ZX296702_GPIO_CLK] = zx296702_lsp0_clocks_init()
620 clk[ZX296702_SPDIF0_WCLK_MUX] = zx296702_lsp0_clocks_init()
623 clk[ZX296702_SPDIF0_WCLK] = zx296702_lsp0_clocks_init()
625 clk[ZX296702_SPDIF0_PCLK] = zx296702_lsp0_clocks_init()
628 clk[ZX296702_SPDIF0_DIV] = zx296702_lsp0_clocks_init()
633 clk[ZX296702_I2S0_WCLK_MUX] = zx296702_lsp0_clocks_init()
636 clk[ZX296702_I2S0_WCLK] = zx296702_lsp0_clocks_init()
638 clk[ZX296702_I2S0_PCLK] = zx296702_lsp0_clocks_init()
641 clk[ZX296702_I2S0_DIV] = zx296702_lsp0_clocks_init()
644 clk[ZX296702_I2S1_WCLK_MUX] = zx296702_lsp0_clocks_init()
647 clk[ZX296702_I2S1_WCLK] = zx296702_lsp0_clocks_init()
649 clk[ZX296702_I2S1_PCLK] = zx296702_lsp0_clocks_init()
652 clk[ZX296702_I2S1_DIV] = zx296702_lsp0_clocks_init()
655 clk[ZX296702_I2S2_WCLK_MUX] = zx296702_lsp0_clocks_init()
658 clk[ZX296702_I2S2_WCLK] = zx296702_lsp0_clocks_init()
660 clk[ZX296702_I2S2_PCLK] = zx296702_lsp0_clocks_init()
663 clk[ZX296702_I2S2_DIV] = zx296702_lsp0_clocks_init()
667 if (IS_ERR(clk[i])) { zx296702_lsp0_clocks_init()
668 pr_err("zx296702 clk %d: register failed with %ld\n", zx296702_lsp0_clocks_init()
669 i, PTR_ERR(clk[i])); zx296702_lsp0_clocks_init()
678 CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
683 struct clk **clk = lsp1clk; zx296702_lsp1_clocks_init() local
690 clk[ZX296702_UART0_WCLK_MUX] = zx296702_lsp1_clocks_init()
694 * UART does not work after parent clk is disabled/enabled */ zx296702_lsp1_clocks_init()
695 clk[ZX296702_UART0_WCLK] = zx296702_lsp1_clocks_init()
697 clk[ZX296702_UART0_PCLK] = zx296702_lsp1_clocks_init()
701 clk[ZX296702_UART1_WCLK_MUX] = zx296702_lsp1_clocks_init()
704 clk[ZX296702_UART1_WCLK] = zx296702_lsp1_clocks_init()
706 clk[ZX296702_UART1_PCLK] = zx296702_lsp1_clocks_init()
710 clk[ZX296702_SDMMC0_WCLK_MUX] = zx296702_lsp1_clocks_init()
713 clk[ZX296702_SDMMC0_WCLK_DIV] = zx296702_lsp1_clocks_init()
715 clk[ZX296702_SDMMC0_WCLK] = zx296702_lsp1_clocks_init()
717 clk[ZX296702_SDMMC0_PCLK] = zx296702_lsp1_clocks_init()
720 clk[ZX296702_SPDIF1_WCLK_MUX] = zx296702_lsp1_clocks_init()
723 clk[ZX296702_SPDIF1_WCLK] = zx296702_lsp1_clocks_init()
725 clk[ZX296702_SPDIF1_PCLK] = zx296702_lsp1_clocks_init()
728 clk[ZX296702_SPDIF1_DIV] = zx296702_lsp1_clocks_init()
733 if (IS_ERR(clk[i])) { zx296702_lsp1_clocks_init()
734 pr_err("zx296702 clk %d: register failed with %ld\n", zx296702_lsp1_clocks_init()
735 i, PTR_ERR(clk[i])); zx296702_lsp1_clocks_init()
744 CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",
|
| /linux-4.4.14/drivers/clk/x86/ |
| H A D | Makefile | 0 clk-x86-lpss-objs := clk-lpt.o
2 obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
|
| H A D | clk-lpt.c | 13 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
18 #include <linux/platform_data/clk-lpss.h>
24 struct clk *clk; lpt_clk_probe() local
32 clk = clk_register_fixed_rate(&pdev->dev, drvdata->name, NULL, lpt_clk_probe()
34 if (IS_ERR(clk)) lpt_clk_probe()
35 return PTR_ERR(clk); lpt_clk_probe()
37 drvdata->clk = clk; lpt_clk_probe()
44 .name = "clk-lpt",
|
| /linux-4.4.14/drivers/clk/ti/ |
| H A D | Makefile | 1 obj-y += clk.o autoidle.o clockdomain.o
2 clk-common = dpll.o composite.o divider.o gate.o \
5 obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
6 obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
7 obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
8 obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
9 clk-3xxx.o dpll3xxx.o
10 obj-$(CONFIG_ARCH_OMAP4) += $(clk-common) clk-44xx.o \
12 obj-$(CONFIG_SOC_OMAP5) += $(clk-common) clk-54xx.o \
14 obj-$(CONFIG_SOC_DRA7XX) += $(clk-common) clk-7xx.o \
15 clk-dra7-atl.o dpll3xxx.o dpll44xx.o
16 obj-$(CONFIG_SOC_AM43XX) += $(clk-common) dpll3xxx.o clk-43xx.o
19 obj-$(CONFIG_ARCH_OMAP3) += clk-3xxx-legacy.o
|
| H A D | autoidle.c | 18 #include <linux/clk-provider.h>
23 #include <linux/clk/ti.h>
42 * @clk: struct clk * to disable autoidle for
46 int omap2_clk_deny_idle(struct clk *clk) omap2_clk_deny_idle() argument
50 c = to_clk_hw_omap(__clk_get_hw(clk)); omap2_clk_deny_idle()
58 * @clk: struct clk * to enable autoidle for
62 int omap2_clk_allow_idle(struct clk *clk) omap2_clk_allow_idle() argument
66 c = to_clk_hw_omap(__clk_get_hw(clk)); omap2_clk_allow_idle()
72 static void _allow_autoidle(struct clk_ti_autoidle *clk) _allow_autoidle() argument
76 val = ti_clk_ll_ops->clk_readl(clk->reg); _allow_autoidle()
78 if (clk->flags & AUTOIDLE_LOW) _allow_autoidle()
79 val &= ~(1 << clk->shift); _allow_autoidle()
81 val |= (1 << clk->shift); _allow_autoidle()
83 ti_clk_ll_ops->clk_writel(val, clk->reg); _allow_autoidle()
86 static void _deny_autoidle(struct clk_ti_autoidle *clk) _deny_autoidle() argument
90 val = ti_clk_ll_ops->clk_readl(clk->reg); _deny_autoidle()
92 if (clk->flags & AUTOIDLE_LOW) _deny_autoidle()
93 val |= (1 << clk->shift); _deny_autoidle()
95 val &= ~(1 << clk->shift); _deny_autoidle()
97 ti_clk_ll_ops->clk_writel(val, clk->reg); _deny_autoidle()
142 struct clk_ti_autoidle *clk; of_ti_clk_autoidle_setup() local
148 clk = kzalloc(sizeof(*clk), GFP_KERNEL); of_ti_clk_autoidle_setup()
150 if (!clk) of_ti_clk_autoidle_setup()
153 clk->shift = shift; of_ti_clk_autoidle_setup()
154 clk->name = node->name; of_ti_clk_autoidle_setup()
155 clk->reg = ti_clk_get_reg_addr(node, 0); of_ti_clk_autoidle_setup()
157 if (IS_ERR(clk->reg)) { of_ti_clk_autoidle_setup()
158 kfree(clk); of_ti_clk_autoidle_setup()
163 clk->flags |= AUTOIDLE_LOW; of_ti_clk_autoidle_setup()
165 list_add(&clk->node, &autoidle_clks); of_ti_clk_autoidle_setup()
174 * Add an OMAP clock @clk to the internal list of OMAP clocks. Used
|
| H A D | clkt_dflt.c | 24 #include <linux/clk-provider.h>
26 #include <linux/clk/ti.h>
46 * @clk: module clock to wait for (needed for register offsets)
58 static int _wait_idlest_generic(struct clk_hw_omap *clk, void __iomem *reg, _wait_idlest_generic() argument
84 * @clk: struct clk * belonging to the module
87 * corresponds to clock @clk are enabled, then wait for the module to
92 static void _omap2_module_wait_ready(struct clk_hw_omap *clk) _omap2_module_wait_ready() argument
100 if (clk->ops->find_companion) { _omap2_module_wait_ready()
101 clk->ops->find_companion(clk, &companion_reg, &other_bit); _omap2_module_wait_ready()
107 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val); _omap2_module_wait_ready()
112 _wait_idlest_generic(clk, idlest_reg, (1 << idlest_bit), _omap2_module_wait_ready()
113 idlest_val, clk_hw_get_name(&clk->hw)); _omap2_module_wait_ready()
121 * omap2_clk_dflt_find_companion - find companion clock to @clk
122 * @clk: struct clk * to find the companion clock of
141 void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk, omap2_clk_dflt_find_companion() argument
150 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN)); omap2_clk_dflt_find_companion()
153 *other_bit = clk->enable_bit; omap2_clk_dflt_find_companion()
157 * omap2_clk_dflt_find_idlest - find CM_IDLEST reg va, bit shift for @clk
158 * @clk: struct clk * to find IDLEST info for
170 void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, omap2_clk_dflt_find_idlest() argument
176 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20); omap2_clk_dflt_find_idlest()
178 *idlest_bit = clk->enable_bit; omap2_clk_dflt_find_idlest()
202 struct clk_hw_omap *clk; omap2_dflt_clk_enable() local
212 clk = to_clk_hw_omap(hw); omap2_dflt_clk_enable()
214 if (clkdm_control && clk->clkdm) { omap2_dflt_clk_enable()
215 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); omap2_dflt_clk_enable()
220 clk->clkdm_name, ret); omap2_dflt_clk_enable()
225 if (unlikely(IS_ERR(clk->enable_reg))) { omap2_dflt_clk_enable()
233 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); omap2_dflt_clk_enable()
234 if (clk->flags & INVERT_ENABLE) omap2_dflt_clk_enable()
235 v &= ~(1 << clk->enable_bit); omap2_dflt_clk_enable()
237 v |= (1 << clk->enable_bit); omap2_dflt_clk_enable()
238 ti_clk_ll_ops->clk_writel(v, clk->enable_reg); omap2_dflt_clk_enable()
239 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); /* OCP barrier */ omap2_dflt_clk_enable()
241 if (clk->ops && clk->ops->find_idlest) omap2_dflt_clk_enable()
242 _omap2_module_wait_ready(clk); omap2_dflt_clk_enable()
247 if (clkdm_control && clk->clkdm) omap2_dflt_clk_enable()
248 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); omap2_dflt_clk_enable()
263 struct clk_hw_omap *clk; omap2_dflt_clk_disable() local
266 clk = to_clk_hw_omap(hw); omap2_dflt_clk_disable()
267 if (IS_ERR(clk->enable_reg)) { omap2_dflt_clk_disable()
277 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); omap2_dflt_clk_disable()
278 if (clk->flags & INVERT_ENABLE) omap2_dflt_clk_disable()
279 v |= (1 << clk->enable_bit); omap2_dflt_clk_disable()
281 v &= ~(1 << clk->enable_bit); omap2_dflt_clk_disable()
282 ti_clk_ll_ops->clk_writel(v, clk->enable_reg); omap2_dflt_clk_disable()
286 clk->clkdm) omap2_dflt_clk_disable()
287 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); omap2_dflt_clk_disable()
300 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_dflt_clk_is_enabled() local
303 v = ti_clk_ll_ops->clk_readl(clk->enable_reg); omap2_dflt_clk_is_enabled()
305 if (clk->flags & INVERT_ENABLE) omap2_dflt_clk_is_enabled()
306 v ^= BIT(clk->enable_bit); omap2_dflt_clk_is_enabled()
308 v &= BIT(clk->enable_bit); omap2_dflt_clk_is_enabled()
|
| H A D | dpll3xxx.c | 26 #include <linux/clk.h>
30 #include <linux/clk/ti.h>
43 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk);
44 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk);
45 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk);
50 static void _omap3_dpll_write_clken(struct clk_hw_omap *clk, u8 clken_bits) _omap3_dpll_write_clken() argument
55 dd = clk->dpll_data; _omap3_dpll_write_clken()
64 static int _omap3_wait_dpll_status(struct clk_hw_omap *clk, u8 state) _omap3_wait_dpll_status() argument
71 dd = clk->dpll_data; _omap3_wait_dpll_status()
72 clk_name = clk_hw_get_name(&clk->hw); _omap3_wait_dpll_status()
96 static u16 _omap3_dpll_compute_freqsel(struct clk_hw_omap *clk, u8 n) _omap3_dpll_compute_freqsel() argument
101 fint = clk_get_rate(clk->dpll_data->clk_ref) / n; _omap3_dpll_compute_freqsel()
133 * @clk: pointer to a DPLL struct clk
141 static int _omap3_noncore_dpll_lock(struct clk_hw_omap *clk) _omap3_noncore_dpll_lock() argument
148 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); _omap3_noncore_dpll_lock()
150 dd = clk->dpll_data; _omap3_noncore_dpll_lock()
158 ai = omap3_dpll_autoidle_read(clk); _omap3_noncore_dpll_lock()
161 omap3_dpll_deny_idle(clk); _omap3_noncore_dpll_lock()
163 _omap3_dpll_write_clken(clk, DPLL_LOCKED); _omap3_noncore_dpll_lock()
165 r = _omap3_wait_dpll_status(clk, 1); _omap3_noncore_dpll_lock()
168 omap3_dpll_allow_idle(clk); _omap3_noncore_dpll_lock()
176 * @clk: pointer to a DPLL struct clk
187 static int _omap3_noncore_dpll_bypass(struct clk_hw_omap *clk) _omap3_noncore_dpll_bypass() argument
192 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) _omap3_noncore_dpll_bypass()
196 clk_hw_get_name(&clk->hw)); _omap3_noncore_dpll_bypass()
198 ai = omap3_dpll_autoidle_read(clk); _omap3_noncore_dpll_bypass()
200 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); _omap3_noncore_dpll_bypass()
202 r = _omap3_wait_dpll_status(clk, 0); _omap3_noncore_dpll_bypass()
205 omap3_dpll_allow_idle(clk); _omap3_noncore_dpll_bypass()
212 * @clk: pointer to a DPLL struct clk
219 static int _omap3_noncore_dpll_stop(struct clk_hw_omap *clk) _omap3_noncore_dpll_stop() argument
223 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) _omap3_noncore_dpll_stop()
226 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); _omap3_noncore_dpll_stop()
228 ai = omap3_dpll_autoidle_read(clk); _omap3_noncore_dpll_stop()
230 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); _omap3_noncore_dpll_stop()
233 omap3_dpll_allow_idle(clk); _omap3_noncore_dpll_stop()
240 * @clk: pointer to a DPLL struct clk
250 static void _lookup_dco(struct clk_hw_omap *clk, u8 *dco, u16 m, u8 n) _lookup_dco() argument
254 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); _lookup_dco()
265 * @clk: pointer to a DPLL struct clk
275 static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) _lookup_sddiv() argument
280 clkinp = clk_hw_get_rate(clk_hw_get_parent(&clk->hw)); _lookup_sddiv()
299 * @clk: struct clk * of DPLL to set
305 static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) omap3_noncore_dpll_program() argument
307 struct dpll_data *dd = clk->dpll_data; omap3_noncore_dpll_program()
312 _omap3_noncore_dpll_bypass(clk); omap3_noncore_dpll_program()
342 _lookup_dco(clk, &dco, dd->last_rounded_m, dd->last_rounded_n); omap3_noncore_dpll_program()
347 _lookup_sddiv(clk, &sd_div, dd->last_rounded_m, omap3_noncore_dpll_program()
380 _omap3_noncore_dpll_lock(clk); omap3_noncore_dpll_program()
389 * @clk: DPLL struct clk
395 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_dpll_recalc() local
397 return omap2_get_dpll_rate(clk); omap3_dpll_recalc()
404 * @clk: pointer to a DPLL struct clk
411 * to enter the target state. Intended to be used as the struct clk's
418 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_enable() local
423 dd = clk->dpll_data; omap3_noncore_dpll_enable()
427 if (clk->clkdm) { omap3_noncore_dpll_enable()
428 r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); omap3_noncore_dpll_enable()
433 clk->clkdm_name, r); omap3_noncore_dpll_enable()
442 r = _omap3_noncore_dpll_bypass(clk); omap3_noncore_dpll_enable()
445 r = _omap3_noncore_dpll_lock(clk); omap3_noncore_dpll_enable()
453 * @clk: pointer to a DPLL struct clk
460 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_disable() local
462 _omap3_noncore_dpll_stop(clk); omap3_noncore_dpll_disable()
463 if (clk->clkdm) omap3_noncore_dpll_disable()
464 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); omap3_noncore_dpll_disable()
482 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_determine_rate() local
488 dd = clk->dpll_data; omap3_noncore_dpll_determine_rate()
516 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_set_parent() local
523 ret = _omap3_noncore_dpll_bypass(clk); omap3_noncore_dpll_set_parent()
525 ret = _omap3_noncore_dpll_lock(clk); omap3_noncore_dpll_set_parent()
544 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap3_noncore_dpll_set_rate() local
552 dd = clk->dpll_data; omap3_noncore_dpll_set_rate()
564 freqsel = _omap3_dpll_compute_freqsel(clk, dd->last_rounded_n); omap3_noncore_dpll_set_rate()
571 ret = omap3_noncore_dpll_program(clk, freqsel); omap3_noncore_dpll_set_rate()
600 * clk-ref at index[0], in which case we only need to set rate, omap3_noncore_dpll_set_rate_and_parent()
602 * With clk-bypass case we only need to change parent. omap3_noncore_dpll_set_rate_and_parent()
616 * @clk: struct clk * of the DPLL to read
619 * -EINVAL if passed a null pointer or if the struct clk does not
622 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk) omap3_dpll_autoidle_read() argument
627 if (!clk || !clk->dpll_data) omap3_dpll_autoidle_read()
630 dd = clk->dpll_data; omap3_dpll_autoidle_read()
644 * @clk: struct clk * of the DPLL to operate on
651 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk) omap3_dpll_allow_idle() argument
656 if (!clk || !clk->dpll_data) omap3_dpll_allow_idle()
659 dd = clk->dpll_data; omap3_dpll_allow_idle()
677 * @clk: struct clk * of the DPLL to operate on
681 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk) omap3_dpll_deny_idle() argument
686 if (!clk || !clk->dpll_data) omap3_dpll_deny_idle()
689 dd = clk->dpll_data; omap3_dpll_deny_idle()
707 /* Walk up the parents of clk, looking for a DPLL */ omap3_find_clkoutx2_dpll()
717 /* clk does not have a DPLL as a parent? error in the clock data */ omap3_find_clkoutx2_dpll()
728 * @clk: DPLL output struct clk
|
| H A D | clk.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
21 #include <linux/clk/ti.h>
106 struct clk *clk; ti_dt_clocks_register() local
112 clk = of_clk_get_from_provider(&clkspec); ti_dt_clocks_register()
114 if (!IS_ERR(clk)) { ti_dt_clocks_register()
115 c->lk.clk = clk; ti_dt_clocks_register()
184 pr_err("clk-provider not found for %s!\n", node->name); ti_clk_get_reg_addr()
294 struct clk __init *ti_clk_register_clk(struct ti_clk *setup) ti_clk_register_clk()
296 struct clk *clk; ti_clk_register_clk() local
301 if (setup->clk) ti_clk_register_clk()
302 return setup->clk; ti_clk_register_clk()
308 clk = clk_register_fixed_rate(NULL, setup->name, NULL, ti_clk_register_clk()
312 clk = ti_clk_register_mux(setup); ti_clk_register_clk()
315 clk = ti_clk_register_divider(setup); ti_clk_register_clk()
318 clk = ti_clk_register_composite(setup); ti_clk_register_clk()
323 clk = clk_register_fixed_factor(NULL, setup->name, ti_clk_register_clk()
329 clk = ti_clk_register_gate(setup); ti_clk_register_clk()
332 clk = ti_clk_register_dpll(setup); ti_clk_register_clk()
336 clk = ERR_PTR(-EINVAL); ti_clk_register_clk()
339 if (!IS_ERR(clk)) { ti_clk_register_clk()
340 setup->clk = clk; ti_clk_register_clk()
342 clk_hw = __clk_get_hw(clk); ti_clk_register_clk()
344 pr_warn("can't setup clkdm for basic clk %s\n", ti_clk_register_clk()
354 return clk; ti_clk_register_clk()
359 struct clk *clk; ti_clk_register_legacy_clks() local
364 while (clks->clk) { ti_clk_register_legacy_clks()
365 clk = ti_clk_register_clk(clks->clk); ti_clk_register_legacy_clks()
366 if (IS_ERR(clk)) { ti_clk_register_legacy_clks()
367 if (PTR_ERR(clk) == -EAGAIN) { ti_clk_register_legacy_clks()
371 clks->clk->name, PTR_ERR(clk)); ti_clk_register_legacy_clks()
372 return PTR_ERR(clk); ti_clk_register_legacy_clks()
375 clks->lk.clk = clk; ti_clk_register_legacy_clks()
386 pr_debug("retry-init: %s\n", retry_clk->clk->name); ti_clk_register_legacy_clks()
387 clk = ti_clk_register_clk(retry_clk->clk); ti_clk_register_legacy_clks()
388 if (IS_ERR(clk)) { ti_clk_register_legacy_clks()
389 if (PTR_ERR(clk) == -EAGAIN) { ti_clk_register_legacy_clks()
393 retry_clk->clk->name, ti_clk_register_legacy_clks()
394 PTR_ERR(clk)); ti_clk_register_legacy_clks()
395 return PTR_ERR(clk); ti_clk_register_legacy_clks()
399 retry_clk->lk.clk = clk; ti_clk_register_legacy_clks()
445 struct clk *init_clk; omap2_clk_enable_init_clocks()
|
| H A D | clkt_iclk.c | 14 #include <linux/clk-provider.h>
16 #include <linux/clk/ti.h>
31 void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk) omap2_clkt_iclk_allow_idle() argument
37 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); omap2_clkt_iclk_allow_idle()
40 v |= (1 << clk->enable_bit); omap2_clkt_iclk_allow_idle()
45 void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk) omap2_clkt_iclk_deny_idle() argument
51 ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN)); omap2_clkt_iclk_deny_idle()
54 v &= ~(1 << clk->enable_bit); omap2_clkt_iclk_deny_idle()
60 * @clk: struct clk * being enabled
70 static void omap2430_clk_i2chs_find_idlest(struct clk_hw_omap *clk, omap2430_clk_i2chs_find_idlest() argument
77 r = ((__force u32)clk->enable_reg ^ (OMAP24XX_CM_FCLKEN2 ^ CM_IDLEST)); omap2430_clk_i2chs_find_idlest()
79 *idlest_bit = clk->enable_bit; omap2430_clk_i2chs_find_idlest()
|
| H A D | clockdomain.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
23 #include <linux/clk/ti.h>
44 struct clk_hw_omap *clk; omap2_clkops_enable_clkdm() local
47 clk = to_clk_hw_omap(hw); omap2_clkops_enable_clkdm()
49 if (unlikely(!clk->clkdm)) { omap2_clkops_enable_clkdm()
55 if (unlikely(clk->enable_reg)) omap2_clkops_enable_clkdm()
65 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); omap2_clkops_enable_clkdm()
67 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); omap2_clkops_enable_clkdm()
83 struct clk_hw_omap *clk; omap2_clkops_disable_clkdm() local
85 clk = to_clk_hw_omap(hw); omap2_clkops_disable_clkdm()
87 if (unlikely(!clk->clkdm)) { omap2_clkops_disable_clkdm()
93 if (unlikely(clk->enable_reg)) omap2_clkops_disable_clkdm()
103 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); omap2_clkops_disable_clkdm()
108 struct clk *clk; of_ti_clockdomain_setup() local
117 clk = of_clk_get(node, i); of_ti_clockdomain_setup()
118 if (IS_ERR(clk)) { of_ti_clockdomain_setup()
120 __func__, node->full_name, i, PTR_ERR(clk)); of_ti_clockdomain_setup()
123 clk_hw = __clk_get_hw(clk); of_ti_clockdomain_setup()
125 pr_warn("can't setup clkdm for basic clk %s\n", of_ti_clockdomain_setup()
126 __clk_get_name(clk)); of_ti_clockdomain_setup()
|
| H A D | apll.c | 18 #include <linux/clk.h>
19 #include <linux/clk-provider.h>
28 #include <linux/clk/ti.h>
42 struct clk_hw_omap *clk = to_clk_hw_omap(hw); dra7_apll_enable() local
49 ad = clk->dpll_data; dra7_apll_enable()
53 clk_name = clk_hw_get_name(&clk->hw); dra7_apll_enable()
93 struct clk_hw_omap *clk = to_clk_hw_omap(hw); dra7_apll_disable() local
98 ad = clk->dpll_data; dra7_apll_disable()
110 struct clk_hw_omap *clk = to_clk_hw_omap(hw); dra7_apll_is_enabled() local
114 ad = clk->dpll_data; dra7_apll_is_enabled()
141 struct clk *clk; omap_clk_register_apll() local
147 pr_debug("clk-ref or clk-bypass for %s not ready, retry\n", omap_clk_register_apll()
155 clk = clk_register(NULL, &clk_hw->hw); omap_clk_register_apll()
156 if (!IS_ERR(clk)) { omap_clk_register_apll()
157 of_clk_add_provider(node, of_clk_src_simple_get, clk); omap_clk_register_apll()
229 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_is_enabled() local
230 struct dpll_data *ad = clk->dpll_data; omap2_apll_is_enabled()
244 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_recalc() local
247 return clk->fixed_rate; omap2_apll_recalc()
254 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_enable() local
255 struct dpll_data *ad = clk->dpll_data; omap2_apll_enable()
276 clk_hw_get_name(&clk->hw)); omap2_apll_enable()
285 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap2_apll_disable() local
286 struct dpll_data *ad = clk->dpll_data; omap2_apll_disable()
302 static void omap2_apll_set_autoidle(struct clk_hw_omap *clk, u32 val) omap2_apll_set_autoidle() argument
304 struct dpll_data *ad = clk->dpll_data; omap2_apll_set_autoidle()
316 static void omap2_apll_allow_idle(struct clk_hw_omap *clk) omap2_apll_allow_idle() argument
318 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_LOW_POWER_STOP); omap2_apll_allow_idle()
321 static void omap2_apll_deny_idle(struct clk_hw_omap *clk) omap2_apll_deny_idle() argument
323 omap2_apll_set_autoidle(clk, OMAP2_APLL_AUTOIDLE_DISABLE); omap2_apll_deny_idle()
336 struct clk *clk; of_omap2_apll_setup() local
392 clk = clk_register(NULL, &clk_hw->hw); of_omap2_apll_setup()
393 if (!IS_ERR(clk)) { of_omap2_apll_setup()
394 of_clk_add_provider(node, of_clk_src_simple_get, clk); of_omap2_apll_setup()
|
| H A D | dpll44xx.c | 14 #include <linux/clk.h>
17 #include <linux/clk/ti.h>
40 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) omap4_dpllmx_allow_gatectrl() argument
45 if (!clk || !clk->clksel_reg) omap4_dpllmx_allow_gatectrl()
48 mask = clk->flags & CLOCK_CLKOUTX2 ? omap4_dpllmx_allow_gatectrl()
52 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); omap4_dpllmx_allow_gatectrl()
55 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); omap4_dpllmx_allow_gatectrl()
58 static void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) omap4_dpllmx_deny_gatectrl() argument
63 if (!clk || !clk->clksel_reg) omap4_dpllmx_deny_gatectrl()
66 mask = clk->flags & CLOCK_CLKOUTX2 ? omap4_dpllmx_deny_gatectrl()
70 v = ti_clk_ll_ops->clk_readl(clk->clksel_reg); omap4_dpllmx_deny_gatectrl()
73 ti_clk_ll_ops->clk_writel(v, clk->clksel_reg); omap4_dpllmx_deny_gatectrl()
108 * @clk: struct clk * of the DPLL to compute the rate for
110 * Compute the output rate for the OMAP4 DPLL represented by @clk.
118 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap4_dpll_regm4xen_recalc() local
123 if (!clk || !clk->dpll_data) omap4_dpll_regm4xen_recalc()
126 dd = clk->dpll_data; omap4_dpll_regm4xen_recalc()
128 rate = omap2_get_dpll_rate(clk); omap4_dpll_regm4xen_recalc()
140 * @clk: struct clk * of the DPLL to round a rate for
144 * for @clk if set_rate() were to be provided with the rate
147 * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or
154 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap4_dpll_regm4xen_round_rate() local
158 if (!clk || !clk->dpll_data) omap4_dpll_regm4xen_round_rate()
161 dd = clk->dpll_data; omap4_dpll_regm4xen_round_rate()
205 struct clk_hw_omap *clk = to_clk_hw_omap(hw); omap4_dpll_regm4xen_determine_rate() local
211 dd = clk->dpll_data; omap4_dpll_regm4xen_determine_rate()
|
| /linux-4.4.14/arch/m68k/coldfire/ |
| H A D | clk.c | 4 * clk.c -- general ColdFire CPU kernel clk handling
15 #include <linux/clk.h>
30 void __clk_init_enabled(struct clk *clk) __clk_init_enabled() argument
32 clk->enabled = 1; __clk_init_enabled()
33 clk->clk_ops->enable(clk); __clk_init_enabled()
36 void __clk_init_disabled(struct clk *clk) __clk_init_disabled() argument
38 clk->enabled = 0; __clk_init_disabled()
39 clk->clk_ops->disable(clk); __clk_init_disabled()
42 static void __clk_enable0(struct clk *clk) __clk_enable0() argument
44 __raw_writeb(clk->slot, MCFPM_PPMCR0); __clk_enable0()
47 static void __clk_disable0(struct clk *clk) __clk_disable0() argument
49 __raw_writeb(clk->slot, MCFPM_PPMSR0); __clk_disable0()
58 static void __clk_enable1(struct clk *clk) __clk_enable1() argument
60 __raw_writeb(clk->slot, MCFPM_PPMCR1); __clk_enable1()
63 static void __clk_disable1(struct clk *clk) __clk_disable1() argument
65 __raw_writeb(clk->slot, MCFPM_PPMSR1); __clk_disable1()
75 struct clk *clk_get(struct device *dev, const char *id) clk_get()
78 struct clk *clk; clk_get() local
81 for (i = 0; (clk = mcf_clks[i]) != NULL; ++i) clk_get()
82 if (!strcmp(clk->name, clk_name)) clk_get()
83 return clk; clk_get()
89 int clk_enable(struct clk *clk) clk_enable() argument
93 if ((clk->enabled++ == 0) && clk->clk_ops) clk_enable()
94 clk->clk_ops->enable(clk); clk_enable()
101 void clk_disable(struct clk *clk) clk_disable() argument
105 if ((--clk->enabled == 0) && clk->clk_ops) clk_disable()
106 clk->clk_ops->disable(clk); clk_disable()
111 void clk_put(struct clk *clk) clk_put() argument
113 if (clk->enabled != 0) clk_put()
114 pr_warn("clk_put %s still enabled\n", clk->name); clk_put()
118 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
120 return clk->rate; clk_get_rate()
|
| /linux-4.4.14/arch/mips/lantiq/ |
| H A D | clk.c | 14 #include <linux/clk.h>
25 #include "clk.h"
29 static struct clk cpu_clk_generic[4];
40 struct clk *clk_get_cpu(void) clk_get_cpu()
45 struct clk *clk_get_fpi(void) clk_get_fpi()
51 struct clk *clk_get_io(void) clk_get_io()
56 struct clk *clk_get_ppe(void) clk_get_ppe()
62 static inline int clk_good(struct clk *clk) clk_good() argument
64 return clk && !IS_ERR(clk); clk_good()
67 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
69 if (unlikely(!clk_good(clk))) clk_get_rate()
72 if (clk->rate != 0) clk_get_rate()
73 return clk->rate; clk_get_rate()
75 if (clk->get_rate != NULL) clk_get_rate()
76 return clk->get_rate(); clk_get_rate()
82 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
84 if (unlikely(!clk_good(clk))) clk_set_rate()
86 if (clk->rates && *clk->rates) { clk_set_rate()
87 unsigned long *r = clk->rates; clk_set_rate()
92 pr_err("clk %s.%s: trying to set invalid rate %ld\n", clk_set_rate()
93 clk->cl.dev_id, clk->cl.con_id, rate); clk_set_rate()
97 clk->rate = rate; clk_set_rate()
102 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
104 if (unlikely(!clk_good(clk))) clk_round_rate()
106 if (clk->rates && *clk->rates) { clk_round_rate()
107 unsigned long *r = clk->rates; clk_round_rate()
112 return clk->rate; clk_round_rate()
119 int clk_enable(struct clk *clk) clk_enable() argument
121 if (unlikely(!clk_good(clk))) clk_enable()
124 if (clk->enable) clk_enable()
125 return clk->enable(clk); clk_enable()
131 void clk_disable(struct clk *clk) clk_disable() argument
133 if (unlikely(!clk_good(clk))) clk_disable()
136 if (clk->disable) clk_disable()
137 clk->disable(clk); clk_disable()
141 int clk_activate(struct clk *clk) clk_activate() argument
143 if (unlikely(!clk_good(clk))) clk_activate()
146 if (clk->activate) clk_activate()
147 return clk->activate(clk); clk_activate()
153 void clk_deactivate(struct clk *clk) clk_deactivate() argument
155 if (unlikely(!clk_good(clk))) clk_deactivate()
158 if (clk->deactivate) clk_deactivate()
159 clk->deactivate(clk); clk_deactivate()
163 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) of_clk_get_from_provider()
186 struct clk *clk; plat_time_init() local
190 clk = clk_get_cpu(); plat_time_init()
191 mips_hpt_frequency = clk_get_rate(clk) / get_counter_resolution(); plat_time_init()
193 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); plat_time_init()
194 clk_put(clk); plat_time_init()
|
| H A D | clk.h | 60 struct clk { struct
67 int (*enable) (struct clk *clk);
68 void (*disable) (struct clk *clk);
69 int (*activate) (struct clk *clk);
70 void (*deactivate) (struct clk *clk);
71 void (*reboot) (struct clk *clk);
|
| /linux-4.4.14/arch/arm/mach-mmp/ |
| H A D | clock.c | 13 #include <linux/clk.h>
19 static void apbc_clk_enable(struct clk *clk) apbc_clk_enable() argument
23 clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(clk->fnclksel); apbc_clk_enable()
24 __raw_writel(clk_rst, clk->clk_rst); apbc_clk_enable()
27 static void apbc_clk_disable(struct clk *clk) apbc_clk_disable() argument
29 __raw_writel(0, clk->clk_rst); apbc_clk_disable()
37 static void apmu_clk_enable(struct clk *clk) apmu_clk_enable() argument
39 __raw_writel(clk->enable_val, clk->clk_rst); apmu_clk_enable()
42 static void apmu_clk_disable(struct clk *clk) apmu_clk_disable() argument
44 __raw_writel(0, clk->clk_rst); apmu_clk_disable()
54 int clk_enable(struct clk *clk) clk_enable() argument
59 if (clk->enabled++ == 0) clk_enable()
60 clk->ops->enable(clk); clk_enable()
66 void clk_disable(struct clk *clk) clk_disable() argument
70 WARN_ON(clk->enabled == 0); clk_disable()
73 if (--clk->enabled == 0) clk_disable()
74 clk->ops->disable(clk); clk_disable()
79 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
83 if (clk->ops->getrate) clk_get_rate()
84 rate = clk->ops->getrate(clk); clk_get_rate()
86 rate = clk->rate; clk_get_rate()
92 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
97 if (clk->ops->setrate) { clk_set_rate()
99 ret = clk->ops->setrate(clk, rate); clk_set_rate()
|
| H A D | clock.h | 12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
14 unsigned long (*getrate)(struct clk *);
15 int (*setrate)(struct clk *, unsigned long);
18 struct clk { struct
32 struct clk clk_##_name = { \
40 struct clk clk_##_name = { \
48 struct clk clk_##_name = { \
56 struct clk clk_##_name = { \
65 .clk = _clk, \
70 extern struct clk clk_pxa168_gpio;
71 extern struct clk clk_pxa168_timers;
|
| /linux-4.4.14/arch/blackfin/mach-common/ |
| H A D | clock.h | 4 #include <linux/clk.h>
7 unsigned long (*get_rate)(struct clk *clk);
8 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
9 int (*set_rate)(struct clk *clk, unsigned long rate);
10 int (*enable)(struct clk *clk);
11 int (*disable)(struct clk *clk);
14 struct clk { struct
|
| /linux-4.4.14/drivers/clk/imx/ |
| H A D | clk-imx27.c | 1 #include <linux/clk.h>
2 #include <linux/clk-provider.h>
12 #include "clk.h"
47 static struct clk *clk[IMX27_CLK_MAX]; variable in typeref:struct:clk
50 static struct clk ** const uart_clks[] __initconst = {
51 &clk[IMX27_CLK_PER1_GATE],
52 &clk[IMX27_CLK_UART1_IPG_GATE],
53 &clk[IMX27_CLK_UART2_IPG_GATE],
54 &clk[IMX27_CLK_UART3_IPG_GATE],
55 &clk[IMX27_CLK_UART4_IPG_GATE],
56 &clk[IMX27_CLK_UART5_IPG_GATE],
57 &clk[IMX27_CLK_UART6_IPG_GATE],
65 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); _mx27_clocks_init()
66 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); _mx27_clocks_init()
67 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); _mx27_clocks_init()
68 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); _mx27_clocks_init()
69 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); _mx27_clocks_init()
70 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); _mx27_clocks_init()
71 clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); _mx27_clocks_init()
72 clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); _mx27_clocks_init()
73 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); _mx27_clocks_init()
74 clk[IMX27_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "spll", "ckih_gate", CCM_SPCTL0); _mx27_clocks_init()
75 clk[IMX27_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); _mx27_clocks_init()
76 clk[IMX27_CLK_MPLL_MAIN2] = imx_clk_fixed_factor("mpll_main2", "mpll", 2, 3); _mx27_clocks_init()
79 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 8, 2); _mx27_clocks_init()
80 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); _mx27_clocks_init()
82 clk[IMX27_CLK_AHB] = imx_clk_divider("ahb", "mpll_main2", CCM_CSCR, 9, 4); _mx27_clocks_init()
83 clk[IMX27_CLK_IPG] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); _mx27_clocks_init()
86 clk[IMX27_CLK_MSHC_DIV] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6); _mx27_clocks_init()
87 clk[IMX27_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); _mx27_clocks_init()
88 clk[IMX27_CLK_PER1_DIV] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); _mx27_clocks_init()
89 clk[IMX27_CLK_PER2_DIV] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); _mx27_clocks_init()
90 clk[IMX27_CLK_PER3_DIV] = imx_clk_divider("per3_div", "mpll_main2", CCM_PCDR1, 16, 6); _mx27_clocks_init()
91 clk[IMX27_CLK_PER4_DIV] = imx_clk_divider("per4_div", "mpll_main2", CCM_PCDR1, 24, 6); _mx27_clocks_init()
92 clk[IMX27_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", CCM_CSCR, 21, 1, vpu_sel_clks, ARRAY_SIZE(vpu_sel_clks)); _mx27_clocks_init()
93 clk[IMX27_CLK_VPU_DIV] = imx_clk_divider("vpu_div", "vpu_sel", CCM_PCDR0, 10, 6); _mx27_clocks_init()
94 clk[IMX27_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 28, 3); _mx27_clocks_init()
95 clk[IMX27_CLK_CPU_SEL] = imx_clk_mux("cpu_sel", CCM_CSCR, 15, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); _mx27_clocks_init()
96 clk[IMX27_CLK_CLKO_SEL] = imx_clk_mux("clko_sel", CCM_CCSR, 0, 5, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); _mx27_clocks_init()
99 clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 12, 2); _mx27_clocks_init()
101 clk[IMX27_CLK_CPU_DIV] = imx_clk_divider("cpu_div", "cpu_sel", CCM_CSCR, 13, 3); _mx27_clocks_init()
103 clk[IMX27_CLK_CLKO_DIV] = imx_clk_divider("clko_div", "clko_sel", CCM_PCDR0, 22, 3); _mx27_clocks_init()
104 clk[IMX27_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx27_clocks_init()
105 clk[IMX27_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 23, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx27_clocks_init()
106 clk[IMX27_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); _mx27_clocks_init()
107 clk[IMX27_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); _mx27_clocks_init()
108 clk[IMX27_CLK_CLKO_EN] = imx_clk_gate("clko_en", "clko_div", CCM_PCCR0, 0); _mx27_clocks_init()
109 clk[IMX27_CLK_SSI2_IPG_GATE] = imx_clk_gate("ssi2_ipg_gate", "ipg", CCM_PCCR0, 0); _mx27_clocks_init()
110 clk[IMX27_CLK_SSI1_IPG_GATE] = imx_clk_gate("ssi1_ipg_gate", "ipg", CCM_PCCR0, 1); _mx27_clocks_init()
111 clk[IMX27_CLK_SLCDC_IPG_GATE] = imx_clk_gate("slcdc_ipg_gate", "ipg", CCM_PCCR0, 2); _mx27_clocks_init()
112 clk[IMX27_CLK_SDHC3_IPG_GATE] = imx_clk_gate("sdhc3_ipg_gate", "ipg", CCM_PCCR0, 3); _mx27_clocks_init()
113 clk[IMX27_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 4); _mx27_clocks_init()
114 clk[IMX27_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); _mx27_clocks_init()
115 clk[IMX27_CLK_SCC_IPG_GATE] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); _mx27_clocks_init()
116 clk[IMX27_CLK_SAHARA_IPG_GATE] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); _mx27_clocks_init()
117 clk[IMX27_CLK_RTIC_IPG_GATE] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8); _mx27_clocks_init()
118 clk[IMX27_CLK_RTC_IPG_GATE] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); _mx27_clocks_init()
119 clk[IMX27_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); _mx27_clocks_init()
120 clk[IMX27_CLK_OWIRE_IPG_GATE] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); _mx27_clocks_init()
121 clk[IMX27_CLK_MSHC_IPG_GATE] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13); _mx27_clocks_init()
122 clk[IMX27_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); _mx27_clocks_init()
123 clk[IMX27_CLK_KPP_IPG_GATE] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); _mx27_clocks_init()
124 clk[IMX27_CLK_IIM_IPG_GATE] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); _mx27_clocks_init()
125 clk[IMX27_CLK_I2C2_IPG_GATE] = imx_clk_gate("i2c2_ipg_gate", "ipg", CCM_PCCR0, 17); _mx27_clocks_init()
126 clk[IMX27_CLK_I2C1_IPG_GATE] = imx_clk_gate("i2c1_ipg_gate", "ipg", CCM_PCCR0, 18); _mx27_clocks_init()
127 clk[IMX27_CLK_GPT6_IPG_GATE] = imx_clk_gate("gpt6_ipg_gate", "ipg", CCM_PCCR0, 19); _mx27_clocks_init()
128 clk[IMX27_CLK_GPT5_IPG_GATE] = imx_clk_gate("gpt5_ipg_gate", "ipg", CCM_PCCR0, 20); _mx27_clocks_init()
129 clk[IMX27_CLK_GPT4_IPG_GATE] = imx_clk_gate("gpt4_ipg_gate", "ipg", CCM_PCCR0, 21); _mx27_clocks_init()
130 clk[IMX27_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR0, 22); _mx27_clocks_init()
131 clk[IMX27_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR0, 23); _mx27_clocks_init()
132 clk[IMX27_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR0, 24); _mx27_clocks_init()
133 clk[IMX27_CLK_GPIO_IPG_GATE] = imx_clk_gate("gpio_ipg_gate", "ipg", CCM_PCCR0, 25); _mx27_clocks_init()
134 clk[IMX27_CLK_FEC_IPG_GATE] = imx_clk_gate("fec_ipg_gate", "ipg", CCM_PCCR0, 26); _mx27_clocks_init()
135 clk[IMX27_CLK_EMMA_IPG_GATE] = imx_clk_gate("emma_ipg_gate", "ipg", CCM_PCCR0, 27); _mx27_clocks_init()
136 clk[IMX27_CLK_DMA_IPG_GATE] = imx_clk_gate("dma_ipg_gate", "ipg", CCM_PCCR0, 28); _mx27_clocks_init()
137 clk[IMX27_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); _mx27_clocks_init()
138 clk[IMX27_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); _mx27_clocks_init()
139 clk[IMX27_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); _mx27_clocks_init()
140 clk[IMX27_CLK_MSHC_BAUD_GATE] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2); _mx27_clocks_init()
141 clk[IMX27_CLK_NFC_BAUD_GATE] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); _mx27_clocks_init()
142 clk[IMX27_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); _mx27_clocks_init()
143 clk[IMX27_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); _mx27_clocks_init()
144 clk[IMX27_CLK_VPU_BAUD_GATE] = imx_clk_gate("vpu_baud_gate", "vpu_div", CCM_PCCR1, 6); _mx27_clocks_init()
145 clk[IMX27_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4_div", CCM_PCCR1, 7); _mx27_clocks_init()
146 clk[IMX27_CLK_PER3_GATE] = imx_clk_gate("per3_gate", "per3_div", CCM_PCCR1, 8); _mx27_clocks_init()
147 clk[IMX27_CLK_PER2_GATE] = imx_clk_gate("per2_gate", "per2_div", CCM_PCCR1, 9); _mx27_clocks_init()
148 clk[IMX27_CLK_PER1_GATE] = imx_clk_gate("per1_gate", "per1_div", CCM_PCCR1, 10); _mx27_clocks_init()
149 clk[IMX27_CLK_USB_AHB_GATE] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); _mx27_clocks_init()
150 clk[IMX27_CLK_SLCDC_AHB_GATE] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); _mx27_clocks_init()
151 clk[IMX27_CLK_SAHARA_AHB_GATE] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); _mx27_clocks_init()
152 clk[IMX27_CLK_RTIC_AHB_GATE] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14); _mx27_clocks_init()
153 clk[IMX27_CLK_LCDC_AHB_GATE] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); _mx27_clocks_init()
154 clk[IMX27_CLK_VPU_AHB_GATE] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); _mx27_clocks_init()
155 clk[IMX27_CLK_FEC_AHB_GATE] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); _mx27_clocks_init()
156 clk[IMX27_CLK_EMMA_AHB_GATE] = imx_clk_gate("emma_ahb_gate", "ahb", CCM_PCCR1, 18); _mx27_clocks_init()
157 clk[IMX27_CLK_EMI_AHB_GATE] = imx_clk_gate("emi_ahb_gate", "ahb", CCM_PCCR1, 19); _mx27_clocks_init()
158 clk[IMX27_CLK_DMA_AHB_GATE] = imx_clk_gate("dma_ahb_gate", "ahb", CCM_PCCR1, 20); _mx27_clocks_init()
159 clk[IMX27_CLK_CSI_AHB_GATE] = imx_clk_gate("csi_ahb_gate", "ahb", CCM_PCCR1, 21); _mx27_clocks_init()
160 clk[IMX27_CLK_BROM_AHB_GATE] = imx_clk_gate("brom_ahb_gate", "ahb", CCM_PCCR1, 22); _mx27_clocks_init()
161 clk[IMX27_CLK_ATA_AHB_GATE] = imx_clk_gate("ata_ahb_gate", "ahb", CCM_PCCR1, 23); _mx27_clocks_init()
162 clk[IMX27_CLK_WDOG_IPG_GATE] = imx_clk_gate("wdog_ipg_gate", "ipg", CCM_PCCR1, 24); _mx27_clocks_init()
163 clk[IMX27_CLK_USB_IPG_GATE] = imx_clk_gate("usb_ipg_gate", "ipg", CCM_PCCR1, 25); _mx27_clocks_init()
164 clk[IMX27_CLK_UART6_IPG_GATE] = imx_clk_gate("uart6_ipg_gate", "ipg", CCM_PCCR1, 26); _mx27_clocks_init()
165 clk[IMX27_CLK_UART5_IPG_GATE] = imx_clk_gate("uart5_ipg_gate", "ipg", CCM_PCCR1, 27); _mx27_clocks_init()
166 clk[IMX27_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR1, 28); _mx27_clocks_init()
167 clk[IMX27_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR1, 29); _mx27_clocks_init()
168 clk[IMX27_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR1, 30); _mx27_clocks_init()
169 clk[IMX27_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR1, 31); _mx27_clocks_init()
171 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx27_clocks_init()
173 clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); _mx27_clocks_init()
175 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); _mx27_clocks_init()
188 clk_register_clkdev(clk[IMX27_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx27_clocks_init()
189 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.0"); mx27_clocks_init()
190 clk_register_clkdev(clk[IMX27_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx27_clocks_init()
191 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.1"); mx27_clocks_init()
192 clk_register_clkdev(clk[IMX27_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx27_clocks_init()
193 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.2"); mx27_clocks_init()
194 clk_register_clkdev(clk[IMX27_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx27_clocks_init()
195 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.3"); mx27_clocks_init()
196 clk_register_clkdev(clk[IMX27_CLK_UART5_IPG_GATE], "ipg", "imx21-uart.4"); mx27_clocks_init()
197 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.4"); mx27_clocks_init()
198 clk_register_clkdev(clk[IMX27_CLK_UART6_IPG_GATE], "ipg", "imx21-uart.5"); mx27_clocks_init()
199 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx21-uart.5"); mx27_clocks_init()
200 clk_register_clkdev(clk[IMX27_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); mx27_clocks_init()
201 clk_register_clkdev(clk[IMX27_CLK_PER1_GATE], "per", "imx-gpt.0"); mx27_clocks_init()
202 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.0"); mx27_clocks_init()
203 clk_register_clkdev(clk[IMX27_CLK_SDHC1_IPG_GATE], "ipg", "imx21-mmc.0"); mx27_clocks_init()
204 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.1"); mx27_clocks_init()
205 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.1"); mx27_clocks_init()
206 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx21-mmc.2"); mx27_clocks_init()
207 clk_register_clkdev(clk[IMX27_CLK_SDHC2_IPG_GATE], "ipg", "imx21-mmc.2"); mx27_clocks_init()
208 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.0"); mx27_clocks_init()
209 clk_register_clkdev(clk[IMX27_CLK_CSPI1_IPG_GATE], "ipg", "imx27-cspi.0"); mx27_clocks_init()
210 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.1"); mx27_clocks_init()
211 clk_register_clkdev(clk[IMX27_CLK_CSPI2_IPG_GATE], "ipg", "imx27-cspi.1"); mx27_clocks_init()
212 clk_register_clkdev(clk[IMX27_CLK_PER2_GATE], "per", "imx27-cspi.2"); mx27_clocks_init()
213 clk_register_clkdev(clk[IMX27_CLK_CSPI3_IPG_GATE], "ipg", "imx27-cspi.2"); mx27_clocks_init()
214 clk_register_clkdev(clk[IMX27_CLK_PER3_GATE], "per", "imx21-fb.0"); mx27_clocks_init()
215 clk_register_clkdev(clk[IMX27_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx27_clocks_init()
216 clk_register_clkdev(clk[IMX27_CLK_LCDC_AHB_GATE], "ahb", "imx21-fb.0"); mx27_clocks_init()
217 clk_register_clkdev(clk[IMX27_CLK_CSI_AHB_GATE], "ahb", "imx27-camera.0"); mx27_clocks_init()
218 clk_register_clkdev(clk[IMX27_CLK_PER4_GATE], "per", "imx27-camera.0"); mx27_clocks_init()
219 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "imx-udc-mx27"); mx27_clocks_init()
220 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "imx-udc-mx27"); mx27_clocks_init()
221 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "imx-udc-mx27"); mx27_clocks_init()
222 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.0"); mx27_clocks_init()
223 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.0"); mx27_clocks_init()
224 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.0"); mx27_clocks_init()
225 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.1"); mx27_clocks_init()
226 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.1"); mx27_clocks_init()
227 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.1"); mx27_clocks_init()
228 clk_register_clkdev(clk[IMX27_CLK_USB_DIV], "per", "mxc-ehci.2"); mx27_clocks_init()
229 clk_register_clkdev(clk[IMX27_CLK_USB_IPG_GATE], "ipg", "mxc-ehci.2"); mx27_clocks_init()
230 clk_register_clkdev(clk[IMX27_CLK_USB_AHB_GATE], "ahb", "mxc-ehci.2"); mx27_clocks_init()
231 clk_register_clkdev(clk[IMX27_CLK_SSI1_IPG_GATE], NULL, "imx-ssi.0"); mx27_clocks_init()
232 clk_register_clkdev(clk[IMX27_CLK_SSI2_IPG_GATE], NULL, "imx-ssi.1"); mx27_clocks_init()
233 clk_register_clkdev(clk[IMX27_CLK_NFC_BAUD_GATE], NULL, "imx27-nand.0"); mx27_clocks_init()
234 clk_register_clkdev(clk[IMX27_CLK_VPU_BAUD_GATE], "per", "coda-imx27.0"); mx27_clocks_init()
235 clk_register_clkdev(clk[IMX27_CLK_VPU_AHB_GATE], "ahb", "coda-imx27.0"); mx27_clocks_init()
236 clk_register_clkdev(clk[IMX27_CLK_DMA_AHB_GATE], "ahb", "imx27-dma"); mx27_clocks_init()
237 clk_register_clkdev(clk[IMX27_CLK_DMA_IPG_GATE], "ipg", "imx27-dma"); mx27_clocks_init()
238 clk_register_clkdev(clk[IMX27_CLK_FEC_IPG_GATE], "ipg", "imx27-fec.0"); mx27_clocks_init()
239 clk_register_clkdev(clk[IMX27_CLK_FEC_AHB_GATE], "ahb", "imx27-fec.0"); mx27_clocks_init()
240 clk_register_clkdev(clk[IMX27_CLK_WDOG_IPG_GATE], NULL, "imx2-wdt.0"); mx27_clocks_init()
241 clk_register_clkdev(clk[IMX27_CLK_I2C1_IPG_GATE], NULL, "imx21-i2c.0"); mx27_clocks_init()
242 clk_register_clkdev(clk[IMX27_CLK_I2C2_IPG_GATE], NULL, "imx21-i2c.1"); mx27_clocks_init()
243 clk_register_clkdev(clk[IMX27_CLK_OWIRE_IPG_GATE], NULL, "mxc_w1.0"); mx27_clocks_init()
244 clk_register_clkdev(clk[IMX27_CLK_KPP_IPG_GATE], NULL, "imx-keypad"); mx27_clocks_init()
245 clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "emma-ahb", "imx27-camera.0"); mx27_clocks_init()
246 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "emma-ipg", "imx27-camera.0"); mx27_clocks_init()
247 clk_register_clkdev(clk[IMX27_CLK_EMMA_AHB_GATE], "ahb", "m2m-emmaprp.0"); mx27_clocks_init()
248 clk_register_clkdev(clk[IMX27_CLK_EMMA_IPG_GATE], "ipg", "m2m-emmaprp.0"); mx27_clocks_init()
274 clk_data.clks = clk; mx27_clocks_init_dt()
275 clk_data.clk_num = ARRAY_SIZE(clk); mx27_clocks_init_dt()
|
| H A D | clk-imx51-imx53.c | 11 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
22 #include "clk.h"
130 static struct clk *clk[IMX5_CLK_END]; variable in typeref:struct:clk
133 static struct clk ** const uart_clks[] __initconst = {
134 &clk[IMX5_CLK_UART1_IPG_GATE],
135 &clk[IMX5_CLK_UART1_PER_GATE],
136 &clk[IMX5_CLK_UART2_IPG_GATE],
137 &clk[IMX5_CLK_UART2_PER_GATE],
138 &clk[IMX5_CLK_UART3_IPG_GATE],
139 &clk[IMX5_CLK_UART3_PER_GATE],
140 &clk[IMX5_CLK_UART4_IPG_GATE],
141 &clk[IMX5_CLK_UART4_PER_GATE],
142 &clk[IMX5_CLK_UART5_IPG_GATE],
143 &clk[IMX5_CLK_UART5_PER_GATE],
149 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); mx5_clocks_common_init()
150 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); mx5_clocks_common_init()
151 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); mx5_clocks_common_init()
152 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); mx5_clocks_common_init()
153 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); mx5_clocks_common_init()
155 clk[IMX5_CLK_PERIPH_APM] = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2, mx5_clocks_common_init()
157 clk[IMX5_CLK_MAIN_BUS] = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1, mx5_clocks_common_init()
159 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, mx5_clocks_common_init()
161 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); mx5_clocks_common_init()
162 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); mx5_clocks_common_init()
163 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); mx5_clocks_common_init()
164 clk[IMX5_CLK_PER_ROOT] = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1, mx5_clocks_common_init()
166 clk[IMX5_CLK_AHB] = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3); mx5_clocks_common_init()
167 clk[IMX5_CLK_AHB_MAX] = imx_clk_gate2("ahb_max", "ahb", MXC_CCM_CCGR0, 28); mx5_clocks_common_init()
168 clk[IMX5_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", MXC_CCM_CCGR0, 24); mx5_clocks_common_init()
169 clk[IMX5_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", MXC_CCM_CCGR0, 26); mx5_clocks_common_init()
170 clk[IMX5_CLK_TMAX1] = imx_clk_gate2("tmax1", "ahb", MXC_CCM_CCGR1, 0); mx5_clocks_common_init()
171 clk[IMX5_CLK_TMAX2] = imx_clk_gate2("tmax2", "ahb", MXC_CCM_CCGR1, 2); mx5_clocks_common_init()
172 clk[IMX5_CLK_TMAX3] = imx_clk_gate2("tmax3", "ahb", MXC_CCM_CCGR1, 4); mx5_clocks_common_init()
173 clk[IMX5_CLK_SPBA] = imx_clk_gate2("spba", "ipg", MXC_CCM_CCGR5, 0); mx5_clocks_common_init()
174 clk[IMX5_CLK_IPG] = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2); mx5_clocks_common_init()
175 clk[IMX5_CLK_AXI_A] = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3); mx5_clocks_common_init()
176 clk[IMX5_CLK_AXI_B] = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3); mx5_clocks_common_init()
177 clk[IMX5_CLK_UART_SEL] = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2, mx5_clocks_common_init()
179 clk[IMX5_CLK_UART_PRED] = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3); mx5_clocks_common_init()
180 clk[IMX5_CLK_UART_ROOT] = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3); mx5_clocks_common_init()
182 clk[IMX5_CLK_ESDHC_A_SEL] = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2, mx5_clocks_common_init()
184 clk[IMX5_CLK_ESDHC_B_SEL] = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2, mx5_clocks_common_init()
186 clk[IMX5_CLK_ESDHC_A_PRED] = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3); mx5_clocks_common_init()
187 clk[IMX5_CLK_ESDHC_A_PODF] = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3); mx5_clocks_common_init()
188 clk[IMX5_CLK_ESDHC_B_PRED] = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3); mx5_clocks_common_init()
189 clk[IMX5_CLK_ESDHC_B_PODF] = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3); mx5_clocks_common_init()
190 clk[IMX5_CLK_ESDHC_C_SEL] = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel)); mx5_clocks_common_init()
191 clk[IMX5_CLK_ESDHC_D_SEL] = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel)); mx5_clocks_common_init()
193 clk[IMX5_CLK_EMI_SEL] = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1, mx5_clocks_common_init()
195 clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3); mx5_clocks_common_init()
196 clk[IMX5_CLK_NFC_PODF] = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3); mx5_clocks_common_init()
197 clk[IMX5_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2, mx5_clocks_common_init()
199 clk[IMX5_CLK_ECSPI_PRED] = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3); mx5_clocks_common_init()
200 clk[IMX5_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6); mx5_clocks_common_init()
201 clk[IMX5_CLK_USBOH3_SEL] = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2, mx5_clocks_common_init()
203 clk[IMX5_CLK_USBOH3_PRED] = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3); mx5_clocks_common_init()
204 clk[IMX5_CLK_USBOH3_PODF] = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2); mx5_clocks_common_init()
205 clk[IMX5_CLK_USB_PHY_PRED] = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3); mx5_clocks_common_init()
206 clk[IMX5_CLK_USB_PHY_PODF] = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3); mx5_clocks_common_init()
207 clk[IMX5_CLK_USB_PHY_SEL] = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1, mx5_clocks_common_init()
209 clk[IMX5_CLK_STEP_SEL] = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels)); mx5_clocks_common_init()
210 clk[IMX5_CLK_CPU_PODF_SEL] = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels)); mx5_clocks_common_init()
211 clk[IMX5_CLK_CPU_PODF] = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3); mx5_clocks_common_init()
212 clk[IMX5_CLK_DI_PRED] = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3); mx5_clocks_common_init()
213 clk[IMX5_CLK_IIM_GATE] = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30); mx5_clocks_common_init()
214 clk[IMX5_CLK_UART1_IPG_GATE] = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6); mx5_clocks_common_init()
215 clk[IMX5_CLK_UART1_PER_GATE] = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8); mx5_clocks_common_init()
216 clk[IMX5_CLK_UART2_IPG_GATE] = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10); mx5_clocks_common_init()
217 clk[IMX5_CLK_UART2_PER_GATE] = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12); mx5_clocks_common_init()
218 clk[IMX5_CLK_UART3_IPG_GATE] = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14); mx5_clocks_common_init()
219 clk[IMX5_CLK_UART3_PER_GATE] = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16); mx5_clocks_common_init()
220 clk[IMX5_CLK_I2C1_GATE] = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18); mx5_clocks_common_init()
221 clk[IMX5_CLK_I2C2_GATE] = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20); mx5_clocks_common_init()
222 clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10); mx5_clocks_common_init()
223 clk[IMX5_CLK_PWM1_HF_GATE] = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12); mx5_clocks_common_init()
224 clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14); mx5_clocks_common_init()
225 clk[IMX5_CLK_PWM2_HF_GATE] = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16); mx5_clocks_common_init()
226 clk[IMX5_CLK_GPT_IPG_GATE] = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18); mx5_clocks_common_init()
227 clk[IMX5_CLK_GPT_HF_GATE] = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20); mx5_clocks_common_init()
228 clk[IMX5_CLK_FEC_GATE] = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24); mx5_clocks_common_init()
229 clk[IMX5_CLK_USBOH3_GATE] = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26); mx5_clocks_common_init()
230 clk[IMX5_CLK_USBOH3_PER_GATE] = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28); mx5_clocks_common_init()
231 clk[IMX5_CLK_ESDHC1_IPG_GATE] = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0); mx5_clocks_common_init()
232 clk[IMX5_CLK_ESDHC2_IPG_GATE] = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4); mx5_clocks_common_init()
233 clk[IMX5_CLK_ESDHC3_IPG_GATE] = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8); mx5_clocks_common_init()
234 clk[IMX5_CLK_ESDHC4_IPG_GATE] = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12); mx5_clocks_common_init()
235 clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16); mx5_clocks_common_init()
236 clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20); mx5_clocks_common_init()
237 clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24); mx5_clocks_common_init()
238 clk[IMX5_CLK_ECSPI1_IPG_GATE] = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18); mx5_clocks_common_init()
239 clk[IMX5_CLK_ECSPI1_PER_GATE] = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20); mx5_clocks_common_init()
240 clk[IMX5_CLK_ECSPI2_IPG_GATE] = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22); mx5_clocks_common_init()
241 clk[IMX5_CLK_ECSPI2_PER_GATE] = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24); mx5_clocks_common_init()
242 clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26); mx5_clocks_common_init()
243 clk[IMX5_CLK_SDMA_GATE] = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30); mx5_clocks_common_init()
244 clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14); mx5_clocks_common_init()
245 clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16); mx5_clocks_common_init()
246 clk[IMX5_CLK_IPU_SEL] = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel)); mx5_clocks_common_init()
247 clk[IMX5_CLK_IPU_GATE] = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10); mx5_clocks_common_init()
248 clk[IMX5_CLK_NFC_GATE] = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20); mx5_clocks_common_init()
249 clk[IMX5_CLK_IPU_DI0_GATE] = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10); mx5_clocks_common_init()
250 clk[IMX5_CLK_IPU_DI1_GATE] = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12); mx5_clocks_common_init()
251 clk[IMX5_CLK_GPU3D_SEL] = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel)); mx5_clocks_common_init()
252 clk[IMX5_CLK_GPU2D_SEL] = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel)); mx5_clocks_common_init()
253 clk[IMX5_CLK_GPU3D_GATE] = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2); mx5_clocks_common_init()
254 clk[IMX5_CLK_GARB_GATE] = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4); mx5_clocks_common_init()
255 clk[IMX5_CLK_GPU2D_GATE] = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14); mx5_clocks_common_init()
256 clk[IMX5_CLK_VPU_SEL] = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel)); mx5_clocks_common_init()
257 clk[IMX5_CLK_VPU_GATE] = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6); mx5_clocks_common_init()
258 clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8); mx5_clocks_common_init()
259 clk[IMX5_CLK_UART4_IPG_GATE] = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8); mx5_clocks_common_init()
260 clk[IMX5_CLK_UART4_PER_GATE] = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10); mx5_clocks_common_init()
261 clk[IMX5_CLK_UART5_IPG_GATE] = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12); mx5_clocks_common_init()
262 clk[IMX5_CLK_UART5_PER_GATE] = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14); mx5_clocks_common_init()
263 clk[IMX5_CLK_GPC_DVFS] = imx_clk_gate2("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24); mx5_clocks_common_init()
265 clk[IMX5_CLK_SSI_APM] = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels)); mx5_clocks_common_init()
266 clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
267 clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
268 clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels)); mx5_clocks_common_init()
269 clk[IMX5_CLK_SSI_EXT1_SEL] = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
270 clk[IMX5_CLK_SSI_EXT2_SEL] = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels)); mx5_clocks_common_init()
271 clk[IMX5_CLK_SSI_EXT1_COM_SEL] = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels)); mx5_clocks_common_init()
272 clk[IMX5_CLK_SSI_EXT2_COM_SEL] = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels)); mx5_clocks_common_init()
273 clk[IMX5_CLK_SSI1_ROOT_PRED] = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3); mx5_clocks_common_init()
274 clk[IMX5_CLK_SSI1_ROOT_PODF] = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6); mx5_clocks_common_init()
275 clk[IMX5_CLK_SSI2_ROOT_PRED] = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3); mx5_clocks_common_init()
276 clk[IMX5_CLK_SSI2_ROOT_PODF] = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6); mx5_clocks_common_init()
277 clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3); mx5_clocks_common_init()
278 clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6); mx5_clocks_common_init()
279 clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3); mx5_clocks_common_init()
280 clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6); mx5_clocks_common_init()
281 clk[IMX5_CLK_SSI1_ROOT_GATE] = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18); mx5_clocks_common_init()
282 clk[IMX5_CLK_SSI2_ROOT_GATE] = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22); mx5_clocks_common_init()
283 clk[IMX5_CLK_SSI3_ROOT_GATE] = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26); mx5_clocks_common_init()
284 clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28); mx5_clocks_common_init()
285 clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30); mx5_clocks_common_init()
286 clk[IMX5_CLK_EPIT1_IPG_GATE] = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2); mx5_clocks_common_init()
287 clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); mx5_clocks_common_init()
288 clk[IMX5_CLK_EPIT2_IPG_GATE] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); mx5_clocks_common_init()
289 clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); mx5_clocks_common_init()
290 clk[IMX5_CLK_OWIRE_GATE] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); mx5_clocks_common_init()
291 clk[IMX5_CLK_SRTC_GATE] = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28); mx5_clocks_common_init()
292 clk[IMX5_CLK_PATA_GATE] = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0); mx5_clocks_common_init()
293 clk[IMX5_CLK_SPDIF0_SEL] = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel)); mx5_clocks_common_init()
294 clk[IMX5_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3); mx5_clocks_common_init()
295 clk[IMX5_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6); mx5_clocks_common_init()
296 clk[IMX5_CLK_SPDIF0_COM_SEL] = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1, mx5_clocks_common_init()
298 clk[IMX5_CLK_SPDIF0_GATE] = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26); mx5_clocks_common_init()
299 clk[IMX5_CLK_SPDIF_IPG_GATE] = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30); mx5_clocks_common_init()
300 clk[IMX5_CLK_SAHARA_IPG_GATE] = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14); mx5_clocks_common_init()
301 clk[IMX5_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1); mx5_clocks_common_init()
303 clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0"); mx5_clocks_common_init()
304 clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL); mx5_clocks_common_init()
307 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); mx5_clocks_common_init()
308 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); mx5_clocks_common_init()
310 /* move usb phy clk to 24MHz */ mx5_clocks_common_init()
311 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); mx5_clocks_common_init()
313 clk_prepare_enable(clk[IMX5_CLK_GPC_DVFS]); mx5_clocks_common_init()
314 clk_prepare_enable(clk[IMX5_CLK_AHB_MAX]); /* esdhc3 */ mx5_clocks_common_init()
315 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ1]); mx5_clocks_common_init()
316 clk_prepare_enable(clk[IMX5_CLK_AIPS_TZ2]); /* fec */ mx5_clocks_common_init()
317 clk_prepare_enable(clk[IMX5_CLK_SPBA]); mx5_clocks_common_init()
318 clk_prepare_enable(clk[IMX5_CLK_EMI_FAST_GATE]); /* fec */ mx5_clocks_common_init()
319 clk_prepare_enable(clk[IMX5_CLK_EMI_SLOW_GATE]); /* eim */ mx5_clocks_common_init()
320 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC1_GATE]); mx5_clocks_common_init()
321 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSC2_GATE]); mx5_clocks_common_init()
322 clk_prepare_enable(clk[IMX5_CLK_MIPI_ESC_GATE]); mx5_clocks_common_init()
323 clk_prepare_enable(clk[IMX5_CLK_MIPI_HSP_GATE]); mx5_clocks_common_init()
324 clk_prepare_enable(clk[IMX5_CLK_TMAX1]); mx5_clocks_common_init()
325 clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */ mx5_clocks_common_init()
326 clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */ mx5_clocks_common_init()
339 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx50_clocks_init()
343 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx50_clocks_init()
347 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx50_clocks_init()
354 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, mx50_clocks_init()
356 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); mx50_clocks_init()
357 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); mx50_clocks_init()
358 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); mx50_clocks_init()
359 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); mx50_clocks_init()
360 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); mx50_clocks_init()
361 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); mx50_clocks_init()
362 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); mx50_clocks_init()
364 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, mx50_clocks_init()
366 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); mx50_clocks_init()
367 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); mx50_clocks_init()
369 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, mx50_clocks_init()
371 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); mx50_clocks_init()
372 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); mx50_clocks_init()
374 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx50_clocks_init()
376 clk_data.clks = clk; mx50_clocks_init()
377 clk_data.clk_num = ARRAY_SIZE(clk); mx50_clocks_init()
381 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); mx50_clocks_init()
382 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); mx50_clocks_init()
384 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); mx50_clocks_init()
386 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); mx50_clocks_init()
388 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); mx50_clocks_init()
389 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mx50_clocks_init()
401 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx51_clocks_init()
405 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx51_clocks_init()
409 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx51_clocks_init()
416 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1, mx51_clocks_init()
418 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, mx51_clocks_init()
420 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, mx51_clocks_init()
422 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, mx51_clocks_init()
424 clk[IMX5_CLK_TVE_SEL] = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1, mx51_clocks_init()
426 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30); mx51_clocks_init()
427 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3); mx51_clocks_init()
428 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); mx51_clocks_init()
429 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6); mx51_clocks_init()
430 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10); mx51_clocks_init()
431 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); mx51_clocks_init()
432 clk[IMX5_CLK_USB_PHY_GATE] = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0); mx51_clocks_init()
433 clk[IMX5_CLK_HSI2C_GATE] = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22); mx51_clocks_init()
434 clk[IMX5_CLK_MIPI_HSC1_GATE] = imx_clk_gate2("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6); mx51_clocks_init()
435 clk[IMX5_CLK_MIPI_HSC2_GATE] = imx_clk_gate2("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8); mx51_clocks_init()
436 clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10); mx51_clocks_init()
437 clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12); mx51_clocks_init()
438 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, mx51_clocks_init()
440 clk[IMX5_CLK_SPDIF1_SEL] = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2, mx51_clocks_init()
442 clk[IMX5_CLK_SPDIF1_PRED] = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3); mx51_clocks_init()
443 clk[IMX5_CLK_SPDIF1_PODF] = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6); mx51_clocks_init()
444 clk[IMX5_CLK_SPDIF1_COM_SEL] = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1, mx51_clocks_init()
446 clk[IMX5_CLK_SPDIF1_GATE] = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28); mx51_clocks_init()
448 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx51_clocks_init()
450 clk_data.clks = clk; mx51_clocks_init()
451 clk_data.clk_num = ARRAY_SIZE(clk); mx51_clocks_init()
455 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); mx51_clocks_init()
458 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000); mx51_clocks_init()
459 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000); mx51_clocks_init()
461 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); mx51_clocks_init()
463 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); mx51_clocks_init()
490 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); mx53_clocks_init()
494 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); mx53_clocks_init()
498 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); mx53_clocks_init()
502 clk[IMX5_CLK_PLL4_SW] = imx_clk_pllv2("pll4_sw", "osc", pll_base); mx53_clocks_init()
509 clk[IMX5_CLK_LP_APM] = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1, mx53_clocks_init()
511 clk[IMX5_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); mx53_clocks_init()
512 clk[IMX5_CLK_LDB_DI1_DIV] = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0); mx53_clocks_init()
513 clk[IMX5_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1, mx53_clocks_init()
515 clk[IMX5_CLK_DI_PLL4_PODF] = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3); mx53_clocks_init()
516 clk[IMX5_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); mx53_clocks_init()
517 clk[IMX5_CLK_LDB_DI0_DIV] = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0); mx53_clocks_init()
518 clk[IMX5_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1, mx53_clocks_init()
520 clk[IMX5_CLK_LDB_DI0_GATE] = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28); mx53_clocks_init()
521 clk[IMX5_CLK_LDB_DI1_GATE] = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30); mx53_clocks_init()
522 clk[IMX5_CLK_IPU_DI0_SEL] = imx_clk_mux("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3, mx53_clocks_init()
524 clk[IMX5_CLK_IPU_DI1_SEL] = imx_clk_mux("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3, mx53_clocks_init()
526 clk[IMX5_CLK_TVE_EXT_SEL] = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1, mx53_clocks_init()
528 clk[IMX5_CLK_TVE_GATE] = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30); mx53_clocks_init()
529 clk[IMX5_CLK_TVE_PRED] = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3); mx53_clocks_init()
530 clk[IMX5_CLK_ESDHC1_PER_GATE] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2); mx53_clocks_init()
531 clk[IMX5_CLK_ESDHC2_PER_GATE] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6); mx53_clocks_init()
532 clk[IMX5_CLK_ESDHC3_PER_GATE] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10); mx53_clocks_init()
533 clk[IMX5_CLK_ESDHC4_PER_GATE] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14); mx53_clocks_init()
534 clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10); mx53_clocks_init()
535 clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12); mx53_clocks_init()
536 clk[IMX5_CLK_CAN_SEL] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2, mx53_clocks_init()
538 clk[IMX5_CLK_CAN1_SERIAL_GATE] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); mx53_clocks_init()
539 clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); mx53_clocks_init()
540 clk[IMX5_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2); mx53_clocks_init()
541 clk[IMX5_CLK_CAN2_SERIAL_GATE] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); mx53_clocks_init()
542 clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); mx53_clocks_init()
543 clk[IMX5_CLK_I2C3_GATE] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); mx53_clocks_init()
544 clk[IMX5_CLK_SATA_GATE] = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2); mx53_clocks_init()
546 clk[IMX5_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4, mx53_clocks_init()
548 clk[IMX5_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3); mx53_clocks_init()
549 clk[IMX5_CLK_CKO1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7); mx53_clocks_init()
551 clk[IMX5_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5, mx53_clocks_init()
553 clk[IMX5_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3); mx53_clocks_init()
554 clk[IMX5_CLK_CKO2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24); mx53_clocks_init()
555 clk[IMX5_CLK_SPDIF_XTAL_SEL] = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2, mx53_clocks_init()
557 clk[IMX5_CLK_ARM] = imx_clk_cpu("arm", "cpu_podf", mx53_clocks_init()
558 clk[IMX5_CLK_CPU_PODF], mx53_clocks_init()
559 clk[IMX5_CLK_CPU_PODF_SEL], mx53_clocks_init()
560 clk[IMX5_CLK_PLL1_SW], mx53_clocks_init()
561 clk[IMX5_CLK_STEP_SEL]); mx53_clocks_init()
563 imx_check_clocks(clk, ARRAY_SIZE(clk)); mx53_clocks_init()
565 clk_data.clks = clk; mx53_clocks_init()
566 clk_data.clk_num = ARRAY_SIZE(clk); mx53_clocks_init()
570 clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000); mx53_clocks_init()
571 clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000); mx53_clocks_init()
573 /* move can bus clk to 24MHz */ mx53_clocks_init()
574 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); mx53_clocks_init()
577 clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]); mx53_clocks_init()
579 clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]); mx53_clocks_init()
581 clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]); mx53_clocks_init()
583 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); mx53_clocks_init()
584 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); mx53_clocks_init()
|
| H A D | clk-imx31.c | 19 #include <linux/clk.h>
28 #include "clk.h"
62 static struct clk *clk[clk_max]; variable in typeref:struct:clk
65 static struct clk ** const uart_clks[] __initconst = {
66 &clk[ipg],
67 &clk[uart1_gate],
68 &clk[uart2_gate],
69 &clk[uart3_gate],
70 &clk[uart4_gate],
71 &clk[uart5_gate],
83 clk[dummy] = imx_clk_fixed("dummy", 0); _mx31_clocks_init()
84 clk[ckih] = imx_clk_fixed("ckih", fref); _mx31_clocks_init()
85 clk[ckil] = imx_clk_fixed("ckil", 32768); _mx31_clocks_init()
86 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); _mx31_clocks_init()
87 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); _mx31_clocks_init()
88 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); _mx31_clocks_init()
89 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel)); _mx31_clocks_init()
90 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); _mx31_clocks_init()
91 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); _mx31_clocks_init()
92 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); _mx31_clocks_init()
93 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); _mx31_clocks_init()
94 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); _mx31_clocks_init()
95 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel)); _mx31_clocks_init()
96 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel)); _mx31_clocks_init()
97 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel)); _mx31_clocks_init()
98 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9); _mx31_clocks_init()
99 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2); _mx31_clocks_init()
100 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3); _mx31_clocks_init()
101 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3); _mx31_clocks_init()
102 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6); _mx31_clocks_init()
103 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0); _mx31_clocks_init()
104 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2); _mx31_clocks_init()
105 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4); _mx31_clocks_init()
106 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6); _mx31_clocks_init()
107 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8); _mx31_clocks_init()
108 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10); _mx31_clocks_init()
109 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12); _mx31_clocks_init()
110 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); _mx31_clocks_init()
111 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16); _mx31_clocks_init()
112 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18); _mx31_clocks_init()
113 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20); _mx31_clocks_init()
114 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22); _mx31_clocks_init()
115 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24); _mx31_clocks_init()
116 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26); _mx31_clocks_init()
117 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28); _mx31_clocks_init()
118 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30); _mx31_clocks_init()
119 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0); _mx31_clocks_init()
120 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2); _mx31_clocks_init()
121 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4); _mx31_clocks_init()
122 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6); _mx31_clocks_init()
123 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8); _mx31_clocks_init()
124 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10); _mx31_clocks_init()
125 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12); _mx31_clocks_init()
126 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14); _mx31_clocks_init()
127 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16); _mx31_clocks_init()
128 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); _mx31_clocks_init()
129 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20); _mx31_clocks_init()
130 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22); _mx31_clocks_init()
131 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24); _mx31_clocks_init()
132 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26); _mx31_clocks_init()
133 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28); _mx31_clocks_init()
134 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30); _mx31_clocks_init()
135 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0); _mx31_clocks_init()
136 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2); _mx31_clocks_init()
137 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4); _mx31_clocks_init()
138 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6); _mx31_clocks_init()
139 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); _mx31_clocks_init()
140 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); _mx31_clocks_init()
141 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12); _mx31_clocks_init()
143 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx31_clocks_init()
145 clk_set_parent(clk[csi], clk[upll]); _mx31_clocks_init()
146 clk_prepare_enable(clk[emi_gate]); _mx31_clocks_init()
147 clk_prepare_enable(clk[iim_gate]); _mx31_clocks_init()
149 clk_disable_unprepare(clk[iim_gate]); _mx31_clocks_init()
154 clk_data.clks = clk; _mx31_clocks_init()
155 clk_data.clk_num = ARRAY_SIZE(clk); _mx31_clocks_init()
166 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); mx31_clocks_init()
167 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); mx31_clocks_init()
168 clk_register_clkdev(clk[cspi1_gate], NULL, "imx31-cspi.0"); mx31_clocks_init()
169 clk_register_clkdev(clk[cspi2_gate], NULL, "imx31-cspi.1"); mx31_clocks_init()
170 clk_register_clkdev(clk[cspi3_gate], NULL, "imx31-cspi.2"); mx31_clocks_init()
171 clk_register_clkdev(clk[pwm_gate], "pwm", NULL); mx31_clocks_init()
172 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); mx31_clocks_init()
173 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); mx31_clocks_init()
174 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); mx31_clocks_init()
175 clk_register_clkdev(clk[epit1_gate], "epit", NULL); mx31_clocks_init()
176 clk_register_clkdev(clk[epit2_gate], "epit", NULL); mx31_clocks_init()
177 clk_register_clkdev(clk[nfc], NULL, "imx27-nand.0"); mx31_clocks_init()
178 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); mx31_clocks_init()
179 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); mx31_clocks_init()
180 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); mx31_clocks_init()
181 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.0"); mx31_clocks_init()
182 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.0"); mx31_clocks_init()
183 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); mx31_clocks_init()
184 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.1"); mx31_clocks_init()
185 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.1"); mx31_clocks_init()
186 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); mx31_clocks_init()
187 clk_register_clkdev(clk[usb_div_post], "per", "mxc-ehci.2"); mx31_clocks_init()
188 clk_register_clkdev(clk[usb_gate], "ahb", "mxc-ehci.2"); mx31_clocks_init()
189 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); mx31_clocks_init()
190 clk_register_clkdev(clk[usb_div_post], "per", "imx-udc-mx27"); mx31_clocks_init()
191 clk_register_clkdev(clk[usb_gate], "ahb", "imx-udc-mx27"); mx31_clocks_init()
192 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); mx31_clocks_init()
193 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); mx31_clocks_init()
195 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); mx31_clocks_init()
196 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx31_clocks_init()
197 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); mx31_clocks_init()
198 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx31_clocks_init()
199 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); mx31_clocks_init()
200 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx31_clocks_init()
201 clk_register_clkdev(clk[uart4_gate], "per", "imx21-uart.3"); mx31_clocks_init()
202 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.3"); mx31_clocks_init()
203 clk_register_clkdev(clk[uart5_gate], "per", "imx21-uart.4"); mx31_clocks_init()
204 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.4"); mx31_clocks_init()
205 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); mx31_clocks_init()
206 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); mx31_clocks_init()
207 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); mx31_clocks_init()
208 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0"); mx31_clocks_init()
209 clk_register_clkdev(clk[sdhc1_gate], NULL, "imx31-mmc.0"); mx31_clocks_init()
210 clk_register_clkdev(clk[sdhc2_gate], NULL, "imx31-mmc.1"); mx31_clocks_init()
211 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); mx31_clocks_init()
212 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); mx31_clocks_init()
213 clk_register_clkdev(clk[firi_gate], "firi", NULL); mx31_clocks_init()
214 clk_register_clkdev(clk[ata_gate], NULL, "pata_imx"); mx31_clocks_init()
215 clk_register_clkdev(clk[rtic_gate], "rtic", NULL); mx31_clocks_init()
216 clk_register_clkdev(clk[rng_gate], NULL, "mxc_rnga"); mx31_clocks_init()
217 clk_register_clkdev(clk[sdma_gate], NULL, "imx31-sdma"); mx31_clocks_init()
218 clk_register_clkdev(clk[iim_gate], "iim", NULL); mx31_clocks_init()
|
| H A D | clk-imx21.c | 12 #include <linux/clk-provider.h>
20 #include "clk.h"
42 static struct clk *clk[IMX21_CLK_MAX]; variable in typeref:struct:clk
49 clk[IMX21_CLK_DUMMY] = imx_clk_fixed("dummy", 0); _mx21_clocks_init()
50 clk[IMX21_CLK_CKIL] = imx_obtain_fixed_clock("ckil", lref); _mx21_clocks_init()
51 clk[IMX21_CLK_CKIH] = imx_obtain_fixed_clock("ckih", href); _mx21_clocks_init()
52 clk[IMX21_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 512, 1); _mx21_clocks_init()
53 clk[IMX21_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); _mx21_clocks_init()
55 clk[IMX21_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); _mx21_clocks_init()
56 clk[IMX21_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); _mx21_clocks_init()
57 clk[IMX21_CLK_FPM_GATE] = imx_clk_gate("fpm_gate", "fpm", CCM_CSCR, 2); _mx21_clocks_init()
58 clk[IMX21_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); _mx21_clocks_init()
59 clk[IMX21_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY_SIZE(mpll_osc_sel_clks)); _mx21_clocks_init()
60 clk[IMX21_CLK_IPG] = imx_clk_divider("ipg", "hclk", CCM_CSCR, 9, 1); _mx21_clocks_init()
61 clk[IMX21_CLK_HCLK] = imx_clk_divider("hclk", "fclk", CCM_CSCR, 10, 4); _mx21_clocks_init()
62 clk[IMX21_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_sel_clks)); _mx21_clocks_init()
63 clk[IMX21_CLK_SPLL_SEL] = imx_clk_mux("spll_sel", CCM_CSCR, 17, 1, spll_sel_clks, ARRAY_SIZE(spll_sel_clks)); _mx21_clocks_init()
64 clk[IMX21_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", CCM_CSCR, 19, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx21_clocks_init()
65 clk[IMX21_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", CCM_CSCR, 20, 1, ssi_sel_clks, ARRAY_SIZE(ssi_sel_clks)); _mx21_clocks_init()
66 clk[IMX21_CLK_USB_DIV] = imx_clk_divider("usb_div", "spll_gate", CCM_CSCR, 26, 3); _mx21_clocks_init()
67 clk[IMX21_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 29, 3); _mx21_clocks_init()
69 clk[IMX21_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "mpll", "mpll_sel", CCM_MPCTL0); _mx21_clocks_init()
71 clk[IMX21_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX21, "spll", "spll_sel", CCM_SPCTL0); _mx21_clocks_init()
73 clk[IMX21_CLK_NFC_DIV] = imx_clk_divider("nfc_div", "fclk", CCM_PCDR0, 12, 4); _mx21_clocks_init()
74 clk[IMX21_CLK_SSI1_DIV] = imx_clk_divider("ssi1_div", "ssi1_sel", CCM_PCDR0, 16, 6); _mx21_clocks_init()
75 clk[IMX21_CLK_SSI2_DIV] = imx_clk_divider("ssi2_div", "ssi2_sel", CCM_PCDR0, 26, 6); _mx21_clocks_init()
77 clk[IMX21_CLK_PER1] = imx_clk_divider("per1", "mpll_gate", CCM_PCDR1, 0, 6); _mx21_clocks_init()
78 clk[IMX21_CLK_PER2] = imx_clk_divider("per2", "mpll_gate", CCM_PCDR1, 8, 6); _mx21_clocks_init()
79 clk[IMX21_CLK_PER3] = imx_clk_divider("per3", "mpll_gate", CCM_PCDR1, 16, 6); _mx21_clocks_init()
80 clk[IMX21_CLK_PER4] = imx_clk_divider("per4", "mpll_gate", CCM_PCDR1, 24, 6); _mx21_clocks_init()
82 clk[IMX21_CLK_UART1_IPG_GATE] = imx_clk_gate("uart1_ipg_gate", "ipg", CCM_PCCR0, 0); _mx21_clocks_init()
83 clk[IMX21_CLK_UART2_IPG_GATE] = imx_clk_gate("uart2_ipg_gate", "ipg", CCM_PCCR0, 1); _mx21_clocks_init()
84 clk[IMX21_CLK_UART3_IPG_GATE] = imx_clk_gate("uart3_ipg_gate", "ipg", CCM_PCCR0, 2); _mx21_clocks_init()
85 clk[IMX21_CLK_UART4_IPG_GATE] = imx_clk_gate("uart4_ipg_gate", "ipg", CCM_PCCR0, 3); _mx21_clocks_init()
86 clk[IMX21_CLK_CSPI1_IPG_GATE] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 4); _mx21_clocks_init()
87 clk[IMX21_CLK_CSPI2_IPG_GATE] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 5); _mx21_clocks_init()
88 clk[IMX21_CLK_SSI1_GATE] = imx_clk_gate("ssi1_gate", "ipg", CCM_PCCR0, 6); _mx21_clocks_init()
89 clk[IMX21_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "ipg", CCM_PCCR0, 7); _mx21_clocks_init()
90 clk[IMX21_CLK_SDHC1_IPG_GATE] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 9); _mx21_clocks_init()
91 clk[IMX21_CLK_SDHC2_IPG_GATE] = imx_clk_gate("sdhc2_ipg_gate", "ipg", CCM_PCCR0, 10); _mx21_clocks_init()
92 clk[IMX21_CLK_GPIO_GATE] = imx_clk_gate("gpio_gate", "ipg", CCM_PCCR0, 11); _mx21_clocks_init()
93 clk[IMX21_CLK_I2C_GATE] = imx_clk_gate("i2c_gate", "ipg", CCM_PCCR0, 12); _mx21_clocks_init()
94 clk[IMX21_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "ipg", CCM_PCCR0, 13); _mx21_clocks_init()
95 clk[IMX21_CLK_USB_GATE] = imx_clk_gate("usb_gate", "usb_div", CCM_PCCR0, 14); _mx21_clocks_init()
96 clk[IMX21_CLK_EMMA_GATE] = imx_clk_gate("emma_gate", "ipg", CCM_PCCR0, 15); _mx21_clocks_init()
97 clk[IMX21_CLK_SSI2_BAUD_GATE] = imx_clk_gate("ssi2_baud_gate", "ipg", CCM_PCCR0, 16); _mx21_clocks_init()
98 clk[IMX21_CLK_SSI1_BAUD_GATE] = imx_clk_gate("ssi1_baud_gate", "ipg", CCM_PCCR0, 17); _mx21_clocks_init()
99 clk[IMX21_CLK_LCDC_IPG_GATE] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 18); _mx21_clocks_init()
100 clk[IMX21_CLK_NFC_GATE] = imx_clk_gate("nfc_gate", "nfc_div", CCM_PCCR0, 19); _mx21_clocks_init()
101 clk[IMX21_CLK_SLCDC_HCLK_GATE] = imx_clk_gate("slcdc_hclk_gate", "hclk", CCM_PCCR0, 21); _mx21_clocks_init()
102 clk[IMX21_CLK_PER4_GATE] = imx_clk_gate("per4_gate", "per4", CCM_PCCR0, 22); _mx21_clocks_init()
103 clk[IMX21_CLK_BMI_GATE] = imx_clk_gate("bmi_gate", "hclk", CCM_PCCR0, 23); _mx21_clocks_init()
104 clk[IMX21_CLK_USB_HCLK_GATE] = imx_clk_gate("usb_hclk_gate", "hclk", CCM_PCCR0, 24); _mx21_clocks_init()
105 clk[IMX21_CLK_SLCDC_GATE] = imx_clk_gate("slcdc_gate", "hclk", CCM_PCCR0, 25); _mx21_clocks_init()
106 clk[IMX21_CLK_LCDC_HCLK_GATE] = imx_clk_gate("lcdc_hclk_gate", "hclk", CCM_PCCR0, 26); _mx21_clocks_init()
107 clk[IMX21_CLK_EMMA_HCLK_GATE] = imx_clk_gate("emma_hclk_gate", "hclk", CCM_PCCR0, 27); _mx21_clocks_init()
108 clk[IMX21_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", CCM_PCCR0, 28); _mx21_clocks_init()
109 clk[IMX21_CLK_DMA_HCLK_GATE] = imx_clk_gate("dma_hclk_gate", "hclk", CCM_PCCR0, 30); _mx21_clocks_init()
110 clk[IMX21_CLK_CSI_HCLK_GATE] = imx_clk_gate("csi_hclk_gate", "hclk", CCM_PCCR0, 31); _mx21_clocks_init()
112 clk[IMX21_CLK_CSPI3_IPG_GATE] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR1, 23); _mx21_clocks_init()
113 clk[IMX21_CLK_WDOG_GATE] = imx_clk_gate("wdog_gate", "ipg", CCM_PCCR1, 24); _mx21_clocks_init()
114 clk[IMX21_CLK_GPT1_IPG_GATE] = imx_clk_gate("gpt1_ipg_gate", "ipg", CCM_PCCR1, 25); _mx21_clocks_init()
115 clk[IMX21_CLK_GPT2_IPG_GATE] = imx_clk_gate("gpt2_ipg_gate", "ipg", CCM_PCCR1, 26); _mx21_clocks_init()
116 clk[IMX21_CLK_GPT3_IPG_GATE] = imx_clk_gate("gpt3_ipg_gate", "ipg", CCM_PCCR1, 27); _mx21_clocks_init()
117 clk[IMX21_CLK_PWM_IPG_GATE] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR1, 28); _mx21_clocks_init()
118 clk[IMX21_CLK_RTC_GATE] = imx_clk_gate("rtc_gate", "ipg", CCM_PCCR1, 29); _mx21_clocks_init()
119 clk[IMX21_CLK_KPP_GATE] = imx_clk_gate("kpp_gate", "ipg", CCM_PCCR1, 30); _mx21_clocks_init()
120 clk[IMX21_CLK_OWIRE_GATE] = imx_clk_gate("owire_gate", "ipg", CCM_PCCR1, 31); _mx21_clocks_init()
122 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx21_clocks_init()
131 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.0"); mx21_clocks_init()
132 clk_register_clkdev(clk[IMX21_CLK_UART1_IPG_GATE], "ipg", "imx21-uart.0"); mx21_clocks_init()
133 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.1"); mx21_clocks_init()
134 clk_register_clkdev(clk[IMX21_CLK_UART2_IPG_GATE], "ipg", "imx21-uart.1"); mx21_clocks_init()
135 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.2"); mx21_clocks_init()
136 clk_register_clkdev(clk[IMX21_CLK_UART3_IPG_GATE], "ipg", "imx21-uart.2"); mx21_clocks_init()
137 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx21-uart.3"); mx21_clocks_init()
138 clk_register_clkdev(clk[IMX21_CLK_UART4_IPG_GATE], "ipg", "imx21-uart.3"); mx21_clocks_init()
139 clk_register_clkdev(clk[IMX21_CLK_GPT1_IPG_GATE], "ipg", "imx-gpt.0"); mx21_clocks_init()
140 clk_register_clkdev(clk[IMX21_CLK_PER1], "per", "imx-gpt.0"); mx21_clocks_init()
141 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.0"); mx21_clocks_init()
142 clk_register_clkdev(clk[IMX21_CLK_CSPI1_IPG_GATE], "ipg", "imx21-cspi.0"); mx21_clocks_init()
143 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.1"); mx21_clocks_init()
144 clk_register_clkdev(clk[IMX21_CLK_CSPI2_IPG_GATE], "ipg", "imx21-cspi.1"); mx21_clocks_init()
145 clk_register_clkdev(clk[IMX21_CLK_PER2], "per", "imx21-cspi.2"); mx21_clocks_init()
146 clk_register_clkdev(clk[IMX21_CLK_CSPI3_IPG_GATE], "ipg", "imx21-cspi.2"); mx21_clocks_init()
147 clk_register_clkdev(clk[IMX21_CLK_PER3], "per", "imx21-fb.0"); mx21_clocks_init()
148 clk_register_clkdev(clk[IMX21_CLK_LCDC_IPG_GATE], "ipg", "imx21-fb.0"); mx21_clocks_init()
149 clk_register_clkdev(clk[IMX21_CLK_LCDC_HCLK_GATE], "ahb", "imx21-fb.0"); mx21_clocks_init()
150 clk_register_clkdev(clk[IMX21_CLK_USB_GATE], "per", "imx21-hcd.0"); mx21_clocks_init()
151 clk_register_clkdev(clk[IMX21_CLK_USB_HCLK_GATE], "ahb", "imx21-hcd.0"); mx21_clocks_init()
152 clk_register_clkdev(clk[IMX21_CLK_NFC_GATE], NULL, "imx21-nand.0"); mx21_clocks_init()
153 clk_register_clkdev(clk[IMX21_CLK_DMA_HCLK_GATE], "ahb", "imx21-dma"); mx21_clocks_init()
154 clk_register_clkdev(clk[IMX21_CLK_DMA_GATE], "ipg", "imx21-dma"); mx21_clocks_init()
155 clk_register_clkdev(clk[IMX21_CLK_WDOG_GATE], NULL, "imx2-wdt.0"); mx21_clocks_init()
156 clk_register_clkdev(clk[IMX21_CLK_I2C_GATE], NULL, "imx21-i2c.0"); mx21_clocks_init()
157 clk_register_clkdev(clk[IMX21_CLK_OWIRE_GATE], NULL, "mxc_w1.0"); mx21_clocks_init()
170 clk_data.clks = clk; mx21_clocks_init_dt()
171 clk_data.clk_num = ARRAY_SIZE(clk); mx21_clocks_init_dt()
|
| H A D | clk-vf610.c | 12 #include <linux/clk.h>
15 #include "clk.h"
115 static struct clk *clk[VF610_CLK_END]; variable in typeref:struct:clk
124 static struct clk * __init vf610_get_fixed_clock( vf610_get_fixed_clock()
127 struct clk *clk = of_clk_get_by_name(ccm_node, name); vf610_get_fixed_clock() local
130 if (IS_ERR(clk)) vf610_get_fixed_clock()
131 clk = imx_obtain_fixed_clock(name, 0); vf610_get_fixed_clock()
132 return clk; vf610_get_fixed_clock()
140 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); vf610_clocks_init()
141 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); vf610_clocks_init()
142 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); vf610_clocks_init()
143 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); vf610_clocks_init()
145 clk[VF610_CLK_SXOSC] = vf610_get_fixed_clock(ccm_node, "sxosc"); vf610_clocks_init()
146 clk[VF610_CLK_FXOSC] = vf610_get_fixed_clock(ccm_node, "fxosc"); vf610_clocks_init()
147 clk[VF610_CLK_AUDIO_EXT] = vf610_get_fixed_clock(ccm_node, "audio_ext"); vf610_clocks_init()
148 clk[VF610_CLK_ENET_EXT] = vf610_get_fixed_clock(ccm_node, "enet_ext"); vf610_clocks_init()
151 clk[VF610_CLK_ANACLK1] = vf610_get_fixed_clock(ccm_node, "anaclk1"); vf610_clocks_init()
153 clk[VF610_CLK_FXOSC_HALF] = imx_clk_fixed_factor("fxosc_half", "fxosc", 1, 2); vf610_clocks_init()
163 clk[VF610_CLK_SLOW_CLK_SEL] = imx_clk_mux("slow_clk_sel", CCM_CCSR, 4, 1, slow_sels, ARRAY_SIZE(slow_sels)); vf610_clocks_init()
164 clk[VF610_CLK_FASK_CLK_SEL] = imx_clk_mux("fast_clk_sel", CCM_CCSR, 5, 1, fast_sels, ARRAY_SIZE(fast_sels)); vf610_clocks_init()
166 clk[VF610_CLK_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", PLL1_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
167 clk[VF610_CLK_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", PLL2_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
168 clk[VF610_CLK_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", PLL3_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
169 clk[VF610_CLK_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", PLL4_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
170 clk[VF610_CLK_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", PLL5_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
171 clk[VF610_CLK_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", PLL6_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
172 clk[VF610_CLK_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", PLL7_CTRL, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); vf610_clocks_init()
174 clk[VF610_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll1", "pll1_bypass_src", PLL1_CTRL, 0x1); vf610_clocks_init()
175 clk[VF610_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", PLL2_CTRL, 0x1); vf610_clocks_init()
176 clk[VF610_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll3", "pll3_bypass_src", PLL3_CTRL, 0x2); vf610_clocks_init()
177 clk[VF610_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", PLL4_CTRL, 0x7f); vf610_clocks_init()
178 clk[VF610_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll5", "pll5_bypass_src", PLL5_CTRL, 0x3); vf610_clocks_init()
179 clk[VF610_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_AV, "pll6", "pll6_bypass_src", PLL6_CTRL, 0x7f); vf610_clocks_init()
180 clk[VF610_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB_VF610, "pll7", "pll7_bypass_src", PLL7_CTRL, 0x2); vf610_clocks_init()
182 clk[VF610_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", PLL1_CTRL, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
183 clk[VF610_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", PLL2_CTRL, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
184 clk[VF610_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", PLL3_CTRL, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
185 clk[VF610_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", PLL4_CTRL, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
186 clk[VF610_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", PLL5_CTRL, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
187 clk[VF610_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", PLL6_CTRL, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
188 clk[VF610_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", PLL7_CTRL, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); vf610_clocks_init()
191 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); vf610_clocks_init()
192 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); vf610_clocks_init()
193 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); vf610_clocks_init()
194 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); vf610_clocks_init()
195 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); vf610_clocks_init()
196 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); vf610_clocks_init()
197 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); vf610_clocks_init()
199 clk[VF610_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", PLL1_CTRL, 13); vf610_clocks_init()
200 clk[VF610_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", PLL2_CTRL, 13); vf610_clocks_init()
201 clk[VF610_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", PLL3_CTRL, 13); vf610_clocks_init()
202 clk[VF610_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", PLL4_CTRL, 13); vf610_clocks_init()
203 clk[VF610_CLK_PLL5_ENET] = imx_clk_gate("pll5_enet", "pll5_bypass", PLL5_CTRL, 13); vf610_clocks_init()
204 clk[VF610_CLK_PLL6_VIDEO] = imx_clk_gate("pll6_video", "pll6_bypass", PLL6_CTRL, 13); vf610_clocks_init()
205 clk[VF610_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", PLL7_CTRL, 13); vf610_clocks_init()
207 clk[VF610_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", ANA_MISC1, 12, BIT(10)); vf610_clocks_init()
209 clk[VF610_CLK_PLL1_PFD1] = imx_clk_pfd("pll1_pfd1", "pll1_sys", PFD_PLL1_BASE, 0); vf610_clocks_init()
210 clk[VF610_CLK_PLL1_PFD2] = imx_clk_pfd("pll1_pfd2", "pll1_sys", PFD_PLL1_BASE, 1); vf610_clocks_init()
211 clk[VF610_CLK_PLL1_PFD3] = imx_clk_pfd("pll1_pfd3", "pll1_sys", PFD_PLL1_BASE, 2); vf610_clocks_init()
212 clk[VF610_CLK_PLL1_PFD4] = imx_clk_pfd("pll1_pfd4", "pll1_sys", PFD_PLL1_BASE, 3); vf610_clocks_init()
214 clk[VF610_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1", "pll2_bus", PFD_PLL2_BASE, 0); vf610_clocks_init()
215 clk[VF610_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2", "pll2_bus", PFD_PLL2_BASE, 1); vf610_clocks_init()
216 clk[VF610_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3", "pll2_bus", PFD_PLL2_BASE, 2); vf610_clocks_init()
217 clk[VF610_CLK_PLL2_PFD4] = imx_clk_pfd("pll2_pfd4", "pll2_bus", PFD_PLL2_BASE, 3); vf610_clocks_init()
219 clk[VF610_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1", "pll3_usb_otg", PFD_PLL3_BASE, 0); vf610_clocks_init()
220 clk[VF610_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2", "pll3_usb_otg", PFD_PLL3_BASE, 1); vf610_clocks_init()
221 clk[VF610_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3", "pll3_usb_otg", PFD_PLL3_BASE, 2); vf610_clocks_init()
222 clk[VF610_CLK_PLL3_PFD4] = imx_clk_pfd("pll3_pfd4", "pll3_usb_otg", PFD_PLL3_BASE, 3); vf610_clocks_init()
224 clk[VF610_CLK_PLL1_PFD_SEL] = imx_clk_mux("pll1_pfd_sel", CCM_CCSR, 16, 3, pll1_sels, 5); vf610_clocks_init()
225 clk[VF610_CLK_PLL2_PFD_SEL] = imx_clk_mux("pll2_pfd_sel", CCM_CCSR, 19, 3, pll2_sels, 5); vf610_clocks_init()
226 clk[VF610_CLK_SYS_SEL] = imx_clk_mux("sys_sel", CCM_CCSR, 0, 3, sys_sels, ARRAY_SIZE(sys_sels)); vf610_clocks_init()
227 clk[VF610_CLK_DDR_SEL] = imx_clk_mux("ddr_sel", CCM_CCSR, 6, 1, ddr_sels, ARRAY_SIZE(ddr_sels)); vf610_clocks_init()
228 clk[VF610_CLK_SYS_BUS] = imx_clk_divider("sys_bus", "sys_sel", CCM_CACRR, 0, 3); vf610_clocks_init()
229 clk[VF610_CLK_PLATFORM_BUS] = imx_clk_divider("platform_bus", "sys_bus", CCM_CACRR, 3, 3); vf610_clocks_init()
230 clk[VF610_CLK_IPG_BUS] = imx_clk_divider("ipg_bus", "platform_bus", CCM_CACRR, 11, 2); vf610_clocks_init()
232 clk[VF610_CLK_PLL3_MAIN_DIV] = imx_clk_divider("pll3_usb_otg_div", "pll3_usb_otg", CCM_CACRR, 20, 1); vf610_clocks_init()
233 clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0, CCM_CACRR, 6, 3, 0, pll4_audio_div_table, &imx_ccm_lock); vf610_clocks_init()
234 clk[VF610_CLK_PLL6_MAIN_DIV] = imx_clk_divider("pll6_video_div", "pll6_video", CCM_CACRR, 21, 1); vf610_clocks_init()
236 clk[VF610_CLK_USBPHY0] = imx_clk_gate("usbphy0", "pll3_usb_otg", PLL3_CTRL, 6); vf610_clocks_init()
237 clk[VF610_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll7_usb_host", PLL7_CTRL, 6); vf610_clocks_init()
239 clk[VF610_CLK_USBC0] = imx_clk_gate2("usbc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(4)); vf610_clocks_init()
240 clk[VF610_CLK_USBC1] = imx_clk_gate2("usbc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(4)); vf610_clocks_init()
242 clk[VF610_CLK_QSPI0_SEL] = imx_clk_mux("qspi0_sel", CCM_CSCMR1, 22, 2, qspi_sels, 4); vf610_clocks_init()
243 clk[VF610_CLK_QSPI0_EN] = imx_clk_gate("qspi0_en", "qspi0_sel", CCM_CSCDR3, 4); vf610_clocks_init()
244 clk[VF610_CLK_QSPI0_X4_DIV] = imx_clk_divider("qspi0_x4", "qspi0_en", CCM_CSCDR3, 0, 2); vf610_clocks_init()
245 clk[VF610_CLK_QSPI0_X2_DIV] = imx_clk_divider("qspi0_x2", "qspi0_x4", CCM_CSCDR3, 2, 1); vf610_clocks_init()
246 clk[VF610_CLK_QSPI0_X1_DIV] = imx_clk_divider("qspi0_x1", "qspi0_x2", CCM_CSCDR3, 3, 1); vf610_clocks_init()
247 clk[VF610_CLK_QSPI0] = imx_clk_gate2("qspi0", "qspi0_x1", CCM_CCGR2, CCM_CCGRx_CGn(4)); vf610_clocks_init()
249 clk[VF610_CLK_QSPI1_SEL] = imx_clk_mux("qspi1_sel", CCM_CSCMR1, 24, 2, qspi_sels, 4); vf610_clocks_init()
250 clk[VF610_CLK_QSPI1_EN] = imx_clk_gate("qspi1_en", "qspi1_sel", CCM_CSCDR3, 12); vf610_clocks_init()
251 clk[VF610_CLK_QSPI1_X4_DIV] = imx_clk_divider("qspi1_x4", "qspi1_en", CCM_CSCDR3, 8, 2); vf610_clocks_init()
252 clk[VF610_CLK_QSPI1_X2_DIV] = imx_clk_divider("qspi1_x2", "qspi1_x4", CCM_CSCDR3, 10, 1); vf610_clocks_init()
253 clk[VF610_CLK_QSPI1_X1_DIV] = imx_clk_divider("qspi1_x1", "qspi1_x2", CCM_CSCDR3, 11, 1); vf610_clocks_init()
254 clk[VF610_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_x1", CCM_CCGR8, CCM_CCGRx_CGn(4)); vf610_clocks_init()
256 clk[VF610_CLK_ENET_50M] = imx_clk_fixed_factor("enet_50m", "pll5_enet", 1, 10); vf610_clocks_init()
257 clk[VF610_CLK_ENET_25M] = imx_clk_fixed_factor("enet_25m", "pll5_enet", 1, 20); vf610_clocks_init()
258 clk[VF610_CLK_ENET_SEL] = imx_clk_mux("enet_sel", CCM_CSCMR2, 4, 2, rmii_sels, 4); vf610_clocks_init()
259 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7); vf610_clocks_init()
260 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24); vf610_clocks_init()
261 clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23); vf610_clocks_init()
262 clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0)); vf610_clocks_init()
263 clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1)); vf610_clocks_init()
265 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7)); vf610_clocks_init()
267 clk[VF610_CLK_UART0] = imx_clk_gate2("uart0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(7)); vf610_clocks_init()
268 clk[VF610_CLK_UART1] = imx_clk_gate2("uart1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(8)); vf610_clocks_init()
269 clk[VF610_CLK_UART2] = imx_clk_gate2("uart2", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(9)); vf610_clocks_init()
270 clk[VF610_CLK_UART3] = imx_clk_gate2("uart3", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(10)); vf610_clocks_init()
271 clk[VF610_CLK_UART4] = imx_clk_gate2("uart4", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(9)); vf610_clocks_init()
272 clk[VF610_CLK_UART5] = imx_clk_gate2("uart5", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(10)); vf610_clocks_init()
274 clk[VF610_CLK_I2C0] = imx_clk_gate2("i2c0", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(6)); vf610_clocks_init()
275 clk[VF610_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(7)); vf610_clocks_init()
276 clk[VF610_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(6)); vf610_clocks_init()
277 clk[VF610_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(7)); vf610_clocks_init()
279 clk[VF610_CLK_DSPI0] = imx_clk_gate2("dspi0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(12)); vf610_clocks_init()
280 clk[VF610_CLK_DSPI1] = imx_clk_gate2("dspi1", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(13)); vf610_clocks_init()
281 clk[VF610_CLK_DSPI2] = imx_clk_gate2("dspi2", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(12)); vf610_clocks_init()
282 clk[VF610_CLK_DSPI3] = imx_clk_gate2("dspi3", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(13)); vf610_clocks_init()
284 clk[VF610_CLK_WDT] = imx_clk_gate2("wdt", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(14)); vf610_clocks_init()
286 clk[VF610_CLK_ESDHC0_SEL] = imx_clk_mux("esdhc0_sel", CCM_CSCMR1, 16, 2, esdhc_sels, 4); vf610_clocks_init()
287 clk[VF610_CLK_ESDHC0_EN] = imx_clk_gate("esdhc0_en", "esdhc0_sel", CCM_CSCDR2, 28); vf610_clocks_init()
288 clk[VF610_CLK_ESDHC0_DIV] = imx_clk_divider("esdhc0_div", "esdhc0_en", CCM_CSCDR2, 16, 4); vf610_clocks_init()
289 clk[VF610_CLK_ESDHC0] = imx_clk_gate2("eshc0", "esdhc0_div", CCM_CCGR7, CCM_CCGRx_CGn(1)); vf610_clocks_init()
291 clk[VF610_CLK_ESDHC1_SEL] = imx_clk_mux("esdhc1_sel", CCM_CSCMR1, 18, 2, esdhc_sels, 4); vf610_clocks_init()
292 clk[VF610_CLK_ESDHC1_EN] = imx_clk_gate("esdhc1_en", "esdhc1_sel", CCM_CSCDR2, 29); vf610_clocks_init()
293 clk[VF610_CLK_ESDHC1_DIV] = imx_clk_divider("esdhc1_div", "esdhc1_en", CCM_CSCDR2, 20, 4); vf610_clocks_init()
294 clk[VF610_CLK_ESDHC1] = imx_clk_gate2("eshc1", "esdhc1_div", CCM_CCGR7, CCM_CCGRx_CGn(2)); vf610_clocks_init()
302 clk[VF610_CLK_FTM0_EXT_SEL] = imx_clk_mux("ftm0_ext_sel", CCM_CSCMR2, 6, 2, ftm_ext_sels, 4); vf610_clocks_init()
303 clk[VF610_CLK_FTM0_FIX_SEL] = imx_clk_mux("ftm0_fix_sel", CCM_CSCMR2, 14, 1, ftm_fix_sels, 2); vf610_clocks_init()
304 clk[VF610_CLK_FTM0_EXT_FIX_EN] = imx_clk_gate("ftm0_ext_fix_en", "dummy", CCM_CSCDR1, 25); vf610_clocks_init()
305 clk[VF610_CLK_FTM1_EXT_SEL] = imx_clk_mux("ftm1_ext_sel", CCM_CSCMR2, 8, 2, ftm_ext_sels, 4); vf610_clocks_init()
306 clk[VF610_CLK_FTM1_FIX_SEL] = imx_clk_mux("ftm1_fix_sel", CCM_CSCMR2, 15, 1, ftm_fix_sels, 2); vf610_clocks_init()
307 clk[VF610_CLK_FTM1_EXT_FIX_EN] = imx_clk_gate("ftm1_ext_fix_en", "dummy", CCM_CSCDR1, 26); vf610_clocks_init()
308 clk[VF610_CLK_FTM2_EXT_SEL] = imx_clk_mux("ftm2_ext_sel", CCM_CSCMR2, 10, 2, ftm_ext_sels, 4); vf610_clocks_init()
309 clk[VF610_CLK_FTM2_FIX_SEL] = imx_clk_mux("ftm2_fix_sel", CCM_CSCMR2, 16, 1, ftm_fix_sels, 2); vf610_clocks_init()
310 clk[VF610_CLK_FTM2_EXT_FIX_EN] = imx_clk_gate("ftm2_ext_fix_en", "dummy", CCM_CSCDR1, 27); vf610_clocks_init()
311 clk[VF610_CLK_FTM3_EXT_SEL] = imx_clk_mux("ftm3_ext_sel", CCM_CSCMR2, 12, 2, ftm_ext_sels, 4); vf610_clocks_init()
312 clk[VF610_CLK_FTM3_FIX_SEL] = imx_clk_mux("ftm3_fix_sel", CCM_CSCMR2, 17, 1, ftm_fix_sels, 2); vf610_clocks_init()
313 clk[VF610_CLK_FTM3_EXT_FIX_EN] = imx_clk_gate("ftm3_ext_fix_en", "dummy", CCM_CSCDR1, 28); vf610_clocks_init()
316 clk[VF610_CLK_FTM0] = imx_clk_gate2("ftm0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(8)); vf610_clocks_init()
317 clk[VF610_CLK_FTM1] = imx_clk_gate2("ftm1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(9)); vf610_clocks_init()
318 clk[VF610_CLK_FTM2] = imx_clk_gate2("ftm2", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(8)); vf610_clocks_init()
319 clk[VF610_CLK_FTM3] = imx_clk_gate2("ftm3", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(9)); vf610_clocks_init()
321 clk[VF610_CLK_DCU0_SEL] = imx_clk_mux("dcu0_sel", CCM_CSCMR1, 28, 1, dcu_sels, 2); vf610_clocks_init()
322 clk[VF610_CLK_DCU0_EN] = imx_clk_gate("dcu0_en", "dcu0_sel", CCM_CSCDR3, 19); vf610_clocks_init()
323 clk[VF610_CLK_DCU0_DIV] = imx_clk_divider("dcu0_div", "dcu0_en", CCM_CSCDR3, 16, 3); vf610_clocks_init()
324 clk[VF610_CLK_DCU0] = imx_clk_gate2("dcu0", "dcu0_div", CCM_CCGR3, CCM_CCGRx_CGn(8)); vf610_clocks_init()
325 clk[VF610_CLK_DCU1_SEL] = imx_clk_mux("dcu1_sel", CCM_CSCMR1, 29, 1, dcu_sels, 2); vf610_clocks_init()
326 clk[VF610_CLK_DCU1_EN] = imx_clk_gate("dcu1_en", "dcu1_sel", CCM_CSCDR3, 23); vf610_clocks_init()
327 clk[VF610_CLK_DCU1_DIV] = imx_clk_divider("dcu1_div", "dcu1_en", CCM_CSCDR3, 20, 3); vf610_clocks_init()
328 clk[VF610_CLK_DCU1] = imx_clk_gate2("dcu1", "dcu1_div", CCM_CCGR9, CCM_CCGRx_CGn(8)); vf610_clocks_init()
330 clk[VF610_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", CCM_CSCMR1, 20, 2, esai_sels, 4); vf610_clocks_init()
331 clk[VF610_CLK_ESAI_EN] = imx_clk_gate("esai_en", "esai_sel", CCM_CSCDR2, 30); vf610_clocks_init()
332 clk[VF610_CLK_ESAI_DIV] = imx_clk_divider("esai_div", "esai_en", CCM_CSCDR2, 24, 4); vf610_clocks_init()
333 clk[VF610_CLK_ESAI] = imx_clk_gate2("esai", "esai_div", CCM_CCGR4, CCM_CCGRx_CGn(2)); vf610_clocks_init()
335 clk[VF610_CLK_SAI0_SEL] = imx_clk_mux("sai0_sel", CCM_CSCMR1, 0, 2, sai_sels, 4); vf610_clocks_init()
336 clk[VF610_CLK_SAI0_EN] = imx_clk_gate("sai0_en", "sai0_sel", CCM_CSCDR1, 16); vf610_clocks_init()
337 clk[VF610_CLK_SAI0_DIV] = imx_clk_divider("sai0_div", "sai0_en", CCM_CSCDR1, 0, 4); vf610_clocks_init()
338 clk[VF610_CLK_SAI0] = imx_clk_gate2("sai0", "ipg_bus", CCM_CCGR0, CCM_CCGRx_CGn(15)); vf610_clocks_init()
340 clk[VF610_CLK_SAI1_SEL] = imx_clk_mux("sai1_sel", CCM_CSCMR1, 2, 2, sai_sels, 4); vf610_clocks_init()
341 clk[VF610_CLK_SAI1_EN] = imx_clk_gate("sai1_en", "sai1_sel", CCM_CSCDR1, 17); vf610_clocks_init()
342 clk[VF610_CLK_SAI1_DIV] = imx_clk_divider("sai1_div", "sai1_en", CCM_CSCDR1, 4, 4); vf610_clocks_init()
343 clk[VF610_CLK_SAI1] = imx_clk_gate2("sai1", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(0)); vf610_clocks_init()
345 clk[VF610_CLK_SAI2_SEL] = imx_clk_mux("sai2_sel", CCM_CSCMR1, 4, 2, sai_sels, 4); vf610_clocks_init()
346 clk[VF610_CLK_SAI2_EN] = imx_clk_gate("sai2_en", "sai2_sel", CCM_CSCDR1, 18); vf610_clocks_init()
347 clk[VF610_CLK_SAI2_DIV] = imx_clk_divider("sai2_div", "sai2_en", CCM_CSCDR1, 8, 4); vf610_clocks_init()
348 clk[VF610_CLK_SAI2] = imx_clk_gate2("sai2", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(1)); vf610_clocks_init()
350 clk[VF610_CLK_SAI3_SEL] = imx_clk_mux("sai3_sel", CCM_CSCMR1, 6, 2, sai_sels, 4); vf610_clocks_init()
351 clk[VF610_CLK_SAI3_EN] = imx_clk_gate("sai3_en", "sai3_sel", CCM_CSCDR1, 19); vf610_clocks_init()
352 clk[VF610_CLK_SAI3_DIV] = imx_clk_divider("sai3_div", "sai3_en", CCM_CSCDR1, 12, 4); vf610_clocks_init()
353 clk[VF610_CLK_SAI3] = imx_clk_gate2("sai3", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(2)); vf610_clocks_init()
355 clk[VF610_CLK_NFC_SEL] = imx_clk_mux("nfc_sel", CCM_CSCMR1, 12, 2, nfc_sels, 4); vf610_clocks_init()
356 clk[VF610_CLK_NFC_EN] = imx_clk_gate("nfc_en", "nfc_sel", CCM_CSCDR2, 9); vf610_clocks_init()
357 clk[VF610_CLK_NFC_PRE_DIV] = imx_clk_divider("nfc_pre_div", "nfc_en", CCM_CSCDR3, 13, 3); vf610_clocks_init()
358 clk[VF610_CLK_NFC_FRAC_DIV] = imx_clk_divider("nfc_frac_div", "nfc_pre_div", CCM_CSCDR2, 4, 4); vf610_clocks_init()
359 clk[VF610_CLK_NFC] = imx_clk_gate2("nfc", "nfc_frac_div", CCM_CCGR10, CCM_CCGRx_CGn(0)); vf610_clocks_init()
361 clk[VF610_CLK_GPU_SEL] = imx_clk_mux("gpu_sel", CCM_CSCMR1, 14, 1, gpu_sels, 2); vf610_clocks_init()
362 clk[VF610_CLK_GPU_EN] = imx_clk_gate("gpu_en", "gpu_sel", CCM_CSCDR2, 10); vf610_clocks_init()
363 clk[VF610_CLK_GPU2D] = imx_clk_gate2("gpu", "gpu_en", CCM_CCGR8, CCM_CCGRx_CGn(15)); vf610_clocks_init()
365 clk[VF610_CLK_VADC_SEL] = imx_clk_mux("vadc_sel", CCM_CSCMR1, 8, 2, vadc_sels, 3); vf610_clocks_init()
366 clk[VF610_CLK_VADC_EN] = imx_clk_gate("vadc_en", "vadc_sel", CCM_CSCDR1, 22); vf610_clocks_init()
367 clk[VF610_CLK_VADC_DIV] = imx_clk_divider("vadc_div", "vadc_en", CCM_CSCDR1, 20, 2); vf610_clocks_init()
368 clk[VF610_CLK_VADC_DIV_HALF] = imx_clk_fixed_factor("vadc_div_half", "vadc_div", 1, 2); vf610_clocks_init()
369 clk[VF610_CLK_VADC] = imx_clk_gate2("vadc", "vadc_div", CCM_CCGR8, CCM_CCGRx_CGn(7)); vf610_clocks_init()
371 clk[VF610_CLK_ADC0] = imx_clk_gate2("adc0", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(11)); vf610_clocks_init()
372 clk[VF610_CLK_ADC1] = imx_clk_gate2("adc1", "ipg_bus", CCM_CCGR7, CCM_CCGRx_CGn(11)); vf610_clocks_init()
373 clk[VF610_CLK_DAC0] = imx_clk_gate2("dac0", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(12)); vf610_clocks_init()
374 clk[VF610_CLK_DAC1] = imx_clk_gate2("dac1", "ipg_bus", CCM_CCGR8, CCM_CCGRx_CGn(13)); vf610_clocks_init()
376 clk[VF610_CLK_ASRC] = imx_clk_gate2("asrc", "ipg_bus", CCM_CCGR4, CCM_CCGRx_CGn(1)); vf610_clocks_init()
378 clk[VF610_CLK_FLEXCAN0_EN] = imx_clk_gate("flexcan0_en", "ipg_bus", CCM_CSCDR2, 11); vf610_clocks_init()
379 clk[VF610_CLK_FLEXCAN0] = imx_clk_gate2("flexcan0", "flexcan0_en", CCM_CCGR0, CCM_CCGRx_CGn(0)); vf610_clocks_init()
380 clk[VF610_CLK_FLEXCAN1_EN] = imx_clk_gate("flexcan1_en", "ipg_bus", CCM_CSCDR2, 12); vf610_clocks_init()
381 clk[VF610_CLK_FLEXCAN1] = imx_clk_gate2("flexcan1", "flexcan1_en", CCM_CCGR9, CCM_CCGRx_CGn(4)); vf610_clocks_init()
383 clk[VF610_CLK_DMAMUX0] = imx_clk_gate2("dmamux0", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(4)); vf610_clocks_init()
384 clk[VF610_CLK_DMAMUX1] = imx_clk_gate2("dmamux1", "platform_bus", CCM_CCGR0, CCM_CCGRx_CGn(5)); vf610_clocks_init()
385 clk[VF610_CLK_DMAMUX2] = imx_clk_gate2("dmamux2", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(1)); vf610_clocks_init()
386 clk[VF610_CLK_DMAMUX3] = imx_clk_gate2("dmamux3", "platform_bus", CCM_CCGR6, CCM_CCGRx_CGn(2)); vf610_clocks_init()
388 clk[VF610_CLK_SNVS] = imx_clk_gate2("snvs-rtc", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(7)); vf610_clocks_init()
389 clk[VF610_CLK_DAP] = imx_clk_gate("dap", "platform_bus", CCM_CCSR, 24); vf610_clocks_init()
390 clk[VF610_CLK_OCOTP] = imx_clk_gate("ocotp", "ipg_bus", CCM_CCGR6, CCM_CCGRx_CGn(5)); vf610_clocks_init()
392 imx_check_clocks(clk, ARRAY_SIZE(clk)); vf610_clocks_init()
394 clk_set_parent(clk[VF610_CLK_QSPI0_SEL], clk[VF610_CLK_PLL1_PFD4]); vf610_clocks_init()
395 clk_set_rate(clk[VF610_CLK_QSPI0_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_SEL]) / 2); vf610_clocks_init()
396 clk_set_rate(clk[VF610_CLK_QSPI0_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X4_DIV]) / 2); vf610_clocks_init()
397 clk_set_rate(clk[VF610_CLK_QSPI0_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI0_X2_DIV]) / 2); vf610_clocks_init()
399 clk_set_parent(clk[VF610_CLK_QSPI1_SEL], clk[VF610_CLK_PLL1_PFD4]); vf610_clocks_init()
400 clk_set_rate(clk[VF610_CLK_QSPI1_X4_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_SEL]) / 2); vf610_clocks_init()
401 clk_set_rate(clk[VF610_CLK_QSPI1_X2_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X4_DIV]) / 2); vf610_clocks_init()
402 clk_set_rate(clk[VF610_CLK_QSPI1_X1_DIV], clk_get_rate(clk[VF610_CLK_QSPI1_X2_DIV]) / 2); vf610_clocks_init()
404 clk_set_parent(clk[VF610_CLK_SAI0_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
405 clk_set_parent(clk[VF610_CLK_SAI1_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
406 clk_set_parent(clk[VF610_CLK_SAI2_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
407 clk_set_parent(clk[VF610_CLK_SAI3_SEL], clk[VF610_CLK_AUDIO_EXT]); vf610_clocks_init()
410 clk_prepare_enable(clk[clks_init_on[i]]); vf610_clocks_init()
413 clk_data.clks = clk; vf610_clocks_init()
414 clk_data.clk_num = ARRAY_SIZE(clk); vf610_clocks_init()
|
| H A D | clk-imx35.c | 11 #include <linux/clk.h>
20 #include "clk.h"
85 static struct clk *clk[clk_max]; variable in typeref:struct:clk
87 static struct clk ** const uart_clks[] __initconst = {
88 &clk[ipg],
89 &clk[uart1_gate],
90 &clk[uart2_gate],
91 &clk[uart3_gate],
109 pr_err("i.MX35 clk: illegal consumer mux selection 0x%x\n", consumer_sel); _mx35_clocks_init()
117 clk[ckih] = imx_clk_fixed("ckih", 24000000); _mx35_clocks_init()
118 clk[ckil] = imx_clk_fixed("ckih", 32768); _mx35_clocks_init()
119 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); _mx35_clocks_init()
120 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); _mx35_clocks_init()
122 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); _mx35_clocks_init()
125 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); _mx35_clocks_init()
127 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); _mx35_clocks_init()
129 if (clk_get_rate(clk[arm]) > 400000000) _mx35_clocks_init()
136 pr_err("i.MX35 clk: illegal hsp clk selection 0x%x\n", hsp_sel); _mx35_clocks_init()
140 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); _mx35_clocks_init()
142 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); _mx35_clocks_init()
143 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); _mx35_clocks_init()
145 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); _mx35_clocks_init()
146 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); _mx35_clocks_init()
147 clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_sel)); _mx35_clocks_init()
149 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
150 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); _mx35_clocks_init()
152 clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
153 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); _mx35_clocks_init()
154 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); _mx35_clocks_init()
155 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); _mx35_clocks_init()
157 clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
158 clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /* divide by 1 not allowed */ _mx35_clocks_init()
159 clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23, 6); _mx35_clocks_init()
161 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
162 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); _mx35_clocks_init()
163 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); _mx35_clocks_init()
164 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); _mx35_clocks_init()
165 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); _mx35_clocks_init()
167 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
168 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); _mx35_clocks_init()
170 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); _mx35_clocks_init()
172 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); _mx35_clocks_init()
173 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); _mx35_clocks_init()
175 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); _mx35_clocks_init()
176 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); _mx35_clocks_init()
177 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); _mx35_clocks_init()
178 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); _mx35_clocks_init()
179 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); _mx35_clocks_init()
180 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); _mx35_clocks_init()
181 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); _mx35_clocks_init()
182 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); _mx35_clocks_init()
183 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); _mx35_clocks_init()
184 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); _mx35_clocks_init()
185 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); _mx35_clocks_init()
186 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); _mx35_clocks_init()
187 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); _mx35_clocks_init()
188 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); _mx35_clocks_init()
189 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); _mx35_clocks_init()
190 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); _mx35_clocks_init()
192 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); _mx35_clocks_init()
193 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); _mx35_clocks_init()
194 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); _mx35_clocks_init()
195 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); _mx35_clocks_init()
196 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); _mx35_clocks_init()
197 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); _mx35_clocks_init()
198 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); _mx35_clocks_init()
199 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); _mx35_clocks_init()
200 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); _mx35_clocks_init()
201 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); _mx35_clocks_init()
202 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); _mx35_clocks_init()
203 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); _mx35_clocks_init()
204 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); _mx35_clocks_init()
205 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); _mx35_clocks_init()
206 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); _mx35_clocks_init()
207 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); _mx35_clocks_init()
209 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); _mx35_clocks_init()
210 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); _mx35_clocks_init()
211 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); _mx35_clocks_init()
212 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); _mx35_clocks_init()
213 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); _mx35_clocks_init()
214 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); _mx35_clocks_init()
215 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); _mx35_clocks_init()
216 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); _mx35_clocks_init()
217 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); _mx35_clocks_init()
218 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); _mx35_clocks_init()
219 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); _mx35_clocks_init()
220 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); _mx35_clocks_init()
221 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); _mx35_clocks_init()
222 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); _mx35_clocks_init()
223 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); _mx35_clocks_init()
225 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); _mx35_clocks_init()
226 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); _mx35_clocks_init()
227 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); _mx35_clocks_init()
229 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx35_clocks_init()
231 clk_prepare_enable(clk[spba_gate]); _mx35_clocks_init()
232 clk_prepare_enable(clk[gpio1_gate]); _mx35_clocks_init()
233 clk_prepare_enable(clk[gpio2_gate]); _mx35_clocks_init()
234 clk_prepare_enable(clk[gpio3_gate]); _mx35_clocks_init()
235 clk_prepare_enable(clk[iim_gate]); _mx35_clocks_init()
236 clk_prepare_enable(clk[emi_gate]); _mx35_clocks_init()
237 clk_prepare_enable(clk[max_gate]); _mx35_clocks_init()
238 clk_prepare_enable(clk[iomuxc_gate]); _mx35_clocks_init()
242 * before conversion to common clk also enabled UART1 (which isn't _mx35_clocks_init()
246 clk_prepare_enable(clk[scc_gate]); _mx35_clocks_init()
257 clk_register_clkdev(clk[pata_gate], NULL, "pata_imx"); mx35_clocks_init()
258 clk_register_clkdev(clk[can1_gate], NULL, "flexcan.0"); mx35_clocks_init()
259 clk_register_clkdev(clk[can2_gate], NULL, "flexcan.1"); mx35_clocks_init()
260 clk_register_clkdev(clk[cspi1_gate], "per", "imx35-cspi.0"); mx35_clocks_init()
261 clk_register_clkdev(clk[cspi1_gate], "ipg", "imx35-cspi.0"); mx35_clocks_init()
262 clk_register_clkdev(clk[cspi2_gate], "per", "imx35-cspi.1"); mx35_clocks_init()
263 clk_register_clkdev(clk[cspi2_gate], "ipg", "imx35-cspi.1"); mx35_clocks_init()
264 clk_register_clkdev(clk[epit1_gate], NULL, "imx-epit.0"); mx35_clocks_init()
265 clk_register_clkdev(clk[epit2_gate], NULL, "imx-epit.1"); mx35_clocks_init()
266 clk_register_clkdev(clk[esdhc1_gate], "per", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
267 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
268 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.0"); mx35_clocks_init()
269 clk_register_clkdev(clk[esdhc2_gate], "per", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
270 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
271 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.1"); mx35_clocks_init()
272 clk_register_clkdev(clk[esdhc3_gate], "per", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
273 clk_register_clkdev(clk[ipg], "ipg", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
274 clk_register_clkdev(clk[ahb], "ahb", "sdhci-esdhc-imx35.2"); mx35_clocks_init()
276 clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0"); mx35_clocks_init()
277 clk_register_clkdev(clk[gpt_gate], "per", "imx-gpt.0"); mx35_clocks_init()
278 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); mx35_clocks_init()
279 clk_register_clkdev(clk[i2c1_gate], NULL, "imx21-i2c.0"); mx35_clocks_init()
280 clk_register_clkdev(clk[i2c2_gate], NULL, "imx21-i2c.1"); mx35_clocks_init()
281 clk_register_clkdev(clk[i2c3_gate], NULL, "imx21-i2c.2"); mx35_clocks_init()
282 clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core"); mx35_clocks_init()
283 clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb"); mx35_clocks_init()
284 clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad"); mx35_clocks_init()
285 clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1"); mx35_clocks_init()
286 clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma"); mx35_clocks_init()
287 clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0"); mx35_clocks_init()
288 clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1"); mx35_clocks_init()
290 clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0"); mx35_clocks_init()
291 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0"); mx35_clocks_init()
292 clk_register_clkdev(clk[uart2_gate], "per", "imx21-uart.1"); mx35_clocks_init()
293 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); mx35_clocks_init()
294 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); mx35_clocks_init()
295 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); mx35_clocks_init()
297 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc"); mx35_clocks_init()
298 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc"); mx35_clocks_init()
299 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); mx35_clocks_init()
300 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); mx35_clocks_init()
301 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); mx35_clocks_init()
302 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.1"); mx35_clocks_init()
303 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.1"); mx35_clocks_init()
304 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.1"); mx35_clocks_init()
305 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2"); mx35_clocks_init()
306 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.2"); mx35_clocks_init()
307 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.2"); mx35_clocks_init()
308 clk_register_clkdev(clk[usb_div], "per", "imx-udc-mx27"); mx35_clocks_init()
309 clk_register_clkdev(clk[ipg], "ipg", "imx-udc-mx27"); mx35_clocks_init()
310 clk_register_clkdev(clk[usbotg_gate], "ahb", "imx-udc-mx27"); mx35_clocks_init()
311 clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0"); mx35_clocks_init()
312 clk_register_clkdev(clk[nfc_div], NULL, "imx25-nand.0"); mx35_clocks_init()
313 clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0"); mx35_clocks_init()
314 clk_register_clkdev(clk[admux_gate], "audmux", NULL); mx35_clocks_init()
325 clk_data.clks = clk; mx35_clocks_init_dt()
326 clk_data.clk_num = ARRAY_SIZE(clk); mx35_clocks_init_dt()
|
| H A D | clk-imx1.c | 19 #include <linux/clk-provider.h>
28 #include "clk.h"
38 static struct clk *clk[IMX1_CLK_MAX]; variable in typeref:struct:clk
50 clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0); _mx1_clocks_init()
51 clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref); _mx1_clocks_init()
52 clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000); _mx1_clocks_init()
53 clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17); _mx1_clocks_init()
54 clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1); _mx1_clocks_init()
55 clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks)); _mx1_clocks_init()
56 clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0); _mx1_clocks_init()
57 clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0); _mx1_clocks_init()
58 clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0); _mx1_clocks_init()
59 clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1); _mx1_clocks_init()
60 clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); _mx1_clocks_init()
61 clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1); _mx1_clocks_init()
62 clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4); _mx1_clocks_init()
63 clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3); _mx1_clocks_init()
64 clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4); _mx1_clocks_init()
65 clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4); _mx1_clocks_init()
66 clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7); _mx1_clocks_init()
67 clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks)); _mx1_clocks_init()
68 clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6); _mx1_clocks_init()
69 clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5); _mx1_clocks_init()
70 clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4); _mx1_clocks_init()
71 clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3); _mx1_clocks_init()
72 clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); _mx1_clocks_init()
73 clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); _mx1_clocks_init()
74 clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); _mx1_clocks_init()
76 imx_check_clocks(clk, ARRAY_SIZE(clk)); _mx1_clocks_init()
86 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx-gpt.0"); mx1_clocks_init()
87 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx-gpt.0"); mx1_clocks_init()
88 clk_register_clkdev(clk[IMX1_CLK_DMA_GATE], "ahb", "imx1-dma"); mx1_clocks_init()
89 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-dma"); mx1_clocks_init()
90 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.0"); mx1_clocks_init()
91 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.0"); mx1_clocks_init()
92 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.1"); mx1_clocks_init()
93 clk_register_clkdev(clk[IMX1_CLK_HCLK], "ipg", "imx1-uart.1"); mx1_clocks_init()
94 clk_register_clkdev(clk[IMX1_CLK_PER1], "per", "imx1-uart.2"); mx1_clocks_init()
95 clk_register_clkdev(clk[IMX1_CLK_UART3_GATE], "ipg", "imx1-uart.2"); mx1_clocks_init()
96 clk_register_clkdev(clk[IMX1_CLK_HCLK], NULL, "imx1-i2c.0"); mx1_clocks_init()
97 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.0"); mx1_clocks_init()
98 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.0"); mx1_clocks_init()
99 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-cspi.1"); mx1_clocks_init()
100 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-cspi.1"); mx1_clocks_init()
101 clk_register_clkdev(clk[IMX1_CLK_PER2], "per", "imx1-fb.0"); mx1_clocks_init()
102 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ipg", "imx1-fb.0"); mx1_clocks_init()
103 clk_register_clkdev(clk[IMX1_CLK_DUMMY], "ahb", "imx1-fb.0"); mx1_clocks_init()
117 clk_data.clks = clk; mx1_clocks_init_dt()
118 clk_data.clk_num = ARRAY_SIZE(clk); mx1_clocks_init_dt()
|
| H A D | clk-imx6q.c | 15 #include <linux/clk.h>
25 #include "clk.h"
84 static struct clk *clk[IMX6QDL_CLK_END]; variable in typeref:struct:clk
134 static struct clk ** const uart_clks[] __initconst = {
135 &clk[IMX6QDL_CLK_UART_IPG],
136 &clk[IMX6QDL_CLK_UART_SERIAL],
147 clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); imx6q_clocks_init()
148 clk[IMX6QDL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); imx6q_clocks_init()
149 clk[IMX6QDL_CLK_CKIH] = imx_obtain_fixed_clock("ckih1", 0); imx6q_clocks_init()
150 clk[IMX6QDL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); imx6q_clocks_init()
152 clk[IMX6QDL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); imx6q_clocks_init()
153 clk[IMX6QDL_CLK_ANACLK2] = imx_obtain_fixed_clock("anaclk2", 0); imx6q_clocks_init()
167 clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
168 clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
169 clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
170 clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
171 clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
172 clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
173 clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); imx6q_clocks_init()
176 clk[IMX6QDL_CLK_PLL1] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1", "pll1_bypass_src", base + 0x00, 0x7f); imx6q_clocks_init()
177 clk[IMX6QDL_CLK_PLL2] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2", "pll2_bypass_src", base + 0x30, 0x1); imx6q_clocks_init()
178 clk[IMX6QDL_CLK_PLL3] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3", "pll3_bypass_src", base + 0x10, 0x3); imx6q_clocks_init()
179 clk[IMX6QDL_CLK_PLL4] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4", "pll4_bypass_src", base + 0x70, 0x7f); imx6q_clocks_init()
180 clk[IMX6QDL_CLK_PLL5] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5", "pll5_bypass_src", base + 0xa0, 0x7f); imx6q_clocks_init()
181 clk[IMX6QDL_CLK_PLL6] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "pll6_bypass_src", base + 0xe0, 0x3); imx6q_clocks_init()
182 clk[IMX6QDL_CLK_PLL7] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7", "pll7_bypass_src", base + 0x20, 0x3); imx6q_clocks_init()
184 clk[IMX6QDL_PLL1_BYPASS] = imx_clk_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
185 clk[IMX6QDL_PLL2_BYPASS] = imx_clk_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
186 clk[IMX6QDL_PLL3_BYPASS] = imx_clk_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
187 clk[IMX6QDL_PLL4_BYPASS] = imx_clk_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
188 clk[IMX6QDL_PLL5_BYPASS] = imx_clk_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
189 clk[IMX6QDL_PLL6_BYPASS] = imx_clk_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
190 clk[IMX6QDL_PLL7_BYPASS] = imx_clk_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
193 clk_set_parent(clk[IMX6QDL_PLL1_BYPASS], clk[IMX6QDL_CLK_PLL1]); imx6q_clocks_init()
194 clk_set_parent(clk[IMX6QDL_PLL2_BYPASS], clk[IMX6QDL_CLK_PLL2]); imx6q_clocks_init()
195 clk_set_parent(clk[IMX6QDL_PLL3_BYPASS], clk[IMX6QDL_CLK_PLL3]); imx6q_clocks_init()
196 clk_set_parent(clk[IMX6QDL_PLL4_BYPASS], clk[IMX6QDL_CLK_PLL4]); imx6q_clocks_init()
197 clk_set_parent(clk[IMX6QDL_PLL5_BYPASS], clk[IMX6QDL_CLK_PLL5]); imx6q_clocks_init()
198 clk_set_parent(clk[IMX6QDL_PLL6_BYPASS], clk[IMX6QDL_CLK_PLL6]); imx6q_clocks_init()
199 clk_set_parent(clk[IMX6QDL_PLL7_BYPASS], clk[IMX6QDL_CLK_PLL7]); imx6q_clocks_init()
201 clk[IMX6QDL_CLK_PLL1_SYS] = imx_clk_gate("pll1_sys", "pll1_bypass", base + 0x00, 13); imx6q_clocks_init()
202 clk[IMX6QDL_CLK_PLL2_BUS] = imx_clk_gate("pll2_bus", "pll2_bypass", base + 0x30, 13); imx6q_clocks_init()
203 clk[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13); imx6q_clocks_init()
204 clk[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_gate("pll4_audio", "pll4_bypass", base + 0x70, 13); imx6q_clocks_init()
205 clk[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_gate("pll5_video", "pll5_bypass", base + 0xa0, 13); imx6q_clocks_init()
206 clk[IMX6QDL_CLK_PLL6_ENET] = imx_clk_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13); imx6q_clocks_init()
207 clk[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13); imx6q_clocks_init()
213 * the clk framework may need to enable/disable usbphy's parent imx6q_clocks_init()
215 clk[IMX6QDL_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20); imx6q_clocks_init()
216 clk[IMX6QDL_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20); imx6q_clocks_init()
222 clk[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6); imx6q_clocks_init()
223 clk[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6); imx6q_clocks_init()
225 clk[IMX6QDL_CLK_SATA_REF] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5); imx6q_clocks_init()
226 clk[IMX6QDL_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4); imx6q_clocks_init()
228 clk[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20); imx6q_clocks_init()
229 clk[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19); imx6q_clocks_init()
231 clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, imx6q_clocks_init()
235 clk[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6q_clocks_init()
236 clk[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); imx6q_clocks_init()
244 clk[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12)); imx6q_clocks_init()
245 clk[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13)); imx6q_clocks_init()
247 clk[IMX6QDL_CLK_LVDS1_IN] = imx_clk_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10)); imx6q_clocks_init()
248 clk[IMX6QDL_CLK_LVDS2_IN] = imx_clk_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11)); imx6q_clocks_init()
251 clk[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); imx6q_clocks_init()
252 clk[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); imx6q_clocks_init()
253 clk[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2); imx6q_clocks_init()
254 clk[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0); imx6q_clocks_init()
255 clk[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1); imx6q_clocks_init()
256 clk[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2); imx6q_clocks_init()
257 clk[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3); imx6q_clocks_init()
260 clk[IMX6QDL_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2); imx6q_clocks_init()
261 clk[IMX6QDL_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4); imx6q_clocks_init()
262 clk[IMX6QDL_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6); imx6q_clocks_init()
263 clk[IMX6QDL_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8); imx6q_clocks_init()
264 clk[IMX6QDL_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2); imx6q_clocks_init()
265 clk[IMX6QDL_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); imx6q_clocks_init()
266 clk[IMX6QDL_CLK_VIDEO_27M] = imx_clk_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20); imx6q_clocks_init()
268 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1); imx6q_clocks_init()
269 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1); imx6q_clocks_init()
272 clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
273 clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); imx6q_clocks_init()
274 clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); imx6q_clocks_init()
275 clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); imx6q_clocks_init()
282 clk[IMX6QDL_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels)); imx6q_clocks_init()
283 clk[IMX6QDL_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels)); imx6q_clocks_init()
284 clk[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6q_clocks_init()
285 clk[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels)); imx6q_clocks_init()
286 clk[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); imx6q_clocks_init()
287 clk[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels)); imx6q_clocks_init()
288 clk[IMX6QDL_CLK_AXI_SEL] = imx_clk_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels)); imx6q_clocks_init()
289 clk[IMX6QDL_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
290 clk[IMX6QDL_CLK_ASRC_SEL] = imx_clk_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
291 clk[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels)); imx6q_clocks_init()
293 clk[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6q_clocks_init()
294 clk[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels)); imx6q_clocks_init()
296 clk[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels)); imx6q_clocks_init()
297 clk[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels)); imx6q_clocks_init()
298 clk[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels)); imx6q_clocks_init()
299 clk[IMX6QDL_CLK_IPU1_SEL] = imx_clk_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); imx6q_clocks_init()
300 clk[IMX6QDL_CLK_IPU2_SEL] = imx_clk_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels)); imx6q_clocks_init()
301 clk[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
302 clk[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
303 clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
304 clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
305 clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
306 clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
307 clk[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
308 clk[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
309 clk[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
310 clk[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT); imx6q_clocks_init()
311 clk[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); imx6q_clocks_init()
312 clk[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); imx6q_clocks_init()
313 clk[IMX6QDL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
314 clk[IMX6QDL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
315 clk[IMX6QDL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup); imx6q_clocks_init()
316 clk[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
317 clk[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
318 clk[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
319 clk[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup); imx6q_clocks_init()
320 clk[IMX6QDL_CLK_ENFC_SEL] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); imx6q_clocks_init()
321 clk[IMX6QDL_CLK_EIM_SEL] = imx_clk_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup); imx6q_clocks_init()
322 clk[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup); imx6q_clocks_init()
323 clk[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); imx6q_clocks_init()
324 clk[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); imx6q_clocks_init()
325 clk[IMX6QDL_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); imx6q_clocks_init()
326 clk[IMX6QDL_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels)); imx6q_clocks_init()
327 clk[IMX6QDL_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels)); imx6q_clocks_init()
330 clk[IMX6QDL_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); imx6q_clocks_init()
331 clk[IMX6QDL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels)); imx6q_clocks_init()
334 clk[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); imx6q_clocks_init()
335 clk[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); imx6q_clocks_init()
336 clk[IMX6QDL_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); imx6q_clocks_init()
337 clk[IMX6QDL_CLK_IPG_PER] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup); imx6q_clocks_init()
338 clk[IMX6QDL_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); imx6q_clocks_init()
339 clk[IMX6QDL_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); imx6q_clocks_init()
340 clk[IMX6QDL_CLK_ASRC_PRED] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); imx6q_clocks_init()
341 clk[IMX6QDL_CLK_ASRC_PODF] = imx_clk_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3); imx6q_clocks_init()
342 clk[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3); imx6q_clocks_init()
343 clk[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3); imx6q_clocks_init()
344 clk[IMX6QDL_CLK_CAN_ROOT] = imx_clk_divider("can_root", "pll3_60m", base + 0x20, 2, 6); imx6q_clocks_init()
345 clk[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6); imx6q_clocks_init()
346 clk[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3); imx6q_clocks_init()
347 clk[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3); imx6q_clocks_init()
348 clk[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3); imx6q_clocks_init()
349 clk[IMX6QDL_CLK_IPU1_PODF] = imx_clk_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3); imx6q_clocks_init()
350 clk[IMX6QDL_CLK_IPU2_PODF] = imx_clk_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3); imx6q_clocks_init()
351 clk[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7); imx6q_clocks_init()
352 clk[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0); imx6q_clocks_init()
353 clk[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7); imx6q_clocks_init()
354 clk[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0); imx6q_clocks_init()
355 clk[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3); imx6q_clocks_init()
356 clk[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3); imx6q_clocks_init()
357 clk[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3); imx6q_clocks_init()
358 clk[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3); imx6q_clocks_init()
359 clk[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3); imx6q_clocks_init()
360 clk[IMX6QDL_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3); imx6q_clocks_init()
361 clk[IMX6QDL_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6); imx6q_clocks_init()
362 clk[IMX6QDL_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3); imx6q_clocks_init()
363 clk[IMX6QDL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); imx6q_clocks_init()
364 clk[IMX6QDL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); imx6q_clocks_init()
365 clk[IMX6QDL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); imx6q_clocks_init()
366 clk[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6); imx6q_clocks_init()
367 clk[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3); imx6q_clocks_init()
368 clk[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3); imx6q_clocks_init()
369 clk[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3); imx6q_clocks_init()
370 clk[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); imx6q_clocks_init()
371 clk[IMX6QDL_CLK_ENFC_PRED] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); imx6q_clocks_init()
372 clk[IMX6QDL_CLK_ENFC_PODF] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); imx6q_clocks_init()
373 clk[IMX6QDL_CLK_EIM_PODF] = imx_clk_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup); imx6q_clocks_init()
374 clk[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup); imx6q_clocks_init()
375 clk[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); imx6q_clocks_init()
376 clk[IMX6QDL_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); imx6q_clocks_init()
377 clk[IMX6QDL_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3); imx6q_clocks_init()
380 clk[IMX6QDL_CLK_AXI] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); imx6q_clocks_init()
381 clk[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4); imx6q_clocks_init()
382 clk[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2); imx6q_clocks_init()
383 clk[IMX6QDL_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16); imx6q_clocks_init()
384 clk[IMX6QDL_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1); imx6q_clocks_init()
387 clk[IMX6QDL_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4); imx6q_clocks_init()
388 clk[IMX6QDL_CLK_ASRC] = imx_clk_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
389 clk[IMX6QDL_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
390 clk[IMX6QDL_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc); imx6q_clocks_init()
391 clk[IMX6QDL_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8); imx6q_clocks_init()
392 clk[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10); imx6q_clocks_init()
393 clk[IMX6QDL_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12); imx6q_clocks_init()
394 clk[IMX6QDL_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14); imx6q_clocks_init()
395 clk[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_root", base + 0x68, 16); imx6q_clocks_init()
396 clk[IMX6QDL_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18); imx6q_clocks_init()
397 clk[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_root", base + 0x68, 20); imx6q_clocks_init()
398 clk[IMX6QDL_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0); imx6q_clocks_init()
399 clk[IMX6QDL_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); imx6q_clocks_init()
400 clk[IMX6QDL_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); imx6q_clocks_init()
401 clk[IMX6QDL_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); imx6q_clocks_init()
403 clk[IMX6DL_CLK_I2C4] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8); imx6q_clocks_init()
405 clk[IMX6Q_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); imx6q_clocks_init()
406 clk[IMX6QDL_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); imx6q_clocks_init()
407 clk[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
408 clk[IMX6QDL_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
409 clk[IMX6QDL_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai); imx6q_clocks_init()
410 clk[IMX6QDL_CLK_GPT_IPG] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); imx6q_clocks_init()
411 clk[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); imx6q_clocks_init()
417 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu3d_shader", base + 0x6c, 24); imx6q_clocks_init()
419 clk[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24); imx6q_clocks_init()
420 clk[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26); imx6q_clocks_init()
421 clk[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_gate2("hdmi_iahb", "ahb", base + 0x70, 0); imx6q_clocks_init()
422 clk[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_gate2("hdmi_isfr", "video_27m", base + 0x70, 4); imx6q_clocks_init()
423 clk[IMX6QDL_CLK_I2C1] = imx_clk_gate2("i2c1", "ipg_per", base + 0x70, 6); imx6q_clocks_init()
424 clk[IMX6QDL_CLK_I2C2] = imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8); imx6q_clocks_init()
425 clk[IMX6QDL_CLK_I2C3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); imx6q_clocks_init()
426 clk[IMX6QDL_CLK_IIM] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); imx6q_clocks_init()
427 clk[IMX6QDL_CLK_ENFC] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); imx6q_clocks_init()
428 clk[IMX6QDL_CLK_VDOA] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26); imx6q_clocks_init()
429 clk[IMX6QDL_CLK_IPU1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); imx6q_clocks_init()
430 clk[IMX6QDL_CLK_IPU1_DI0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); imx6q_clocks_init()
431 clk[IMX6QDL_CLK_IPU1_DI1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); imx6q_clocks_init()
432 clk[IMX6QDL_CLK_IPU2] = imx_clk_gate2("ipu2", "ipu2_podf", base + 0x74, 6); imx6q_clocks_init()
433 clk[IMX6QDL_CLK_IPU2_DI0] = imx_clk_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8); imx6q_clocks_init()
434 clk[IMX6QDL_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12); imx6q_clocks_init()
435 clk[IMX6QDL_CLK_LDB_DI1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14); imx6q_clocks_init()
436 clk[IMX6QDL_CLK_IPU2_DI1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10); imx6q_clocks_init()
437 clk[IMX6QDL_CLK_HSI_TX] = imx_clk_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
438 clk[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
439 clk[IMX6QDL_CLK_MIPI_IPG] = imx_clk_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg); imx6q_clocks_init()
445 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "gpu2d_core_podf", base + 0x74, 18); imx6q_clocks_init()
447 clk[IMX6QDL_CLK_MLB] = imx_clk_gate2("mlb", "axi", base + 0x74, 18); imx6q_clocks_init()
448 clk[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20); imx6q_clocks_init()
449 clk[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22); imx6q_clocks_init()
450 clk[IMX6QDL_CLK_OCRAM] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28); imx6q_clocks_init()
451 clk[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_gate2("openvg_axi", "axi", base + 0x74, 30); imx6q_clocks_init()
452 clk[IMX6QDL_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0); imx6q_clocks_init()
453 clk[IMX6QDL_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12); imx6q_clocks_init()
454 clk[IMX6QDL_CLK_PWM1] = imx_clk_gate2("pwm1", "ipg_per", base + 0x78, 16); imx6q_clocks_init()
455 clk[IMX6QDL_CLK_PWM2] = imx_clk_gate2("pwm2", "ipg_per", base + 0x78, 18); imx6q_clocks_init()
456 clk[IMX6QDL_CLK_PWM3] = imx_clk_gate2("pwm3", "ipg_per", base + 0x78, 20); imx6q_clocks_init()
457 clk[IMX6QDL_CLK_PWM4] = imx_clk_gate2("pwm4", "ipg_per", base + 0x78, 22); imx6q_clocks_init()
458 clk[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24); imx6q_clocks_init()
459 clk[IMX6QDL_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26); imx6q_clocks_init()
460 clk[IMX6QDL_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "enfc", base + 0x78, 28); imx6q_clocks_init()
461 clk[IMX6QDL_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30); imx6q_clocks_init()
462 clk[IMX6QDL_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0); imx6q_clocks_init()
463 clk[IMX6QDL_CLK_SATA] = imx_clk_gate2("sata", "ahb", base + 0x7c, 4); imx6q_clocks_init()
464 clk[IMX6QDL_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); imx6q_clocks_init()
465 clk[IMX6QDL_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); imx6q_clocks_init()
466 clk[IMX6QDL_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif); imx6q_clocks_init()
467 clk[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif); imx6q_clocks_init()
468 clk[IMX6QDL_CLK_SSI1_IPG] = imx_clk_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
469 clk[IMX6QDL_CLK_SSI2_IPG] = imx_clk_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
470 clk[IMX6QDL_CLK_SSI3_IPG] = imx_clk_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
471 clk[IMX6QDL_CLK_SSI1] = imx_clk_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1); imx6q_clocks_init()
472 clk[IMX6QDL_CLK_SSI2] = imx_clk_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2); imx6q_clocks_init()
473 clk[IMX6QDL_CLK_SSI3] = imx_clk_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3); imx6q_clocks_init()
474 clk[IMX6QDL_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24); imx6q_clocks_init()
475 clk[IMX6QDL_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26); imx6q_clocks_init()
476 clk[IMX6QDL_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0); imx6q_clocks_init()
477 clk[IMX6QDL_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2); imx6q_clocks_init()
478 clk[IMX6QDL_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4); imx6q_clocks_init()
479 clk[IMX6QDL_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6); imx6q_clocks_init()
480 clk[IMX6QDL_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8); imx6q_clocks_init()
481 clk[IMX6QDL_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10); imx6q_clocks_init()
482 clk[IMX6QDL_CLK_VDO_AXI] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); imx6q_clocks_init()
483 clk[IMX6QDL_CLK_VPU_AXI] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); imx6q_clocks_init()
484 clk[IMX6QDL_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); imx6q_clocks_init()
485 clk[IMX6QDL_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24); imx6q_clocks_init()
492 clk[IMX6QDL_CLK_GPT_3M] = clk[IMX6QDL_CLK_GPT_IPG_PER]; imx6q_clocks_init()
494 imx_check_clocks(clk, ARRAY_SIZE(clk)); imx6q_clocks_init()
496 clk_data.clks = clk; imx6q_clocks_init()
497 clk_data.clk_num = ARRAY_SIZE(clk); imx6q_clocks_init()
500 clk_register_clkdev(clk[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL); imx6q_clocks_init()
504 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI0_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
505 clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
508 clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000); imx6q_clocks_init()
510 clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); imx6q_clocks_init()
512 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
513 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
514 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
515 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); imx6q_clocks_init()
516 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_SEL], clk[IMX6QDL_CLK_IPU1_DI0_PRE]); imx6q_clocks_init()
517 clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_SEL], clk[IMX6QDL_CLK_IPU1_DI1_PRE]); imx6q_clocks_init()
518 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_SEL], clk[IMX6QDL_CLK_IPU2_DI0_PRE]); imx6q_clocks_init()
519 clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI1_SEL], clk[IMX6QDL_CLK_IPU2_DI1_PRE]); imx6q_clocks_init()
526 clk_set_parent(clk[IMX6QDL_CLK_ENFC_SEL], clk[IMX6QDL_CLK_PLL2_PFD2_396M]); imx6q_clocks_init()
529 clk_prepare_enable(clk[clks_init_on[i]]); imx6q_clocks_init()
532 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY1_GATE]); imx6q_clocks_init()
533 clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); imx6q_clocks_init()
540 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO2_SEL], clk[IMX6QDL_CLK_OSC]); imx6q_clocks_init()
542 ret = clk_set_parent(clk[IMX6QDL_CLK_CKO], clk[IMX6QDL_CLK_CKO2]); imx6q_clocks_init()
547 clk_set_parent(clk[IMX6QDL_CLK_SPDIF_SEL], clk[IMX6QDL_CLK_PLL3_PFD3_454M]); imx6q_clocks_init()
551 clk_set_parent(clk[IMX6QDL_CLK_LVDS1_SEL], clk[IMX6QDL_CLK_SATA_REF_100M]); imx6q_clocks_init()
|
| H A D | clk-imx25.c | 22 #include <linux/clk.h>
30 #include "clk.h"
87 static struct clk *clk[clk_max]; variable in typeref:struct:clk
89 static struct clk ** const uart_clks[] __initconst = {
90 &clk[uart_ipg_per],
91 &clk[uart1_ipg],
92 &clk[uart2_ipg],
93 &clk[uart3_ipg],
94 &clk[uart4_ipg],
95 &clk[uart5_ipg],
104 clk[dummy] = imx_clk_fixed("dummy", 0); __mx25_clocks_init()
105 clk[osc] = imx_clk_fixed("osc", osc_rate); __mx25_clocks_init()
106 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); __mx25_clocks_init()
107 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); __mx25_clocks_init()
108 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); __mx25_clocks_init()
109 clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)); __mx25_clocks_init()
110 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); __mx25_clocks_init()
111 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); __mx25_clocks_init()
112 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); __mx25_clocks_init()
113 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); __mx25_clocks_init()
114 clk[per0_sel] = imx_clk_mux("per0_sel", ccm(CCM_MCR), 0, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
115 clk[per1_sel] = imx_clk_mux("per1_sel", ccm(CCM_MCR), 1, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
116 clk[per2_sel] = imx_clk_mux("per2_sel", ccm(CCM_MCR), 2, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
117 clk[per3_sel] = imx_clk_mux("per3_sel", ccm(CCM_MCR), 3, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
118 clk[per4_sel] = imx_clk_mux("per4_sel", ccm(CCM_MCR), 4, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
119 clk[per5_sel] = imx_clk_mux("per5_sel", ccm(CCM_MCR), 5, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
120 clk[per6_sel] = imx_clk_mux("per6_sel", ccm(CCM_MCR), 6, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
121 clk[per7_sel] = imx_clk_mux("per7_sel", ccm(CCM_MCR), 7, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
122 clk[per8_sel] = imx_clk_mux("per8_sel", ccm(CCM_MCR), 8, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
123 clk[per9_sel] = imx_clk_mux("per9_sel", ccm(CCM_MCR), 9, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
124 clk[per10_sel] = imx_clk_mux("per10_sel", ccm(CCM_MCR), 10, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
125 clk[per11_sel] = imx_clk_mux("per11_sel", ccm(CCM_MCR), 11, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
126 clk[per12_sel] = imx_clk_mux("per12_sel", ccm(CCM_MCR), 12, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
127 clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
128 clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
129 clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); __mx25_clocks_init()
130 clk[cko_div] = imx_clk_divider("cko_div", "cko_sel", ccm(CCM_MCR), 24, 6); __mx25_clocks_init()
131 clk[cko_sel] = imx_clk_mux("cko_sel", ccm(CCM_MCR), 20, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks)); __mx25_clocks_init()
132 clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30); __mx25_clocks_init()
133 clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6); __mx25_clocks_init()
134 clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6); __mx25_clocks_init()
135 clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6); __mx25_clocks_init()
136 clk[per3] = imx_clk_divider("per3", "per3_sel", ccm(CCM_PCDR0), 24, 6); __mx25_clocks_init()
137 clk[per4] = imx_clk_divider("per4", "per4_sel", ccm(CCM_PCDR1), 0, 6); __mx25_clocks_init()
138 clk[per5] = imx_clk_divider("per5", "per5_sel", ccm(CCM_PCDR1), 8, 6); __mx25_clocks_init()
139 clk[per6] = imx_clk_divider("per6", "per6_sel", ccm(CCM_PCDR1), 16, 6); __mx25_clocks_init()
140 clk[per7] = imx_clk_divider("per7", "per7_sel", ccm(CCM_PCDR1), 24, 6); __mx25_clocks_init()
141 clk[per8] = imx_clk_divider("per8", "per8_sel", ccm(CCM_PCDR2), 0, 6); __mx25_clocks_init()
142 clk[per9] = imx_clk_divider("per9", "per9_sel", ccm(CCM_PCDR2), 8, 6); __mx25_clocks_init()
143 clk[per10] = imx_clk_divider("per10", "per10_sel", ccm(CCM_PCDR2), 16, 6); __mx25_clocks_init()
144 clk[per11] = imx_clk_divider("per11", "per11_sel", ccm(CCM_PCDR2), 24, 6); __mx25_clocks_init()
145 clk[per12] = imx_clk_divider("per12", "per12_sel", ccm(CCM_PCDR3), 0, 6); __mx25_clocks_init()
146 clk[per13] = imx_clk_divider("per13", "per13_sel", ccm(CCM_PCDR3), 8, 6); __mx25_clocks_init()
147 clk[per14] = imx_clk_divider("per14", "per14_sel", ccm(CCM_PCDR3), 16, 6); __mx25_clocks_init()
148 clk[per15] = imx_clk_divider("per15", "per15_sel", ccm(CCM_PCDR3), 24, 6); __mx25_clocks_init()
149 clk[csi_ipg_per] = imx_clk_gate("csi_ipg_per", "per0", ccm(CCM_CGCR0), 0); __mx25_clocks_init()
150 clk[epit_ipg_per] = imx_clk_gate("epit_ipg_per", "per1", ccm(CCM_CGCR0), 1); __mx25_clocks_init()
151 clk[esai_ipg_per] = imx_clk_gate("esai_ipg_per", "per2", ccm(CCM_CGCR0), 2); __mx25_clocks_init()
152 clk[esdhc1_ipg_per] = imx_clk_gate("esdhc1_ipg_per", "per3", ccm(CCM_CGCR0), 3); __mx25_clocks_init()
153 clk[esdhc2_ipg_per] = imx_clk_gate("esdhc2_ipg_per", "per4", ccm(CCM_CGCR0), 4); __mx25_clocks_init()
154 clk[gpt_ipg_per] = imx_clk_gate("gpt_ipg_per", "per5", ccm(CCM_CGCR0), 5); __mx25_clocks_init()
155 clk[i2c_ipg_per] = imx_clk_gate("i2c_ipg_per", "per6", ccm(CCM_CGCR0), 6); __mx25_clocks_init()
156 clk[lcdc_ipg_per] = imx_clk_gate("lcdc_ipg_per", "per7", ccm(CCM_CGCR0), 7); __mx25_clocks_init()
157 clk[nfc_ipg_per] = imx_clk_gate("nfc_ipg_per", "per8", ccm(CCM_CGCR0), 8); __mx25_clocks_init()
158 clk[owire_ipg_per] = imx_clk_gate("owire_ipg_per", "per9", ccm(CCM_CGCR0), 9); __mx25_clocks_init()
159 clk[pwm_ipg_per] = imx_clk_gate("pwm_ipg_per", "per10", ccm(CCM_CGCR0), 10); __mx25_clocks_init()
160 clk[sim1_ipg_per] = imx_clk_gate("sim1_ipg_per", "per11", ccm(CCM_CGCR0), 11); __mx25_clocks_init()
161 clk[sim2_ipg_per] = imx_clk_gate("sim2_ipg_per", "per12", ccm(CCM_CGCR0), 12); __mx25_clocks_init()
162 clk[ssi1_ipg_per] = imx_clk_gate("ssi1_ipg_per", "per13", ccm(CCM_CGCR0), 13); __mx25_clocks_init()
163 clk[ssi2_ipg_per] = imx_clk_gate("ssi2_ipg_per", "per14", ccm(CCM_CGCR0), 14); __mx25_clocks_init()
164 clk[uart_ipg_per] = imx_clk_gate("uart_ipg_per", "per15", ccm(CCM_CGCR0), 15); __mx25_clocks_init()
165 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); __mx25_clocks_init()
167 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); __mx25_clocks_init()
168 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); __mx25_clocks_init()
169 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); __mx25_clocks_init()
170 clk[esdhc1_ahb] = imx_clk_gate("esdhc1_ahb", "ahb", ccm(CCM_CGCR0), 21); __mx25_clocks_init()
171 clk[esdhc2_ahb] = imx_clk_gate("esdhc2_ahb", "ahb", ccm(CCM_CGCR0), 22); __mx25_clocks_init()
172 clk[fec_ahb] = imx_clk_gate("fec_ahb", "ahb", ccm(CCM_CGCR0), 23); __mx25_clocks_init()
173 clk[lcdc_ahb] = imx_clk_gate("lcdc_ahb", "ahb", ccm(CCM_CGCR0), 24); __mx25_clocks_init()
174 clk[rtic_ahb] = imx_clk_gate("rtic_ahb", "ahb", ccm(CCM_CGCR0), 25); __mx25_clocks_init()
175 clk[sdma_ahb] = imx_clk_gate("sdma_ahb", "ahb", ccm(CCM_CGCR0), 26); __mx25_clocks_init()
176 clk[slcdc_ahb] = imx_clk_gate("slcdc_ahb", "ahb", ccm(CCM_CGCR0), 27); __mx25_clocks_init()
177 clk[usbotg_ahb] = imx_clk_gate("usbotg_ahb", "ahb", ccm(CCM_CGCR0), 28); __mx25_clocks_init()
180 clk[can1_ipg] = imx_clk_gate("can1_ipg", "ipg", ccm(CCM_CGCR1), 2); __mx25_clocks_init()
181 clk[can2_ipg] = imx_clk_gate("can2_ipg", "ipg", ccm(CCM_CGCR1), 3); __mx25_clocks_init()
182 clk[csi_ipg] = imx_clk_gate("csi_ipg", "ipg", ccm(CCM_CGCR1), 4); __mx25_clocks_init()
183 clk[cspi1_ipg] = imx_clk_gate("cspi1_ipg", "ipg", ccm(CCM_CGCR1), 5); __mx25_clocks_init()
184 clk[cspi2_ipg] = imx_clk_gate("cspi2_ipg", "ipg", ccm(CCM_CGCR1), 6); __mx25_clocks_init()
185 clk[cspi3_ipg] = imx_clk_gate("cspi3_ipg", "ipg", ccm(CCM_CGCR1), 7); __mx25_clocks_init()
186 clk[dryice_ipg] = imx_clk_gate("dryice_ipg", "ipg", ccm(CCM_CGCR1), 8); __mx25_clocks_init()
187 clk[ect_ipg] = imx_clk_gate("ect_ipg", "ipg", ccm(CCM_CGCR1), 9); __mx25_clocks_init()
188 clk[epit1_ipg] = imx_clk_gate("epit1_ipg", "ipg", ccm(CCM_CGCR1), 10); __mx25_clocks_init()
189 clk[epit2_ipg] = imx_clk_gate("epit2_ipg", "ipg", ccm(CCM_CGCR1), 11); __mx25_clocks_init()
191 clk[esdhc1_ipg] = imx_clk_gate("esdhc1_ipg", "ipg", ccm(CCM_CGCR1), 13); __mx25_clocks_init()
192 clk[esdhc2_ipg] = imx_clk_gate("esdhc2_ipg", "ipg", ccm(CCM_CGCR1), 14); __mx25_clocks_init()
193 clk[fec_ipg] = imx_clk_gate("fec_ipg", "ipg", ccm(CCM_CGCR1), 15); __mx25_clocks_init()
197 clk[gpt1_ipg] = imx_clk_gate("gpt1_ipg", "ipg", ccm(CCM_CGCR1), 19); __mx25_clocks_init()
198 clk[gpt2_ipg] = imx_clk_gate("gpt2_ipg", "ipg", ccm(CCM_CGCR1), 20); __mx25_clocks_init()
199 clk[gpt3_ipg] = imx_clk_gate("gpt3_ipg", "ipg", ccm(CCM_CGCR1), 21); __mx25_clocks_init()
200 clk[gpt4_ipg] = imx_clk_gate("gpt4_ipg", "ipg", ccm(CCM_CGCR1), 22); __mx25_clocks_init()
204 clk[iim_ipg] = imx_clk_gate("iim_ipg", "ipg", ccm(CCM_CGCR1), 26); __mx25_clocks_init()
207 clk[kpp_ipg] = imx_clk_gate("kpp_ipg", "ipg", ccm(CCM_CGCR1), 28); __mx25_clocks_init()
208 clk[lcdc_ipg] = imx_clk_gate("lcdc_ipg", "ipg", ccm(CCM_CGCR1), 29); __mx25_clocks_init()
210 clk[pwm1_ipg] = imx_clk_gate("pwm1_ipg", "ipg", ccm(CCM_CGCR1), 31); __mx25_clocks_init()
211 clk[pwm2_ipg] = imx_clk_gate("pwm2_ipg", "ipg", ccm(CCM_CGCR2), 0); __mx25_clocks_init()
212 clk[pwm3_ipg] = imx_clk_gate("pwm3_ipg", "ipg", ccm(CCM_CGCR2), 1); __mx25_clocks_init()
213 clk[pwm4_ipg] = imx_clk_gate("pwm4_ipg", "ipg", ccm(CCM_CGCR2), 2); __mx25_clocks_init()
214 clk[rngb_ipg] = imx_clk_gate("rngb_ipg", "ipg", ccm(CCM_CGCR2), 3); __mx25_clocks_init()
216 clk[scc_ipg] = imx_clk_gate("scc_ipg", "ipg", ccm(CCM_CGCR2), 5); __mx25_clocks_init()
217 clk[sdma_ipg] = imx_clk_gate("sdma_ipg", "ipg", ccm(CCM_CGCR2), 6); __mx25_clocks_init()
218 clk[sim1_ipg] = imx_clk_gate("sim1_ipg", "ipg", ccm(CCM_CGCR2), 7); __mx25_clocks_init()
219 clk[sim2_ipg] = imx_clk_gate("sim2_ipg", "ipg", ccm(CCM_CGCR2), 8); __mx25_clocks_init()
220 clk[slcdc_ipg] = imx_clk_gate("slcdc_ipg", "ipg", ccm(CCM_CGCR2), 9); __mx25_clocks_init()
221 clk[spba_ipg] = imx_clk_gate("spba_ipg", "ipg", ccm(CCM_CGCR2), 10); __mx25_clocks_init()
222 clk[ssi1_ipg] = imx_clk_gate("ssi1_ipg", "ipg", ccm(CCM_CGCR2), 11); __mx25_clocks_init()
223 clk[ssi2_ipg] = imx_clk_gate("ssi2_ipg", "ipg", ccm(CCM_CGCR2), 12); __mx25_clocks_init()
224 clk[tsc_ipg] = imx_clk_gate("tsc_ipg", "ipg", ccm(CCM_CGCR2), 13); __mx25_clocks_init()
225 clk[uart1_ipg] = imx_clk_gate("uart1_ipg", "ipg", ccm(CCM_CGCR2), 14); __mx25_clocks_init()
226 clk[uart2_ipg] = imx_clk_gate("uart2_ipg", "ipg", ccm(CCM_CGCR2), 15); __mx25_clocks_init()
227 clk[uart3_ipg] = imx_clk_gate("uart3_ipg", "ipg", ccm(CCM_CGCR2), 16); __mx25_clocks_init()
228 clk[uart4_ipg] = imx_clk_gate("uart4_ipg", "ipg", ccm(CCM_CGCR2), 17); __mx25_clocks_init()
229 clk[uart5_ipg] = imx_clk_gate("uart5_ipg", "ipg", ccm(CCM_CGCR2), 18); __mx25_clocks_init()
231 clk[wdt_ipg] = imx_clk_gate("wdt_ipg", "ipg", ccm(CCM_CGCR2), 19); __mx25_clocks_init()
233 imx_check_clocks(clk, ARRAY_SIZE(clk)); __mx25_clocks_init()
235 clk_prepare_enable(clk[emi_ahb]); __mx25_clocks_init()
238 clk_set_parent(clk[per5_sel], clk[ahb]); __mx25_clocks_init()
244 clk_set_parent(clk[cko_sel], clk[ipg]); __mx25_clocks_init()
270 clk_data.clks = clk; mx25_clocks_init_dt()
271 clk_data.clk_num = ARRAY_SIZE(clk); mx25_clocks_init_dt()
|
| H A D | clk.c | 1 #include <linux/clk.h>
6 #include "clk.h"
10 void __init imx_check_clocks(struct clk *clks[], unsigned int count) imx_check_clocks()
16 pr_err("i.MX clk %u: register failed with %ld\n", imx_check_clocks()
20 static struct clk * __init imx_obtain_fixed_clock_from_dt(const char *name) imx_obtain_fixed_clock_from_dt()
23 struct clk *clk = ERR_PTR(-ENODEV); imx_obtain_fixed_clock_from_dt() local
34 clk = of_clk_get_from_provider(&phandle); imx_obtain_fixed_clock_from_dt()
37 return clk; imx_obtain_fixed_clock_from_dt()
40 struct clk * __init imx_obtain_fixed_clock( imx_obtain_fixed_clock()
43 struct clk *clk; imx_obtain_fixed_clock() local
45 clk = imx_obtain_fixed_clock_from_dt(name); imx_obtain_fixed_clock()
46 if (IS_ERR(clk)) imx_obtain_fixed_clock()
47 clk = imx_clk_fixed(name, rate); imx_obtain_fixed_clock()
48 return clk; imx_obtain_fixed_clock()
78 static struct clk ** const *imx_uart_clocks __initdata;
91 void __init imx_register_uart_clocks(struct clk ** const clks[]) imx_register_uart_clocks()
|
| H A D | clk-cpu.c | 12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
15 #include "clk.h"
19 struct clk *div;
20 struct clk *mux;
21 struct clk *pll;
22 struct clk *step;
78 struct clk *imx_clk_cpu(const char *name, const char *parent_name, imx_clk_cpu()
79 struct clk *div, struct clk *mux, struct clk *pll, imx_clk_cpu()
80 struct clk *step) imx_clk_cpu()
83 struct clk *clk; imx_clk_cpu() local
103 clk = clk_register(NULL, &cpu->hw); imx_clk_cpu()
104 if (IS_ERR(clk)) imx_clk_cpu()
107 return clk; imx_clk_cpu()
|
| H A D | clk.h | 5 #include <linux/clk-provider.h>
9 void imx_check_clocks(struct clk *clks[], unsigned int count);
10 void imx_register_uart_clocks(struct clk ** const clks[]);
23 struct clk *imx_clk_pllv1(enum imx_pllv1_type type, const char *name,
26 struct clk *imx_clk_pllv2(const char *name, const char *parent,
39 struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
42 struct clk *clk_register_gate2(struct device *dev, const char *name,
48 struct clk * imx_obtain_fixed_clock(
51 struct clk *imx_clk_gate_exclusive(const char *name, const char *parent,
54 static inline struct clk *imx_clk_gate2(const char *name, const char *parent, imx_clk_gate2()
61 static inline struct clk *imx_clk_gate2_shared(const char *name, imx_clk_gate2_shared()
69 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
72 struct clk *imx_clk_busy_divider(const char *name, const char *parent_name,
76 struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
80 struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
84 struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
88 static inline struct clk *imx_clk_fixed(const char *name, int rate) imx_clk_fixed()
93 static inline struct clk *imx_clk_divider(const char *name, const char *parent, imx_clk_divider()
100 static inline struct clk *imx_clk_divider_flags(const char *name, imx_clk_divider_flags()
108 static inline struct clk *imx_clk_gate(const char *name, const char *parent, imx_clk_gate()
115 static inline struct clk *imx_clk_gate_dis(const char *name, const char *parent, imx_clk_gate_dis()
122 static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, imx_clk_mux()
130 static inline struct clk *imx_clk_mux_flags(const char *name, imx_clk_mux_flags()
139 static inline struct clk *imx_clk_fixed_factor(const char *name, imx_clk_fixed_factor()
146 struct clk *imx_clk_cpu(const char *name, const char *parent_name,
147 struct clk *div, struct clk *mux, struct clk *pll,
148 struct clk *step);
|
| /linux-4.4.14/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 12 #include <linux/clk-provider.h>
14 #include <linux/platform_data/clk-ux500.h>
15 #include "clk.h"
20 static struct clk *prcmu_clk[PRCMU_NUM_CLKS];
21 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
24 #define PRCC_SHOW(clk, base, bit) \
25 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
26 #define PRCC_PCLK_STORE(clk, base, bit) \
27 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
28 #define PRCC_KCLK_STORE(clk, base, bit) \
29 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
31 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, ux500_twocell_get()
34 struct clk **clk_data = data; ux500_twocell_get()
72 struct clk *clk, *rtc_clk, *twd_clk; u8500_clk_init() local
93 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, u8500_clk_init()
95 prcmu_clk[PRCMU_PLLSOC0] = clk; u8500_clk_init()
97 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, u8500_clk_init()
99 prcmu_clk[PRCMU_PLLSOC1] = clk; u8500_clk_init()
101 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8500_clk_init()
103 prcmu_clk[PRCMU_PLLDDR] = clk; u8500_clk_init()
126 clk = clk_reg_prcmu_gate("sgclk", sgaclk_parent, u8500_clk_init()
129 clk = clk_reg_prcmu_gate("sgclk", NULL, u8500_clk_init()
131 prcmu_clk[PRCMU_SGACLK] = clk; u8500_clk_init()
133 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); u8500_clk_init()
134 prcmu_clk[PRCMU_UARTCLK] = clk; u8500_clk_init()
136 clk = clk_reg_prcmu_gate("msp02clk", NULL, PRCMU_MSP02CLK, CLK_IS_ROOT); u8500_clk_init()
137 prcmu_clk[PRCMU_MSP02CLK] = clk; u8500_clk_init()
139 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); u8500_clk_init()
140 prcmu_clk[PRCMU_MSP1CLK] = clk; u8500_clk_init()
142 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); u8500_clk_init()
143 prcmu_clk[PRCMU_I2CCLK] = clk; u8500_clk_init()
145 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); u8500_clk_init()
146 prcmu_clk[PRCMU_SLIMCLK] = clk; u8500_clk_init()
148 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); u8500_clk_init()
149 prcmu_clk[PRCMU_PER1CLK] = clk; u8500_clk_init()
151 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); u8500_clk_init()
152 prcmu_clk[PRCMU_PER2CLK] = clk; u8500_clk_init()
154 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); u8500_clk_init()
155 prcmu_clk[PRCMU_PER3CLK] = clk; u8500_clk_init()
157 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); u8500_clk_init()
158 prcmu_clk[PRCMU_PER5CLK] = clk; u8500_clk_init()
160 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); u8500_clk_init()
161 prcmu_clk[PRCMU_PER6CLK] = clk; u8500_clk_init()
163 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); u8500_clk_init()
164 prcmu_clk[PRCMU_PER7CLK] = clk; u8500_clk_init()
166 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, u8500_clk_init()
168 prcmu_clk[PRCMU_LCDCLK] = clk; u8500_clk_init()
170 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, CLK_IS_ROOT); u8500_clk_init()
171 prcmu_clk[PRCMU_BMLCLK] = clk; u8500_clk_init()
173 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, u8500_clk_init()
175 prcmu_clk[PRCMU_HSITXCLK] = clk; u8500_clk_init()
177 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, u8500_clk_init()
179 prcmu_clk[PRCMU_HSIRXCLK] = clk; u8500_clk_init()
181 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, u8500_clk_init()
183 prcmu_clk[PRCMU_HDMICLK] = clk; u8500_clk_init()
185 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); u8500_clk_init()
186 prcmu_clk[PRCMU_APEATCLK] = clk; u8500_clk_init()
188 clk = clk_reg_prcmu_scalable("apetraceclk", NULL, PRCMU_APETRACECLK, 0, u8500_clk_init()
190 prcmu_clk[PRCMU_APETRACECLK] = clk; u8500_clk_init()
192 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); u8500_clk_init()
193 prcmu_clk[PRCMU_MCDECLK] = clk; u8500_clk_init()
195 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, u8500_clk_init()
197 prcmu_clk[PRCMU_IPI2CCLK] = clk; u8500_clk_init()
199 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, u8500_clk_init()
201 prcmu_clk[PRCMU_DSIALTCLK] = clk; u8500_clk_init()
203 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); u8500_clk_init()
204 prcmu_clk[PRCMU_DMACLK] = clk; u8500_clk_init()
206 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); u8500_clk_init()
207 prcmu_clk[PRCMU_B2R2CLK] = clk; u8500_clk_init()
209 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, u8500_clk_init()
211 prcmu_clk[PRCMU_TVCLK] = clk; u8500_clk_init()
213 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); u8500_clk_init()
214 prcmu_clk[PRCMU_SSPCLK] = clk; u8500_clk_init()
216 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); u8500_clk_init()
217 prcmu_clk[PRCMU_RNGCLK] = clk; u8500_clk_init()
219 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); u8500_clk_init()
220 prcmu_clk[PRCMU_UICCCLK] = clk; u8500_clk_init()
222 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); u8500_clk_init()
223 prcmu_clk[PRCMU_TIMCLK] = clk; u8500_clk_init()
225 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK, u8500_clk_init()
228 prcmu_clk[PRCMU_SDMMCCLK] = clk; u8500_clk_init()
230 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", u8500_clk_init()
232 prcmu_clk[PRCMU_PLLDSI] = clk; u8500_clk_init()
234 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", u8500_clk_init()
236 prcmu_clk[PRCMU_DSI0CLK] = clk; u8500_clk_init()
238 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", u8500_clk_init()
240 prcmu_clk[PRCMU_DSI1CLK] = clk; u8500_clk_init()
242 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", u8500_clk_init()
244 prcmu_clk[PRCMU_DSI0ESCCLK] = clk; u8500_clk_init()
246 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", u8500_clk_init()
248 prcmu_clk[PRCMU_DSI1ESCCLK] = clk; u8500_clk_init()
250 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", u8500_clk_init()
252 prcmu_clk[PRCMU_DSI2ESCCLK] = clk; u8500_clk_init()
254 clk = clk_reg_prcmu_scalable_rate("armss", NULL, u8500_clk_init()
256 prcmu_clk[PRCMU_ARMSS] = clk; u8500_clk_init()
268 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
270 PRCC_PCLK_STORE(clk, 1, 0); u8500_clk_init()
272 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
274 PRCC_PCLK_STORE(clk, 1, 1); u8500_clk_init()
276 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
278 PRCC_PCLK_STORE(clk, 1, 2); u8500_clk_init()
280 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
282 PRCC_PCLK_STORE(clk, 1, 3); u8500_clk_init()
284 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
286 PRCC_PCLK_STORE(clk, 1, 4); u8500_clk_init()
288 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
290 PRCC_PCLK_STORE(clk, 1, 5); u8500_clk_init()
292 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
294 PRCC_PCLK_STORE(clk, 1, 6); u8500_clk_init()
296 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
298 PRCC_PCLK_STORE(clk, 1, 7); u8500_clk_init()
300 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
302 PRCC_PCLK_STORE(clk, 1, 8); u8500_clk_init()
304 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
306 PRCC_PCLK_STORE(clk, 1, 9); u8500_clk_init()
308 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
310 PRCC_PCLK_STORE(clk, 1, 10); u8500_clk_init()
312 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], u8500_clk_init()
314 PRCC_PCLK_STORE(clk, 1, 11); u8500_clk_init()
316 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
318 PRCC_PCLK_STORE(clk, 2, 0); u8500_clk_init()
320 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
322 PRCC_PCLK_STORE(clk, 2, 1); u8500_clk_init()
324 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
326 PRCC_PCLK_STORE(clk, 2, 2); u8500_clk_init()
328 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
330 PRCC_PCLK_STORE(clk, 2, 3); u8500_clk_init()
332 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
334 PRCC_PCLK_STORE(clk, 2, 4); u8500_clk_init()
336 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
338 PRCC_PCLK_STORE(clk, 2, 5); u8500_clk_init()
340 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
342 PRCC_PCLK_STORE(clk, 2, 6); u8500_clk_init()
344 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
346 PRCC_PCLK_STORE(clk, 2, 7); u8500_clk_init()
348 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
350 PRCC_PCLK_STORE(clk, 2, 8); u8500_clk_init()
352 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
354 PRCC_PCLK_STORE(clk, 2, 9); u8500_clk_init()
356 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
358 PRCC_PCLK_STORE(clk, 2, 10); u8500_clk_init()
360 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
362 PRCC_PCLK_STORE(clk, 2, 11); u8500_clk_init()
364 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], u8500_clk_init()
366 PRCC_PCLK_STORE(clk, 2, 12); u8500_clk_init()
368 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
370 PRCC_PCLK_STORE(clk, 3, 0); u8500_clk_init()
372 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
374 PRCC_PCLK_STORE(clk, 3, 1); u8500_clk_init()
376 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
378 PRCC_PCLK_STORE(clk, 3, 2); u8500_clk_init()
380 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
382 PRCC_PCLK_STORE(clk, 3, 3); u8500_clk_init()
384 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
386 PRCC_PCLK_STORE(clk, 3, 4); u8500_clk_init()
388 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
390 PRCC_PCLK_STORE(clk, 3, 5); u8500_clk_init()
392 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
394 PRCC_PCLK_STORE(clk, 3, 6); u8500_clk_init()
396 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
398 PRCC_PCLK_STORE(clk, 3, 7); u8500_clk_init()
400 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], u8500_clk_init()
402 PRCC_PCLK_STORE(clk, 3, 8); u8500_clk_init()
404 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], u8500_clk_init()
406 PRCC_PCLK_STORE(clk, 5, 0); u8500_clk_init()
408 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], u8500_clk_init()
410 PRCC_PCLK_STORE(clk, 5, 1); u8500_clk_init()
412 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
414 PRCC_PCLK_STORE(clk, 6, 0); u8500_clk_init()
416 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
418 PRCC_PCLK_STORE(clk, 6, 1); u8500_clk_init()
420 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
422 PRCC_PCLK_STORE(clk, 6, 2); u8500_clk_init()
424 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
426 PRCC_PCLK_STORE(clk, 6, 3); u8500_clk_init()
428 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
430 PRCC_PCLK_STORE(clk, 6, 4); u8500_clk_init()
432 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
434 PRCC_PCLK_STORE(clk, 6, 5); u8500_clk_init()
436 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
438 PRCC_PCLK_STORE(clk, 6, 6); u8500_clk_init()
440 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], u8500_clk_init()
442 PRCC_PCLK_STORE(clk, 6, 7); u8500_clk_init()
453 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", u8500_clk_init()
455 PRCC_KCLK_STORE(clk, 1, 0); u8500_clk_init()
457 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", u8500_clk_init()
459 PRCC_KCLK_STORE(clk, 1, 1); u8500_clk_init()
461 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", u8500_clk_init()
463 PRCC_KCLK_STORE(clk, 1, 2); u8500_clk_init()
465 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", u8500_clk_init()
467 PRCC_KCLK_STORE(clk, 1, 3); u8500_clk_init()
469 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", u8500_clk_init()
471 PRCC_KCLK_STORE(clk, 1, 4); u8500_clk_init()
473 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmcclk", u8500_clk_init()
475 PRCC_KCLK_STORE(clk, 1, 5); u8500_clk_init()
477 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", u8500_clk_init()
479 PRCC_KCLK_STORE(clk, 1, 6); u8500_clk_init()
481 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", u8500_clk_init()
483 PRCC_KCLK_STORE(clk, 1, 8); u8500_clk_init()
485 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", u8500_clk_init()
487 PRCC_KCLK_STORE(clk, 1, 9); u8500_clk_init()
489 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", u8500_clk_init()
491 PRCC_KCLK_STORE(clk, 1, 10); u8500_clk_init()
494 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", u8500_clk_init()
496 PRCC_KCLK_STORE(clk, 2, 0); u8500_clk_init()
498 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmcclk", u8500_clk_init()
500 PRCC_KCLK_STORE(clk, 2, 2); u8500_clk_init()
502 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", u8500_clk_init()
504 PRCC_KCLK_STORE(clk, 2, 3); u8500_clk_init()
506 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmcclk", u8500_clk_init()
508 PRCC_KCLK_STORE(clk, 2, 4); u8500_clk_init()
510 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", u8500_clk_init()
512 PRCC_KCLK_STORE(clk, 2, 5); u8500_clk_init()
515 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", u8500_clk_init()
518 PRCC_KCLK_STORE(clk, 2, 6); u8500_clk_init()
520 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", u8500_clk_init()
523 PRCC_KCLK_STORE(clk, 2, 7); u8500_clk_init()
526 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", u8500_clk_init()
528 PRCC_KCLK_STORE(clk, 3, 1); u8500_clk_init()
530 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", u8500_clk_init()
532 PRCC_KCLK_STORE(clk, 3, 2); u8500_clk_init()
534 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", u8500_clk_init()
536 PRCC_KCLK_STORE(clk, 3, 3); u8500_clk_init()
538 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmcclk", u8500_clk_init()
540 PRCC_KCLK_STORE(clk, 3, 4); u8500_clk_init()
542 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", u8500_clk_init()
544 PRCC_KCLK_STORE(clk, 3, 5); u8500_clk_init()
546 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", u8500_clk_init()
548 PRCC_KCLK_STORE(clk, 3, 6); u8500_clk_init()
550 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", u8500_clk_init()
552 PRCC_KCLK_STORE(clk, 3, 7); u8500_clk_init()
555 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", u8500_clk_init()
557 PRCC_KCLK_STORE(clk, 6, 0); u8500_clk_init()
|
| H A D | u8540_clk.c | 13 #include <linux/clk-provider.h>
15 #include <linux/platform_data/clk-ux500.h>
16 #include "clk.h"
35 struct clk *clk; u8540_clk_init() local
58 clk = clk_reg_prcmu_gate("soc0_pll", NULL, PRCMU_PLLSOC0, u8540_clk_init()
60 clk_register_clkdev(clk, "soc0_pll", NULL); u8540_clk_init()
62 clk = clk_reg_prcmu_gate("soc1_pll", NULL, PRCMU_PLLSOC1, u8540_clk_init()
64 clk_register_clkdev(clk, "soc1_pll", NULL); u8540_clk_init()
66 clk = clk_reg_prcmu_gate("ddr_pll", NULL, PRCMU_PLLDDR, u8540_clk_init()
68 clk_register_clkdev(clk, "ddr_pll", NULL); u8540_clk_init()
70 clk = clk_register_fixed_rate(NULL, "rtc32k", NULL, u8540_clk_init()
73 clk_register_clkdev(clk, "clk32k", NULL); u8540_clk_init()
74 clk_register_clkdev(clk, "apb_pclk", "rtc-pl031"); u8540_clk_init()
76 clk = clk_register_fixed_rate(NULL, "ulp38m4", NULL, u8540_clk_init()
80 clk = clk_reg_prcmu_gate("uartclk", NULL, PRCMU_UARTCLK, CLK_IS_ROOT); u8540_clk_init()
81 clk_register_clkdev(clk, NULL, "UART"); u8540_clk_init()
83 /* msp02clk needs a abx500 clk as parent. Handle by abx500 clk driver */ u8540_clk_init()
84 clk = clk_reg_prcmu_gate("msp02clk", "ab9540_sysclk12_b1", u8540_clk_init()
86 clk_register_clkdev(clk, NULL, "MSP02"); u8540_clk_init()
88 clk = clk_reg_prcmu_gate("msp1clk", NULL, PRCMU_MSP1CLK, CLK_IS_ROOT); u8540_clk_init()
89 clk_register_clkdev(clk, NULL, "MSP1"); u8540_clk_init()
91 clk = clk_reg_prcmu_gate("i2cclk", NULL, PRCMU_I2CCLK, CLK_IS_ROOT); u8540_clk_init()
92 clk_register_clkdev(clk, NULL, "I2C"); u8540_clk_init()
94 clk = clk_reg_prcmu_gate("slimclk", NULL, PRCMU_SLIMCLK, CLK_IS_ROOT); u8540_clk_init()
95 clk_register_clkdev(clk, NULL, "slim"); u8540_clk_init()
97 clk = clk_reg_prcmu_gate("per1clk", NULL, PRCMU_PER1CLK, CLK_IS_ROOT); u8540_clk_init()
98 clk_register_clkdev(clk, NULL, "PERIPH1"); u8540_clk_init()
100 clk = clk_reg_prcmu_gate("per2clk", NULL, PRCMU_PER2CLK, CLK_IS_ROOT); u8540_clk_init()
101 clk_register_clkdev(clk, NULL, "PERIPH2"); u8540_clk_init()
103 clk = clk_reg_prcmu_gate("per3clk", NULL, PRCMU_PER3CLK, CLK_IS_ROOT); u8540_clk_init()
104 clk_register_clkdev(clk, NULL, "PERIPH3"); u8540_clk_init()
106 clk = clk_reg_prcmu_gate("per5clk", NULL, PRCMU_PER5CLK, CLK_IS_ROOT); u8540_clk_init()
107 clk_register_clkdev(clk, NULL, "PERIPH5"); u8540_clk_init()
109 clk = clk_reg_prcmu_gate("per6clk", NULL, PRCMU_PER6CLK, CLK_IS_ROOT); u8540_clk_init()
110 clk_register_clkdev(clk, NULL, "PERIPH6"); u8540_clk_init()
112 clk = clk_reg_prcmu_gate("per7clk", NULL, PRCMU_PER7CLK, CLK_IS_ROOT); u8540_clk_init()
113 clk_register_clkdev(clk, NULL, "PERIPH7"); u8540_clk_init()
115 clk = clk_reg_prcmu_scalable("lcdclk", NULL, PRCMU_LCDCLK, 0, u8540_clk_init()
117 clk_register_clkdev(clk, NULL, "lcd"); u8540_clk_init()
118 clk_register_clkdev(clk, "lcd", "mcde"); u8540_clk_init()
120 clk = clk_reg_prcmu_opp_gate("bmlclk", NULL, PRCMU_BMLCLK, u8540_clk_init()
122 clk_register_clkdev(clk, NULL, "bml"); u8540_clk_init()
124 clk = clk_reg_prcmu_scalable("hsitxclk", NULL, PRCMU_HSITXCLK, 0, u8540_clk_init()
127 clk = clk_reg_prcmu_scalable("hsirxclk", NULL, PRCMU_HSIRXCLK, 0, u8540_clk_init()
130 clk = clk_reg_prcmu_scalable("hdmiclk", NULL, PRCMU_HDMICLK, 0, u8540_clk_init()
132 clk_register_clkdev(clk, NULL, "hdmi"); u8540_clk_init()
133 clk_register_clkdev(clk, "hdmi", "mcde"); u8540_clk_init()
135 clk = clk_reg_prcmu_gate("apeatclk", NULL, PRCMU_APEATCLK, CLK_IS_ROOT); u8540_clk_init()
136 clk_register_clkdev(clk, NULL, "apeat"); u8540_clk_init()
138 clk = clk_reg_prcmu_gate("apetraceclk", NULL, PRCMU_APETRACECLK, u8540_clk_init()
140 clk_register_clkdev(clk, NULL, "apetrace"); u8540_clk_init()
142 clk = clk_reg_prcmu_gate("mcdeclk", NULL, PRCMU_MCDECLK, CLK_IS_ROOT); u8540_clk_init()
143 clk_register_clkdev(clk, NULL, "mcde"); u8540_clk_init()
144 clk_register_clkdev(clk, "mcde", "mcde"); u8540_clk_init()
145 clk_register_clkdev(clk, NULL, "dsilink.0"); u8540_clk_init()
146 clk_register_clkdev(clk, NULL, "dsilink.1"); u8540_clk_init()
147 clk_register_clkdev(clk, NULL, "dsilink.2"); u8540_clk_init()
149 clk = clk_reg_prcmu_opp_gate("ipi2cclk", NULL, PRCMU_IPI2CCLK, u8540_clk_init()
151 clk_register_clkdev(clk, NULL, "ipi2"); u8540_clk_init()
153 clk = clk_reg_prcmu_gate("dsialtclk", NULL, PRCMU_DSIALTCLK, u8540_clk_init()
155 clk_register_clkdev(clk, NULL, "dsialt"); u8540_clk_init()
157 clk = clk_reg_prcmu_gate("dmaclk", NULL, PRCMU_DMACLK, CLK_IS_ROOT); u8540_clk_init()
158 clk_register_clkdev(clk, NULL, "dma40.0"); u8540_clk_init()
160 clk = clk_reg_prcmu_gate("b2r2clk", NULL, PRCMU_B2R2CLK, CLK_IS_ROOT); u8540_clk_init()
161 clk_register_clkdev(clk, NULL, "b2r2"); u8540_clk_init()
162 clk_register_clkdev(clk, NULL, "b2r2_core"); u8540_clk_init()
163 clk_register_clkdev(clk, NULL, "U8500-B2R2.0"); u8540_clk_init()
164 clk_register_clkdev(clk, NULL, "b2r2_1_core"); u8540_clk_init()
166 clk = clk_reg_prcmu_scalable("tvclk", NULL, PRCMU_TVCLK, 0, u8540_clk_init()
168 clk_register_clkdev(clk, NULL, "tv"); u8540_clk_init()
169 clk_register_clkdev(clk, "tv", "mcde"); u8540_clk_init()
171 clk = clk_reg_prcmu_gate("sspclk", NULL, PRCMU_SSPCLK, CLK_IS_ROOT); u8540_clk_init()
172 clk_register_clkdev(clk, NULL, "SSP"); u8540_clk_init()
174 clk = clk_reg_prcmu_gate("rngclk", NULL, PRCMU_RNGCLK, CLK_IS_ROOT); u8540_clk_init()
175 clk_register_clkdev(clk, NULL, "rngclk"); u8540_clk_init()
177 clk = clk_reg_prcmu_gate("uiccclk", NULL, PRCMU_UICCCLK, CLK_IS_ROOT); u8540_clk_init()
178 clk_register_clkdev(clk, NULL, "uicc"); u8540_clk_init()
180 clk = clk_reg_prcmu_gate("timclk", NULL, PRCMU_TIMCLK, CLK_IS_ROOT); u8540_clk_init()
181 clk_register_clkdev(clk, NULL, "mtu0"); u8540_clk_init()
182 clk_register_clkdev(clk, NULL, "mtu1"); u8540_clk_init()
184 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, u8540_clk_init()
187 clk_register_clkdev(clk, NULL, "sdmmc"); u8540_clk_init()
189 clk = clk_reg_prcmu_opp_volt_scalable("sdmmchclk", NULL, u8540_clk_init()
192 clk_register_clkdev(clk, NULL, "sdmmchclk"); u8540_clk_init()
194 clk = clk_reg_prcmu_gate("hvaclk", NULL, PRCMU_HVACLK, CLK_IS_ROOT); u8540_clk_init()
195 clk_register_clkdev(clk, NULL, "hva"); u8540_clk_init()
197 clk = clk_reg_prcmu_gate("g1clk", NULL, PRCMU_G1CLK, CLK_IS_ROOT); u8540_clk_init()
198 clk_register_clkdev(clk, NULL, "g1"); u8540_clk_init()
200 clk = clk_reg_prcmu_scalable("spare1clk", NULL, PRCMU_SPARE1CLK, 0, u8540_clk_init()
202 clk_register_clkdev(clk, "dsilcd", "mcde"); u8540_clk_init()
204 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", u8540_clk_init()
206 clk_register_clkdev(clk, "dsihs2", "mcde"); u8540_clk_init()
207 clk_register_clkdev(clk, "hs_clk", "dsilink.2"); u8540_clk_init()
209 clk = clk_reg_prcmu_scalable("dsilcd_pll", "spare1clk", u8540_clk_init()
211 clk_register_clkdev(clk, "dsilcd_pll", "mcde"); u8540_clk_init()
213 clk = clk_reg_prcmu_scalable("dsi0clk", "dsi_pll", u8540_clk_init()
215 clk_register_clkdev(clk, "dsihs0", "mcde"); u8540_clk_init()
217 clk = clk_reg_prcmu_scalable("dsi0lcdclk", "dsilcd_pll", u8540_clk_init()
219 clk_register_clkdev(clk, "dsihs0", "mcde"); u8540_clk_init()
220 clk_register_clkdev(clk, "hs_clk", "dsilink.0"); u8540_clk_init()
222 clk = clk_reg_prcmu_scalable("dsi1clk", "dsi_pll", u8540_clk_init()
224 clk_register_clkdev(clk, "dsihs1", "mcde"); u8540_clk_init()
226 clk = clk_reg_prcmu_scalable("dsi1lcdclk", "dsilcd_pll", u8540_clk_init()
228 clk_register_clkdev(clk, "dsihs1", "mcde"); u8540_clk_init()
229 clk_register_clkdev(clk, "hs_clk", "dsilink.1"); u8540_clk_init()
231 clk = clk_reg_prcmu_scalable("dsi0escclk", "tvclk", u8540_clk_init()
233 clk_register_clkdev(clk, "lp_clk", "dsilink.0"); u8540_clk_init()
234 clk_register_clkdev(clk, "dsilp0", "mcde"); u8540_clk_init()
236 clk = clk_reg_prcmu_scalable("dsi1escclk", "tvclk", u8540_clk_init()
238 clk_register_clkdev(clk, "lp_clk", "dsilink.1"); u8540_clk_init()
239 clk_register_clkdev(clk, "dsilp1", "mcde"); u8540_clk_init()
241 clk = clk_reg_prcmu_scalable("dsi2escclk", "tvclk", u8540_clk_init()
243 clk_register_clkdev(clk, "lp_clk", "dsilink.2"); u8540_clk_init()
244 clk_register_clkdev(clk, "dsilp2", "mcde"); u8540_clk_init()
246 clk = clk_reg_prcmu_scalable_rate("armss", NULL, u8540_clk_init()
248 clk_register_clkdev(clk, "armss", NULL); u8540_clk_init()
250 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss", u8540_clk_init()
252 clk_register_clkdev(clk, NULL, "smp_twd"); u8540_clk_init()
256 clk = clk_reg_prcc_pclk("p1_pclk0", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
258 clk_register_clkdev(clk, "apb_pclk", "uart0"); u8540_clk_init()
260 clk = clk_reg_prcc_pclk("p1_pclk1", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
262 clk_register_clkdev(clk, "apb_pclk", "uart1"); u8540_clk_init()
264 clk = clk_reg_prcc_pclk("p1_pclk2", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
266 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.1"); u8540_clk_init()
268 clk = clk_reg_prcc_pclk("p1_pclk3", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
270 clk_register_clkdev(clk, "apb_pclk", "msp0"); u8540_clk_init()
271 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.0"); u8540_clk_init()
273 clk = clk_reg_prcc_pclk("p1_pclk4", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
275 clk_register_clkdev(clk, "apb_pclk", "msp1"); u8540_clk_init()
276 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.1"); u8540_clk_init()
278 clk = clk_reg_prcc_pclk("p1_pclk5", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
280 clk_register_clkdev(clk, "apb_pclk", "sdi0"); u8540_clk_init()
282 clk = clk_reg_prcc_pclk("p1_pclk6", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
284 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.2"); u8540_clk_init()
286 clk = clk_reg_prcc_pclk("p1_pclk7", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
288 clk_register_clkdev(clk, NULL, "spi3"); u8540_clk_init()
290 clk = clk_reg_prcc_pclk("p1_pclk8", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
292 clk_register_clkdev(clk, "apb_pclk", "slimbus0"); u8540_clk_init()
294 clk = clk_reg_prcc_pclk("p1_pclk9", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
296 clk_register_clkdev(clk, NULL, "gpio.0"); u8540_clk_init()
297 clk_register_clkdev(clk, NULL, "gpio.1"); u8540_clk_init()
298 clk_register_clkdev(clk, NULL, "gpioblock0"); u8540_clk_init()
299 clk_register_clkdev(clk, "apb_pclk", "ab85xx-codec.0"); u8540_clk_init()
301 clk = clk_reg_prcc_pclk("p1_pclk10", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
303 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.4"); u8540_clk_init()
305 clk = clk_reg_prcc_pclk("p1_pclk11", "per1clk", bases[CLKRST1_INDEX], u8540_clk_init()
307 clk_register_clkdev(clk, "apb_pclk", "msp3"); u8540_clk_init()
308 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.3"); u8540_clk_init()
311 clk = clk_reg_prcc_pclk("p2_pclk0", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
313 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.3"); u8540_clk_init()
315 clk = clk_reg_prcc_pclk("p2_pclk1", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
317 clk_register_clkdev(clk, NULL, "spi2"); u8540_clk_init()
319 clk = clk_reg_prcc_pclk("p2_pclk2", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
321 clk_register_clkdev(clk, NULL, "spi1"); u8540_clk_init()
323 clk = clk_reg_prcc_pclk("p2_pclk3", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
325 clk_register_clkdev(clk, NULL, "pwl"); u8540_clk_init()
327 clk = clk_reg_prcc_pclk("p2_pclk4", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
329 clk_register_clkdev(clk, "apb_pclk", "sdi4"); u8540_clk_init()
331 clk = clk_reg_prcc_pclk("p2_pclk5", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
333 clk_register_clkdev(clk, "apb_pclk", "msp2"); u8540_clk_init()
334 clk_register_clkdev(clk, "apb_pclk", "dbx5x0-msp-i2s.2"); u8540_clk_init()
336 clk = clk_reg_prcc_pclk("p2_pclk6", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
338 clk_register_clkdev(clk, "apb_pclk", "sdi1"); u8540_clk_init()
340 clk = clk_reg_prcc_pclk("p2_pclk7", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
342 clk_register_clkdev(clk, "apb_pclk", "sdi3"); u8540_clk_init()
344 clk = clk_reg_prcc_pclk("p2_pclk8", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
346 clk_register_clkdev(clk, NULL, "spi0"); u8540_clk_init()
348 clk = clk_reg_prcc_pclk("p2_pclk9", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
350 clk_register_clkdev(clk, "hsir_hclk", "ste_hsi.0"); u8540_clk_init()
352 clk = clk_reg_prcc_pclk("p2_pclk10", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
354 clk_register_clkdev(clk, "hsit_hclk", "ste_hsi.0"); u8540_clk_init()
356 clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
358 clk_register_clkdev(clk, NULL, "gpio.6"); u8540_clk_init()
359 clk_register_clkdev(clk, NULL, "gpio.7"); u8540_clk_init()
360 clk_register_clkdev(clk, NULL, "gpioblock1"); u8540_clk_init()
362 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", bases[CLKRST2_INDEX], u8540_clk_init()
364 clk_register_clkdev(clk, "msp4-pclk", "ab85xx-codec.0"); u8540_clk_init()
367 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
369 clk_register_clkdev(clk, NULL, "fsmc"); u8540_clk_init()
371 clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
373 clk_register_clkdev(clk, "apb_pclk", "ssp0"); u8540_clk_init()
375 clk = clk_reg_prcc_pclk("p3_pclk2", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
377 clk_register_clkdev(clk, "apb_pclk", "ssp1"); u8540_clk_init()
379 clk = clk_reg_prcc_pclk("p3_pclk3", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
381 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.0"); u8540_clk_init()
383 clk = clk_reg_prcc_pclk("p3_pclk4", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
385 clk_register_clkdev(clk, "apb_pclk", "sdi2"); u8540_clk_init()
387 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
389 clk_register_clkdev(clk, "apb_pclk", "ske"); u8540_clk_init()
390 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad"); u8540_clk_init()
392 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
394 clk_register_clkdev(clk, "apb_pclk", "uart2"); u8540_clk_init()
396 clk = clk_reg_prcc_pclk("p3_pclk7", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
398 clk_register_clkdev(clk, "apb_pclk", "sdi5"); u8540_clk_init()
400 clk = clk_reg_prcc_pclk("p3_pclk8", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
402 clk_register_clkdev(clk, NULL, "gpio.2"); u8540_clk_init()
403 clk_register_clkdev(clk, NULL, "gpio.3"); u8540_clk_init()
404 clk_register_clkdev(clk, NULL, "gpio.4"); u8540_clk_init()
405 clk_register_clkdev(clk, NULL, "gpio.5"); u8540_clk_init()
406 clk_register_clkdev(clk, NULL, "gpioblock2"); u8540_clk_init()
408 clk = clk_reg_prcc_pclk("p3_pclk9", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
410 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.5"); u8540_clk_init()
412 clk = clk_reg_prcc_pclk("p3_pclk10", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
414 clk_register_clkdev(clk, "apb_pclk", "nmk-i2c.6"); u8540_clk_init()
416 clk = clk_reg_prcc_pclk("p3_pclk11", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
418 clk_register_clkdev(clk, "apb_pclk", "uart3"); u8540_clk_init()
420 clk = clk_reg_prcc_pclk("p3_pclk12", "per3clk", bases[CLKRST3_INDEX], u8540_clk_init()
422 clk_register_clkdev(clk, "apb_pclk", "uart4"); u8540_clk_init()
425 clk = clk_reg_prcc_pclk("p5_pclk0", "per5clk", bases[CLKRST5_INDEX], u8540_clk_init()
427 clk_register_clkdev(clk, "usb", "musb-ux500.0"); u8540_clk_init()
428 clk_register_clkdev(clk, "usbclk", "ab-iddet.0"); u8540_clk_init()
430 clk = clk_reg_prcc_pclk("p5_pclk1", "per5clk", bases[CLKRST5_INDEX], u8540_clk_init()
432 clk_register_clkdev(clk, NULL, "gpio.8"); u8540_clk_init()
433 clk_register_clkdev(clk, NULL, "gpioblock3"); u8540_clk_init()
436 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
438 clk_register_clkdev(clk, "apb_pclk", "rng"); u8540_clk_init()
440 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
442 clk_register_clkdev(clk, NULL, "cryp0"); u8540_clk_init()
443 clk_register_clkdev(clk, NULL, "cryp1"); u8540_clk_init()
445 clk = clk_reg_prcc_pclk("p6_pclk2", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
447 clk_register_clkdev(clk, NULL, "hash0"); u8540_clk_init()
449 clk = clk_reg_prcc_pclk("p6_pclk3", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
451 clk_register_clkdev(clk, NULL, "pka"); u8540_clk_init()
453 clk = clk_reg_prcc_pclk("p6_pclk4", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
455 clk_register_clkdev(clk, NULL, "db8540-hash1"); u8540_clk_init()
457 clk = clk_reg_prcc_pclk("p6_pclk5", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
459 clk_register_clkdev(clk, NULL, "cfgreg"); u8540_clk_init()
461 clk = clk_reg_prcc_pclk("p6_pclk6", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
463 clk_register_clkdev(clk, "apb_pclk", "mtu0"); u8540_clk_init()
465 clk = clk_reg_prcc_pclk("p6_pclk7", "per6clk", bases[CLKRST6_INDEX], u8540_clk_init()
467 clk_register_clkdev(clk, "apb_pclk", "mtu1"); u8540_clk_init()
478 clk = clk_reg_prcc_kclk("p1_uart0_kclk", "uartclk", u8540_clk_init()
480 clk_register_clkdev(clk, NULL, "uart0"); u8540_clk_init()
482 clk = clk_reg_prcc_kclk("p1_uart1_kclk", "uartclk", u8540_clk_init()
484 clk_register_clkdev(clk, NULL, "uart1"); u8540_clk_init()
486 clk = clk_reg_prcc_kclk("p1_i2c1_kclk", "i2cclk", u8540_clk_init()
488 clk_register_clkdev(clk, NULL, "nmk-i2c.1"); u8540_clk_init()
490 clk = clk_reg_prcc_kclk("p1_msp0_kclk", "msp02clk", u8540_clk_init()
492 clk_register_clkdev(clk, NULL, "msp0"); u8540_clk_init()
493 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.0"); u8540_clk_init()
495 clk = clk_reg_prcc_kclk("p1_msp1_kclk", "msp1clk", u8540_clk_init()
497 clk_register_clkdev(clk, NULL, "msp1"); u8540_clk_init()
498 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.1"); u8540_clk_init()
500 clk = clk_reg_prcc_kclk("p1_sdi0_kclk", "sdmmchclk", u8540_clk_init()
502 clk_register_clkdev(clk, NULL, "sdi0"); u8540_clk_init()
504 clk = clk_reg_prcc_kclk("p1_i2c2_kclk", "i2cclk", u8540_clk_init()
506 clk_register_clkdev(clk, NULL, "nmk-i2c.2"); u8540_clk_init()
508 clk = clk_reg_prcc_kclk("p1_slimbus0_kclk", "slimclk", u8540_clk_init()
510 clk_register_clkdev(clk, NULL, "slimbus0"); u8540_clk_init()
512 clk = clk_reg_prcc_kclk("p1_i2c4_kclk", "i2cclk", u8540_clk_init()
514 clk_register_clkdev(clk, NULL, "nmk-i2c.4"); u8540_clk_init()
516 clk = clk_reg_prcc_kclk("p1_msp3_kclk", "msp1clk", u8540_clk_init()
518 clk_register_clkdev(clk, NULL, "msp3"); u8540_clk_init()
519 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.3"); u8540_clk_init()
522 clk = clk_reg_prcc_kclk("p2_i2c3_kclk", "i2cclk", u8540_clk_init()
524 clk_register_clkdev(clk, NULL, "nmk-i2c.3"); u8540_clk_init()
526 clk = clk_reg_prcc_kclk("p2_pwl_kclk", "rtc32k", u8540_clk_init()
528 clk_register_clkdev(clk, NULL, "pwl"); u8540_clk_init()
530 clk = clk_reg_prcc_kclk("p2_sdi4_kclk", "sdmmchclk", u8540_clk_init()
532 clk_register_clkdev(clk, NULL, "sdi4"); u8540_clk_init()
534 clk = clk_reg_prcc_kclk("p2_msp2_kclk", "msp02clk", u8540_clk_init()
536 clk_register_clkdev(clk, NULL, "msp2"); u8540_clk_init()
537 clk_register_clkdev(clk, NULL, "dbx5x0-msp-i2s.2"); u8540_clk_init()
539 clk = clk_reg_prcc_kclk("p2_sdi1_kclk", "sdmmchclk", u8540_clk_init()
541 clk_register_clkdev(clk, NULL, "sdi1"); u8540_clk_init()
543 clk = clk_reg_prcc_kclk("p2_sdi3_kclk", "sdmmcclk", u8540_clk_init()
545 clk_register_clkdev(clk, NULL, "sdi3"); u8540_clk_init()
547 clk = clk_reg_prcc_kclk("p2_ssirx_kclk", "hsirxclk", u8540_clk_init()
550 clk_register_clkdev(clk, "hsir_hsirxclk", "ste_hsi.0"); u8540_clk_init()
552 clk = clk_reg_prcc_kclk("p2_ssitx_kclk", "hsitxclk", u8540_clk_init()
555 clk_register_clkdev(clk, "hsit_hsitxclk", "ste_hsi.0"); u8540_clk_init()
558 clk = clk_reg_prcc_kclk("p2_msp4_kclk", "msp02clk", u8540_clk_init()
560 clk_register_clkdev(clk, NULL, "msp4"); u8540_clk_init()
561 clk_register_clkdev(clk, "msp4", "ab85xx-codec.0"); u8540_clk_init()
564 clk = clk_reg_prcc_kclk("p3_ssp0_kclk", "sspclk", u8540_clk_init()
566 clk_register_clkdev(clk, NULL, "ssp0"); u8540_clk_init()
568 clk = clk_reg_prcc_kclk("p3_ssp1_kclk", "sspclk", u8540_clk_init()
570 clk_register_clkdev(clk, NULL, "ssp1"); u8540_clk_init()
572 clk = clk_reg_prcc_kclk("p3_i2c0_kclk", "i2cclk", u8540_clk_init()
574 clk_register_clkdev(clk, NULL, "nmk-i2c.0"); u8540_clk_init()
576 clk = clk_reg_prcc_kclk("p3_sdi2_kclk", "sdmmchclk", u8540_clk_init()
578 clk_register_clkdev(clk, NULL, "sdi2"); u8540_clk_init()
580 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", u8540_clk_init()
582 clk_register_clkdev(clk, NULL, "ske"); u8540_clk_init()
583 clk_register_clkdev(clk, NULL, "nmk-ske-keypad"); u8540_clk_init()
585 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", u8540_clk_init()
587 clk_register_clkdev(clk, NULL, "uart2"); u8540_clk_init()
589 clk = clk_reg_prcc_kclk("p3_sdi5_kclk", "sdmmcclk", u8540_clk_init()
591 clk_register_clkdev(clk, NULL, "sdi5"); u8540_clk_init()
593 clk = clk_reg_prcc_kclk("p3_i2c5_kclk", "i2cclk", u8540_clk_init()
595 clk_register_clkdev(clk, NULL, "nmk-i2c.5"); u8540_clk_init()
597 clk = clk_reg_prcc_kclk("p3_i2c6_kclk", "i2cclk", u8540_clk_init()
599 clk_register_clkdev(clk, NULL, "nmk-i2c.6"); u8540_clk_init()
601 clk = clk_reg_prcc_kclk("p3_uart3_kclk", "uartclk", u8540_clk_init()
603 clk_register_clkdev(clk, NULL, "uart3"); u8540_clk_init()
605 clk = clk_reg_prcc_kclk("p3_uart4_kclk", "uartclk", u8540_clk_init()
607 clk_register_clkdev(clk, NULL, "uart4"); u8540_clk_init()
610 clk = clk_reg_prcc_kclk("p6_rng_kclk", "rngclk", u8540_clk_init()
612 clk_register_clkdev(clk, NULL, "rng"); u8540_clk_init()
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| H A D | clk-prcc.c | 10 #include <linux/clk-provider.h>
16 #include "clk.h"
38 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_pclk_enable() local
40 writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); clk_prcc_pclk_enable()
41 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) clk_prcc_pclk_enable()
44 clk->is_enabled = 1; clk_prcc_pclk_enable()
50 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_pclk_disable() local
52 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); clk_prcc_pclk_disable()
53 clk->is_enabled = 0; clk_prcc_pclk_disable()
58 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_kclk_enable() local
60 writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); clk_prcc_kclk_enable()
61 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) clk_prcc_kclk_enable()
64 clk->is_enabled = 1; clk_prcc_kclk_enable()
70 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_kclk_disable() local
72 writel(clk->cg_sel, (clk->base + PRCC_KCKDIS)); clk_prcc_kclk_disable()
73 clk->is_enabled = 0; clk_prcc_kclk_disable()
78 struct clk_prcc *clk = to_clk_prcc(hw); clk_prcc_is_enabled() local
79 return clk->is_enabled; clk_prcc_is_enabled()
94 static struct clk *clk_reg_prcc(const char *name, clk_reg_prcc()
101 struct clk_prcc *clk; clk_reg_prcc() local
103 struct clk *clk_reg; clk_reg_prcc()
110 clk = kzalloc(sizeof(struct clk_prcc), GFP_KERNEL); clk_reg_prcc()
111 if (!clk) { clk_reg_prcc()
112 pr_err("clk_prcc: %s could not allocate clk\n", __func__); clk_reg_prcc()
116 clk->base = ioremap(phy_base, SZ_4K); clk_reg_prcc()
117 if (!clk->base) clk_reg_prcc()
120 clk->cg_sel = cg_sel; clk_reg_prcc()
121 clk->is_enabled = 1; clk_reg_prcc()
128 clk->hw.init = &clk_prcc_init; clk_reg_prcc()
130 clk_reg = clk_register(NULL, &clk->hw); clk_reg_prcc()
137 iounmap(clk->base); clk_reg_prcc()
139 kfree(clk); clk_reg_prcc()
140 pr_err("clk_prcc: %s failed to register clk\n", __func__); clk_reg_prcc()
144 struct clk *clk_reg_prcc_pclk(const char *name, clk_reg_prcc_pclk()
154 struct clk *clk_reg_prcc_kclk(const char *name, clk_reg_prcc_kclk()
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| H A D | clk-sysctrl.c | 10 #include <linux/clk-provider.h>
17 #include "clk.h"
39 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_prepare() local
41 ret = ab8500_sysctrl_write(clk->reg_sel[0], clk->reg_mask[0], clk_sysctrl_prepare()
42 clk->reg_bits[0]); clk_sysctrl_prepare()
44 if (!ret && clk->enable_delay_us) clk_sysctrl_prepare()
45 usleep_range(clk->enable_delay_us, clk->enable_delay_us); clk_sysctrl_prepare()
52 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_unprepare() local
53 if (ab8500_sysctrl_clear(clk->reg_sel[0], clk->reg_mask[0])) clk_sysctrl_unprepare()
54 dev_err(clk->dev, "clk_sysctrl: %s fail to clear %s.\n", clk_sysctrl_unprepare()
61 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_recalc_rate() local
62 return clk->rate; clk_sysctrl_recalc_rate()
67 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_set_parent() local
68 u8 old_index = clk->parent_index; clk_sysctrl_set_parent()
71 if (clk->reg_sel[old_index]) { clk_sysctrl_set_parent()
72 ret = ab8500_sysctrl_clear(clk->reg_sel[old_index], clk_sysctrl_set_parent()
73 clk->reg_mask[old_index]); clk_sysctrl_set_parent()
78 if (clk->reg_sel[index]) { clk_sysctrl_set_parent()
79 ret = ab8500_sysctrl_write(clk->reg_sel[index], clk_sysctrl_set_parent()
80 clk->reg_mask[index], clk_sysctrl_set_parent()
81 clk->reg_bits[index]); clk_sysctrl_set_parent()
83 if (clk->reg_sel[old_index]) clk_sysctrl_set_parent()
84 ab8500_sysctrl_write(clk->reg_sel[old_index], clk_sysctrl_set_parent()
85 clk->reg_mask[old_index], clk_sysctrl_set_parent()
86 clk->reg_bits[old_index]); clk_sysctrl_set_parent()
90 clk->parent_index = index; clk_sysctrl_set_parent()
97 struct clk_sysctrl *clk = to_clk_sysctrl(hw); clk_sysctrl_get_parent() local
98 return clk->parent_index; clk_sysctrl_get_parent()
117 static struct clk *clk_reg_sysctrl(struct device *dev, clk_reg_sysctrl()
129 struct clk_sysctrl *clk; clk_reg_sysctrl() local
131 struct clk *clk_reg; clk_reg_sysctrl()
142 clk = devm_kzalloc(dev, sizeof(struct clk_sysctrl), GFP_KERNEL); clk_reg_sysctrl()
143 if (!clk) { clk_reg_sysctrl()
144 dev_err(dev, "clk_sysctrl: could not allocate clk\n"); clk_reg_sysctrl()
149 clk->reg_sel[0] = reg_sel[0]; clk_reg_sysctrl()
150 clk->reg_bits[0] = reg_bits[0]; clk_reg_sysctrl()
151 clk->reg_mask[0] = reg_mask[0]; clk_reg_sysctrl()
155 clk->reg_sel[i] = reg_sel[i]; clk_reg_sysctrl()
156 clk->reg_bits[i] = reg_bits[i]; clk_reg_sysctrl()
157 clk->reg_mask[i] = reg_mask[i]; clk_reg_sysctrl()
160 clk->parent_index = 0; clk_reg_sysctrl()
161 clk->rate = rate; clk_reg_sysctrl()
162 clk->enable_delay_us = enable_delay_us; clk_reg_sysctrl()
163 clk->dev = dev; clk_reg_sysctrl()
170 clk->hw.init = &clk_sysctrl_init; clk_reg_sysctrl()
172 clk_reg = devm_clk_register(clk->dev, &clk->hw); clk_reg_sysctrl()
179 struct clk *clk_reg_sysctrl_gate(struct device *dev, clk_reg_sysctrl_gate()
196 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev, clk_reg_sysctrl_gate_fixed_rate()
215 struct clk *clk_reg_sysctrl_set_parent(struct device *dev, clk_reg_sysctrl_set_parent()
|
| H A D | abx500-clk.c | 17 #include <linux/clk-provider.h>
19 #include "clk.h"
25 struct clk *clk; ab8500_reg_clks() local
43 clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK, ab8500_reg_clks()
45 clk_register_clkdev(clk, "sysclk", "ab8500-usb.0"); ab8500_reg_clks()
46 clk_register_clkdev(clk, "sysclk", "ab-iddet.0"); ab8500_reg_clks()
47 clk_register_clkdev(clk, "sysclk", "snd-soc-mop500.0"); ab8500_reg_clks()
48 clk_register_clkdev(clk, "sysclk", "shrm_bus"); ab8500_reg_clks()
51 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk", ab8500_reg_clks()
54 clk_register_clkdev(clk, "sysclk", "0-0070"); ab8500_reg_clks()
57 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk", ab8500_reg_clks()
60 clk_register_clkdev(clk, "sysclk", "cg1960_core.0"); ab8500_reg_clks()
63 clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk", ab8500_reg_clks()
68 clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL, ab8500_reg_clks()
72 clk_register_clkdev(clk, "ulpclk", "snd-soc-mop500.0"); ab8500_reg_clks()
75 clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2, ab8500_reg_clks()
77 clk_register_clkdev(clk, "intclk", "snd-soc-mop500.0"); ab8500_reg_clks()
78 clk_register_clkdev(clk, NULL, "ab8500-pwm.1"); ab8500_reg_clks()
81 clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk", ab8500_reg_clks()
84 clk_register_clkdev(clk, "audioclk", "ab8500-codec.0"); ab8500_reg_clks()
122 .name = "abx500-clk",
135 MODULE_DESCRIPTION("ABX500 clk driver");
|
| H A D | clk-prcmu.c | 10 #include <linux/clk-provider.h>
15 #include "clk.h"
32 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_prepare() local
34 ret = prcmu_request_clock(clk->cg_sel, true); clk_prcmu_prepare()
36 clk->is_prepared = 1; clk_prcmu_prepare()
43 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_unprepare() local
44 if (prcmu_request_clock(clk->cg_sel, false)) clk_prcmu_unprepare()
48 clk->is_prepared = 0; clk_prcmu_unprepare()
53 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_is_prepared() local
54 return clk->is_prepared; clk_prcmu_is_prepared()
59 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_enable() local
60 clk->is_enabled = 1; clk_prcmu_enable()
66 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_disable() local
67 clk->is_enabled = 0; clk_prcmu_disable()
72 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_is_enabled() local
73 return clk->is_enabled; clk_prcmu_is_enabled()
79 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_recalc_rate() local
80 return prcmu_clock_rate(clk->cg_sel); clk_prcmu_recalc_rate()
86 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_round_rate() local
87 return prcmu_round_clock_rate(clk->cg_sel, rate); clk_prcmu_round_rate()
93 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_set_rate() local
94 return prcmu_set_clock_rate(clk->cg_sel, rate); clk_prcmu_set_rate()
100 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_prepare() local
102 if (!clk->opp_requested) { clk_prcmu_opp_prepare()
111 clk->opp_requested = 1; clk_prcmu_opp_prepare()
114 err = prcmu_request_clock(clk->cg_sel, true); clk_prcmu_opp_prepare()
118 clk->opp_requested = 0; clk_prcmu_opp_prepare()
122 clk->is_prepared = 1; clk_prcmu_opp_prepare()
128 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_unprepare() local
130 if (prcmu_request_clock(clk->cg_sel, false)) { clk_prcmu_opp_unprepare()
136 if (clk->opp_requested) { clk_prcmu_opp_unprepare()
139 clk->opp_requested = 0; clk_prcmu_opp_unprepare()
142 clk->is_prepared = 0; clk_prcmu_opp_unprepare()
148 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_volt_prepare() local
150 if (!clk->opp_requested) { clk_prcmu_opp_volt_prepare()
157 clk->opp_requested = 1; clk_prcmu_opp_volt_prepare()
160 err = prcmu_request_clock(clk->cg_sel, true); clk_prcmu_opp_volt_prepare()
163 clk->opp_requested = 0; clk_prcmu_opp_volt_prepare()
167 clk->is_prepared = 1; clk_prcmu_opp_volt_prepare()
173 struct clk_prcmu *clk = to_clk_prcmu(hw); clk_prcmu_opp_volt_unprepare() local
175 if (prcmu_request_clock(clk->cg_sel, false)) { clk_prcmu_opp_volt_unprepare()
181 if (clk->opp_requested) { clk_prcmu_opp_volt_unprepare()
183 clk->opp_requested = 0; clk_prcmu_opp_volt_unprepare()
186 clk->is_prepared = 0; clk_prcmu_opp_volt_unprepare()
245 static struct clk *clk_reg_prcmu(const char *name, clk_reg_prcmu()
252 struct clk_prcmu *clk; clk_reg_prcmu() local
254 struct clk *clk_reg; clk_reg_prcmu()
261 clk = kzalloc(sizeof(struct clk_prcmu), GFP_KERNEL); clk_reg_prcmu()
262 if (!clk) { clk_reg_prcmu()
263 pr_err("clk_prcmu: %s could not allocate clk\n", __func__); clk_reg_prcmu()
267 clk->cg_sel = cg_sel; clk_reg_prcmu()
268 clk->is_prepared = 1; clk_reg_prcmu()
269 clk->is_enabled = 1; clk_reg_prcmu()
270 clk->opp_requested = 0; clk_reg_prcmu()
280 clk->hw.init = &clk_prcmu_init; clk_reg_prcmu()
282 clk_reg = clk_register(NULL, &clk->hw); clk_reg_prcmu()
289 kfree(clk); clk_reg_prcmu()
290 pr_err("clk_prcmu: %s failed to register clk\n", __func__); clk_reg_prcmu()
294 struct clk *clk_reg_prcmu_scalable(const char *name, clk_reg_prcmu_scalable()
304 struct clk *clk_reg_prcmu_gate(const char *name, clk_reg_prcmu_gate()
313 struct clk *clk_reg_prcmu_scalable_rate(const char *name, clk_reg_prcmu_scalable_rate()
323 struct clk *clk_reg_prcmu_rate(const char *name, clk_reg_prcmu_rate()
332 struct clk *clk_reg_prcmu_opp_gate(const char *name, clk_reg_prcmu_opp_gate()
341 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, clk_reg_prcmu_opp_volt_scalable()
|
| H A D | clk.h | 16 struct clk;
18 struct clk *clk_reg_prcc_pclk(const char *name,
24 struct clk *clk_reg_prcc_kclk(const char *name,
30 struct clk *clk_reg_prcmu_scalable(const char *name,
36 struct clk *clk_reg_prcmu_gate(const char *name,
41 struct clk *clk_reg_prcmu_scalable_rate(const char *name,
47 struct clk *clk_reg_prcmu_rate(const char *name,
52 struct clk *clk_reg_prcmu_opp_gate(const char *name,
57 struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
63 struct clk *clk_reg_sysctrl_gate(struct device *dev,
72 struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
82 struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
|
| H A D | u9540_clk.c | 10 #include <linux/clk-provider.h>
12 #include <linux/platform_data/clk-ux500.h>
13 #include "clk.h"
|
| /linux-4.4.14/arch/mips/include/asm/ |
| H A D | clock.h | 7 #include <linux/clk.h>
9 struct clk;
12 void (*init) (struct clk *clk);
13 void (*enable) (struct clk *clk);
14 void (*disable) (struct clk *clk);
15 void (*recalc) (struct clk *clk);
16 int (*set_rate) (struct clk *clk, unsigned long rate, int algo_id);
17 long (*round_rate) (struct clk *clk, unsigned long rate);
20 struct clk { struct
26 struct clk *parent;
40 int __clk_enable(struct clk *);
41 void __clk_disable(struct clk *);
43 void clk_recalc_rate(struct clk *);
45 int clk_register(struct clk *);
46 void clk_unregister(struct clk *);
|
| H A D | clkdev.h | 10 * Helper for the clk API to assist looking up a struct clk.
18 #define __clk_get(clk) ({ 1; })
19 #define __clk_put(clk) do { } while (0)
|
| /linux-4.4.14/drivers/clk/mmp/ |
| H A D | clk-mmp2.c | 12 #include <linux/clk.h>
22 #include "clk.h"
79 struct clk *clk; mmp2_clk_init() local
80 struct clk *vctcxo; mmp2_clk_init()
103 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); mmp2_clk_init()
104 clk_register_clkdev(clk, "clk32", NULL); mmp2_clk_init()
110 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, mmp2_clk_init()
112 clk_register_clkdev(clk, "pll1", NULL); mmp2_clk_init()
114 clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT, mmp2_clk_init()
116 clk_register_clkdev(clk, "usb_pll", NULL); mmp2_clk_init()
118 clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT, mmp2_clk_init()
120 clk_register_clkdev(clk, "pll2", NULL); mmp2_clk_init()
122 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", mmp2_clk_init()
124 clk_register_clkdev(clk, "pll1_2", NULL); mmp2_clk_init()
126 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", mmp2_clk_init()
128 clk_register_clkdev(clk, "pll1_4", NULL); mmp2_clk_init()
130 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", mmp2_clk_init()
132 clk_register_clkdev(clk, "pll1_8", NULL); mmp2_clk_init()
134 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", mmp2_clk_init()
136 clk_register_clkdev(clk, "pll1_16", NULL); mmp2_clk_init()
138 clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4", mmp2_clk_init()
140 clk_register_clkdev(clk, "pll1_20", NULL); mmp2_clk_init()
142 clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1", mmp2_clk_init()
144 clk_register_clkdev(clk, "pll1_3", NULL); mmp2_clk_init()
146 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3", mmp2_clk_init()
148 clk_register_clkdev(clk, "pll1_6", NULL); mmp2_clk_init()
150 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", mmp2_clk_init()
152 clk_register_clkdev(clk, "pll1_12", NULL); mmp2_clk_init()
154 clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2", mmp2_clk_init()
156 clk_register_clkdev(clk, "pll2_2", NULL); mmp2_clk_init()
158 clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2", mmp2_clk_init()
160 clk_register_clkdev(clk, "pll2_4", NULL); mmp2_clk_init()
162 clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4", mmp2_clk_init()
164 clk_register_clkdev(clk, "pll2_8", NULL); mmp2_clk_init()
166 clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8", mmp2_clk_init()
168 clk_register_clkdev(clk, "pll2_16", NULL); mmp2_clk_init()
170 clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2", mmp2_clk_init()
172 clk_register_clkdev(clk, "pll2_3", NULL); mmp2_clk_init()
174 clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3", mmp2_clk_init()
176 clk_register_clkdev(clk, "pll2_6", NULL); mmp2_clk_init()
178 clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6", mmp2_clk_init()
180 clk_register_clkdev(clk, "pll2_12", NULL); mmp2_clk_init()
182 clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo", mmp2_clk_init()
184 clk_register_clkdev(clk, "vctcxo_2", NULL); mmp2_clk_init()
186 clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2", mmp2_clk_init()
188 clk_register_clkdev(clk, "vctcxo_4", NULL); mmp2_clk_init()
190 clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0, mmp2_clk_init()
194 clk_set_rate(clk, 14745600); mmp2_clk_init()
195 clk_register_clkdev(clk, "uart_pll", NULL); mmp2_clk_init()
197 clk = mmp_clk_register_apbc("twsi0", "vctcxo", mmp2_clk_init()
199 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); mmp2_clk_init()
201 clk = mmp_clk_register_apbc("twsi1", "vctcxo", mmp2_clk_init()
203 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); mmp2_clk_init()
205 clk = mmp_clk_register_apbc("twsi2", "vctcxo", mmp2_clk_init()
207 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2"); mmp2_clk_init()
209 clk = mmp_clk_register_apbc("twsi3", "vctcxo", mmp2_clk_init()
211 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3"); mmp2_clk_init()
213 clk = mmp_clk_register_apbc("twsi4", "vctcxo", mmp2_clk_init()
215 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4"); mmp2_clk_init()
217 clk = mmp_clk_register_apbc("twsi5", "vctcxo", mmp2_clk_init()
219 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5"); mmp2_clk_init()
221 clk = mmp_clk_register_apbc("gpio", "vctcxo", mmp2_clk_init()
223 clk_register_clkdev(clk, NULL, "mmp2-gpio"); mmp2_clk_init()
225 clk = mmp_clk_register_apbc("kpc", "clk32", mmp2_clk_init()
227 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); mmp2_clk_init()
229 clk = mmp_clk_register_apbc("rtc", "clk32", mmp2_clk_init()
231 clk_register_clkdev(clk, NULL, "mmp-rtc"); mmp2_clk_init()
233 clk = mmp_clk_register_apbc("pwm0", "vctcxo", mmp2_clk_init()
235 clk_register_clkdev(clk, NULL, "mmp2-pwm.0"); mmp2_clk_init()
237 clk = mmp_clk_register_apbc("pwm1", "vctcxo", mmp2_clk_init()
239 clk_register_clkdev(clk, NULL, "mmp2-pwm.1"); mmp2_clk_init()
241 clk = mmp_clk_register_apbc("pwm2", "vctcxo", mmp2_clk_init()
243 clk_register_clkdev(clk, NULL, "mmp2-pwm.2"); mmp2_clk_init()
245 clk = mmp_clk_register_apbc("pwm3", "vctcxo", mmp2_clk_init()
247 clk_register_clkdev(clk, NULL, "mmp2-pwm.3"); mmp2_clk_init()
249 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, mmp2_clk_init()
253 clk_set_parent(clk, vctcxo); mmp2_clk_init()
254 clk_register_clkdev(clk, "uart_mux.0", NULL); mmp2_clk_init()
256 clk = mmp_clk_register_apbc("uart0", "uart0_mux", mmp2_clk_init()
258 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); mmp2_clk_init()
260 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, mmp2_clk_init()
264 clk_set_parent(clk, vctcxo); mmp2_clk_init()
265 clk_register_clkdev(clk, "uart_mux.1", NULL); mmp2_clk_init()
267 clk = mmp_clk_register_apbc("uart1", "uart1_mux", mmp2_clk_init()
269 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); mmp2_clk_init()
271 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, mmp2_clk_init()
275 clk_set_parent(clk, vctcxo); mmp2_clk_init()
276 clk_register_clkdev(clk, "uart_mux.2", NULL); mmp2_clk_init()
278 clk = mmp_clk_register_apbc("uart2", "uart2_mux", mmp2_clk_init()
280 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); mmp2_clk_init()
282 clk = clk_register_mux(NULL, "uart3_mux", uart_parent, mmp2_clk_init()
286 clk_set_parent(clk, vctcxo); mmp2_clk_init()
287 clk_register_clkdev(clk, "uart_mux.3", NULL); mmp2_clk_init()
289 clk = mmp_clk_register_apbc("uart3", "uart3_mux", mmp2_clk_init()
291 clk_register_clkdev(clk, NULL, "pxa2xx-uart.3"); mmp2_clk_init()
293 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, mmp2_clk_init()
297 clk_register_clkdev(clk, "uart_mux.0", NULL); mmp2_clk_init()
299 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", mmp2_clk_init()
301 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); mmp2_clk_init()
303 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, mmp2_clk_init()
307 clk_register_clkdev(clk, "ssp_mux.1", NULL); mmp2_clk_init()
309 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", mmp2_clk_init()
311 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); mmp2_clk_init()
313 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, mmp2_clk_init()
317 clk_register_clkdev(clk, "ssp_mux.2", NULL); mmp2_clk_init()
319 clk = mmp_clk_register_apbc("ssp2", "ssp2_mux", mmp2_clk_init()
321 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); mmp2_clk_init()
323 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, mmp2_clk_init()
327 clk_register_clkdev(clk, "ssp_mux.3", NULL); mmp2_clk_init()
329 clk = mmp_clk_register_apbc("ssp3", "ssp3_mux", mmp2_clk_init()
331 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); mmp2_clk_init()
333 clk = clk_register_mux(NULL, "sdh_mux", sdh_parent, mmp2_clk_init()
337 clk_register_clkdev(clk, "sdh_mux", NULL); mmp2_clk_init()
339 clk = clk_register_divider(NULL, "sdh_div", "sdh_mux", mmp2_clk_init()
342 clk_register_clkdev(clk, "sdh_div", NULL); mmp2_clk_init()
344 clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0, mmp2_clk_init()
346 clk_register_clkdev(clk, NULL, "sdhci-pxav3.0"); mmp2_clk_init()
348 clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1, mmp2_clk_init()
350 clk_register_clkdev(clk, NULL, "sdhci-pxav3.1"); mmp2_clk_init()
352 clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2, mmp2_clk_init()
354 clk_register_clkdev(clk, NULL, "sdhci-pxav3.2"); mmp2_clk_init()
356 clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3, mmp2_clk_init()
358 clk_register_clkdev(clk, NULL, "sdhci-pxav3.3"); mmp2_clk_init()
360 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, mmp2_clk_init()
362 clk_register_clkdev(clk, "usb_clk", NULL); mmp2_clk_init()
364 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, mmp2_clk_init()
368 clk_register_clkdev(clk, "disp_mux.0", NULL); mmp2_clk_init()
370 clk = clk_register_divider(NULL, "disp0_div", "disp0_mux", mmp2_clk_init()
373 clk_register_clkdev(clk, "disp_div.0", NULL); mmp2_clk_init()
375 clk = mmp_clk_register_apmu("disp0", "disp0_div", mmp2_clk_init()
377 clk_register_clkdev(clk, NULL, "mmp-disp.0"); mmp2_clk_init()
379 clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0, mmp2_clk_init()
381 clk_register_clkdev(clk, "disp_sphy_div.0", NULL); mmp2_clk_init()
383 clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div", mmp2_clk_init()
385 clk_register_clkdev(clk, "disp_sphy.0", NULL); mmp2_clk_init()
387 clk = clk_register_mux(NULL, "disp1_mux", disp_parent, mmp2_clk_init()
391 clk_register_clkdev(clk, "disp_mux.1", NULL); mmp2_clk_init()
393 clk = clk_register_divider(NULL, "disp1_div", "disp1_mux", mmp2_clk_init()
396 clk_register_clkdev(clk, "disp_div.1", NULL); mmp2_clk_init()
398 clk = mmp_clk_register_apmu("disp1", "disp1_div", mmp2_clk_init()
400 clk_register_clkdev(clk, NULL, "mmp-disp.1"); mmp2_clk_init()
402 clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo", mmp2_clk_init()
404 clk_register_clkdev(clk, "ccic_arbiter", NULL); mmp2_clk_init()
406 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, mmp2_clk_init()
410 clk_register_clkdev(clk, "ccic_mux.0", NULL); mmp2_clk_init()
412 clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux", mmp2_clk_init()
415 clk_register_clkdev(clk, "ccic_div.0", NULL); mmp2_clk_init()
417 clk = mmp_clk_register_apmu("ccic0", "ccic0_div", mmp2_clk_init()
419 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); mmp2_clk_init()
421 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div", mmp2_clk_init()
423 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); mmp2_clk_init()
425 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div", mmp2_clk_init()
428 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0"); mmp2_clk_init()
430 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", mmp2_clk_init()
432 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); mmp2_clk_init()
434 clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent, mmp2_clk_init()
438 clk_register_clkdev(clk, "ccic_mux.1", NULL); mmp2_clk_init()
440 clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux", mmp2_clk_init()
443 clk_register_clkdev(clk, "ccic_div.1", NULL); mmp2_clk_init()
445 clk = mmp_clk_register_apmu("ccic1", "ccic1_div", mmp2_clk_init()
447 clk_register_clkdev(clk, "fnclk", "mmp-ccic.1"); mmp2_clk_init()
449 clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div", mmp2_clk_init()
451 clk_register_clkdev(clk, "phyclk", "mmp-ccic.1"); mmp2_clk_init()
453 clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div", mmp2_clk_init()
456 clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1"); mmp2_clk_init()
458 clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div", mmp2_clk_init()
460 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1"); mmp2_clk_init()
|
| H A D | clk-pxa168.c | 12 #include <linux/clk.h>
22 #include "clk.h"
72 struct clk *clk; pxa168_clk_init() local
73 struct clk *uart_pll; pxa168_clk_init()
96 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); pxa168_clk_init()
97 clk_register_clkdev(clk, "clk32", NULL); pxa168_clk_init()
99 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, pxa168_clk_init()
101 clk_register_clkdev(clk, "vctcxo", NULL); pxa168_clk_init()
103 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, pxa168_clk_init()
105 clk_register_clkdev(clk, "pll1", NULL); pxa168_clk_init()
107 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", pxa168_clk_init()
109 clk_register_clkdev(clk, "pll1_2", NULL); pxa168_clk_init()
111 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", pxa168_clk_init()
113 clk_register_clkdev(clk, "pll1_4", NULL); pxa168_clk_init()
115 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", pxa168_clk_init()
117 clk_register_clkdev(clk, "pll1_8", NULL); pxa168_clk_init()
119 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", pxa168_clk_init()
121 clk_register_clkdev(clk, "pll1_16", NULL); pxa168_clk_init()
123 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", pxa168_clk_init()
125 clk_register_clkdev(clk, "pll1_6", NULL); pxa168_clk_init()
127 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", pxa168_clk_init()
129 clk_register_clkdev(clk, "pll1_12", NULL); pxa168_clk_init()
131 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", pxa168_clk_init()
133 clk_register_clkdev(clk, "pll1_24", NULL); pxa168_clk_init()
135 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", pxa168_clk_init()
137 clk_register_clkdev(clk, "pll1_48", NULL); pxa168_clk_init()
139 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", pxa168_clk_init()
141 clk_register_clkdev(clk, "pll1_96", NULL); pxa168_clk_init()
143 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", pxa168_clk_init()
145 clk_register_clkdev(clk, "pll1_13", NULL); pxa168_clk_init()
147 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", pxa168_clk_init()
149 clk_register_clkdev(clk, "pll1_13_1_5", NULL); pxa168_clk_init()
151 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", pxa168_clk_init()
153 clk_register_clkdev(clk, "pll1_2_1_5", NULL); pxa168_clk_init()
155 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", pxa168_clk_init()
157 clk_register_clkdev(clk, "pll1_3_16", NULL); pxa168_clk_init()
166 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", pxa168_clk_init()
168 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); pxa168_clk_init()
170 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", pxa168_clk_init()
172 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); pxa168_clk_init()
174 clk = mmp_clk_register_apbc("gpio", "vctcxo", pxa168_clk_init()
176 clk_register_clkdev(clk, NULL, "mmp-gpio"); pxa168_clk_init()
178 clk = mmp_clk_register_apbc("kpc", "clk32", pxa168_clk_init()
180 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); pxa168_clk_init()
182 clk = mmp_clk_register_apbc("rtc", "clk32", pxa168_clk_init()
184 clk_register_clkdev(clk, NULL, "sa1100-rtc"); pxa168_clk_init()
186 clk = mmp_clk_register_apbc("pwm0", "pll1_48", pxa168_clk_init()
188 clk_register_clkdev(clk, NULL, "pxa168-pwm.0"); pxa168_clk_init()
190 clk = mmp_clk_register_apbc("pwm1", "pll1_48", pxa168_clk_init()
192 clk_register_clkdev(clk, NULL, "pxa168-pwm.1"); pxa168_clk_init()
194 clk = mmp_clk_register_apbc("pwm2", "pll1_48", pxa168_clk_init()
196 clk_register_clkdev(clk, NULL, "pxa168-pwm.2"); pxa168_clk_init()
198 clk = mmp_clk_register_apbc("pwm3", "pll1_48", pxa168_clk_init()
200 clk_register_clkdev(clk, NULL, "pxa168-pwm.3"); pxa168_clk_init()
202 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, pxa168_clk_init()
206 clk_set_parent(clk, uart_pll); pxa168_clk_init()
207 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa168_clk_init()
209 clk = mmp_clk_register_apbc("uart0", "uart0_mux", pxa168_clk_init()
211 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); pxa168_clk_init()
213 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, pxa168_clk_init()
217 clk_set_parent(clk, uart_pll); pxa168_clk_init()
218 clk_register_clkdev(clk, "uart_mux.1", NULL); pxa168_clk_init()
220 clk = mmp_clk_register_apbc("uart1", "uart1_mux", pxa168_clk_init()
222 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); pxa168_clk_init()
224 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, pxa168_clk_init()
228 clk_set_parent(clk, uart_pll); pxa168_clk_init()
229 clk_register_clkdev(clk, "uart_mux.2", NULL); pxa168_clk_init()
231 clk = mmp_clk_register_apbc("uart2", "uart2_mux", pxa168_clk_init()
233 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); pxa168_clk_init()
235 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, pxa168_clk_init()
239 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa168_clk_init()
241 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", apbc_base + APBC_SSP0, pxa168_clk_init()
243 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); pxa168_clk_init()
245 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, pxa168_clk_init()
249 clk_register_clkdev(clk, "ssp_mux.1", NULL); pxa168_clk_init()
251 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", apbc_base + APBC_SSP1, pxa168_clk_init()
253 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); pxa168_clk_init()
255 clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent, pxa168_clk_init()
259 clk_register_clkdev(clk, "ssp_mux.2", NULL); pxa168_clk_init()
261 clk = mmp_clk_register_apbc("ssp2", "ssp1_mux", apbc_base + APBC_SSP2, pxa168_clk_init()
263 clk_register_clkdev(clk, NULL, "mmp-ssp.2"); pxa168_clk_init()
265 clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent, pxa168_clk_init()
269 clk_register_clkdev(clk, "ssp_mux.3", NULL); pxa168_clk_init()
271 clk = mmp_clk_register_apbc("ssp3", "ssp1_mux", apbc_base + APBC_SSP3, pxa168_clk_init()
273 clk_register_clkdev(clk, NULL, "mmp-ssp.3"); pxa168_clk_init()
275 clk = clk_register_mux(NULL, "ssp4_mux", ssp_parent, pxa168_clk_init()
279 clk_register_clkdev(clk, "ssp_mux.4", NULL); pxa168_clk_init()
281 clk = mmp_clk_register_apbc("ssp4", "ssp1_mux", apbc_base + APBC_SSP4, pxa168_clk_init()
283 clk_register_clkdev(clk, NULL, "mmp-ssp.4"); pxa168_clk_init()
285 clk = mmp_clk_register_apmu("dfc", "pll1_4", apmu_base + APMU_DFC, pxa168_clk_init()
287 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); pxa168_clk_init()
289 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, pxa168_clk_init()
293 clk_register_clkdev(clk, "sdh0_mux", NULL); pxa168_clk_init()
295 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", apmu_base + APMU_SDH0, pxa168_clk_init()
297 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); pxa168_clk_init()
299 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, pxa168_clk_init()
303 clk_register_clkdev(clk, "sdh1_mux", NULL); pxa168_clk_init()
305 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", apmu_base + APMU_SDH1, pxa168_clk_init()
307 clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); pxa168_clk_init()
309 clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB, pxa168_clk_init()
311 clk_register_clkdev(clk, "usb_clk", NULL); pxa168_clk_init()
313 clk = mmp_clk_register_apmu("sph", "usb_pll", apmu_base + APMU_USB, pxa168_clk_init()
315 clk_register_clkdev(clk, "sph_clk", NULL); pxa168_clk_init()
317 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, pxa168_clk_init()
321 clk_register_clkdev(clk, "disp_mux.0", NULL); pxa168_clk_init()
323 clk = mmp_clk_register_apmu("disp0", "disp0_mux", pxa168_clk_init()
325 clk_register_clkdev(clk, "fnclk", "mmp-disp.0"); pxa168_clk_init()
327 clk = mmp_clk_register_apmu("disp0_hclk", "disp0_mux", pxa168_clk_init()
329 clk_register_clkdev(clk, "hclk", "mmp-disp.0"); pxa168_clk_init()
331 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, pxa168_clk_init()
335 clk_register_clkdev(clk, "ccic_mux.0", NULL); pxa168_clk_init()
337 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", pxa168_clk_init()
339 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); pxa168_clk_init()
341 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, pxa168_clk_init()
345 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); pxa168_clk_init()
347 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", pxa168_clk_init()
349 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); pxa168_clk_init()
351 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", pxa168_clk_init()
354 clk_register_clkdev(clk, "sphyclk_div", NULL); pxa168_clk_init()
356 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", pxa168_clk_init()
358 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); pxa168_clk_init()
|
| H A D | clk-pxa910.c | 12 #include <linux/clk.h>
22 #include "clk.h"
70 struct clk *clk; pxa910_clk_init() local
71 struct clk *uart_pll; pxa910_clk_init()
101 clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200); pxa910_clk_init()
102 clk_register_clkdev(clk, "clk32", NULL); pxa910_clk_init()
104 clk = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT, pxa910_clk_init()
106 clk_register_clkdev(clk, "vctcxo", NULL); pxa910_clk_init()
108 clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT, pxa910_clk_init()
110 clk_register_clkdev(clk, "pll1", NULL); pxa910_clk_init()
112 clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1", pxa910_clk_init()
114 clk_register_clkdev(clk, "pll1_2", NULL); pxa910_clk_init()
116 clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2", pxa910_clk_init()
118 clk_register_clkdev(clk, "pll1_4", NULL); pxa910_clk_init()
120 clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4", pxa910_clk_init()
122 clk_register_clkdev(clk, "pll1_8", NULL); pxa910_clk_init()
124 clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8", pxa910_clk_init()
126 clk_register_clkdev(clk, "pll1_16", NULL); pxa910_clk_init()
128 clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_2", pxa910_clk_init()
130 clk_register_clkdev(clk, "pll1_6", NULL); pxa910_clk_init()
132 clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6", pxa910_clk_init()
134 clk_register_clkdev(clk, "pll1_12", NULL); pxa910_clk_init()
136 clk = clk_register_fixed_factor(NULL, "pll1_24", "pll1_12", pxa910_clk_init()
138 clk_register_clkdev(clk, "pll1_24", NULL); pxa910_clk_init()
140 clk = clk_register_fixed_factor(NULL, "pll1_48", "pll1_24", pxa910_clk_init()
142 clk_register_clkdev(clk, "pll1_48", NULL); pxa910_clk_init()
144 clk = clk_register_fixed_factor(NULL, "pll1_96", "pll1_48", pxa910_clk_init()
146 clk_register_clkdev(clk, "pll1_96", NULL); pxa910_clk_init()
148 clk = clk_register_fixed_factor(NULL, "pll1_13", "pll1", pxa910_clk_init()
150 clk_register_clkdev(clk, "pll1_13", NULL); pxa910_clk_init()
152 clk = clk_register_fixed_factor(NULL, "pll1_13_1_5", "pll1", pxa910_clk_init()
154 clk_register_clkdev(clk, "pll1_13_1_5", NULL); pxa910_clk_init()
156 clk = clk_register_fixed_factor(NULL, "pll1_2_1_5", "pll1", pxa910_clk_init()
158 clk_register_clkdev(clk, "pll1_2_1_5", NULL); pxa910_clk_init()
160 clk = clk_register_fixed_factor(NULL, "pll1_3_16", "pll1", pxa910_clk_init()
162 clk_register_clkdev(clk, "pll1_3_16", NULL); pxa910_clk_init()
171 clk = mmp_clk_register_apbc("twsi0", "pll1_13_1_5", pxa910_clk_init()
173 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0"); pxa910_clk_init()
175 clk = mmp_clk_register_apbc("twsi1", "pll1_13_1_5", pxa910_clk_init()
177 clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1"); pxa910_clk_init()
179 clk = mmp_clk_register_apbc("gpio", "vctcxo", pxa910_clk_init()
181 clk_register_clkdev(clk, NULL, "mmp-gpio"); pxa910_clk_init()
183 clk = mmp_clk_register_apbc("kpc", "clk32", pxa910_clk_init()
185 clk_register_clkdev(clk, NULL, "pxa27x-keypad"); pxa910_clk_init()
187 clk = mmp_clk_register_apbc("rtc", "clk32", pxa910_clk_init()
189 clk_register_clkdev(clk, NULL, "sa1100-rtc"); pxa910_clk_init()
191 clk = mmp_clk_register_apbc("pwm0", "pll1_48", pxa910_clk_init()
193 clk_register_clkdev(clk, NULL, "pxa910-pwm.0"); pxa910_clk_init()
195 clk = mmp_clk_register_apbc("pwm1", "pll1_48", pxa910_clk_init()
197 clk_register_clkdev(clk, NULL, "pxa910-pwm.1"); pxa910_clk_init()
199 clk = mmp_clk_register_apbc("pwm2", "pll1_48", pxa910_clk_init()
201 clk_register_clkdev(clk, NULL, "pxa910-pwm.2"); pxa910_clk_init()
203 clk = mmp_clk_register_apbc("pwm3", "pll1_48", pxa910_clk_init()
205 clk_register_clkdev(clk, NULL, "pxa910-pwm.3"); pxa910_clk_init()
207 clk = clk_register_mux(NULL, "uart0_mux", uart_parent, pxa910_clk_init()
211 clk_set_parent(clk, uart_pll); pxa910_clk_init()
212 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa910_clk_init()
214 clk = mmp_clk_register_apbc("uart0", "uart0_mux", pxa910_clk_init()
216 clk_register_clkdev(clk, NULL, "pxa2xx-uart.0"); pxa910_clk_init()
218 clk = clk_register_mux(NULL, "uart1_mux", uart_parent, pxa910_clk_init()
222 clk_set_parent(clk, uart_pll); pxa910_clk_init()
223 clk_register_clkdev(clk, "uart_mux.1", NULL); pxa910_clk_init()
225 clk = mmp_clk_register_apbc("uart1", "uart1_mux", pxa910_clk_init()
227 clk_register_clkdev(clk, NULL, "pxa2xx-uart.1"); pxa910_clk_init()
229 clk = clk_register_mux(NULL, "uart2_mux", uart_parent, pxa910_clk_init()
233 clk_set_parent(clk, uart_pll); pxa910_clk_init()
234 clk_register_clkdev(clk, "uart_mux.2", NULL); pxa910_clk_init()
236 clk = mmp_clk_register_apbc("uart2", "uart2_mux", pxa910_clk_init()
238 clk_register_clkdev(clk, NULL, "pxa2xx-uart.2"); pxa910_clk_init()
240 clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent, pxa910_clk_init()
244 clk_register_clkdev(clk, "uart_mux.0", NULL); pxa910_clk_init()
246 clk = mmp_clk_register_apbc("ssp0", "ssp0_mux", pxa910_clk_init()
248 clk_register_clkdev(clk, NULL, "mmp-ssp.0"); pxa910_clk_init()
250 clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent, pxa910_clk_init()
254 clk_register_clkdev(clk, "ssp_mux.1", NULL); pxa910_clk_init()
256 clk = mmp_clk_register_apbc("ssp1", "ssp1_mux", pxa910_clk_init()
258 clk_register_clkdev(clk, NULL, "mmp-ssp.1"); pxa910_clk_init()
260 clk = mmp_clk_register_apmu("dfc", "pll1_4", pxa910_clk_init()
262 clk_register_clkdev(clk, NULL, "pxa3xx-nand.0"); pxa910_clk_init()
264 clk = clk_register_mux(NULL, "sdh0_mux", sdh_parent, pxa910_clk_init()
268 clk_register_clkdev(clk, "sdh0_mux", NULL); pxa910_clk_init()
270 clk = mmp_clk_register_apmu("sdh0", "sdh_mux", pxa910_clk_init()
272 clk_register_clkdev(clk, NULL, "sdhci-pxa.0"); pxa910_clk_init()
274 clk = clk_register_mux(NULL, "sdh1_mux", sdh_parent, pxa910_clk_init()
278 clk_register_clkdev(clk, "sdh1_mux", NULL); pxa910_clk_init()
280 clk = mmp_clk_register_apmu("sdh1", "sdh1_mux", pxa910_clk_init()
282 clk_register_clkdev(clk, NULL, "sdhci-pxa.1"); pxa910_clk_init()
284 clk = mmp_clk_register_apmu("usb", "usb_pll", pxa910_clk_init()
286 clk_register_clkdev(clk, "usb_clk", NULL); pxa910_clk_init()
288 clk = mmp_clk_register_apmu("sph", "usb_pll", pxa910_clk_init()
290 clk_register_clkdev(clk, "sph_clk", NULL); pxa910_clk_init()
292 clk = clk_register_mux(NULL, "disp0_mux", disp_parent, pxa910_clk_init()
296 clk_register_clkdev(clk, "disp_mux.0", NULL); pxa910_clk_init()
298 clk = mmp_clk_register_apmu("disp0", "disp0_mux", pxa910_clk_init()
300 clk_register_clkdev(clk, NULL, "mmp-disp.0"); pxa910_clk_init()
302 clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent, pxa910_clk_init()
306 clk_register_clkdev(clk, "ccic_mux.0", NULL); pxa910_clk_init()
308 clk = mmp_clk_register_apmu("ccic0", "ccic0_mux", pxa910_clk_init()
310 clk_register_clkdev(clk, "fnclk", "mmp-ccic.0"); pxa910_clk_init()
312 clk = clk_register_mux(NULL, "ccic0_phy_mux", ccic_phy_parent, pxa910_clk_init()
316 clk_register_clkdev(clk, "ccic_phy_mux.0", NULL); pxa910_clk_init()
318 clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_phy_mux", pxa910_clk_init()
320 clk_register_clkdev(clk, "phyclk", "mmp-ccic.0"); pxa910_clk_init()
322 clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_mux", pxa910_clk_init()
325 clk_register_clkdev(clk, "sphyclk_div", NULL); pxa910_clk_init()
327 clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div", pxa910_clk_init()
329 clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0"); pxa910_clk_init()
|
| H A D | clk.c | 2 #include <linux/clk-provider.h>
7 #include "clk.h"
12 static struct clk **clk_table; mmp_clk_init()
14 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); mmp_clk_init()
30 struct clk *clk; mmp_register_fixed_rate_clks() local
33 clk = clk_register_fixed_rate(NULL, clks[i].name, mmp_register_fixed_rate_clks()
37 if (IS_ERR(clk)) { mmp_register_fixed_rate_clks()
43 unit->clk_table[clks[i].id] = clk; mmp_register_fixed_rate_clks()
51 struct clk *clk; mmp_register_fixed_factor_clks() local
55 clk = clk_register_fixed_factor(NULL, clks[i].name, mmp_register_fixed_factor_clks()
59 if (IS_ERR(clk)) { mmp_register_fixed_factor_clks()
65 unit->clk_table[clks[i].id] = clk; mmp_register_fixed_factor_clks()
73 struct clk *clk; mmp_register_general_gate_clks() local
77 clk = clk_register_gate(NULL, clks[i].name, mmp_register_general_gate_clks()
85 if (IS_ERR(clk)) { mmp_register_general_gate_clks()
91 unit->clk_table[clks[i].id] = clk; mmp_register_general_gate_clks()
99 struct clk *clk; mmp_register_gate_clks() local
103 clk = mmp_clk_register_gate(NULL, clks[i].name, mmp_register_gate_clks()
113 if (IS_ERR(clk)) { mmp_register_gate_clks()
119 unit->clk_table[clks[i].id] = clk; mmp_register_gate_clks()
127 struct clk *clk; mmp_register_mux_clks() local
131 clk = clk_register_mux(NULL, clks[i].name, mmp_register_mux_clks()
141 if (IS_ERR(clk)) { mmp_register_mux_clks()
147 unit->clk_table[clks[i].id] = clk; mmp_register_mux_clks()
155 struct clk *clk; mmp_register_div_clks() local
159 clk = clk_register_divider(NULL, clks[i].name, mmp_register_div_clks()
168 if (IS_ERR(clk)) { mmp_register_div_clks()
174 unit->clk_table[clks[i].id] = clk; mmp_register_div_clks()
179 struct clk *clk) mmp_clk_add()
181 if (IS_ERR_OR_NULL(clk)) { mmp_clk_add()
182 pr_err("CLK %d has invalid pointer %p\n", id, clk); mmp_clk_add()
190 unit->clk_table[id] = clk; mmp_clk_add()
178 mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id, struct clk *clk) mmp_clk_add() argument
|
| H A D | clk-apmu.c | 18 #include "clk.h"
20 #define to_clk_apmu(clk) (container_of(clk, struct clk_apmu, clk))
68 struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, mmp_clk_register_apmu()
72 struct clk *clk; mmp_clk_register_apmu() local
90 clk = clk_register(NULL, &apmu->hw); mmp_clk_register_apmu()
92 if (IS_ERR(clk)) mmp_clk_register_apmu()
95 return clk; mmp_clk_register_apmu()
|
| /linux-4.4.14/arch/c6x/include/asm/ |
| H A D | clkdev.h | 6 struct clk;
8 static inline int __clk_get(struct clk *clk) __clk_get() argument
13 static inline void __clk_put(struct clk *clk) __clk_put() argument
|
| H A D | clock.h | 82 struct clk { struct
89 struct clk *parent;
94 unsigned long (*recalc) (struct clk *);
95 int (*set_rate) (struct clk *clk, unsigned long rate);
96 int (*round_rate) (struct clk *clk, unsigned long rate);
116 struct clk sysclks[MAX_PLL_SYSCLKS + 1];
128 .clk = ck, \
132 extern int clk_register(struct clk *clk);
133 extern void clk_unregister(struct clk *clk);
138 extern struct clk clkin1;
139 extern struct clk c6x_core_clk;
140 extern struct clk c6x_i2c_clk;
141 extern struct clk c6x_watchdog_clk;
142 extern struct clk c6x_mcbsp1_clk;
143 extern struct clk c6x_mcbsp2_clk;
144 extern struct clk c6x_mdio_clk;
|
| /linux-4.4.14/arch/arm/plat-versatile/ |
| H A D | clock.c | 14 #include <linux/clk.h>
21 int clk_enable(struct clk *clk) clk_enable() argument
27 void clk_disable(struct clk *clk) clk_disable() argument
32 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
34 return clk->rate; clk_get_rate()
38 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
41 if (clk->ops && clk->ops->round) clk_round_rate()
42 ret = clk->ops->round(clk, rate); clk_round_rate()
47 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
50 if (clk->ops && clk->ops->set) clk_set_rate()
51 ret = clk->ops->set(clk, rate); clk_set_rate()
56 long icst_clk_round(struct clk *clk, unsigned long rate) icst_clk_round() argument
59 vco = icst_hz_to_vco(clk->params, rate); icst_clk_round()
60 return icst_hz(clk->params, vco); icst_clk_round()
64 int icst_clk_set(struct clk *clk, unsigned long rate) icst_clk_set() argument
68 vco = icst_hz_to_vco(clk->params, rate); icst_clk_set()
69 clk->rate = icst_hz(clk->params, vco); icst_clk_set()
70 clk->ops->setvco(clk, vco); icst_clk_set()
|
| /linux-4.4.14/arch/c6x/platforms/ |
| H A D | pll.c | 20 #include <linux/clk.h>
31 static void __clk_enable(struct clk *clk) __clk_enable() argument
33 if (clk->parent) __clk_enable()
34 __clk_enable(clk->parent); __clk_enable()
35 clk->usecount++; __clk_enable()
38 static void __clk_disable(struct clk *clk) __clk_disable() argument
40 if (WARN_ON(clk->usecount == 0)) __clk_disable()
42 --clk->usecount; __clk_disable()
44 if (clk->parent) __clk_disable()
45 __clk_disable(clk->parent); __clk_disable()
48 int clk_enable(struct clk *clk) clk_enable() argument
52 if (clk == NULL || IS_ERR(clk)) clk_enable()
56 __clk_enable(clk); clk_enable()
63 void clk_disable(struct clk *clk) clk_disable() argument
67 if (clk == NULL || IS_ERR(clk)) clk_disable()
71 __clk_disable(clk); clk_disable()
76 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
78 if (clk == NULL || IS_ERR(clk)) clk_get_rate()
81 return clk->rate; clk_get_rate()
85 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
87 if (clk == NULL || IS_ERR(clk)) clk_round_rate()
90 if (clk->round_rate) clk_round_rate()
91 return clk->round_rate(clk, rate); clk_round_rate()
93 return clk->rate; clk_round_rate()
98 static void propagate_rate(struct clk *root) propagate_rate()
100 struct clk *clk; propagate_rate() local
102 list_for_each_entry(clk, &root->children, childnode) { propagate_rate()
103 if (clk->recalc) propagate_rate()
104 clk->rate = clk->recalc(clk); propagate_rate()
105 propagate_rate(clk); propagate_rate()
109 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
114 if (clk == NULL || IS_ERR(clk)) clk_set_rate()
117 if (clk->set_rate) clk_set_rate()
118 ret = clk->set_rate(clk, rate); clk_set_rate()
122 if (clk->recalc) clk_set_rate()
123 clk->rate = clk->recalc(clk); clk_set_rate()
124 propagate_rate(clk); clk_set_rate()
132 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
136 if (clk == NULL || IS_ERR(clk)) clk_set_parent()
140 if (WARN_ON(clk->usecount)) clk_set_parent()
144 clk->parent = parent; clk_set_parent()
145 list_del_init(&clk->childnode); clk_set_parent()
146 list_add(&clk->childnode, &clk->parent->children); clk_set_parent()
150 if (clk->recalc) clk_set_parent()
151 clk->rate = clk->recalc(clk); clk_set_parent()
152 propagate_rate(clk); clk_set_parent()
159 int clk_register(struct clk *clk) clk_register() argument
161 if (clk == NULL || IS_ERR(clk)) clk_register()
164 if (WARN(clk->parent && !clk->parent->rate, clk_register()
166 clk->name, clk->parent->name)) clk_register()
170 list_add_tail(&clk->node, &clocks); clk_register()
171 if (clk->parent) clk_register()
172 list_add_tail(&clk->childnode, &clk->parent->children); clk_register()
176 if (clk->rate) clk_register()
180 if (clk->recalc) clk_register()
181 clk->rate = clk->recalc(clk); clk_register()
184 else if (clk->parent) clk_register()
185 clk->rate = clk->parent->rate; clk_register()
191 void clk_unregister(struct clk *clk) clk_unregister() argument
193 if (clk == NULL || IS_ERR(clk)) clk_unregister()
197 list_del(&clk->node); clk_unregister()
198 list_del(&clk->childnode); clk_unregister()
209 static unsigned long clk_sysclk_recalc(struct clk *clk) clk_sysclk_recalc() argument
213 unsigned long rate = clk->rate; clk_sysclk_recalc()
215 if (WARN_ON(!clk->parent)) clk_sysclk_recalc()
218 rate = clk->parent->rate; clk_sysclk_recalc()
221 if (WARN_ON(!clk->parent->pll_data)) clk_sysclk_recalc()
224 pll = clk->parent->pll_data; clk_sysclk_recalc()
227 if (clk->flags & PRE_PLL) clk_sysclk_recalc()
230 if (!clk->div) { clk_sysclk_recalc()
232 clk->name, rate / 1000); clk_sysclk_recalc()
236 if (clk->flags & FIXED_DIV_PLL) { clk_sysclk_recalc()
237 rate /= clk->div; clk_sysclk_recalc()
239 clk->name, clk->div, rate / 1000); clk_sysclk_recalc()
243 v = pll_read(pll, clk->div); clk_sysclk_recalc()
253 clk->name, plldiv, rate / 1000); clk_sysclk_recalc()
258 static unsigned long clk_leafclk_recalc(struct clk *clk) clk_leafclk_recalc() argument
260 if (WARN_ON(!clk->parent)) clk_leafclk_recalc()
261 return clk->rate; clk_leafclk_recalc()
264 clk->name, clk->parent->name, clk->parent->rate / 1000); clk_leafclk_recalc()
266 return clk->parent->rate; clk_leafclk_recalc()
269 static unsigned long clk_pllclk_recalc(struct clk *clk) clk_pllclk_recalc() argument
273 struct pll_data *pll = clk->pll_data; clk_pllclk_recalc()
274 unsigned long rate = clk->rate; clk_pllclk_recalc()
276 if (clk->flags & FIXED_RATE_PLL) clk_pllclk_recalc()
280 rate = pll->input_rate = clk->parent->rate; clk_pllclk_recalc()
316 pll->num, clk->parent->rate / 1000000, clk_pllclk_recalc()
320 pll->num, clk->parent->rate / 1000000); clk_pllclk_recalc()
326 static void __init __init_clk(struct clk *clk) __init_clk() argument
328 INIT_LIST_HEAD(&clk->node); __init_clk()
329 INIT_LIST_HEAD(&clk->children); __init_clk()
330 INIT_LIST_HEAD(&clk->childnode); __init_clk()
332 if (!clk->recalc) { __init_clk()
335 if (clk->pll_data) __init_clk()
336 clk->recalc = clk_pllclk_recalc; __init_clk()
339 else if (clk->flags & CLK_PLL) __init_clk()
340 clk->recalc = clk_sysclk_recalc; __init_clk()
343 else if (clk->parent) __init_clk()
344 clk->recalc = clk_leafclk_recalc; __init_clk()
351 struct clk *clk; c6x_clks_init() local
354 for (c = clocks; c->clk; c++) { c6x_clks_init()
355 clk = c->clk; c6x_clks_init()
357 __init_clk(clk); c6x_clks_init()
358 clk_register(clk); c6x_clks_init()
362 if (clk->flags & ALWAYS_ENABLED) c6x_clks_init()
363 clk_enable(clk); c6x_clks_init()
379 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) dump_clock()
383 struct clk *clk; dump_clock() local
403 list_for_each_entry(clk, &parent->children, childnode) { dump_clock()
404 dump_clock(s, nest + NEST_DELTA, clk); dump_clock()
410 struct clk *clk; c6x_ck_show() local
416 list_for_each_entry(clk, &clocks, node) c6x_ck_show()
417 if (!clk->parent) c6x_ck_show()
418 dump_clock(m, 0, clk); c6x_ck_show()
|
| /linux-4.4.14/arch/arm/mach-davinci/ |
| H A D | clock.c | 17 #include <linux/clk.h>
34 static void __clk_enable(struct clk *clk) __clk_enable() argument
36 if (clk->parent) __clk_enable()
37 __clk_enable(clk->parent); __clk_enable()
38 if (clk->usecount++ == 0) { __clk_enable()
39 if (clk->flags & CLK_PSC) __clk_enable()
40 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, __clk_enable()
41 true, clk->flags); __clk_enable()
42 else if (clk->clk_enable) __clk_enable()
43 clk->clk_enable(clk); __clk_enable()
47 static void __clk_disable(struct clk *clk) __clk_disable() argument
49 if (WARN_ON(clk->usecount == 0)) __clk_disable()
51 if (--clk->usecount == 0) { __clk_disable()
52 if (!(clk->flags & CLK_PLL) && (clk->flags & CLK_PSC)) __clk_disable()
53 davinci_psc_config(clk->domain, clk->gpsc, clk->lpsc, __clk_disable()
54 false, clk->flags); __clk_disable()
55 else if (clk->clk_disable) __clk_disable()
56 clk->clk_disable(clk); __clk_disable()
58 if (clk->parent) __clk_disable()
59 __clk_disable(clk->parent); __clk_disable()
62 int davinci_clk_reset(struct clk *clk, bool reset) davinci_clk_reset() argument
66 if (clk == NULL || IS_ERR(clk)) davinci_clk_reset()
70 if (clk->flags & CLK_PSC) davinci_clk_reset()
71 davinci_psc_reset(clk->gpsc, clk->lpsc, reset); davinci_clk_reset()
78 int davinci_clk_reset_assert(struct clk *clk) davinci_clk_reset_assert() argument
80 if (clk == NULL || IS_ERR(clk) || !clk->reset) davinci_clk_reset_assert()
83 return clk->reset(clk, true); davinci_clk_reset_assert()
87 int davinci_clk_reset_deassert(struct clk *clk) davinci_clk_reset_deassert() argument
89 if (clk == NULL || IS_ERR(clk) || !clk->reset) davinci_clk_reset_deassert()
92 return clk->reset(clk, false); davinci_clk_reset_deassert()
96 int clk_enable(struct clk *clk) clk_enable() argument
100 if (!clk) clk_enable()
102 else if (IS_ERR(clk)) clk_enable()
106 __clk_enable(clk); clk_enable()
113 void clk_disable(struct clk *clk) clk_disable() argument
117 if (clk == NULL || IS_ERR(clk)) clk_disable()
121 __clk_disable(clk); clk_disable()
126 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
128 if (clk == NULL || IS_ERR(clk)) clk_get_rate()
131 return clk->rate; clk_get_rate()
135 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
137 if (clk == NULL || IS_ERR(clk)) clk_round_rate()
140 if (clk->round_rate) clk_round_rate()
141 return clk->round_rate(clk, rate); clk_round_rate()
143 return clk->rate; clk_round_rate()
148 static void propagate_rate(struct clk *root) propagate_rate()
150 struct clk *clk; propagate_rate() local
152 list_for_each_entry(clk, &root->children, childnode) { propagate_rate()
153 if (clk->recalc) propagate_rate()
154 clk->rate = clk->recalc(clk); propagate_rate()
155 propagate_rate(clk); propagate_rate()
159 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
164 if (!clk) clk_set_rate()
166 else if (IS_ERR(clk)) clk_set_rate()
169 if (clk->set_rate) clk_set_rate()
170 ret = clk->set_rate(clk, rate); clk_set_rate()
174 if (clk->recalc) clk_set_rate()
175 clk->rate = clk->recalc(clk); clk_set_rate()
176 propagate_rate(clk); clk_set_rate()
184 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
188 if (!clk) clk_set_parent()
190 else if (IS_ERR(clk)) clk_set_parent()
194 if (WARN_ON(clk->usecount)) clk_set_parent()
198 clk->parent = parent; clk_set_parent()
199 list_del_init(&clk->childnode); clk_set_parent()
200 list_add(&clk->childnode, &clk->parent->children); clk_set_parent()
204 if (clk->recalc) clk_set_parent()
205 clk->rate = clk->recalc(clk); clk_set_parent()
206 propagate_rate(clk); clk_set_parent()
213 int clk_register(struct clk *clk) clk_register() argument
215 if (clk == NULL || IS_ERR(clk)) clk_register()
218 if (WARN(clk->parent && !clk->parent->rate, clk_register()
220 clk->name, clk->parent->name)) clk_register()
223 INIT_LIST_HEAD(&clk->children); clk_register()
226 list_add_tail(&clk->node, &clocks); clk_register()
227 if (clk->parent) clk_register()
228 list_add_tail(&clk->childnode, &clk->parent->children); clk_register()
232 if (clk->rate) clk_register()
236 if (clk->recalc) clk_register()
237 clk->rate = clk->recalc(clk); clk_register()
240 else if (clk->parent) clk_register()
241 clk->rate = clk->parent->rate; clk_register()
247 void clk_unregister(struct clk *clk) clk_unregister() argument
249 if (clk == NULL || IS_ERR(clk)) clk_unregister()
253 list_del(&clk->node); clk_unregister()
254 list_del(&clk->childnode); clk_unregister()
265 struct clk *ck; davinci_clk_disable_unused()
289 static unsigned long clk_sysclk_recalc(struct clk *clk) clk_sysclk_recalc() argument
293 unsigned long rate = clk->rate; clk_sysclk_recalc()
296 if (clk->pll_data) clk_sysclk_recalc()
299 if (WARN_ON(!clk->parent)) clk_sysclk_recalc()
302 rate = clk->parent->rate; clk_sysclk_recalc()
305 if (WARN_ON(!clk->parent->pll_data)) clk_sysclk_recalc()
308 pll = clk->parent->pll_data; clk_sysclk_recalc()
311 if (clk->flags & PRE_PLL) clk_sysclk_recalc()
314 if (!clk->div_reg) clk_sysclk_recalc()
317 v = __raw_readl(pll->base + clk->div_reg); clk_sysclk_recalc()
327 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate) davinci_set_sysclk_rate() argument
335 if (clk->pll_data) davinci_set_sysclk_rate()
339 if (WARN_ON(!clk->parent)) davinci_set_sysclk_rate()
343 if (WARN_ON(!clk->parent->pll_data)) davinci_set_sysclk_rate()
347 if (WARN_ON(!clk->div_reg)) davinci_set_sysclk_rate()
350 pll = clk->parent->pll_data; davinci_set_sysclk_rate()
352 input = clk->parent->rate; davinci_set_sysclk_rate()
355 if (clk->flags & PRE_PLL) davinci_set_sysclk_rate()
364 if (clk->maxrate) { davinci_set_sysclk_rate()
366 if (input / ratio > clk->maxrate) davinci_set_sysclk_rate()
383 v = __raw_readl(pll->base + clk->div_reg); davinci_set_sysclk_rate()
386 __raw_writel(v, pll->base + clk->div_reg); davinci_set_sysclk_rate()
400 static unsigned long clk_leafclk_recalc(struct clk *clk) clk_leafclk_recalc() argument
402 if (WARN_ON(!clk->parent)) clk_leafclk_recalc()
403 return clk->rate; clk_leafclk_recalc()
405 return clk->parent->rate; clk_leafclk_recalc()
408 int davinci_simple_set_rate(struct clk *clk, unsigned long rate) davinci_simple_set_rate() argument
410 clk->rate = rate; davinci_simple_set_rate()
414 static unsigned long clk_pllclk_recalc(struct clk *clk) clk_pllclk_recalc() argument
418 struct pll_data *pll = clk->pll_data; clk_pllclk_recalc()
419 unsigned long rate = clk->rate; clk_pllclk_recalc()
422 rate = pll->input_rate = clk->parent->rate; clk_pllclk_recalc()
461 pll->num, clk->parent->rate / 1000000); clk_pllclk_recalc()
569 struct clk *refclk; davinci_set_refclk_rate()
587 struct clk *clk; davinci_clk_init() local
590 for (c = clocks; c->clk; c++) { davinci_clk_init()
591 clk = c->clk; davinci_clk_init()
593 if (!clk->recalc) { davinci_clk_init()
596 if (clk->pll_data) davinci_clk_init()
597 clk->recalc = clk_pllclk_recalc; davinci_clk_init()
600 else if (clk->flags & CLK_PLL) davinci_clk_init()
601 clk->recalc = clk_sysclk_recalc; davinci_clk_init()
604 else if (clk->parent) davinci_clk_init()
605 clk->recalc = clk_leafclk_recalc; davinci_clk_init()
608 if (clk->pll_data) { davinci_clk_init()
609 struct pll_data *pll = clk->pll_data; davinci_clk_init()
620 if (clk->recalc) davinci_clk_init()
621 clk->rate = clk->recalc(clk); davinci_clk_init()
623 if (clk->lpsc) davinci_clk_init()
624 clk->flags |= CLK_PSC; davinci_clk_init()
626 if (clk->flags & PSC_LRST) davinci_clk_init()
627 clk->reset = davinci_clk_reset; davinci_clk_init()
629 clk_register(clk); davinci_clk_init()
633 if (clk->flags & ALWAYS_ENABLED) davinci_clk_init()
634 clk_enable(clk); davinci_clk_init()
652 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent) dump_clock()
656 struct clk *clk; dump_clock() local
678 list_for_each_entry(clk, &parent->children, childnode) { dump_clock()
679 dump_clock(s, nest + NEST_DELTA, clk); dump_clock()
685 struct clk *clk; davinci_ck_show() local
691 list_for_each_entry(clk, &clocks, node) davinci_ck_show()
692 if (!clk->parent) davinci_ck_show()
693 dump_clock(m, 0, clk); davinci_ck_show()
|
| H A D | clock.h | 87 struct clk { struct
98 struct clk *parent;
103 unsigned long (*recalc) (struct clk *);
104 int (*set_rate) (struct clk *clk, unsigned long rate);
105 int (*round_rate) (struct clk *clk, unsigned long rate);
106 int (*reset) (struct clk *clk, bool reset);
107 void (*clk_enable) (struct clk *clk);
108 void (*clk_disable) (struct clk *clk);
124 .clk = ck, \
130 int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
132 int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
133 int davinci_clk_reset(struct clk *clk, bool reset);
|
| /linux-4.4.14/arch/arm/mach-sa1100/ |
| H A D | clock.c | 11 #include <linux/clk.h>
21 void (*enable)(struct clk *);
22 void (*disable)(struct clk *);
23 unsigned long (*get_rate)(struct clk *);
26 struct clk { struct
32 struct clk clk_##_name = { \
38 static void clk_gpio27_enable(struct clk *clk) clk_gpio27_enable() argument
49 static void clk_gpio27_disable(struct clk *clk) clk_gpio27_disable() argument
56 static void clk_cpu_enable(struct clk *clk) clk_cpu_enable() argument
60 static void clk_cpu_disable(struct clk *clk) clk_cpu_disable() argument
64 static unsigned long clk_cpu_get_rate(struct clk *clk) clk_cpu_get_rate() argument
69 int clk_enable(struct clk *clk) clk_enable() argument
73 if (clk) { clk_enable()
75 if (clk->enabled++ == 0) clk_enable()
76 clk->ops->enable(clk); clk_enable()
84 void clk_disable(struct clk *clk) clk_disable() argument
88 if (clk) { clk_disable()
89 WARN_ON(clk->enabled == 0); clk_disable()
91 if (--clk->enabled == 0) clk_disable()
92 clk->ops->disable(clk); clk_disable()
98 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
100 if (clk && clk->ops && clk->ops->get_rate) clk_get_rate()
101 return clk->ops->get_rate(clk); clk_get_rate()
122 static unsigned long clk_36864_get_rate(struct clk *clk) clk_36864_get_rate() argument
|
| /linux-4.4.14/arch/mips/ralink/ |
| H A D | clk.c | 13 #include <linux/clk.h>
19 struct clk { struct
26 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); ralink_clk_add() local
28 if (!clk) ralink_clk_add()
31 clk->cl.dev_id = dev; ralink_clk_add()
32 clk->cl.clk = clk; ralink_clk_add()
34 clk->rate = rate; ralink_clk_add()
36 clkdev_add(&clk->cl); ralink_clk_add()
42 int clk_enable(struct clk *clk) clk_enable() argument
48 void clk_disable(struct clk *clk) clk_disable() argument
53 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
55 return clk->rate; clk_get_rate()
59 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
67 struct clk *clk; plat_time_init() local
72 clk = clk_get_sys("cpu", NULL); plat_time_init()
73 if (IS_ERR(clk)) plat_time_init()
74 panic("unable to get CPU clock, err=%ld", PTR_ERR(clk)); plat_time_init()
75 pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); plat_time_init()
76 mips_hpt_frequency = clk_get_rate(clk) / 2; plat_time_init()
77 clk_put(clk); plat_time_init()
|
| /linux-4.4.14/drivers/sh/clk/ |
| H A D | cpg.c | 11 #include <linux/clk.h>
19 static unsigned int sh_clk_read(struct clk *clk) sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) sh_clk_read()
22 return ioread8(clk->mapped_reg); sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) sh_clk_read()
24 return ioread16(clk->mapped_reg); sh_clk_read()
26 return ioread32(clk->mapped_reg); sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) sh_clk_write()
32 iowrite8(value, clk->mapped_reg); sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) sh_clk_write()
34 iowrite16(value, clk->mapped_reg); sh_clk_write()
36 iowrite32(value, clk->mapped_reg); sh_clk_write()
54 static int sh_clk_mstp_enable(struct clk *clk) sh_clk_mstp_enable() argument
56 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); sh_clk_mstp_enable()
57 if (clk->status_reg) { sh_clk_mstp_enable()
60 void __iomem *mapped_status = (phys_addr_t)clk->status_reg - sh_clk_mstp_enable()
61 (phys_addr_t)clk->enable_reg + clk->mapped_reg; sh_clk_mstp_enable()
63 if (clk->flags & CLK_ENABLE_REG_8BIT) sh_clk_mstp_enable()
65 else if (clk->flags & CLK_ENABLE_REG_16BIT) sh_clk_mstp_enable()
71 (read(mapped_status) & (1 << clk->enable_bit)) && i; sh_clk_mstp_enable()
76 clk->enable_reg, clk->enable_bit); sh_clk_mstp_enable()
83 static void sh_clk_mstp_disable(struct clk *clk) sh_clk_mstp_disable() argument
85 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); sh_clk_mstp_disable()
94 int __init sh_clk_mstp_register(struct clk *clks, int nr) sh_clk_mstp_register()
96 struct clk *clkp; sh_clk_mstp_register()
112 static inline struct clk_div_table *clk_to_div_table(struct clk *clk) clk_to_div_table() argument
114 return clk->priv; clk_to_div_table()
117 static inline struct clk_div_mult_table *clk_to_div_mult_table(struct clk *clk) clk_to_div_mult_table() argument
119 return clk_to_div_table(clk)->div_mult_table; clk_to_div_mult_table()
125 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate) sh_clk_div_round_rate() argument
127 return clk_rate_table_round(clk, clk->freq_table, rate); sh_clk_div_round_rate()
130 static unsigned long sh_clk_div_recalc(struct clk *clk) sh_clk_div_recalc() argument
132 struct clk_div_mult_table *table = clk_to_div_mult_table(clk); sh_clk_div_recalc()
135 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, sh_clk_div_recalc()
136 table, clk->arch_flags ? &clk->arch_flags : NULL); sh_clk_div_recalc()
138 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; sh_clk_div_recalc()
140 return clk->freq_table[idx].frequency; sh_clk_div_recalc()
143 static int sh_clk_div_set_rate(struct clk *clk, unsigned long rate) sh_clk_div_set_rate() argument
145 struct clk_div_table *dt = clk_to_div_table(clk); sh_clk_div_set_rate()
149 idx = clk_rate_table_find(clk, clk->freq_table, rate); sh_clk_div_set_rate()
153 value = sh_clk_read(clk); sh_clk_div_set_rate()
154 value &= ~(clk->div_mask << clk->enable_bit); sh_clk_div_set_rate()
155 value |= (idx << clk->enable_bit); sh_clk_div_set_rate()
156 sh_clk_write(value, clk); sh_clk_div_set_rate()
160 dt->kick(clk); sh_clk_div_set_rate()
165 static int sh_clk_div_enable(struct clk *clk) sh_clk_div_enable() argument
167 if (clk->div_mask == SH_CLK_DIV6_MSK) { sh_clk_div_enable()
168 int ret = sh_clk_div_set_rate(clk, clk->rate); sh_clk_div_enable()
173 sh_clk_write(sh_clk_read(clk) & ~CPG_CKSTP_BIT, clk); sh_clk_div_enable()
177 static void sh_clk_div_disable(struct clk *clk) sh_clk_div_disable() argument
181 val = sh_clk_read(clk); sh_clk_div_disable()
189 if (clk->flags & CLK_MASK_DIV_ON_DISABLE) sh_clk_div_disable()
190 val |= clk->div_mask; sh_clk_div_disable()
192 sh_clk_write(val, clk); sh_clk_div_disable()
209 static int __init sh_clk_init_parent(struct clk *clk) sh_clk_init_parent() argument
213 if (clk->parent) sh_clk_init_parent()
216 if (!clk->parent_table || !clk->parent_num) sh_clk_init_parent()
219 if (!clk->src_width) { sh_clk_init_parent()
224 val = (sh_clk_read(clk) >> clk->src_shift); sh_clk_init_parent()
225 val &= (1 << clk->src_width) - 1; sh_clk_init_parent()
227 if (val >= clk->parent_num) { sh_clk_init_parent()
232 clk_reparent(clk, clk->parent_table[val]); sh_clk_init_parent()
233 if (!clk->parent) { sh_clk_init_parent()
241 static int __init sh_clk_div_register_ops(struct clk *clks, int nr, sh_clk_div_register_ops()
244 struct clk *clkp; sh_clk_div_register_ops()
294 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) sh_clk_div6_set_parent() argument
296 struct clk_div_mult_table *table = clk_to_div_mult_table(clk); sh_clk_div6_set_parent()
300 if (!clk->parent_table || !clk->parent_num) sh_clk_div6_set_parent()
304 for (i = 0; i < clk->parent_num; i++) sh_clk_div6_set_parent()
305 if (clk->parent_table[i] == parent) sh_clk_div6_set_parent()
308 if (i == clk->parent_num) sh_clk_div6_set_parent()
311 ret = clk_reparent(clk, parent); sh_clk_div6_set_parent()
315 value = sh_clk_read(clk) & sh_clk_div6_set_parent()
316 ~(((1 << clk->src_width) - 1) << clk->src_shift); sh_clk_div6_set_parent()
318 sh_clk_write(value | (i << clk->src_shift), clk); sh_clk_div6_set_parent()
321 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, sh_clk_div6_set_parent()
336 int __init sh_clk_div6_register(struct clk *clks, int nr) sh_clk_div6_register()
342 int __init sh_clk_div6_reparent_register(struct clk *clks, int nr) sh_clk_div6_reparent_register()
351 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) sh_clk_div4_set_parent() argument
353 struct clk_div_mult_table *table = clk_to_div_mult_table(clk); sh_clk_div4_set_parent()
363 value = sh_clk_read(clk) & ~(1 << 7); sh_clk_div4_set_parent()
365 value = sh_clk_read(clk) | (1 << 7); sh_clk_div4_set_parent()
367 ret = clk_reparent(clk, parent); sh_clk_div4_set_parent()
371 sh_clk_write(value, clk); sh_clk_div4_set_parent()
374 clk_rate_table_build(clk, clk->freq_table, table->nr_divisors, sh_clk_div4_set_parent()
375 table, &clk->arch_flags); sh_clk_div4_set_parent()
389 int __init sh_clk_div4_register(struct clk *clks, int nr, sh_clk_div4_register()
395 int __init sh_clk_div4_enable_register(struct clk *clks, int nr, sh_clk_div4_enable_register()
402 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr, sh_clk_div4_reparent_register()
410 static unsigned long fsidiv_recalc(struct clk *clk) fsidiv_recalc() argument
414 value = __raw_readl(clk->mapping->base); fsidiv_recalc()
418 return clk->parent->rate; fsidiv_recalc()
420 return clk->parent->rate / value; fsidiv_recalc()
423 static long fsidiv_round_rate(struct clk *clk, unsigned long rate) fsidiv_round_rate() argument
425 return clk_rate_div_range_round(clk, 1, 0xffff, rate); fsidiv_round_rate()
428 static void fsidiv_disable(struct clk *clk) fsidiv_disable() argument
430 __raw_writel(0, clk->mapping->base); fsidiv_disable()
433 static int fsidiv_enable(struct clk *clk) fsidiv_enable() argument
437 value = __raw_readl(clk->mapping->base) >> 16; fsidiv_enable()
441 __raw_writel((value << 16) | 0x3, clk->mapping->base); fsidiv_enable()
446 static int fsidiv_set_rate(struct clk *clk, unsigned long rate) fsidiv_set_rate() argument
450 idx = (clk->parent->rate / rate) & 0xffff; fsidiv_set_rate()
452 __raw_writel(0, clk->mapping->base); fsidiv_set_rate()
454 __raw_writel(idx << 16, clk->mapping->base); fsidiv_set_rate()
467 int __init sh_clk_fsidiv_register(struct clk *clks, int nr) sh_clk_fsidiv_register()
|
| H A D | core.c | 29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, clk_rate_table_round()
149 if (clk->nr_freqs < 1) clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), clk_rate_mult_range_round()
195 int clk_rate_table_find(struct clk *clk, clk_rate_table_find() argument
209 unsigned long followparent_recalc(struct clk *clk) followparent_recalc() argument
211 return clk->parent ? clk->parent->rate : 0; followparent_recalc()
214 int clk_reparent(struct clk *child, struct clk *parent) clk_reparent()
225 void propagate_rate(struct clk *tclk) propagate_rate()
227 struct clk *clkp; propagate_rate()
237 static void __clk_disable(struct clk *clk) __clk_disable() argument
239 if (WARN(!clk->usecount, "Trying to disable clock %p with 0 usecount\n", __clk_disable()
240 clk)) __clk_disable()
243 if (!(--clk->usecount)) { __clk_disable()
244 if (likely(allow_disable && clk->ops && clk->ops->disable)) __clk_disable()
245 clk->ops->disable(clk); __clk_disable()
246 if (likely(clk->parent)) __clk_disable()
247 __clk_disable(clk->parent); __clk_disable()
251 void clk_disable(struct clk *clk) clk_disable() argument
255 if (!clk) clk_disable()
259 __clk_disable(clk); clk_disable()
264 static int __clk_enable(struct clk *clk) __clk_enable() argument
268 if (clk->usecount++ == 0) { __clk_enable()
269 if (clk->parent) { __clk_enable()
270 ret = __clk_enable(clk->parent); __clk_enable()
275 if (clk->ops && clk->ops->enable) { __clk_enable()
276 ret = clk->ops->enable(clk); __clk_enable()
278 if (clk->parent) __clk_enable()
279 __clk_disable(clk->parent); __clk_enable()
287 clk->usecount--; __clk_enable()
291 int clk_enable(struct clk *clk) clk_enable() argument
296 if (!clk) clk_enable()
300 ret = __clk_enable(clk); clk_enable()
318 struct clk *clkp; recalculate_root_clocks()
329 static struct clk *lookup_root_clock(struct clk *clk) lookup_root_clock() argument
331 while (clk->parent) lookup_root_clock()
332 clk = clk->parent; lookup_root_clock()
334 return clk; lookup_root_clock()
337 static int clk_establish_mapping(struct clk *clk) clk_establish_mapping() argument
339 struct clk_mapping *mapping = clk->mapping; clk_establish_mapping()
345 struct clk *clkp; clk_establish_mapping()
350 if (!clk->parent) { clk_establish_mapping()
351 clk->mapping = &dummy_mapping; clk_establish_mapping()
359 clkp = lookup_root_clock(clk); clk_establish_mapping()
380 clk->mapping = mapping; clk_establish_mapping()
382 clk->mapped_reg = clk->mapping->base; clk_establish_mapping()
383 clk->mapped_reg += (phys_addr_t)clk->enable_reg - clk->mapping->phys; clk_establish_mapping()
396 static void clk_teardown_mapping(struct clk *clk) clk_teardown_mapping() argument
398 struct clk_mapping *mapping = clk->mapping; clk_teardown_mapping()
405 clk->mapping = NULL; clk_teardown_mapping()
407 clk->mapped_reg = NULL; clk_teardown_mapping()
410 int clk_register(struct clk *clk) clk_register() argument
414 if (IS_ERR_OR_NULL(clk)) clk_register()
420 if (clk->node.next || clk->node.prev) clk_register()
425 INIT_LIST_HEAD(&clk->children); clk_register()
426 clk->usecount = 0; clk_register()
428 ret = clk_establish_mapping(clk); clk_register()
432 if (clk->parent) clk_register()
433 list_add(&clk->sibling, &clk->parent->children); clk_register()
435 list_add(&clk->sibling, &root_clks); clk_register()
437 list_add(&clk->node, &clock_list); clk_register()
440 if (clk->ops && clk->ops->init) clk_register()
441 clk->ops->init(clk); clk_register()
451 void clk_unregister(struct clk *clk) clk_unregister() argument
454 list_del(&clk->sibling); clk_unregister()
455 list_del(&clk->node); clk_unregister()
456 clk_teardown_mapping(clk); clk_unregister()
463 struct clk *clkp; clk_enable_init_clocks()
470 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
472 return clk->rate; clk_get_rate()
476 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
483 if (likely(clk->ops && clk->ops->set_rate)) { clk_set_rate()
484 ret = clk->ops->set_rate(clk, rate); clk_set_rate()
488 clk->rate = rate; clk_set_rate()
492 if (clk->ops && clk->ops->recalc) clk_set_rate()
493 clk->rate = clk->ops->recalc(clk); clk_set_rate()
495 propagate_rate(clk); clk_set_rate()
504 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
509 if (!parent || !clk) clk_set_parent()
511 if (clk->parent == parent) clk_set_parent()
515 if (clk->usecount == 0) { clk_set_parent()
516 if (clk->ops->set_parent) clk_set_parent()
517 ret = clk->ops->set_parent(clk, parent); clk_set_parent()
519 ret = clk_reparent(clk, parent); clk_set_parent()
522 if (clk->ops->recalc) clk_set_parent()
523 clk->rate = clk->ops->recalc(clk); clk_set_parent()
525 clk, clk->parent, clk->rate); clk_set_parent()
526 propagate_rate(clk); clk_set_parent()
536 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
538 return clk->parent; clk_get_parent()
542 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
544 if (likely(clk->ops && clk->ops->round_rate)) { clk_round_rate()
548 rounded = clk->ops->round_rate(clk, rate); clk_round_rate()
554 return clk_get_rate(clk); clk_round_rate()
558 long clk_round_parent(struct clk *clk, unsigned long target, clk_round_parent() argument
564 struct clk *parent = clk_get_parent(clk); clk_round_parent()
568 *best_freq = clk_round_rate(clk, target); clk_round_parent()
649 struct clk *clkp; clks_core_resume()
682 struct clk *clk; clk_late_init() local
688 list_for_each_entry(clk, &clock_list, node) clk_late_init()
689 if (!clk->usecount && clk->ops && clk->ops->disable) clk_late_init()
690 clk->ops->disable(clk); clk_late_init()
|
| /linux-4.4.14/drivers/media/v4l2-core/ |
| H A D | v4l2-clk.c | 12 #include <linux/clk.h>
21 #include <media/v4l2-clk.h>
29 struct v4l2_clk *clk; v4l2_clk_find() local
31 list_for_each_entry(clk, &clk_list, list) v4l2_clk_find()
32 if (!strcmp(dev_id, clk->dev_id)) v4l2_clk_find()
33 return clk; v4l2_clk_find()
40 struct v4l2_clk *clk; v4l2_clk_get() local
41 struct clk *ccf_clk = clk_get(dev, id); v4l2_clk_get()
47 clk = kzalloc(sizeof(*clk), GFP_KERNEL); v4l2_clk_get()
48 if (!clk) { v4l2_clk_get()
52 clk->clk = ccf_clk; v4l2_clk_get()
54 return clk; v4l2_clk_get()
58 clk = v4l2_clk_find(dev_name(dev)); v4l2_clk_get()
60 if (!IS_ERR(clk)) v4l2_clk_get()
61 atomic_inc(&clk->use_count); v4l2_clk_get()
64 return clk; v4l2_clk_get()
68 void v4l2_clk_put(struct v4l2_clk *clk) v4l2_clk_put() argument
72 if (IS_ERR(clk)) v4l2_clk_put()
75 if (clk->clk) { v4l2_clk_put()
76 clk_put(clk->clk); v4l2_clk_put()
77 kfree(clk); v4l2_clk_put()
84 if (tmp == clk) v4l2_clk_put()
85 atomic_dec(&clk->use_count); v4l2_clk_put()
91 static int v4l2_clk_lock_driver(struct v4l2_clk *clk) v4l2_clk_lock_driver() argument
99 if (tmp == clk) { v4l2_clk_lock_driver()
100 ret = !try_module_get(clk->ops->owner); v4l2_clk_lock_driver()
111 static void v4l2_clk_unlock_driver(struct v4l2_clk *clk) v4l2_clk_unlock_driver() argument
113 module_put(clk->ops->owner); v4l2_clk_unlock_driver()
116 int v4l2_clk_enable(struct v4l2_clk *clk) v4l2_clk_enable() argument
120 if (clk->clk) v4l2_clk_enable()
121 return clk_prepare_enable(clk->clk); v4l2_clk_enable()
123 ret = v4l2_clk_lock_driver(clk); v4l2_clk_enable()
127 mutex_lock(&clk->lock); v4l2_clk_enable()
129 if (++clk->enable == 1 && clk->ops->enable) { v4l2_clk_enable()
130 ret = clk->ops->enable(clk); v4l2_clk_enable()
132 clk->enable--; v4l2_clk_enable()
135 mutex_unlock(&clk->lock); v4l2_clk_enable()
145 void v4l2_clk_disable(struct v4l2_clk *clk) v4l2_clk_disable() argument
149 if (clk->clk) v4l2_clk_disable()
150 return clk_disable_unprepare(clk->clk); v4l2_clk_disable()
152 mutex_lock(&clk->lock); v4l2_clk_disable()
154 enable = --clk->enable; v4l2_clk_disable()
156 clk->dev_id)) v4l2_clk_disable()
157 clk->enable++; v4l2_clk_disable()
158 else if (!enable && clk->ops->disable) v4l2_clk_disable()
159 clk->ops->disable(clk); v4l2_clk_disable()
161 mutex_unlock(&clk->lock); v4l2_clk_disable()
163 v4l2_clk_unlock_driver(clk); v4l2_clk_disable()
167 unsigned long v4l2_clk_get_rate(struct v4l2_clk *clk) v4l2_clk_get_rate() argument
171 if (clk->clk) v4l2_clk_get_rate()
172 return clk_get_rate(clk->clk); v4l2_clk_get_rate()
174 ret = v4l2_clk_lock_driver(clk); v4l2_clk_get_rate()
178 mutex_lock(&clk->lock); v4l2_clk_get_rate()
179 if (!clk->ops->get_rate) v4l2_clk_get_rate()
182 ret = clk->ops->get_rate(clk); v4l2_clk_get_rate()
183 mutex_unlock(&clk->lock); v4l2_clk_get_rate()
185 v4l2_clk_unlock_driver(clk); v4l2_clk_get_rate()
191 int v4l2_clk_set_rate(struct v4l2_clk *clk, unsigned long rate) v4l2_clk_set_rate() argument
195 if (clk->clk) { v4l2_clk_set_rate()
196 long r = clk_round_rate(clk->clk, rate); v4l2_clk_set_rate()
199 return clk_set_rate(clk->clk, r); v4l2_clk_set_rate()
202 ret = v4l2_clk_lock_driver(clk); v4l2_clk_set_rate()
207 mutex_lock(&clk->lock); v4l2_clk_set_rate()
208 if (!clk->ops->set_rate) v4l2_clk_set_rate()
211 ret = clk->ops->set_rate(clk, rate); v4l2_clk_set_rate()
212 mutex_unlock(&clk->lock); v4l2_clk_set_rate()
214 v4l2_clk_unlock_driver(clk); v4l2_clk_set_rate()
224 struct v4l2_clk *clk; v4l2_clk_register() local
230 clk = kzalloc(sizeof(struct v4l2_clk), GFP_KERNEL); v4l2_clk_register()
231 if (!clk) v4l2_clk_register()
234 clk->dev_id = kstrdup(dev_id, GFP_KERNEL); v4l2_clk_register()
235 if (!clk->dev_id) { v4l2_clk_register()
239 clk->ops = ops; v4l2_clk_register()
240 clk->priv = priv; v4l2_clk_register()
241 atomic_set(&clk->use_count, 0); v4l2_clk_register()
242 mutex_init(&clk->lock); v4l2_clk_register()
250 list_add_tail(&clk->list, &clk_list); v4l2_clk_register()
253 return clk; v4l2_clk_register()
257 kfree(clk->dev_id); v4l2_clk_register()
258 kfree(clk); v4l2_clk_register()
263 void v4l2_clk_unregister(struct v4l2_clk *clk) v4l2_clk_unregister() argument
265 if (WARN(atomic_read(&clk->use_count), v4l2_clk_unregister()
267 __func__, clk->dev_id)) v4l2_clk_unregister()
271 list_del(&clk->list); v4l2_clk_unregister()
274 kfree(clk->dev_id); v4l2_clk_unregister()
275 kfree(clk); v4l2_clk_unregister()
284 static unsigned long fixed_get_rate(struct v4l2_clk *clk) fixed_get_rate() argument
286 struct v4l2_clk_fixed *priv = clk->priv; fixed_get_rate()
293 struct v4l2_clk *clk; __v4l2_clk_register_fixed() local
303 clk = v4l2_clk_register(&priv->ops, dev_id, priv); __v4l2_clk_register_fixed()
304 if (IS_ERR(clk)) __v4l2_clk_register_fixed()
307 return clk; __v4l2_clk_register_fixed()
311 void v4l2_clk_unregister_fixed(struct v4l2_clk *clk) v4l2_clk_unregister_fixed() argument
313 kfree(clk->priv); v4l2_clk_unregister_fixed()
314 v4l2_clk_unregister(clk); v4l2_clk_unregister_fixed()
|
| /linux-4.4.14/arch/avr32/mach-at32ap/ |
| H A D | clock.h | 14 #include <linux/clk.h>
18 void at32_clk_register(struct clk *clk);
20 struct clk { struct
24 struct clk *parent; /* Parent clock, if any */
25 void (*mode)(struct clk *clk, int enabled);
26 unsigned long (*get_rate)(struct clk *clk);
27 long (*set_rate)(struct clk *clk, unsigned long rate,
29 int (*set_parent)(struct clk *clk, struct clk *parent);
34 unsigned long pba_clk_get_rate(struct clk *clk);
35 void pba_clk_mode(struct clk *clk, int enabled);
|
| H A D | clock.c | 14 #include <linux/clk.h>
31 void at32_clk_register(struct clk *clk) at32_clk_register() argument
35 list_add_tail(&clk->list, &at32_clock_list); at32_clk_register()
39 static struct clk *__clk_get(struct device *dev, const char *id) __clk_get()
41 struct clk *clk; __clk_get() local
43 list_for_each_entry(clk, &at32_clock_list, list) { __clk_get()
44 if (clk->dev == dev && strcmp(id, clk->name) == 0) { __clk_get()
45 return clk; __clk_get()
52 struct clk *clk_get(struct device *dev, const char *id) clk_get()
54 struct clk *clk; clk_get() local
57 clk = __clk_get(dev, id); clk_get()
60 return clk; clk_get()
65 void clk_put(struct clk *clk) clk_put() argument
71 static void __clk_enable(struct clk *clk) __clk_enable() argument
73 if (clk->parent) __clk_enable()
74 __clk_enable(clk->parent); __clk_enable()
75 if (clk->users++ == 0 && clk->mode) __clk_enable()
76 clk->mode(clk, 1); __clk_enable()
79 int clk_enable(struct clk *clk) clk_enable() argument
83 if (!clk) clk_enable()
87 __clk_enable(clk); clk_enable()
94 static void __clk_disable(struct clk *clk) __clk_disable() argument
96 if (clk->users == 0) { __clk_disable()
97 printk(KERN_ERR "%s: mismatched disable\n", clk->name); __clk_disable()
102 if (--clk->users == 0 && clk->mode) __clk_disable()
103 clk->mode(clk, 0); __clk_disable()
104 if (clk->parent) __clk_disable()
105 __clk_disable(clk->parent); __clk_disable()
108 void clk_disable(struct clk *clk) clk_disable() argument
112 if (IS_ERR_OR_NULL(clk)) clk_disable()
116 __clk_disable(clk); clk_disable()
121 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
126 if (!clk) clk_get_rate()
130 rate = clk->get_rate(clk); clk_get_rate()
137 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
141 if (!clk) clk_round_rate()
144 if (!clk->set_rate) clk_round_rate()
148 actual_rate = clk->set_rate(clk, rate, 0); clk_round_rate()
155 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
160 if (!clk) clk_set_rate()
163 if (!clk->set_rate) clk_set_rate()
167 ret = clk->set_rate(clk, rate, 1); clk_set_rate()
174 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
179 if (!clk) clk_set_parent()
182 if (!clk->set_parent) clk_set_parent()
186 ret = clk->set_parent(clk, parent); clk_set_parent()
193 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
195 return !clk ? NULL : clk->parent; clk_get_parent()
220 dump_clock(struct clk *parent, struct clkinf *r) dump_clock()
224 struct clk *clk; dump_clock() local
250 list_for_each_entry(clk, &at32_clock_list, list) { dump_clock()
251 if (clk->parent == parent) dump_clock()
252 dump_clock(clk, r); dump_clock()
261 struct clk *clk; clk_show() local
287 clk = __clk_get(NULL, "osc32k"); clk_show()
288 dump_clock(clk, &r); clk_show()
289 clk_put(clk); clk_show()
291 clk = __clk_get(NULL, "osc0"); clk_show()
292 dump_clock(clk, &r); clk_show()
293 clk_put(clk); clk_show()
295 clk = __clk_get(NULL, "osc1"); clk_show()
296 dump_clock(clk, &r); clk_show()
297 clk_put(clk); clk_show()
|
| /linux-4.4.14/include/linux/ |
| H A D | clkdev.h | 10 * Helper for the clk API to assist looking up a struct clk.
17 struct clk;
24 struct clk *clk; member in struct:clk_lookup
32 .clk = c, \
35 struct clk_lookup *clkdev_alloc(struct clk *clk, const char *con_id,
41 struct clk_lookup *clkdev_create(struct clk *clk, const char *con_id,
47 int clk_register_clkdev(struct clk *, const char *, const char *, ...)
49 int clk_register_clkdevs(struct clk *, struct clk_lookup *, size_t);
52 int __clk_get(struct clk *clk);
53 void __clk_put(struct clk *clk);
|
| H A D | sh_clk.h | 9 #include <linux/clk.h>
12 struct clk;
23 void (*init)(struct clk *clk);
25 int (*enable)(struct clk *clk);
26 void (*disable)(struct clk *clk);
27 unsigned long (*recalc)(struct clk *clk);
28 int (*set_rate)(struct clk *clk, unsigned long rate);
29 int (*set_parent)(struct clk *clk, struct clk *parent);
30 long (*round_rate)(struct clk *clk, unsigned long rate);
37 struct clk { struct
39 struct clk *parent;
40 struct clk **parent_table; /* list of parents to */
79 /* drivers/sh/clk.c */
80 unsigned long followparent_recalc(struct clk *);
82 void propagate_rate(struct clk *);
83 int clk_reparent(struct clk *child, struct clk *parent);
84 int clk_register(struct clk *);
85 void clk_unregister(struct clk *);
96 void clk_rate_table_build(struct clk *clk,
102 long clk_rate_table_round(struct clk *clk,
106 int clk_rate_table_find(struct clk *clk,
110 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min,
113 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min,
116 long clk_round_parent(struct clk *clk, unsigned long target,
141 int sh_clk_mstp_register(struct clk *clks, int nr);
149 static inline int __deprecated sh_clk_mstp32_register(struct clk *clks, int nr) sh_clk_mstp32_register()
166 void (*kick)(struct clk *clk);
171 int sh_clk_div4_register(struct clk *clks, int nr,
173 int sh_clk_div4_enable_register(struct clk *clks, int nr,
175 int sh_clk_div4_reparent_register(struct clk *clks, int nr,
200 int sh_clk_div6_register(struct clk *clks, int nr);
201 int sh_clk_div6_reparent_register(struct clk *clks, int nr);
203 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
204 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
205 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
214 int sh_clk_fsidiv_register(struct clk *clks, int nr);
|
| H A D | clk.h | 2 * linux/include/linux/clk.h
21 struct clk;
26 * DOC: clk notifier callback types
28 * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
36 * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
39 * POST_RATE_CHANGE - called after the clk rate change has successfully
48 * struct clk_notifier - associate a clk with a notifier
49 * @clk: struct clk * to associate the notifier with
50 * @notifier_head: a blocking_notifier_head for this clk
55 * particular @clk. Future notifiers on that @clk are added to the
59 struct clk *clk; member in struct:clk_notifier
66 * @clk: struct clk * being changed
67 * @old_rate: previous rate of this clk
68 * @new_rate: new rate of this clk
70 * For a pre-notifier, old_rate is the clk's rate before this rate
72 * post-notifier, old_rate and new_rate are both set to the clk's
76 struct clk *clk; member in struct:clk_notifier_data
83 * @clk: clock whose rate we are interested in
90 int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
94 * @clk: clock whose rate we are no longer interested in
97 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
102 * @clk: clock source
107 long clk_get_accuracy(struct clk *clk);
111 * @clk: clock signal source
117 int clk_set_phase(struct clk *clk, int degrees);
121 * @clk: clock signal source
126 int clk_get_phase(struct clk *clk);
129 * clk_is_match - check if two clk's point to the same hardware clock
130 * @p: clk compared against q
131 * @q: clk compared against p
133 * Returns true if the two struct clk pointers both point to the same hardware
134 * clock node. Put differently, returns true if struct clk *p and struct clk *q
139 bool clk_is_match(const struct clk *p, const struct clk *q);
143 static inline long clk_get_accuracy(struct clk *clk) clk_get_accuracy() argument
148 static inline long clk_set_phase(struct clk *clk, int phase) clk_set_phase() argument
153 static inline long clk_get_phase(struct clk *clk) clk_get_phase() argument
158 static inline bool clk_is_match(const struct clk *p, const struct clk *q) clk_is_match()
167 * @clk: clock source
174 int clk_prepare(struct clk *clk);
176 static inline int clk_prepare(struct clk *clk) clk_prepare() argument
185 * @clk: clock source
193 void clk_unprepare(struct clk *clk);
195 static inline void clk_unprepare(struct clk *clk) clk_unprepare() argument
207 * Returns a struct clk corresponding to the clock producer, or
217 struct clk *clk_get(struct device *dev, const char *id);
224 * Returns a struct clk corresponding to the clock producer, or
237 struct clk *devm_clk_get(struct device *dev, const char *id);
241 * @clk: clock source
249 int clk_enable(struct clk *clk);
253 * @clk: clock source
265 void clk_disable(struct clk *clk);
270 * @clk: clock source
272 unsigned long clk_get_rate(struct clk *clk);
276 * @clk: clock source
284 void clk_put(struct clk *clk);
289 * @clk: clock source acquired with devm_clk_get()
297 void devm_clk_put(struct device *dev, struct clk *clk);
306 * @clk: clock source
313 * rate = clk_round_rate(clk, r);
317 * clk_set_rate(clk, r);
318 * rate = clk_get_rate(clk);
325 long clk_round_rate(struct clk *clk, unsigned long rate);
329 * @clk: clock source
334 int clk_set_rate(struct clk *clk, unsigned long rate);
338 * @clk: clock source
344 * Returns true if @parent is a possible parent for @clk, false otherwise.
346 bool clk_has_parent(struct clk *clk, struct clk *parent);
350 * @clk: clock source
356 int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max);
360 * @clk: clock source
365 int clk_set_min_rate(struct clk *clk, unsigned long rate);
369 * @clk: clock source
374 int clk_set_max_rate(struct clk *clk, unsigned long rate);
378 * @clk: clock source
383 int clk_set_parent(struct clk *clk, struct clk *parent);
387 * @clk: clock source
389 * Returns struct clk corresponding to parent clock source, or
392 struct clk *clk_get_parent(struct clk *clk);
399 * Returns a struct clk corresponding to the clock producer, or
409 struct clk *clk_get_sys(const char *dev_id, const char *con_id);
413 static inline struct clk *clk_get(struct device *dev, const char *id) clk_get()
418 static inline struct clk *devm_clk_get(struct device *dev, const char *id) devm_clk_get()
423 static inline void clk_put(struct clk *clk) {} clk_put() argument
425 static inline void devm_clk_put(struct device *dev, struct clk *clk) {} devm_clk_put() argument
427 static inline int clk_enable(struct clk *clk) clk_enable() argument
432 static inline void clk_disable(struct clk *clk) {} clk_disable() argument
434 static inline unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
439 static inline int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
444 static inline long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
449 static inline bool clk_has_parent(struct clk *clk, struct clk *parent) clk_has_parent() argument
454 static inline int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
459 static inline struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
467 static inline int clk_prepare_enable(struct clk *clk) clk_prepare_enable() argument
471 ret = clk_prepare(clk); clk_prepare_enable()
474 ret = clk_enable(clk); clk_prepare_enable()
476 clk_unprepare(clk); clk_prepare_enable()
482 static inline void clk_disable_unprepare(struct clk *clk) clk_disable_unprepare() argument
484 clk_disable(clk); clk_disable_unprepare()
485 clk_unprepare(clk); clk_disable_unprepare()
492 struct clk *of_clk_get(struct device_node *np, int index);
493 struct clk *of_clk_get_by_name(struct device_node *np, const char *name);
494 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec);
496 static inline struct clk *of_clk_get(struct device_node *np, int index) of_clk_get()
500 static inline struct clk *of_clk_get_by_name(struct device_node *np, of_clk_get_by_name()
|
| /linux-4.4.14/arch/arm/mach-omap1/ |
| H A D | clock.c | 20 #include <linux/clk.h>
34 struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
44 unsigned long omap1_uart_recalc(struct clk *clk) omap1_uart_recalc() argument
46 unsigned int val = __raw_readl(clk->enable_reg); omap1_uart_recalc()
47 return val & clk->enable_bit ? 48000000 : 12000000; omap1_uart_recalc()
50 unsigned long omap1_sossi_recalc(struct clk *clk) omap1_sossi_recalc() argument
57 return clk->parent->rate / div; omap1_sossi_recalc()
60 static void omap1_clk_allow_idle(struct clk *clk) omap1_clk_allow_idle() argument
62 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; omap1_clk_allow_idle()
64 if (!(clk->flags & CLOCK_IDLE_CONTROL)) omap1_clk_allow_idle()
71 static void omap1_clk_deny_idle(struct clk *clk) omap1_clk_deny_idle() argument
73 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; omap1_clk_deny_idle()
75 if (!(clk->flags & CLOCK_IDLE_CONTROL)) omap1_clk_deny_idle()
135 static int calc_dsor_exp(struct clk *clk, unsigned long rate) calc_dsor_exp() argument
149 struct clk * parent; calc_dsor_exp()
152 parent = clk->parent; calc_dsor_exp()
167 unsigned long omap1_ckctl_recalc(struct clk *clk) omap1_ckctl_recalc() argument
170 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); omap1_ckctl_recalc()
172 return clk->parent->rate / dsor; omap1_ckctl_recalc()
175 unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk) omap1_ckctl_recalc_dsp_domain() argument
187 dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); omap1_ckctl_recalc_dsp_domain()
190 return clk->parent->rate / dsor; omap1_ckctl_recalc_dsp_domain()
194 int omap1_select_table_rate(struct clk *clk, unsigned long rate) omap1_select_table_rate() argument
229 int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) omap1_clk_set_rate_dsp_domain() argument
234 dsor_exp = calc_dsor_exp(clk, rate); omap1_clk_set_rate_dsp_domain()
241 regval &= ~(3 << clk->rate_offset); omap1_clk_set_rate_dsp_domain()
242 regval |= dsor_exp << clk->rate_offset; omap1_clk_set_rate_dsp_domain()
244 clk->rate = clk->parent->rate / (1 << dsor_exp); omap1_clk_set_rate_dsp_domain()
249 long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate) omap1_clk_round_rate_ckctl_arm() argument
251 int dsor_exp = calc_dsor_exp(clk, rate); omap1_clk_round_rate_ckctl_arm()
256 return clk->parent->rate / (1 << dsor_exp); omap1_clk_round_rate_ckctl_arm()
259 int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate) omap1_clk_set_rate_ckctl_arm() argument
264 dsor_exp = calc_dsor_exp(clk, rate); omap1_clk_set_rate_ckctl_arm()
271 regval &= ~(3 << clk->rate_offset); omap1_clk_set_rate_ckctl_arm()
272 regval |= dsor_exp << clk->rate_offset; omap1_clk_set_rate_ckctl_arm()
275 clk->rate = clk->parent->rate / (1 << dsor_exp); omap1_clk_set_rate_ckctl_arm()
279 long omap1_round_to_table_rate(struct clk *clk, unsigned long rate) omap1_round_to_table_rate() argument
330 int omap1_set_uart_rate(struct clk *clk, unsigned long rate) omap1_set_uart_rate() argument
334 val = __raw_readl(clk->enable_reg); omap1_set_uart_rate()
336 val &= ~(1 << clk->enable_bit); omap1_set_uart_rate()
338 val |= (1 << clk->enable_bit); omap1_set_uart_rate()
341 __raw_writel(val, clk->enable_reg); omap1_set_uart_rate()
342 clk->rate = rate; omap1_set_uart_rate()
348 int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate) omap1_set_ext_clk_rate() argument
354 clk->rate = 96000000 / dsor; omap1_set_ext_clk_rate()
360 ratio_bits |= __raw_readw(clk->enable_reg) & ~0xfd; omap1_set_ext_clk_rate()
361 __raw_writew(ratio_bits, clk->enable_reg); omap1_set_ext_clk_rate()
366 int omap1_set_sossi_rate(struct clk *clk, unsigned long rate) omap1_set_sossi_rate() argument
372 p_rate = clk->parent->rate; omap1_set_sossi_rate()
384 clk->rate = p_rate / (div + 1); omap1_set_sossi_rate()
389 long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate) omap1_round_ext_clk_rate() argument
394 void omap1_init_ext_clk(struct clk *clk) omap1_init_ext_clk() argument
400 ratio_bits = __raw_readw(clk->enable_reg) & ~1; omap1_init_ext_clk()
401 __raw_writew(ratio_bits, clk->enable_reg); omap1_init_ext_clk()
409 clk-> rate = 96000000 / dsor; omap1_init_ext_clk()
412 int omap1_clk_enable(struct clk *clk) omap1_clk_enable() argument
416 if (clk->usecount++ == 0) { omap1_clk_enable()
417 if (clk->parent) { omap1_clk_enable()
418 ret = omap1_clk_enable(clk->parent); omap1_clk_enable()
422 if (clk->flags & CLOCK_NO_IDLE_PARENT) omap1_clk_enable()
423 omap1_clk_deny_idle(clk->parent); omap1_clk_enable()
426 ret = clk->ops->enable(clk); omap1_clk_enable()
428 if (clk->parent) omap1_clk_enable()
429 omap1_clk_disable(clk->parent); omap1_clk_enable()
436 clk->usecount--; omap1_clk_enable()
440 void omap1_clk_disable(struct clk *clk) omap1_clk_disable() argument
442 if (clk->usecount > 0 && !(--clk->usecount)) { omap1_clk_disable()
443 clk->ops->disable(clk); omap1_clk_disable()
444 if (likely(clk->parent)) { omap1_clk_disable()
445 omap1_clk_disable(clk->parent); omap1_clk_disable()
446 if (clk->flags & CLOCK_NO_IDLE_PARENT) omap1_clk_disable()
447 omap1_clk_allow_idle(clk->parent); omap1_clk_disable()
452 static int omap1_clk_enable_generic(struct clk *clk) omap1_clk_enable_generic() argument
457 if (unlikely(clk->enable_reg == NULL)) { omap1_clk_enable_generic()
459 clk->name); omap1_clk_enable_generic()
463 if (clk->flags & ENABLE_REG_32BIT) { omap1_clk_enable_generic()
464 regval32 = __raw_readl(clk->enable_reg); omap1_clk_enable_generic()
465 regval32 |= (1 << clk->enable_bit); omap1_clk_enable_generic()
466 __raw_writel(regval32, clk->enable_reg); omap1_clk_enable_generic()
468 regval16 = __raw_readw(clk->enable_reg); omap1_clk_enable_generic()
469 regval16 |= (1 << clk->enable_bit); omap1_clk_enable_generic()
470 __raw_writew(regval16, clk->enable_reg); omap1_clk_enable_generic()
476 static void omap1_clk_disable_generic(struct clk *clk) omap1_clk_disable_generic() argument
481 if (clk->enable_reg == NULL) omap1_clk_disable_generic()
484 if (clk->flags & ENABLE_REG_32BIT) { omap1_clk_disable_generic()
485 regval32 = __raw_readl(clk->enable_reg); omap1_clk_disable_generic()
486 regval32 &= ~(1 << clk->enable_bit); omap1_clk_disable_generic()
487 __raw_writel(regval32, clk->enable_reg); omap1_clk_disable_generic()
489 regval16 = __raw_readw(clk->enable_reg); omap1_clk_disable_generic()
490 regval16 &= ~(1 << clk->enable_bit); omap1_clk_disable_generic()
491 __raw_writew(regval16, clk->enable_reg); omap1_clk_disable_generic()
500 static int omap1_clk_enable_dsp_domain(struct clk *clk) omap1_clk_enable_dsp_domain() argument
506 retval = omap1_clk_enable_generic(clk); omap1_clk_enable_dsp_domain()
513 static void omap1_clk_disable_dsp_domain(struct clk *clk) omap1_clk_disable_dsp_domain() argument
516 omap1_clk_disable_generic(clk); omap1_clk_disable_dsp_domain()
527 static int omap1_clk_enable_uart_functional_16xx(struct clk *clk) omap1_clk_enable_uart_functional_16xx() argument
532 ret = omap1_clk_enable_generic(clk); omap1_clk_enable_uart_functional_16xx()
535 uclk = (struct uart_clk *)clk; omap1_clk_enable_uart_functional_16xx()
544 static void omap1_clk_disable_uart_functional_16xx(struct clk *clk) omap1_clk_disable_uart_functional_16xx() argument
549 uclk = (struct uart_clk *)clk; omap1_clk_disable_uart_functional_16xx()
552 omap1_clk_disable_generic(clk); omap1_clk_disable_uart_functional_16xx()
561 long omap1_clk_round_rate(struct clk *clk, unsigned long rate) omap1_clk_round_rate() argument
563 if (clk->round_rate != NULL) omap1_clk_round_rate()
564 return clk->round_rate(clk, rate); omap1_clk_round_rate()
566 return clk->rate; omap1_clk_round_rate()
569 int omap1_clk_set_rate(struct clk *clk, unsigned long rate) omap1_clk_set_rate() argument
573 if (clk->set_rate) omap1_clk_set_rate()
574 ret = clk->set_rate(clk, rate); omap1_clk_set_rate()
584 void omap1_clk_disable_unused(struct clk *clk) omap1_clk_disable_unused() argument
590 if (clk->enable_reg == DSP_IDLECT2) { omap1_clk_disable_unused()
592 clk->name); omap1_clk_disable_unused()
597 if (clk->flags & ENABLE_REG_32BIT) omap1_clk_disable_unused()
598 regval32 = __raw_readl(clk->enable_reg); omap1_clk_disable_unused()
600 regval32 = __raw_readw(clk->enable_reg); omap1_clk_disable_unused()
602 if ((regval32 & (1 << clk->enable_bit)) == 0) omap1_clk_disable_unused()
605 printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); omap1_clk_disable_unused()
606 clk->ops->disable(clk); omap1_clk_disable_unused()
613 int clk_enable(struct clk *clk) clk_enable() argument
618 if (clk == NULL || IS_ERR(clk)) clk_enable()
622 ret = omap1_clk_enable(clk); clk_enable()
629 void clk_disable(struct clk *clk) clk_disable() argument
633 if (clk == NULL || IS_ERR(clk)) clk_disable()
637 if (clk->usecount == 0) { clk_disable()
639 clk->name); clk_disable()
644 omap1_clk_disable(clk); clk_disable()
651 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
656 if (clk == NULL || IS_ERR(clk)) clk_get_rate()
660 ret = clk->rate; clk_get_rate()
668 * Optional clock functions defined in include/linux/clk.h
671 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
676 if (clk == NULL || IS_ERR(clk)) clk_round_rate()
680 ret = omap1_clk_round_rate(clk, rate); clk_round_rate()
687 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
692 if (clk == NULL || IS_ERR(clk)) clk_set_rate()
696 ret = omap1_clk_set_rate(clk, rate); clk_set_rate()
698 propagate_rate(clk); clk_set_rate()
705 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
713 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
715 return clk->parent; clk_get_parent()
744 unsigned long followparent_recalc(struct clk *clk) followparent_recalc() argument
746 return clk->parent->rate; followparent_recalc()
753 unsigned long omap_fixed_divisor_recalc(struct clk *clk) omap_fixed_divisor_recalc() argument
755 WARN_ON(!clk->fixed_div); omap_fixed_divisor_recalc()
757 return clk->parent->rate / clk->fixed_div; omap_fixed_divisor_recalc()
760 void clk_reparent(struct clk *child, struct clk *parent) clk_reparent()
772 void propagate_rate(struct clk *tclk) propagate_rate()
774 struct clk *clkp; propagate_rate()
794 struct clk *clkp; recalculate_root_clocks()
804 * clk_preinit - initialize any fields in the struct clk before clk init
805 * @clk: struct clk * to initialize
807 * Initialize any struct clk fields needed before normal clk initialization
810 void clk_preinit(struct clk *clk) clk_preinit() argument
812 INIT_LIST_HEAD(&clk->children); clk_preinit()
815 int clk_register(struct clk *clk) clk_register() argument
817 if (clk == NULL || IS_ERR(clk)) clk_register()
823 if (clk->node.next || clk->node.prev) clk_register()
827 if (clk->parent) clk_register()
828 list_add(&clk->sibling, &clk->parent->children); clk_register()
830 list_add(&clk->sibling, &root_clks); clk_register()
832 list_add(&clk->node, &clocks); clk_register()
833 if (clk->init) clk_register()
834 clk->init(clk); clk_register()
841 void clk_unregister(struct clk *clk) clk_unregister() argument
843 if (clk == NULL || IS_ERR(clk)) clk_unregister()
847 list_del(&clk->sibling); clk_unregister()
848 list_del(&clk->node); clk_unregister()
855 struct clk *clkp; clk_enable_init_clocks()
863 * omap_clk_get_by_name - locate OMAP struct clk by its name
864 * @name: name of the struct clk to locate
866 * Locate an OMAP struct clk by its name. Assumes that struct clk
868 * struct clk if found.
870 struct clk *omap_clk_get_by_name(const char *name) omap_clk_get_by_name()
872 struct clk *c; omap_clk_get_by_name()
873 struct clk *ret = NULL; omap_clk_get_by_name()
891 struct clk *c; omap_clk_enable_autoidle_all()
907 struct clk *c; omap_clk_disable_autoidle_all()
924 static int clkll_enable_null(struct clk *clk) clkll_enable_null() argument
929 static void clkll_disable_null(struct clk *clk) clkll_disable_null() argument
943 struct clk dummy_ck = {
958 struct clk *ck; clk_disable_unused()
993 struct clk *c; clk_dbg_show_summary()
994 struct clk *pa; clk_dbg_show_summary()
1023 static int clk_debugfs_register_one(struct clk *c) clk_debugfs_register_one()
1027 struct clk *pa = c->parent; clk_debugfs_register_one()
1056 static int clk_debugfs_register(struct clk *c) clk_debugfs_register()
1059 struct clk *pa = c->parent; clk_debugfs_register()
1077 struct clk *c; clk_debugfs_init()
|
| H A D | clock.h | 16 #include <linux/clk.h>
22 struct clk;
35 .clk = ck, \
48 #define __clk_get_name(clk) (clk->name)
49 #define __clk_get_parent(clk) (clk->parent)
50 #define __clk_get_rate(clk) (clk->rate)
57 * @find_companion: function returning the "companion" clk reg for the clock
61 * A "companion" clk is an accompanying clock to the one being queried
71 int (*enable)(struct clk *);
72 void (*disable)(struct clk *);
73 void (*find_idlest)(struct clk *, void __iomem **,
75 void (*find_companion)(struct clk *, void __iomem **,
77 void (*allow_idle)(struct clk *);
78 void (*deny_idle)(struct clk *);
82 * struct clk.flags possibilities
101 * struct clk - OMAP struct clk
105 * @parent: pointer to this clock's parent struct clk
107 * @sibling: list_head connecting this clk to its parent clk's @children
117 * @flags: see "struct clk.flags possibilities" above
141 struct clk { struct
145 struct clk *parent;
150 unsigned long (*recalc)(struct clk *);
151 int (*set_rate)(struct clk *, unsigned long);
152 long (*round_rate)(struct clk *, unsigned long);
153 void (*init)(struct clk *);
166 int (*clk_enable)(struct clk *clk);
167 void (*clk_disable)(struct clk *clk);
168 long (*clk_round_rate)(struct clk *clk, unsigned long rate);
169 int (*clk_set_rate)(struct clk *clk, unsigned long rate);
170 int (*clk_set_parent)(struct clk *clk, struct clk *parent);
171 void (*clk_allow_idle)(struct clk *clk);
172 void (*clk_deny_idle)(struct clk *clk);
173 void (*clk_disable_unused)(struct clk *clk);
179 extern void clk_preinit(struct clk *clk);
180 extern int clk_register(struct clk *clk);
181 extern void clk_reparent(struct clk *child, struct clk *parent);
182 extern void clk_unregister(struct clk *clk);
183 extern void propagate_rate(struct clk *clk);
185 extern unsigned long followparent_recalc(struct clk *clk);
187 unsigned long omap_fixed_divisor_recalc(struct clk *clk);
188 extern struct clk *omap_clk_get_by_name(const char *name);
194 extern struct clk dummy_ck;
198 extern int omap1_clk_enable(struct clk *clk);
199 extern void omap1_clk_disable(struct clk *clk);
200 extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate);
201 extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate);
202 extern unsigned long omap1_ckctl_recalc(struct clk *clk);
203 extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate);
204 extern unsigned long omap1_sossi_recalc(struct clk *clk);
205 extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk);
206 extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate);
207 extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate);
208 extern unsigned long omap1_uart_recalc(struct clk *clk);
209 extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate);
210 extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate);
211 extern void omap1_init_ext_clk(struct clk *clk);
212 extern int omap1_select_table_rate(struct clk *clk, unsigned long rate);
213 extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate);
214 extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate);
215 extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate);
216 extern unsigned long omap1_watchdog_recalc(struct clk *clk);
219 extern void omap1_clk_disable_unused(struct clk *clk);
225 struct clk clk; member in struct:uart_clk
231 struct clk clk; member in struct:arm_idlect1_clk
283 extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p;
|
| H A D | clock_data.c | 19 #include <linux/clk.h>
45 /* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
52 /* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
58 /* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
78 static struct clk ck_ref = {
84 static struct clk ck_dpll1 = {
95 .clk = {
108 static struct clk sossi_ck = {
111 .parent = &ck_dpll1out.clk,
119 static struct clk arm_ck = {
130 .clk = {
149 static struct clk arm_gpio_ck = {
160 .clk = {
173 .clk = {
186 .clk = {
199 static struct clk arminth_ck16xx = {
211 static struct clk dsp_ck = {
223 static struct clk dspmmu_ck = {
233 static struct clk dspper_ck = {
245 static struct clk dspxor_ck = {
254 static struct clk dsptim_ck = {
264 .clk = {
277 static struct clk arminth_ck1510 = {
280 .parent = &tc_ck.clk,
288 static struct clk tipb_ck = {
292 .parent = &tc_ck.clk,
296 static struct clk l3_ocpi_ck = {
300 .parent = &tc_ck.clk,
306 static struct clk tc1_ck = {
309 .parent = &tc_ck.clk,
319 static struct clk tc2_ck = {
322 .parent = &tc_ck.clk,
329 static struct clk dma_ck = {
333 .parent = &tc_ck.clk,
337 static struct clk dma_lcdfree_ck = {
340 .parent = &tc_ck.clk,
345 .clk = {
348 .parent = &tc_ck.clk,
358 .clk = {
361 .parent = &tc_ck.clk,
370 static struct clk rhea1_ck = {
373 .parent = &tc_ck.clk,
377 static struct clk rhea2_ck = {
380 .parent = &tc_ck.clk,
384 static struct clk lcd_ck_16xx = {
397 .clk = {
418 static struct clk uart1_1510 = {
422 .parent = &armper_ck.clk,
438 .clk = {
442 .parent = &armper_ck.clk,
457 static struct clk uart2_ck = {
461 .parent = &armper_ck.clk,
476 static struct clk uart3_1510 = {
480 .parent = &armper_ck.clk,
496 .clk = {
500 .parent = &armper_ck.clk,
509 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
519 static struct clk usb_hhc_ck1510 = {
529 static struct clk usb_hhc_ck16xx = {
540 static struct clk usb_dc_ck = {
549 static struct clk uart1_7xx = {
558 static struct clk uart2_7xx = {
567 static struct clk mclk_1510 = {
576 static struct clk mclk_16xx = {
587 static struct clk bclk_1510 = {
594 static struct clk bclk_16xx = {
605 static struct clk mmc1_ck = {
609 .parent = &armper_ck.clk,
620 static struct clk mmc2_ck = {
624 .parent = &armper_ck.clk,
631 static struct clk mmc3_ck = {
635 .parent = &armper_ck.clk,
642 static struct clk virtual_ck_mpu = {
653 static struct clk i2c_fck = {
657 .parent = &armxor_ck.clk,
661 static struct clk i2c_ick = {
665 .parent = &armper_ck.clk,
678 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
681 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
683 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
684 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
685 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
686 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
697 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
704 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
705 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
709 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
712 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
717 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
728 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
730 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
740 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
743 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
748 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
790 clk_preinit(c->lk.clk); omap1_clk_init()
807 clk_register(c->lk.clk); omap1_clk_init()
896 clk_enable(&armper_ck.clk); omap1_clk_init()
897 clk_enable(&armxor_ck.clk); omap1_clk_init()
898 clk_enable(&armtim_ck.clk); /* This should be done by timer code */ omap1_clk_init()
|
| /linux-4.4.14/arch/blackfin/mach-bf609/ |
| H A D | clock.c | 7 #include <linux/clk.h>
57 .clk = &_clk, \
82 printk(KERN_CRIT "fail to align clk\n"); wait_for_pll_align()
89 int clk_enable(struct clk *clk) clk_enable() argument
92 if (clk->ops && clk->ops->enable) clk_enable()
93 ret = clk->ops->enable(clk); clk_enable()
98 void clk_disable(struct clk *clk) clk_disable() argument
100 if (clk->ops && clk->ops->disable) clk_disable()
101 clk->ops->disable(clk); clk_disable()
106 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
109 if (clk->ops && clk->ops->get_rate) clk_get_rate()
110 ret = clk->ops->get_rate(clk); clk_get_rate()
115 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
118 if (clk->ops && clk->ops->round_rate) clk_round_rate()
119 ret = clk->ops->round_rate(clk, rate); clk_round_rate()
124 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
127 if (clk->ops && clk->ops->set_rate) clk_set_rate()
128 ret = clk->ops->set_rate(clk, rate); clk_set_rate()
133 unsigned long vco_get_rate(struct clk *clk) vco_get_rate() argument
135 return clk->rate; vco_get_rate()
138 unsigned long pll_get_rate(struct clk *clk) pll_get_rate() argument
148 clk->parent->rate = clk_get_rate(clk->parent); pll_get_rate()
149 return clk->parent->rate / (df + 1) * msel * 2; pll_get_rate()
152 unsigned long pll_round_rate(struct clk *clk, unsigned long rate) pll_round_rate() argument
155 div = rate / clk->parent->rate; pll_round_rate()
156 return clk->parent->rate * div; pll_round_rate()
159 int pll_set_rate(struct clk *clk, unsigned long rate) pll_set_rate() argument
169 msel = rate / clk->parent->rate / 2; pll_set_rate()
172 clk->rate = rate; pll_set_rate()
176 unsigned long cclk_get_rate(struct clk *clk) cclk_get_rate() argument
178 if (clk->parent) cclk_get_rate()
179 return clk->parent->rate; cclk_get_rate()
184 unsigned long sys_clk_get_rate(struct clk *clk) sys_clk_get_rate() argument
191 div = (div & clk->mask) >> clk->shift; sys_clk_get_rate()
195 if (!strcmp(clk->parent->name, "SYS_CLKIN")) { sys_clk_get_rate()
196 drate = clk->parent->rate / (df + 1); sys_clk_get_rate()
201 clk->parent->rate = clk_get_rate(clk->parent); sys_clk_get_rate()
202 return clk->parent->rate / div; sys_clk_get_rate()
206 unsigned long dummy_get_rate(struct clk *clk) dummy_get_rate() argument
208 clk->parent->rate = clk_get_rate(clk->parent); dummy_get_rate()
209 return clk->parent->rate; dummy_get_rate()
212 unsigned long sys_clk_round_rate(struct clk *clk, unsigned long rate) sys_clk_round_rate() argument
223 max_rate = clk->parent->rate / (df + 1) * msel; sys_clk_round_rate()
228 for (i = 1; i < clk->mask; i++) { sys_clk_round_rate()
236 int sys_clk_set_rate(struct clk *clk, unsigned long rate) sys_clk_set_rate() argument
239 div = (div & clk->mask) >> clk->shift; sys_clk_set_rate()
241 rate = clk_round_rate(clk, rate); sys_clk_set_rate()
246 div = (clk_get_rate(clk) * div) / rate; sys_clk_set_rate()
250 clk_reg_write_mask(CGU0_DIV, div << clk->shift, sys_clk_set_rate()
251 clk->mask); sys_clk_set_rate()
252 clk->rate = rate; sys_clk_set_rate()
279 static struct clk sys_clkin = {
285 static struct clk pll_clk = {
293 static struct clk cclk = {
303 static struct clk cclk0 = {
309 static struct clk cclk1 = {
315 static struct clk sysclk = {
325 static struct clk sclk0 = {
334 static struct clk sclk1 = {
343 static struct clk dclk = {
352 static struct clk oclk = {
360 static struct clk ethclk = {
366 static struct clk ethpclk = {
372 static struct clk spiclk = {
397 struct clk *clkp; clk_init()
399 clkp = bf609_clks[i].clk; clk_init()
|
| /linux-4.4.14/arch/mips/loongson64/lemote-2f/ |
| H A D | clock.c | 9 #include <linux/clk.h>
44 static struct clk cpu_clk = {
50 struct clk *clk_get(struct device *dev, const char *id) clk_get()
56 static void propagate_rate(struct clk *clk) propagate_rate() argument
58 struct clk *clkp; propagate_rate()
61 if (likely(clkp->parent != clk)) propagate_rate()
70 int clk_enable(struct clk *clk) clk_enable() argument
76 void clk_disable(struct clk *clk) clk_disable() argument
81 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
83 return (unsigned long)clk->rate; clk_get_rate()
87 void clk_put(struct clk *clk) clk_put() argument
92 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
99 if (likely(clk->ops && clk->ops->set_rate)) { clk_set_rate()
103 ret = clk->ops->set_rate(clk, rate, 0); clk_set_rate()
107 if (unlikely(clk->flags & CLK_RATE_PROPAGATES)) clk_set_rate()
108 propagate_rate(clk); clk_set_rate()
116 clk->rate = rate; clk_set_rate()
126 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
128 if (likely(clk->ops && clk->ops->round_rate)) { clk_round_rate()
132 rounded = clk->ops->round_rate(clk, rate); clk_round_rate()
|
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 40 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, nvkm_clk_adjust() argument
43 struct nvkm_bios *bios = clk->subdev.device->bios; nvkm_clk_adjust()
78 nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei) nvkm_cstate_prog() argument
80 struct nvkm_subdev *subdev = &clk->subdev; nvkm_cstate_prog()
109 ret = clk->func->calc(clk, cstate); nvkm_cstate_prog()
111 ret = clk->func->prog(clk); nvkm_cstate_prog()
112 clk->func->tidy(clk); nvkm_cstate_prog()
138 nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate) nvkm_cstate_new() argument
140 struct nvkm_bios *bios = clk->subdev.device->bios; nvkm_cstate_new()
141 const struct nvkm_domain *domain = clk->domains; nvkm_cstate_new()
160 u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate, nvkm_cstate_new()
175 nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei) nvkm_pstate_prog() argument
177 struct nvkm_subdev *subdev = &clk->subdev; nvkm_pstate_prog()
182 list_for_each_entry(pstate, &clk->states, head) { nvkm_pstate_prog()
188 clk->pstate = pstatei; nvkm_pstate_prog()
200 return nvkm_cstate_prog(clk, pstate, 0); nvkm_pstate_prog()
206 struct nvkm_clk *clk = container_of(work, typeof(*clk), work); nvkm_pstate_work() local
207 struct nvkm_subdev *subdev = &clk->subdev; nvkm_pstate_work()
210 if (!atomic_xchg(&clk->waiting, 0)) nvkm_pstate_work()
212 clk->pwrsrc = power_supply_is_system_supplied(); nvkm_pstate_work()
215 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, nvkm_pstate_work()
216 clk->astate, clk->tstate, clk->dstate); nvkm_pstate_work()
218 pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; nvkm_pstate_work()
219 if (clk->state_nr && pstate != -1) { nvkm_pstate_work()
220 pstate = (pstate < 0) ? clk->astate : pstate; nvkm_pstate_work()
221 pstate = min(pstate, clk->state_nr - 1 + clk->tstate); nvkm_pstate_work()
222 pstate = max(pstate, clk->dstate); nvkm_pstate_work()
224 pstate = clk->pstate = -1; nvkm_pstate_work()
228 if (pstate != clk->pstate) { nvkm_pstate_work()
229 int ret = nvkm_pstate_prog(clk, pstate); nvkm_pstate_work()
236 wake_up_all(&clk->wait); nvkm_pstate_work()
237 nvkm_notify_get(&clk->pwrsrc_ntfy); nvkm_pstate_work()
241 nvkm_pstate_calc(struct nvkm_clk *clk, bool wait) nvkm_pstate_calc() argument
243 atomic_set(&clk->waiting, 1); nvkm_pstate_calc()
244 schedule_work(&clk->work); nvkm_pstate_calc()
246 wait_event(clk->wait, !atomic_read(&clk->waiting)); nvkm_pstate_calc()
251 nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate) nvkm_pstate_info() argument
253 const struct nvkm_domain *clock = clk->domains - 1; nvkm_pstate_info()
255 struct nvkm_subdev *subdev = &clk->subdev; nvkm_pstate_info()
307 nvkm_pstate_new(struct nvkm_clk *clk, int idx) nvkm_pstate_new() argument
309 struct nvkm_bios *bios = clk->subdev.device->bios; nvkm_pstate_new()
310 const struct nvkm_domain *domain = clk->domains - 1; nvkm_pstate_new()
349 perfS.v40.freq = nvkm_clk_adjust(clk, false, nvkm_pstate_new()
362 nvkm_cstate_new(clk, idx, pstate); nvkm_pstate_new()
366 nvkm_pstate_info(clk, pstate); nvkm_pstate_new()
367 list_add_tail(&pstate->head, &clk->states); nvkm_pstate_new()
368 clk->state_nr++; nvkm_pstate_new()
376 nvkm_clk_ustate_update(struct nvkm_clk *clk, int req) nvkm_clk_ustate_update() argument
381 if (!clk->allow_reclock) nvkm_clk_ustate_update()
385 list_for_each_entry(pstate, &clk->states, head) { nvkm_clk_ustate_update()
400 nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen) nvkm_clk_nstate() argument
404 if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen)) nvkm_clk_nstate()
413 ret = nvkm_clk_ustate_update(clk, v); nvkm_clk_nstate()
424 nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr) nvkm_clk_ustate() argument
426 int ret = nvkm_clk_ustate_update(clk, req); nvkm_clk_ustate()
428 if (ret -= 2, pwr) clk->ustate_ac = ret; nvkm_clk_ustate()
429 else clk->ustate_dc = ret; nvkm_clk_ustate()
430 return nvkm_pstate_calc(clk, true); nvkm_clk_ustate()
436 nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait) nvkm_clk_astate() argument
438 if (!rel) clk->astate = req; nvkm_clk_astate()
439 if ( rel) clk->astate += rel; nvkm_clk_astate()
440 clk->astate = min(clk->astate, clk->state_nr - 1); nvkm_clk_astate()
441 clk->astate = max(clk->astate, 0); nvkm_clk_astate()
442 return nvkm_pstate_calc(clk, wait); nvkm_clk_astate()
446 nvkm_clk_tstate(struct nvkm_clk *clk, int req, int rel) nvkm_clk_tstate() argument
448 if (!rel) clk->tstate = req; nvkm_clk_tstate()
449 if ( rel) clk->tstate += rel; nvkm_clk_tstate()
450 clk->tstate = min(clk->tstate, 0); nvkm_clk_tstate()
451 clk->tstate = max(clk->tstate, -(clk->state_nr - 1)); nvkm_clk_tstate()
452 return nvkm_pstate_calc(clk, true); nvkm_clk_tstate()
456 nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel) nvkm_clk_dstate() argument
458 if (!rel) clk->dstate = req; nvkm_clk_dstate()
459 if ( rel) clk->dstate += rel; nvkm_clk_dstate()
460 clk->dstate = min(clk->dstate, clk->state_nr - 1); nvkm_clk_dstate()
461 clk->dstate = max(clk->dstate, 0); nvkm_clk_dstate()
462 return nvkm_pstate_calc(clk, true); nvkm_clk_dstate()
468 struct nvkm_clk *clk = nvkm_clk_pwrsrc() local
469 container_of(notify, typeof(*clk), pwrsrc_ntfy); nvkm_clk_pwrsrc()
470 nvkm_pstate_calc(clk, false); nvkm_clk_pwrsrc()
479 nvkm_clk_read(struct nvkm_clk *clk, enum nv_clk_src src) nvkm_clk_read() argument
481 return clk->func->read(clk, src); nvkm_clk_read()
487 struct nvkm_clk *clk = nvkm_clk(subdev); nvkm_clk_fini() local
488 nvkm_notify_put(&clk->pwrsrc_ntfy); nvkm_clk_fini()
489 flush_work(&clk->work); nvkm_clk_fini()
490 if (clk->func->fini) nvkm_clk_fini()
491 clk->func->fini(clk); nvkm_clk_fini()
498 struct nvkm_clk *clk = nvkm_clk(subdev); nvkm_clk_init() local
499 const struct nvkm_domain *clock = clk->domains; nvkm_clk_init()
502 memset(&clk->bstate, 0x00, sizeof(clk->bstate)); nvkm_clk_init()
503 INIT_LIST_HEAD(&clk->bstate.list); nvkm_clk_init()
504 clk->bstate.pstate = 0xff; nvkm_clk_init()
507 ret = nvkm_clk_read(clk, clock->name); nvkm_clk_init()
512 clk->bstate.base.domain[clock->name] = ret; nvkm_clk_init()
516 nvkm_pstate_info(clk, &clk->bstate); nvkm_clk_init()
518 if (clk->func->init) nvkm_clk_init()
519 return clk->func->init(clk); nvkm_clk_init()
521 clk->astate = clk->state_nr - 1; nvkm_clk_init()
522 clk->tstate = 0; nvkm_clk_init()
523 clk->dstate = 0; nvkm_clk_init()
524 clk->pstate = -1; nvkm_clk_init()
525 nvkm_pstate_calc(clk, true); nvkm_clk_init()
532 struct nvkm_clk *clk = nvkm_clk(subdev); nvkm_clk_dtor() local
535 nvkm_notify_fini(&clk->pwrsrc_ntfy); nvkm_clk_dtor()
538 if (clk->func->pstates) nvkm_clk_dtor()
539 return clk; nvkm_clk_dtor()
541 list_for_each_entry_safe(pstate, temp, &clk->states, head) { nvkm_clk_dtor()
545 return clk; nvkm_clk_dtor()
557 int index, bool allow_reclock, struct nvkm_clk *clk) nvkm_clk_ctor()
562 nvkm_subdev_ctor(&nvkm_clk, device, index, 0, &clk->subdev); nvkm_clk_ctor()
563 clk->func = func; nvkm_clk_ctor()
564 INIT_LIST_HEAD(&clk->states); nvkm_clk_ctor()
565 clk->domains = func->domains; nvkm_clk_ctor()
566 clk->ustate_ac = -1; nvkm_clk_ctor()
567 clk->ustate_dc = -1; nvkm_clk_ctor()
568 clk->allow_reclock = allow_reclock; nvkm_clk_ctor()
570 INIT_WORK(&clk->work, nvkm_pstate_work); nvkm_clk_ctor()
571 init_waitqueue_head(&clk->wait); nvkm_clk_ctor()
572 atomic_set(&clk->waiting, 0); nvkm_clk_ctor()
578 ret = nvkm_pstate_new(clk, idx++); nvkm_clk_ctor()
582 list_add_tail(&func->pstates[idx].head, &clk->states); nvkm_clk_ctor()
583 clk->state_nr = func->nr_pstates; nvkm_clk_ctor()
587 NULL, 0, 0, &clk->pwrsrc_ntfy); nvkm_clk_ctor()
593 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_ctor()
594 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_ctor()
599 clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_ctor()
603 clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen); nvkm_clk_ctor()
556 nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device, int index, bool allow_reclock, struct nvkm_clk *clk) nvkm_clk_ctor() argument
|
| H A D | mcp77.c | 42 read_div(struct mcp77_clk *clk) read_div() argument
44 struct nvkm_device *device = clk->base.subdev.device; read_div()
49 read_pll(struct mcp77_clk *clk, u32 base) read_pll() argument
51 struct nvkm_device *device = clk->base.subdev.device; read_pll()
54 u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href); read_pll()
83 struct mcp77_clk *clk = mcp77_clk(base); mcp77_clk_read() local
84 struct nvkm_subdev *subdev = &clk->base.subdev; mcp77_clk_read()
95 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4; mcp77_clk_read()
97 return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3; mcp77_clk_read()
100 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); mcp77_clk_read()
102 case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); mcp77_clk_read()
103 case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk); mcp77_clk_read()
110 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; mcp77_clk_read()
112 case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P; mcp77_clk_read()
113 case 0x00000003: return read_pll(clk, 0x004028) >> P; mcp77_clk_read()
118 return nvkm_clk_read(&clk->base, nv_clk_src_core); mcp77_clk_read()
121 return nvkm_clk_read(&clk->base, nv_clk_src_core); mcp77_clk_read()
124 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); mcp77_clk_read()
125 case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4); mcp77_clk_read()
126 case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3); mcp77_clk_read()
134 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; mcp77_clk_read()
135 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; mcp77_clk_read()
137 case 0x00000020: return read_pll(clk, 0x004028) >> P; mcp77_clk_read()
138 case 0x00000030: return read_pll(clk, 0x004020) >> P; mcp77_clk_read()
145 P = (read_div(clk) & 0x00000700) >> 8; mcp77_clk_read()
149 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; mcp77_clk_read()
165 calc_pll(struct mcp77_clk *clk, u32 reg, calc_pll() argument
168 struct nvkm_subdev *subdev = &clk->base.subdev; calc_pll()
177 pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href); calc_pll()
205 struct mcp77_clk *clk = mcp77_clk(base); mcp77_clk_calc() local
209 struct nvkm_subdev *subdev = &clk->base.subdev; mcp77_clk_calc()
215 if (core < nvkm_clk_read(&clk->base, nv_clk_src_hclkm4)) mcp77_clk_calc()
216 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); mcp77_clk_calc()
219 clock = calc_pll(clk, 0x4028, (core << 1), &N, &M, &P1); mcp77_clk_calc()
222 clk->csrc = nv_clk_src_hclkm4; mcp77_clk_calc()
223 clk->cctrl = divs << 16; mcp77_clk_calc()
233 clk->csrc = nv_clk_src_core; mcp77_clk_calc()
234 clk->ccoef = (N << 8) | M; mcp77_clk_calc()
236 clk->cctrl = (P2 + 1) << 16; mcp77_clk_calc()
237 clk->cpost = (1 << P1) << 16; mcp77_clk_calc()
242 if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) { mcp77_clk_calc()
243 clk->ssrc = nv_clk_src_href; mcp77_clk_calc()
245 clock = calc_pll(clk, 0x4020, shader, &N, &M, &P1); mcp77_clk_calc()
246 if (clk->csrc == nv_clk_src_core) mcp77_clk_calc()
252 clk->ssrc = nv_clk_src_core; mcp77_clk_calc()
253 clk->sctrl = (divs + P2) << 16; mcp77_clk_calc()
255 clk->ssrc = nv_clk_src_shader; mcp77_clk_calc()
256 clk->scoef = (N << 8) | M; mcp77_clk_calc()
257 clk->sctrl = P1 << 16; mcp77_clk_calc()
265 clk->vsrc = nv_clk_src_cclk; mcp77_clk_calc()
266 clk->vdiv = divs << 16; mcp77_clk_calc()
268 clk->vsrc = nv_clk_src_vdec; mcp77_clk_calc()
269 clk->vdiv = P1 << 16; mcp77_clk_calc()
274 clk->ccoef, clk->cpost, clk->cctrl); mcp77_clk_calc()
276 clk->scoef, clk->spost, clk->sctrl); mcp77_clk_calc()
277 nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv); mcp77_clk_calc()
278 if (clk->csrc == nv_clk_src_hclkm4) mcp77_clk_calc()
283 if (clk->ssrc == nv_clk_src_hclkm4) mcp77_clk_calc()
285 else if (clk->ssrc == nv_clk_src_core) mcp77_clk_calc()
290 if (clk->vsrc == nv_clk_src_hclkm4) mcp77_clk_calc()
301 struct mcp77_clk *clk = mcp77_clk(base); mcp77_clk_prog() local
302 struct nvkm_subdev *subdev = &clk->base.subdev; mcp77_clk_prog()
309 ret = gt215_clk_pre(&clk->base, f); mcp77_clk_prog()
318 switch (clk->csrc) { mcp77_clk_prog()
320 nvkm_mask(device, 0x4028, 0x00070000, clk->cctrl); mcp77_clk_prog()
324 nvkm_wr32(device, 0x402c, clk->ccoef); mcp77_clk_prog()
325 nvkm_wr32(device, 0x4028, 0x80000000 | clk->cctrl); mcp77_clk_prog()
326 nvkm_wr32(device, 0x4040, clk->cpost); mcp77_clk_prog()
335 switch (clk->ssrc) { mcp77_clk_prog()
341 nvkm_mask(device, 0x4020, 0x00070000, clk->sctrl); mcp77_clk_prog()
345 nvkm_wr32(device, 0x4024, clk->scoef); mcp77_clk_prog()
346 nvkm_wr32(device, 0x4020, 0x80000000 | clk->sctrl); mcp77_clk_prog()
347 nvkm_wr32(device, 0x4070, clk->spost); mcp77_clk_prog()
363 switch (clk->vsrc) { mcp77_clk_prog()
367 nvkm_wr32(device, 0x4600, clk->vdiv); mcp77_clk_prog()
374 if (clk->csrc != nv_clk_src_core) { mcp77_clk_prog()
379 if (clk->ssrc != nv_clk_src_shader) { mcp77_clk_prog()
388 gt215_clk_post(&clk->base, f); mcp77_clk_prog()
416 struct mcp77_clk *clk; mcp77_clk_new() local
418 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) mcp77_clk_new()
420 *pclk = &clk->base; mcp77_clk_new()
422 return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base); mcp77_clk_new()
|
| H A D | gk20a.c | 125 gk20a_pllg_read_mnp(struct gk20a_clk *clk) gk20a_pllg_read_mnp() argument
127 struct nvkm_device *device = clk->base.subdev.device; gk20a_pllg_read_mnp()
131 clk->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); gk20a_pllg_read_mnp()
132 clk->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); gk20a_pllg_read_mnp()
133 clk->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); gk20a_pllg_read_mnp()
137 gk20a_pllg_calc_rate(struct gk20a_clk *clk) gk20a_pllg_calc_rate() argument
142 rate = clk->parent_rate * clk->n; gk20a_pllg_calc_rate()
143 divider = clk->m * pl_to_div[clk->pl]; gk20a_pllg_calc_rate()
150 gk20a_pllg_calc_mnp(struct gk20a_clk *clk, unsigned long rate) gk20a_pllg_calc_mnp() argument
152 struct nvkm_subdev *subdev = &clk->base.subdev; gk20a_pllg_calc_mnp()
164 ref_clk_f = clk->parent_rate / MHZ; gk20a_pllg_calc_mnp()
166 max_vco_f = clk->params->max_vco; gk20a_pllg_calc_mnp()
167 min_vco_f = clk->params->min_vco; gk20a_pllg_calc_mnp()
168 best_m = clk->params->max_m; gk20a_pllg_calc_mnp()
169 best_n = clk->params->min_n; gk20a_pllg_calc_mnp()
170 best_pl = clk->params->min_pl; gk20a_pllg_calc_mnp()
178 high_pl = min(high_pl, clk->params->max_pl); gk20a_pllg_calc_mnp()
179 high_pl = max(high_pl, clk->params->min_pl); gk20a_pllg_calc_mnp()
183 low_pl = min(low_pl, clk->params->max_pl); gk20a_pllg_calc_mnp()
184 low_pl = max(low_pl, clk->params->min_pl); gk20a_pllg_calc_mnp()
206 for (m = clk->params->min_m; m <= clk->params->max_m; m++) { gk20a_pllg_calc_mnp()
209 if (u_f < clk->params->min_u) gk20a_pllg_calc_mnp()
211 if (u_f > clk->params->max_u) gk20a_pllg_calc_mnp()
217 if (n > clk->params->max_n) gk20a_pllg_calc_mnp()
221 if (n < clk->params->min_n) gk20a_pllg_calc_mnp()
223 if (n > clk->params->max_n) gk20a_pllg_calc_mnp()
255 clk->m = best_m; gk20a_pllg_calc_mnp()
256 clk->n = best_n; gk20a_pllg_calc_mnp()
257 clk->pl = best_pl; gk20a_pllg_calc_mnp()
259 target_freq = gk20a_pllg_calc_rate(clk) / MHZ; gk20a_pllg_calc_mnp()
263 target_freq, clk->m, clk->n, clk->pl, pl_to_div[clk->pl]); gk20a_pllg_calc_mnp()
268 gk20a_pllg_slide(struct gk20a_clk *clk, u32 n) gk20a_pllg_slide() argument
270 struct nvkm_subdev *subdev = &clk->base.subdev; gk20a_pllg_slide()
327 _gk20a_pllg_enable(struct gk20a_clk *clk) _gk20a_pllg_enable() argument
329 struct nvkm_device *device = clk->base.subdev.device; _gk20a_pllg_enable()
335 _gk20a_pllg_disable(struct gk20a_clk *clk) _gk20a_pllg_disable() argument
337 struct nvkm_device *device = clk->base.subdev.device; _gk20a_pllg_disable()
343 _gk20a_pllg_program_mnp(struct gk20a_clk *clk, bool allow_slide) _gk20a_pllg_program_mnp() argument
345 struct nvkm_subdev *subdev = &clk->base.subdev; _gk20a_pllg_program_mnp()
357 if (allow_slide && clk->m == m_old && clk->pl == pl_old && _gk20a_pllg_program_mnp()
359 return gk20a_pllg_slide(clk, clk->n); _gk20a_pllg_program_mnp()
363 n_lo = DIV_ROUND_UP(m_old * clk->params->min_vco, _gk20a_pllg_program_mnp()
364 clk->parent_rate / MHZ); _gk20a_pllg_program_mnp()
366 int ret = gk20a_pllg_slide(clk, n_lo); _gk20a_pllg_program_mnp()
391 _gk20a_pllg_disable(clk); _gk20a_pllg_program_mnp()
394 clk->m, clk->n, clk->pl); _gk20a_pllg_program_mnp()
396 n_lo = DIV_ROUND_UP(clk->m * clk->params->min_vco, _gk20a_pllg_program_mnp()
397 clk->parent_rate / MHZ); _gk20a_pllg_program_mnp()
398 val = clk->m << GPCPLL_COEFF_M_SHIFT; _gk20a_pllg_program_mnp()
399 val |= (allow_slide ? n_lo : clk->n) << GPCPLL_COEFF_N_SHIFT; _gk20a_pllg_program_mnp()
400 val |= clk->pl << GPCPLL_COEFF_P_SHIFT; _gk20a_pllg_program_mnp()
403 _gk20a_pllg_enable(clk); _gk20a_pllg_program_mnp()
427 return allow_slide ? gk20a_pllg_slide(clk, clk->n) : 0; _gk20a_pllg_program_mnp()
431 gk20a_pllg_program_mnp(struct gk20a_clk *clk) gk20a_pllg_program_mnp() argument
435 err = _gk20a_pllg_program_mnp(clk, true); gk20a_pllg_program_mnp()
437 err = _gk20a_pllg_program_mnp(clk, false); gk20a_pllg_program_mnp()
443 gk20a_pllg_disable(struct gk20a_clk *clk) gk20a_pllg_disable() argument
445 struct nvkm_device *device = clk->base.subdev.device; gk20a_pllg_disable()
455 n_lo = DIV_ROUND_UP(m * clk->params->min_vco, gk20a_pllg_disable()
456 clk->parent_rate / MHZ); gk20a_pllg_disable()
457 gk20a_pllg_slide(clk, n_lo); gk20a_pllg_disable()
463 _gk20a_pllg_disable(clk); gk20a_pllg_disable()
565 struct gk20a_clk *clk = gk20a_clk(base); gk20a_clk_read() local
566 struct nvkm_subdev *subdev = &clk->base.subdev; gk20a_clk_read()
573 gk20a_pllg_read_mnp(clk); gk20a_clk_read()
574 return gk20a_pllg_calc_rate(clk) / GK20A_CLK_GPC_MDIV; gk20a_clk_read()
584 struct gk20a_clk *clk = gk20a_clk(base); gk20a_clk_calc() local
586 return gk20a_pllg_calc_mnp(clk, cstate->domain[nv_clk_src_gpc] * gk20a_clk_calc()
593 struct gk20a_clk *clk = gk20a_clk(base); gk20a_clk_prog() local
595 return gk20a_pllg_program_mnp(clk); gk20a_clk_prog()
606 struct gk20a_clk *clk = gk20a_clk(base); gk20a_clk_fini() local
607 gk20a_pllg_disable(clk); gk20a_clk_fini()
613 struct gk20a_clk *clk = gk20a_clk(base); gk20a_clk_init() local
614 struct nvkm_subdev *subdev = &clk->base.subdev; gk20a_clk_init()
620 ret = gk20a_clk_prog(&clk->base); gk20a_clk_init()
650 struct gk20a_clk *clk; gk20a_clk_new() local
653 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) gk20a_clk_new()
655 *pclk = &clk->base; gk20a_clk_new()
663 clk->params = &gk20a_pllg_params; gk20a_clk_new()
664 clk->parent_rate = clk_get_rate(tdev->clk); gk20a_clk_new()
666 ret = nvkm_clk_ctor(&gk20a_clk, device, index, true, &clk->base); gk20a_clk_new()
667 nvkm_info(&clk->base.subdev, "parent clock rate: %d Mhz\n", gk20a_clk_new()
668 clk->parent_rate / MHZ); gk20a_clk_new()
|
| H A D | gt215.c | 43 read_vco(struct gt215_clk *clk, int idx) read_vco() argument
45 struct nvkm_device *device = clk->base.subdev.device; read_vco()
52 return read_pll(clk, 0x41, 0x00e820); read_vco()
54 return read_pll(clk, 0x42, 0x00e8a0); read_vco()
61 read_clk(struct gt215_clk *clk, int idx, bool ignore_en) read_clk() argument
63 struct nvkm_device *device = clk->base.subdev.device; read_clk()
99 sclk = read_vco(clk, idx); read_clk()
108 read_pll(struct gt215_clk *clk, int idx, u32 pll) read_pll() argument
110 struct nvkm_device *device = clk->base.subdev.device; read_pll()
127 sclk = read_clk(clk, 0x00 + idx, false); read_pll()
130 sclk = read_clk(clk, 0x10 + idx, false); read_pll()
142 struct gt215_clk *clk = gt215_clk(base); gt215_clk_read() local
143 struct nvkm_subdev *subdev = &clk->base.subdev; gt215_clk_read()
152 return read_pll(clk, 0x00, 0x4200); gt215_clk_read()
154 return read_pll(clk, 0x01, 0x4220); gt215_clk_read()
156 return read_pll(clk, 0x02, 0x4000); gt215_clk_read()
158 return read_clk(clk, 0x20, false); gt215_clk_read()
160 return read_clk(clk, 0x21, false); gt215_clk_read()
162 return read_clk(clk, 0x25, false); gt215_clk_read()
167 return read_clk(clk, 0x1d, false); gt215_clk_read()
187 struct gt215_clk *clk = gt215_clk(base); gt215_clk_info() local
191 info->clk = 0; gt215_clk_info()
195 info->clk = 0x00000100; gt215_clk_info()
198 info->clk = 0x00002100; gt215_clk_info()
201 info->clk = 0x00002140; gt215_clk_info()
204 sclk = read_vco(clk, idx); gt215_clk_info()
221 info->clk = (((sdiv - 2) << 16) | 0x00003100); gt215_clk_info()
235 struct gt215_clk *clk = gt215_clk(base); gt215_pll_info() local
236 struct nvkm_subdev *subdev = &clk->base.subdev; gt215_pll_info()
245 ret = gt215_clk_info(&clk->base, idx, khz, info); gt215_pll_info()
256 ret = gt215_clk_info(&clk->base, idx - 0x10, limits.refclk, info); gt215_pll_info()
271 calc_clk(struct gt215_clk *clk, struct nvkm_cstate *cstate, calc_clk() argument
274 int ret = gt215_pll_info(&clk->base, idx, pll, cstate->domain[dom], calc_clk()
275 &clk->eng[dom]); calc_clk()
282 calc_host(struct gt215_clk *clk, struct nvkm_cstate *cstate) calc_host() argument
286 struct gt215_clk_info *info = &clk->eng[nv_clk_src_host]; calc_host()
289 info->clk = 0; calc_host()
296 ret = gt215_clk_info(&clk->base, 0x1d, kHz, info); calc_host()
304 gt215_clk_pre(struct nvkm_clk *clk, unsigned long *flags) gt215_clk_pre() argument
306 struct nvkm_device *device = clk->subdev.device; gt215_clk_pre()
339 gt215_clk_post(struct nvkm_clk *clk, unsigned long *flags) gt215_clk_post() argument
341 struct nvkm_device *device = clk->subdev.device; gt215_clk_post()
352 disable_clk_src(struct gt215_clk *clk, u32 src) disable_clk_src() argument
354 struct nvkm_device *device = clk->base.subdev.device; disable_clk_src()
360 prog_pll(struct gt215_clk *clk, int idx, u32 pll, int dom) prog_pll() argument
362 struct gt215_clk_info *info = &clk->eng[dom]; prog_pll()
363 struct nvkm_device *device = clk->base.subdev.device; prog_pll()
379 nvkm_mask(device, src0, 0x003f3141, 0x00000101 | info->clk); prog_pll()
393 disable_clk_src(clk, src1); prog_pll()
395 nvkm_mask(device, src1, 0x003f3141, 0x00000101 | info->clk); prog_pll()
399 disable_clk_src(clk, src0); prog_pll()
404 prog_clk(struct gt215_clk *clk, int idx, int dom) prog_clk() argument
406 struct gt215_clk_info *info = &clk->eng[dom]; prog_clk()
407 struct nvkm_device *device = clk->base.subdev.device; prog_clk()
408 nvkm_mask(device, 0x004120 + (idx * 4), 0x003f3141, 0x00000101 | info->clk); prog_clk()
412 prog_host(struct gt215_clk *clk) prog_host() argument
414 struct gt215_clk_info *info = &clk->eng[nv_clk_src_host]; prog_host()
415 struct nvkm_device *device = clk->base.subdev.device; prog_host()
422 disable_clk_src(clk, 0x4194); prog_host()
426 prog_clk(clk, 0x1d, nv_clk_src_host); prog_host()
440 prog_core(struct gt215_clk *clk, int dom) prog_core() argument
442 struct gt215_clk_info *info = &clk->eng[dom]; prog_core()
443 struct nvkm_device *device = clk->base.subdev.device; prog_core()
449 prog_pll(clk, 0x00, 0x004200, dom); prog_core()
458 struct gt215_clk *clk = gt215_clk(base); gt215_clk_calc() local
459 struct gt215_clk_info *core = &clk->eng[nv_clk_src_core]; gt215_clk_calc()
462 if ((ret = calc_clk(clk, cstate, 0x10, 0x4200, nv_clk_src_core)) || gt215_clk_calc()
463 (ret = calc_clk(clk, cstate, 0x11, 0x4220, nv_clk_src_shader)) || gt215_clk_calc()
464 (ret = calc_clk(clk, cstate, 0x20, 0x0000, nv_clk_src_disp)) || gt215_clk_calc()
465 (ret = calc_clk(clk, cstate, 0x21, 0x0000, nv_clk_src_vdec)) || gt215_clk_calc()
466 (ret = calc_host(clk, cstate))) gt215_clk_calc()
472 ret = gt215_clk_info(&clk->base, 0x10, gt215_clk_calc()
474 &clk->eng[nv_clk_src_core_intm]); gt215_clk_calc()
485 struct gt215_clk *clk = gt215_clk(base); gt215_clk_prog() local
486 struct gt215_clk_info *core = &clk->eng[nv_clk_src_core]; gt215_clk_prog()
491 ret = gt215_clk_pre(&clk->base, f); gt215_clk_prog()
496 prog_core(clk, nv_clk_src_core_intm); gt215_clk_prog()
498 prog_core(clk, nv_clk_src_core); gt215_clk_prog()
499 prog_pll(clk, 0x01, 0x004220, nv_clk_src_shader); gt215_clk_prog()
500 prog_clk(clk, 0x20, nv_clk_src_disp); gt215_clk_prog()
501 prog_clk(clk, 0x21, nv_clk_src_vdec); gt215_clk_prog()
502 prog_host(clk); gt215_clk_prog()
508 gt215_clk_post(&clk->base, f); gt215_clk_prog()
539 struct gt215_clk *clk; gt215_clk_new() local
541 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) gt215_clk_new()
543 *pclk = &clk->base; gt215_clk_new()
545 return nvkm_clk_ctor(>215_clk, device, index, true, &clk->base); gt215_clk_new()
|
| H A D | gk104.c | 50 read_vco(struct gk104_clk *clk, u32 dsrc) read_vco() argument
52 struct nvkm_device *device = clk->base.subdev.device; read_vco()
55 return read_pll(clk, 0x00e800); read_vco()
56 return read_pll(clk, 0x00e820); read_vco()
60 read_pll(struct gk104_clk *clk, u32 pll) read_pll() argument
62 struct nvkm_device *device = clk->base.subdev.device; read_pll()
81 sclk = read_pll(clk, 0x132020); read_pll()
85 sclk = read_div(clk, 0, 0x137320, 0x137330); read_pll()
92 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); read_pll()
106 read_div(struct gk104_clk *clk, int doff, u32 dsrc, u32 dctl) read_div() argument
108 struct nvkm_device *device = clk->base.subdev.device; read_div()
121 u32 sclk = read_vco(clk, dsrc + (doff * 4)); read_div()
126 return read_vco(clk, dsrc + (doff * 4)); read_div()
133 read_mem(struct gk104_clk *clk) read_mem() argument
135 struct nvkm_device *device = clk->base.subdev.device; read_mem()
137 case 1: return read_pll(clk, 0x132020); read_mem()
138 case 2: return read_pll(clk, 0x132000); read_mem()
145 read_clk(struct gk104_clk *clk, int idx) read_clk() argument
147 struct nvkm_device *device = clk->base.subdev.device; read_clk()
154 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); read_clk()
157 sclk = read_div(clk, idx, 0x137160, 0x1371d0); read_clk()
163 sclk = read_div(clk, idx, 0x137160, 0x1371d0); read_clk()
166 sclk = read_pll(clk, 0x1370e0); read_clk()
172 sclk = read_div(clk, idx, 0x137160, 0x1371d0); read_clk()
191 struct gk104_clk *clk = gk104_clk(base); gk104_clk_read() local
192 struct nvkm_subdev *subdev = &clk->base.subdev; gk104_clk_read()
201 return read_mem(clk); gk104_clk_read()
203 return read_clk(clk, 0x00); gk104_clk_read()
205 return read_clk(clk, 0x01); gk104_clk_read()
207 return read_clk(clk, 0x02); gk104_clk_read()
209 return read_clk(clk, 0x07); gk104_clk_read()
211 return read_clk(clk, 0x08); gk104_clk_read()
213 return read_clk(clk, 0x0c); gk104_clk_read()
215 return read_clk(clk, 0x0e); gk104_clk_read()
223 calc_div(struct gk104_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) calc_div() argument
234 calc_src(struct gk104_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) calc_src() argument
256 sclk = read_vco(clk, 0x137160 + (idx * 4)); calc_src()
258 sclk = calc_div(clk, idx, sclk, freq, ddiv); calc_src()
263 calc_pll(struct gk104_clk *clk, int idx, u32 freq, u32 *coef) calc_pll() argument
265 struct nvkm_subdev *subdev = &clk->base.subdev; calc_pll()
274 limits.refclk = read_div(clk, idx, 0x137120, 0x137140); calc_pll()
287 calc_clk(struct gk104_clk *clk, calc_clk() argument
290 struct gk104_clk_info *info = &clk->eng[idx]; calc_clk()
300 clk0 = calc_src(clk, idx, freq, &src0, &div0); calc_clk()
301 clk0 = calc_div(clk, idx, clk0, freq, &div1D); calc_clk()
306 clk1 = calc_pll(clk, idx, freq, &info->coef); calc_clk()
309 clk1 = calc_div(clk, idx, clk1, freq, &div1P); calc_clk()
341 struct gk104_clk *clk = gk104_clk(base); gk104_clk_calc() local
344 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || gk104_clk_calc()
345 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || gk104_clk_calc()
346 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || gk104_clk_calc()
347 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || gk104_clk_calc()
348 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || gk104_clk_calc()
349 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || gk104_clk_calc()
350 (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) gk104_clk_calc()
357 gk104_clk_prog_0(struct gk104_clk *clk, int idx) gk104_clk_prog_0() argument
359 struct gk104_clk_info *info = &clk->eng[idx]; gk104_clk_prog_0()
360 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_0()
368 gk104_clk_prog_1_0(struct gk104_clk *clk, int idx) gk104_clk_prog_1_0() argument
370 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_1_0()
379 gk104_clk_prog_1_1(struct gk104_clk *clk, int idx) gk104_clk_prog_1_1() argument
381 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_1_1()
386 gk104_clk_prog_2(struct gk104_clk *clk, int idx) gk104_clk_prog_2() argument
388 struct gk104_clk_info *info = &clk->eng[idx]; gk104_clk_prog_2()
389 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_2()
405 gk104_clk_prog_3(struct gk104_clk *clk, int idx) gk104_clk_prog_3() argument
407 struct gk104_clk_info *info = &clk->eng[idx]; gk104_clk_prog_3()
408 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_3()
416 gk104_clk_prog_4_0(struct gk104_clk *clk, int idx) gk104_clk_prog_4_0() argument
418 struct gk104_clk_info *info = &clk->eng[idx]; gk104_clk_prog_4_0()
419 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_4_0()
431 gk104_clk_prog_4_1(struct gk104_clk *clk, int idx) gk104_clk_prog_4_1() argument
433 struct gk104_clk_info *info = &clk->eng[idx]; gk104_clk_prog_4_1()
434 struct nvkm_device *device = clk->base.subdev.device; gk104_clk_prog_4_1()
444 struct gk104_clk *clk = gk104_clk(base); gk104_clk_prog() local
460 for (j = 0; j < ARRAY_SIZE(clk->eng); j++) { gk104_clk_prog()
463 if (!clk->eng[j].freq) gk104_clk_prog()
465 stage[i].exec(clk, j); gk104_clk_prog()
475 struct gk104_clk *clk = gk104_clk(base); gk104_clk_tidy() local
476 memset(clk->eng, 0x00, sizeof(clk->eng)); gk104_clk_tidy()
503 struct gk104_clk *clk; gk104_clk_new() local
505 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) gk104_clk_new()
507 *pclk = &clk->base; gk104_clk_new()
509 return nvkm_clk_ctor(&gk104_clk, device, index, true, &clk->base); gk104_clk_new()
|
| H A D | gf100.c | 49 read_vco(struct gf100_clk *clk, u32 dsrc) read_vco() argument
51 struct nvkm_device *device = clk->base.subdev.device; read_vco()
54 return nvkm_clk_read(&clk->base, nv_clk_src_sppll0); read_vco()
55 return nvkm_clk_read(&clk->base, nv_clk_src_sppll1); read_vco()
59 read_pll(struct gf100_clk *clk, u32 pll) read_pll() argument
61 struct nvkm_device *device = clk->base.subdev.device; read_pll()
79 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrc); read_pll()
82 sclk = nvkm_clk_read(&clk->base, nv_clk_src_mpllsrcref); read_pll()
88 sclk = read_div(clk, (pll & 0xff) / 0x20, 0x137120, 0x137140); read_pll()
98 read_div(struct gf100_clk *clk, int doff, u32 dsrc, u32 dctl) read_div() argument
100 struct nvkm_device *device = clk->base.subdev.device; read_div()
113 u32 sclk = read_vco(clk, dsrc + (doff * 4)); read_div()
118 return read_vco(clk, dsrc + (doff * 4)); read_div()
125 read_clk(struct gf100_clk *clk, int idx) read_clk() argument
127 struct nvkm_device *device = clk->base.subdev.device; read_clk()
134 sclk = read_pll(clk, 0x137000 + (idx * 0x20)); read_clk()
136 sclk = read_pll(clk, 0x1370e0); read_clk()
139 sclk = read_div(clk, idx, 0x137160, 0x1371d0); read_clk()
152 struct gf100_clk *clk = gf100_clk(base); gf100_clk_read() local
153 struct nvkm_subdev *subdev = &clk->base.subdev; gf100_clk_read()
162 return read_pll(clk, 0x00e800); gf100_clk_read()
164 return read_pll(clk, 0x00e820); gf100_clk_read()
167 return read_div(clk, 0, 0x137320, 0x137330); gf100_clk_read()
169 return read_pll(clk, 0x132020); gf100_clk_read()
171 return read_pll(clk, 0x132000); gf100_clk_read()
173 return read_div(clk, 0, 0x137300, 0x137310); gf100_clk_read()
176 return nvkm_clk_read(&clk->base, nv_clk_src_mpll); gf100_clk_read()
177 return nvkm_clk_read(&clk->base, nv_clk_src_mdiv); gf100_clk_read()
180 return read_clk(clk, 0x00); gf100_clk_read()
182 return read_clk(clk, 0x01); gf100_clk_read()
184 return read_clk(clk, 0x02); gf100_clk_read()
186 return read_clk(clk, 0x07); gf100_clk_read()
188 return read_clk(clk, 0x08); gf100_clk_read()
190 return read_clk(clk, 0x09); gf100_clk_read()
192 return read_clk(clk, 0x0c); gf100_clk_read()
194 return read_clk(clk, 0x0e); gf100_clk_read()
202 calc_div(struct gf100_clk *clk, int idx, u32 ref, u32 freq, u32 *ddiv) calc_div() argument
213 calc_src(struct gf100_clk *clk, int idx, u32 freq, u32 *dsrc, u32 *ddiv) calc_src() argument
235 sclk = read_vco(clk, 0x137160 + (idx * 4)); calc_src()
237 sclk = calc_div(clk, idx, sclk, freq, ddiv); calc_src()
242 calc_pll(struct gf100_clk *clk, int idx, u32 freq, u32 *coef) calc_pll() argument
244 struct nvkm_subdev *subdev = &clk->base.subdev; calc_pll()
253 limits.refclk = read_div(clk, idx, 0x137120, 0x137140); calc_pll()
266 calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom) calc_clk() argument
268 struct gf100_clk_info *info = &clk->eng[idx]; calc_clk()
278 clk0 = calc_src(clk, idx, freq, &src0, &div0); calc_clk()
279 clk0 = calc_div(clk, idx, clk0, freq, &div1D); calc_clk()
284 clk1 = calc_pll(clk, idx, freq, &info->coef); calc_clk()
287 clk1 = calc_div(clk, idx, clk1, freq, &div1P); calc_clk()
319 struct gf100_clk *clk = gf100_clk(base); gf100_clk_calc() local
322 if ((ret = calc_clk(clk, cstate, 0x00, nv_clk_src_gpc)) || gf100_clk_calc()
323 (ret = calc_clk(clk, cstate, 0x01, nv_clk_src_rop)) || gf100_clk_calc()
324 (ret = calc_clk(clk, cstate, 0x02, nv_clk_src_hubk07)) || gf100_clk_calc()
325 (ret = calc_clk(clk, cstate, 0x07, nv_clk_src_hubk06)) || gf100_clk_calc()
326 (ret = calc_clk(clk, cstate, 0x08, nv_clk_src_hubk01)) || gf100_clk_calc()
327 (ret = calc_clk(clk, cstate, 0x09, nv_clk_src_copy)) || gf100_clk_calc()
328 (ret = calc_clk(clk, cstate, 0x0c, nv_clk_src_daemon)) || gf100_clk_calc()
329 (ret = calc_clk(clk, cstate, 0x0e, nv_clk_src_vdec))) gf100_clk_calc()
336 gf100_clk_prog_0(struct gf100_clk *clk, int idx) gf100_clk_prog_0() argument
338 struct gf100_clk_info *info = &clk->eng[idx]; gf100_clk_prog_0()
339 struct nvkm_device *device = clk->base.subdev.device; gf100_clk_prog_0()
347 gf100_clk_prog_1(struct gf100_clk *clk, int idx) gf100_clk_prog_1() argument
349 struct nvkm_device *device = clk->base.subdev.device; gf100_clk_prog_1()
358 gf100_clk_prog_2(struct gf100_clk *clk, int idx) gf100_clk_prog_2() argument
360 struct gf100_clk_info *info = &clk->eng[idx]; gf100_clk_prog_2()
361 struct nvkm_device *device = clk->base.subdev.device; gf100_clk_prog_2()
379 gf100_clk_prog_3(struct gf100_clk *clk, int idx) gf100_clk_prog_3() argument
381 struct gf100_clk_info *info = &clk->eng[idx]; gf100_clk_prog_3()
382 struct nvkm_device *device = clk->base.subdev.device; gf100_clk_prog_3()
394 gf100_clk_prog_4(struct gf100_clk *clk, int idx) gf100_clk_prog_4() argument
396 struct gf100_clk_info *info = &clk->eng[idx]; gf100_clk_prog_4()
397 struct nvkm_device *device = clk->base.subdev.device; gf100_clk_prog_4()
404 struct gf100_clk *clk = gf100_clk(base); gf100_clk_prog() local
417 for (j = 0; j < ARRAY_SIZE(clk->eng); j++) { gf100_clk_prog()
418 if (!clk->eng[j].freq) gf100_clk_prog()
420 stage[i].exec(clk, j); gf100_clk_prog()
430 struct gf100_clk *clk = gf100_clk(base); gf100_clk_tidy() local
431 memset(clk->eng, 0x00, sizeof(clk->eng)); gf100_clk_tidy()
459 struct gf100_clk *clk; gf100_clk_new() local
461 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) gf100_clk_new()
463 *pclk = &clk->base; gf100_clk_new()
465 return nvkm_clk_ctor(&gf100_clk, device, index, false, &clk->base); gf100_clk_new()
|
| H A D | nv50.c | 32 read_div(struct nv50_clk *clk) read_div() argument
34 struct nvkm_device *device = clk->base.subdev.device; read_div()
52 read_pll_src(struct nv50_clk *clk, u32 base) read_pll_src() argument
54 struct nvkm_subdev *subdev = &clk->base.subdev; read_pll_src()
56 u32 coef, ref = nvkm_clk_read(&clk->base, nv_clk_src_crystal); read_pll_src()
103 case 1: return nvkm_clk_read(&clk->base, nv_clk_src_crystal); read_pll_src()
104 case 2: return nvkm_clk_read(&clk->base, nv_clk_src_href); read_pll_src()
125 read_pll_ref(struct nv50_clk *clk, u32 base) read_pll_ref() argument
127 struct nvkm_subdev *subdev = &clk->base.subdev; read_pll_ref()
145 return nvkm_clk_read(&clk->base, nv_clk_src_crystal); read_pll_ref()
152 return nvkm_clk_read(&clk->base, nv_clk_src_href); read_pll_ref()
154 return read_pll_src(clk, base); read_pll_ref()
158 read_pll(struct nv50_clk *clk, u32 base) read_pll() argument
160 struct nvkm_device *device = clk->base.subdev.device; read_pll()
164 u32 ref = read_pll_ref(clk, base); read_pll()
171 return nvkm_clk_read(&clk->base, nv_clk_src_dom6); read_pll()
194 struct nv50_clk *clk = nv50_clk(base); nv50_clk_read() local
195 struct nvkm_subdev *subdev = &clk->base.subdev; nv50_clk_read()
206 return div_u64((u64)nvkm_clk_read(&clk->base, nv_clk_src_href) * 27778, 10000); nv50_clk_read()
208 return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; nv50_clk_read()
210 return nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3 / 2; nv50_clk_read()
213 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nv50_clk_read()
216 case 0x30000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); nv50_clk_read()
223 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
224 case 0x00000001: return nvkm_clk_read(&clk->base, nv_clk_src_dom6); nv50_clk_read()
225 case 0x00000002: return read_pll(clk, 0x004020) >> P; nv50_clk_read()
226 case 0x00000003: return read_pll(clk, 0x004028) >> P; nv50_clk_read()
234 return nvkm_clk_read(&clk->base, nv_clk_src_host) >> P; nv50_clk_read()
235 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
237 case 0x00000020: return read_pll(clk, 0x004028) >> P; nv50_clk_read()
238 case 0x00000030: return read_pll(clk, 0x004020) >> P; nv50_clk_read()
246 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
249 return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P; nv50_clk_read()
252 return read_pll(clk, 0x004008) >> P; nv50_clk_read()
256 P = (read_div(clk) & 0x00000700) >> 8; nv50_clk_read()
267 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nv50_clk_read()
268 return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P; nv50_clk_read()
273 return read_pll(clk, 0x004028) >> P; nv50_clk_read()
274 return read_pll(clk, 0x004030) >> P; nv50_clk_read()
276 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nv50_clk_read()
282 return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P; nv50_clk_read()
286 return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2) >> P; nv50_clk_read()
288 return nvkm_clk_read(&clk->base, nv_clk_src_mem) >> P; nv50_clk_read()
297 return read_pll(clk, 0x00e810) >> 2; nv50_clk_read()
304 P = (read_div(clk) & 0x00000007) >> 0; nv50_clk_read()
306 case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href); nv50_clk_read()
308 case 0x08000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclk); nv50_clk_read()
310 return nvkm_clk_read(&clk->base, nv_clk_src_hclkm3) >> P; nv50_clk_read()
325 calc_pll(struct nv50_clk *clk, u32 reg, u32 idx, int *N, int *M, int *P) calc_pll() argument
327 struct nvkm_subdev *subdev = &clk->base.subdev; calc_pll()
336 pll.refclk = read_pll_ref(clk, reg); calc_pll()
370 struct nv50_clk *clk = nv50_clk(base); nv50_clk_calc() local
371 struct nv50_clk_hwsq *hwsq = &clk->hwsq; nv50_clk_calc()
372 struct nvkm_subdev *subdev = &clk->base.subdev; nv50_clk_calc()
403 out = read_pll(clk, 0x004030); nv50_clk_calc()
405 out = nvkm_clk_read(&clk->base, nv_clk_src_hclkm3d2); nv50_clk_calc()
426 if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_href))) { nv50_clk_calc()
429 if (clk_same(dom6, nvkm_clk_read(&clk->base, nv_clk_src_hclk))) { nv50_clk_calc()
432 freq = nvkm_clk_read(&clk->base, nv_clk_src_hclk) * 3; nv50_clk_calc()
459 freq = calc_pll(clk, 0x4028, core, &N, &M, &P1); nv50_clk_calc()
477 freq = calc_pll(clk, 0x4020, shader, &N, &M, &P1); nv50_clk_calc()
497 struct nv50_clk *clk = nv50_clk(base); nv50_clk_prog() local
498 return clk_exec(&clk->hwsq, true); nv50_clk_prog()
504 struct nv50_clk *clk = nv50_clk(base); nv50_clk_tidy() local
505 clk_exec(&clk->hwsq, false); nv50_clk_tidy()
512 struct nv50_clk *clk; nv50_clk_new_() local
515 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) nv50_clk_new_()
517 ret = nvkm_clk_ctor(func, device, index, allow_reclock, &clk->base); nv50_clk_new_()
518 *pclk = &clk->base; nv50_clk_new_()
522 clk->hwsq.r_fifo = hwsq_reg(0x002504); nv50_clk_new_()
523 clk->hwsq.r_spll[0] = hwsq_reg(0x004020); nv50_clk_new_()
524 clk->hwsq.r_spll[1] = hwsq_reg(0x004024); nv50_clk_new_()
525 clk->hwsq.r_nvpll[0] = hwsq_reg(0x004028); nv50_clk_new_()
526 clk->hwsq.r_nvpll[1] = hwsq_reg(0x00402c); nv50_clk_new_()
531 clk->hwsq.r_divs = hwsq_reg(0x004800); nv50_clk_new_()
534 clk->hwsq.r_divs = hwsq_reg(0x004700); nv50_clk_new_()
537 clk->hwsq.r_mast = hwsq_reg(0x00c040); nv50_clk_new_()
|
| H A D | nv40.c | 40 read_pll_1(struct nv40_clk *clk, u32 reg) read_pll_1() argument
42 struct nvkm_device *device = clk->base.subdev.device; read_pll_1()
56 read_pll_2(struct nv40_clk *clk, u32 reg) read_pll_2() argument
58 struct nvkm_device *device = clk->base.subdev.device; read_pll_2()
82 read_clk(struct nv40_clk *clk, u32 src) read_clk() argument
86 return read_pll_2(clk, 0x004000); read_clk()
88 return read_pll_1(clk, 0x004008); read_clk()
99 struct nv40_clk *clk = nv40_clk(base); nv40_clk_read() local
100 struct nvkm_subdev *subdev = &clk->base.subdev; nv40_clk_read()
110 return read_clk(clk, (mast & 0x00000003) >> 0); nv40_clk_read()
112 return read_clk(clk, (mast & 0x00000030) >> 4); nv40_clk_read()
114 return read_pll_2(clk, 0x4020); nv40_clk_read()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, nv40_clk_calc_pll() argument
127 struct nvkm_subdev *subdev = &clk->base.subdev; nv40_clk_calc_pll()
148 struct nv40_clk *clk = nv40_clk(base); nv40_clk_calc() local
155 ret = nv40_clk_calc_pll(clk, 0x004000, gclk, nv40_clk_calc()
161 clk->npll_ctrl = 0x80000100 | (log2P << 16); nv40_clk_calc()
162 clk->npll_coef = (N1 << 8) | M1; nv40_clk_calc()
164 clk->npll_ctrl = 0xc0000000 | (log2P << 16); nv40_clk_calc()
165 clk->npll_coef = (N2 << 24) | (M2 << 16) | (N1 << 8) | M1; nv40_clk_calc()
170 ret = nv40_clk_calc_pll(clk, 0x004008, sclk, nv40_clk_calc()
175 clk->spll = 0xc0000000 | (log2P << 16) | (N1 << 8) | M1; nv40_clk_calc()
176 clk->ctrl = 0x00000223; nv40_clk_calc()
178 clk->spll = 0x00000000; nv40_clk_calc()
179 clk->ctrl = 0x00000333; nv40_clk_calc()
188 struct nv40_clk *clk = nv40_clk(base); nv40_clk_prog() local
189 struct nvkm_device *device = clk->base.subdev.device; nv40_clk_prog()
191 nvkm_wr32(device, 0x004004, clk->npll_coef); nv40_clk_prog()
192 nvkm_mask(device, 0x004000, 0xc0070100, clk->npll_ctrl); nv40_clk_prog()
193 nvkm_mask(device, 0x004008, 0xc007ffff, clk->spll); nv40_clk_prog()
195 nvkm_mask(device, 0x00c040, 0x00000333, clk->ctrl); nv40_clk_prog()
223 struct nv40_clk *clk; nv40_clk_new() local
225 if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL))) nv40_clk_new()
227 clk->base.pll_calc = nv04_clk_pll_calc; nv40_clk_new()
228 clk->base.pll_prog = nv04_clk_pll_prog; nv40_clk_new()
229 *pclk = &clk->base; nv40_clk_new()
231 return nvkm_clk_ctor(&nv40_clk, device, index, true, &clk->base); nv40_clk_new()
|
| /linux-4.4.14/arch/arm/mach-davinci/include/mach/ |
| H A D | clock.h | 16 struct clk;
18 extern int clk_register(struct clk *clk);
19 extern void clk_unregister(struct clk *clk);
21 int davinci_clk_reset_assert(struct clk *c);
22 int davinci_clk_reset_deassert(struct clk *c);
|
| /linux-4.4.14/drivers/clk/ |
| H A D | clk-ls1x.c | 11 #include <linux/clk-provider.h>
51 static struct clk *__init clk_register_pll(struct device *dev, clk_register_pll()
57 struct clk *clk; clk_register_pll() local
75 clk = clk_register(dev, hw); clk_register_pll()
77 if (IS_ERR(clk)) clk_register_pll()
80 return clk; clk_register_pll()
89 struct clk *clk; ls1x_clk_init() local
91 clk = clk_register_fixed_rate(NULL, "osc_33m_clk", NULL, CLK_IS_ROOT, ls1x_clk_init()
93 clk_register_clkdev(clk, "osc_33m_clk", NULL); ls1x_clk_init()
95 /* clock derived from 33 MHz OSC clk */ ls1x_clk_init()
96 clk = clk_register_pll(NULL, "pll_clk", "osc_33m_clk", 0); ls1x_clk_init()
97 clk_register_clkdev(clk, "pll_clk", NULL); ls1x_clk_init()
99 /* clock derived from PLL clk */ ls1x_clk_init()
106 clk = clk_register_divider(NULL, "cpu_clk_div", "pll_clk", ls1x_clk_init()
111 clk_register_clkdev(clk, "cpu_clk_div", NULL); ls1x_clk_init()
112 clk = clk_register_mux(NULL, "cpu_clk", cpu_parents, ls1x_clk_init()
116 clk_register_clkdev(clk, "cpu_clk", NULL); ls1x_clk_init()
124 clk = clk_register_divider(NULL, "dc_clk_div", "pll_clk", ls1x_clk_init()
127 clk_register_clkdev(clk, "dc_clk_div", NULL); ls1x_clk_init()
128 clk = clk_register_mux(NULL, "dc_clk", dc_parents, ls1x_clk_init()
132 clk_register_clkdev(clk, "dc_clk", NULL); ls1x_clk_init()
140 clk = clk_register_divider(NULL, "ahb_clk_div", "pll_clk", ls1x_clk_init()
144 clk_register_clkdev(clk, "ahb_clk_div", NULL); ls1x_clk_init()
145 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, ls1x_clk_init()
149 clk_register_clkdev(clk, "ahb_clk", NULL); ls1x_clk_init()
150 clk_register_clkdev(clk, "stmmaceth", NULL); ls1x_clk_init()
152 /* clock derived from AHB clk */ ls1x_clk_init()
153 /* APB clk is always half of the AHB clk */ ls1x_clk_init()
154 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, ls1x_clk_init()
156 clk_register_clkdev(clk, "apb_clk", NULL); ls1x_clk_init()
157 clk_register_clkdev(clk, "ls1x_i2c", NULL); ls1x_clk_init()
158 clk_register_clkdev(clk, "ls1x_pwmtimer", NULL); ls1x_clk_init()
159 clk_register_clkdev(clk, "ls1x_spi", NULL); ls1x_clk_init()
160 clk_register_clkdev(clk, "ls1x_wdt", NULL); ls1x_clk_init()
161 clk_register_clkdev(clk, "serial8250", NULL); ls1x_clk_init()
|
| H A D | clk-devres.c | 7 #include <linux/clk.h>
14 clk_put(*(struct clk **)res); devm_clk_release()
17 struct clk *devm_clk_get(struct device *dev, const char *id) devm_clk_get()
19 struct clk **ptr, *clk; devm_clk_get() local
25 clk = clk_get(dev, id); devm_clk_get()
26 if (!IS_ERR(clk)) { devm_clk_get()
27 *ptr = clk; devm_clk_get()
33 return clk; devm_clk_get()
39 struct clk **c = res; devm_clk_match()
47 void devm_clk_put(struct device *dev, struct clk *clk) devm_clk_put() argument
51 ret = devres_release(dev, devm_clk_release, devm_clk_match, clk); devm_clk_put()
|
| H A D | clk.h | 2 * linux/drivers/clk/clk.h
15 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec,
20 struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
22 void __clk_free_clk(struct clk *clk);
25 static inline struct clk * __clk_create_clk()
28 return (struct clk *)hw; __clk_create_clk()
30 static inline void __clk_free_clk(struct clk *clk) { } __clk_get_hw() argument
31 static struct clk_hw *__clk_get_hw(struct clk *clk) __clk_get_hw() argument
33 return (struct clk_hw *)clk; __clk_get_hw()
|
| H A D | clk-efm32gg.c | 10 #include <linux/clk-provider.h>
18 static struct clk *clk[37]; variable in typeref:struct:clk
20 .clks = clk,
21 .clk_num = ARRAY_SIZE(clk),
29 for (i = 0; i < ARRAY_SIZE(clk); ++i) efm32gg_cmu_init()
30 clk[i] = ERR_PTR(-ENOENT); efm32gg_cmu_init()
38 clk[clk_HFXO] = clk_register_fixed_rate(NULL, "HFXO", NULL, efm32gg_cmu_init()
41 clk[clk_HFPERCLKUSART0] = clk_register_gate(NULL, "HFPERCLK.USART0", efm32gg_cmu_init()
43 clk[clk_HFPERCLKUSART1] = clk_register_gate(NULL, "HFPERCLK.USART1", efm32gg_cmu_init()
45 clk[clk_HFPERCLKUSART2] = clk_register_gate(NULL, "HFPERCLK.USART2", efm32gg_cmu_init()
47 clk[clk_HFPERCLKUART0] = clk_register_gate(NULL, "HFPERCLK.UART0", efm32gg_cmu_init()
49 clk[clk_HFPERCLKUART1] = clk_register_gate(NULL, "HFPERCLK.UART1", efm32gg_cmu_init()
51 clk[clk_HFPERCLKTIMER0] = clk_register_gate(NULL, "HFPERCLK.TIMER0", efm32gg_cmu_init()
53 clk[clk_HFPERCLKTIMER1] = clk_register_gate(NULL, "HFPERCLK.TIMER1", efm32gg_cmu_init()
55 clk[clk_HFPERCLKTIMER2] = clk_register_gate(NULL, "HFPERCLK.TIMER2", efm32gg_cmu_init()
57 clk[clk_HFPERCLKTIMER3] = clk_register_gate(NULL, "HFPERCLK.TIMER3", efm32gg_cmu_init()
59 clk[clk_HFPERCLKACMP0] = clk_register_gate(NULL, "HFPERCLK.ACMP0", efm32gg_cmu_init()
61 clk[clk_HFPERCLKACMP1] = clk_register_gate(NULL, "HFPERCLK.ACMP1", efm32gg_cmu_init()
63 clk[clk_HFPERCLKI2C0] = clk_register_gate(NULL, "HFPERCLK.I2C0", efm32gg_cmu_init()
65 clk[clk_HFPERCLKI2C1] = clk_register_gate(NULL, "HFPERCLK.I2C1", efm32gg_cmu_init()
67 clk[clk_HFPERCLKGPIO] = clk_register_gate(NULL, "HFPERCLK.GPIO", efm32gg_cmu_init()
69 clk[clk_HFPERCLKVCMP] = clk_register_gate(NULL, "HFPERCLK.VCMP", efm32gg_cmu_init()
71 clk[clk_HFPERCLKPRS] = clk_register_gate(NULL, "HFPERCLK.PRS", efm32gg_cmu_init()
73 clk[clk_HFPERCLKADC0] = clk_register_gate(NULL, "HFPERCLK.ADC0", efm32gg_cmu_init()
75 clk[clk_HFPERCLKDAC0] = clk_register_gate(NULL, "HFPERCLK.DAC0", efm32gg_cmu_init()
|
| H A D | clk-conf.c | 10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/clk/clk-conf.h>
21 struct clk *clk, *pclk; __set_clk_parents() local
26 pr_err("clk: invalid value of clock-parents property at %s\n", __set_clk_parents()
43 pr_warn("clk: couldn't get parent clock %d for %s\n", __set_clk_parents()
56 clk = of_clk_get_from_provider(&clkspec); __set_clk_parents()
57 if (IS_ERR(clk)) { __set_clk_parents()
58 pr_warn("clk: couldn't get parent clock %d for %s\n", __set_clk_parents()
60 rc = PTR_ERR(clk); __set_clk_parents()
64 rc = clk_set_parent(clk, pclk); __set_clk_parents()
66 pr_err("clk: failed to reparent %s to %s: %d\n", __set_clk_parents()
67 __clk_get_name(clk), __clk_get_name(pclk), rc); __set_clk_parents()
68 clk_put(clk); __set_clk_parents()
83 struct clk *clk; __set_clk_rates() local
100 clk = of_clk_get_from_provider(&clkspec); __set_clk_rates()
101 if (IS_ERR(clk)) { __set_clk_rates()
102 pr_warn("clk: couldn't get clock %d for %s\n", __set_clk_rates()
104 return PTR_ERR(clk); __set_clk_rates()
107 rc = clk_set_rate(clk, rate); __set_clk_rates()
109 pr_err("clk: couldn't set %s clk rate to %d (%d), current rate: %ld\n", __set_clk_rates()
110 __clk_get_name(clk), rate, rc, __set_clk_rates()
111 clk_get_rate(clk)); __set_clk_rates()
112 clk_put(clk); __set_clk_rates()
|
| H A D | clkdev.c | 2 * drivers/clk/clkdev.c
10 * Helper for the clk API to assist looking up a struct clk.
20 #include <linux/clk.h>
22 #include <linux/clk-provider.h>
25 #include "clk.h"
31 static struct clk *__of_clk_get(struct device_node *np, int index, __of_clk_get()
35 struct clk *clk; __of_clk_get() local
46 clk = __of_clk_get_from_provider(&clkspec, dev_id, con_id); __of_clk_get()
49 return clk; __of_clk_get()
52 struct clk *of_clk_get(struct device_node *np, int index) of_clk_get()
58 static struct clk *__of_clk_get_by_name(struct device_node *np, __of_clk_get_by_name()
62 struct clk *clk = ERR_PTR(-ENOENT); __of_clk_get_by_name() local
75 clk = __of_clk_get(np, index, dev_id, name); __of_clk_get_by_name()
76 if (!IS_ERR(clk)) { __of_clk_get_by_name()
79 if (PTR_ERR(clk) != -EPROBE_DEFER) __of_clk_get_by_name()
82 return clk; __of_clk_get_by_name()
95 return clk; __of_clk_get_by_name()
104 * and uses them to look up the struct clk from the registered list of clock
107 struct clk *of_clk_get_by_name(struct device_node *np, const char *name) of_clk_get_by_name()
118 static struct clk *__of_clk_get_by_name(struct device_node *np, __of_clk_get_by_name()
127 * Find the correct struct clk for the device and connection ID.
169 struct clk *clk_get_sys(const char *dev_id, const char *con_id) clk_get_sys()
172 struct clk *clk = NULL; clk_get_sys() local
180 clk = __clk_create_clk(cl->clk_hw, dev_id, con_id); clk_get_sys()
181 if (IS_ERR(clk)) clk_get_sys()
184 if (!__clk_get(clk)) { clk_get_sys()
185 __clk_free_clk(clk); clk_get_sys()
193 return cl ? clk : ERR_PTR(-ENOENT); clk_get_sys()
197 struct clk *clk_get(struct device *dev, const char *con_id) clk_get()
200 struct clk *clk; clk_get() local
203 clk = __of_clk_get_by_name(dev->of_node, dev_id, con_id); clk_get()
204 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) clk_get()
205 return clk; clk_get()
212 void clk_put(struct clk *clk) clk_put() argument
214 __clk_put(clk); clk_put()
228 cl->clk_hw = __clk_get_hw(cl->clk); clkdev_add()
237 cl->clk_hw = __clk_get_hw(cl->clk); clkdev_add_table()
291 clkdev_alloc(struct clk *clk, const char *con_id, const char *dev_fmt, ...) clkdev_alloc() argument
297 cl = vclkdev_alloc(__clk_get_hw(clk), con_id, dev_fmt, ap); clkdev_alloc()
306 * @clk: struct clk to associate with all clk_lookups
313 struct clk_lookup *clkdev_create(struct clk *clk, const char *con_id, clkdev_create() argument
320 cl = vclkdev_create(__clk_get_hw(clk), con_id, dev_fmt, ap); clkdev_create()
330 struct clk *r = clk_get(dev, con_id); clk_add_alias()
357 * clk_register_clkdev - register one clock lookup for a struct clk
358 * @clk: struct clk to associate with all clk_lookups
370 int clk_register_clkdev(struct clk *clk, const char *con_id, clk_register_clkdev() argument
376 if (IS_ERR(clk)) clk_register_clkdev()
377 return PTR_ERR(clk); clk_register_clkdev()
380 cl = vclkdev_create(__clk_get_hw(clk), con_id, dev_fmt, ap); clk_register_clkdev()
388 * clk_register_clkdevs - register a set of clk_lookup for a struct clk
389 * @clk: struct clk to associate with all clk_lookups
398 int clk_register_clkdevs(struct clk *clk, struct clk_lookup *cl, size_t num) clk_register_clkdevs() argument
402 if (IS_ERR(clk)) clk_register_clkdevs()
403 return PTR_ERR(clk); clk_register_clkdevs()
406 cl->clk_hw = __clk_get_hw(clk); clk_register_clkdevs()
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| H A D | clk-nspire.c | 11 #include <linux/clk-provider.h>
45 static void nspire_clkinfo_cx(u32 val, struct nspire_clk_info *clk) nspire_clkinfo_cx() argument
48 clk->base_clock = 48 * MHZ; nspire_clkinfo_cx()
50 clk->base_clock = 6 * EXTRACT(val, CX_BASE) * MHZ; nspire_clkinfo_cx()
52 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * EXTRACT(val, CX_UNKNOWN); nspire_clkinfo_cx()
53 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); nspire_clkinfo_cx()
56 static void nspire_clkinfo_classic(u32 val, struct nspire_clk_info *clk) nspire_clkinfo_classic() argument
59 clk->base_clock = 27 * MHZ; nspire_clkinfo_classic()
61 clk->base_clock = (300 - 6 * EXTRACT(val, CLASSIC_BASE)) * MHZ; nspire_clkinfo_classic()
63 clk->base_cpu_ratio = EXTRACT(val, BASE_CPU) * 2; nspire_clkinfo_classic()
64 clk->base_ahb_ratio = clk->base_cpu_ratio * (EXTRACT(val, CPU_AHB) + 1); nspire_clkinfo_classic()
72 struct clk *clk; nspire_ahbdiv_setup() local
88 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, nspire_ahbdiv_setup()
90 if (!IS_ERR(clk)) nspire_ahbdiv_setup()
91 of_clk_add_provider(node, of_clk_src_simple_get, clk); nspire_ahbdiv_setup()
114 struct clk *clk; nspire_clk_setup() local
128 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, nspire_clk_setup()
130 if (!IS_ERR(clk)) nspire_clk_setup()
131 of_clk_add_provider(node, of_clk_src_simple_get, clk); nspire_clk_setup()
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| H A D | clk-moxart.c | 13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
22 struct clk *clk, *ref_clk; moxart_of_pll_clk_init() local
45 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1); moxart_of_pll_clk_init()
46 if (IS_ERR(clk)) { moxart_of_pll_clk_init()
51 clk_register_clkdev(clk, NULL, name); moxart_of_pll_clk_init()
52 of_clk_add_provider(node, of_clk_src_simple_get, clk); moxart_of_pll_clk_init()
60 struct clk *clk, *pll_clk; moxart_of_apb_clk_init() local
88 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div); moxart_of_apb_clk_init()
89 if (IS_ERR(clk)) { moxart_of_apb_clk_init()
94 clk_register_clkdev(clk, NULL, name); moxart_of_apb_clk_init()
95 of_clk_add_provider(node, of_clk_src_simple_get, clk); moxart_of_apb_clk_init()
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| H A D | clk-scpi.c | 19 #include <linux/clk-provider.h>
35 #define to_scpi_clk(clk) container_of(clk, struct scpi_clk, hw)
42 struct scpi_clk *clk = to_scpi_clk(hw); scpi_clk_recalc_rate() local
44 return clk->scpi_ops->clk_get_val(clk->id); scpi_clk_recalc_rate()
62 struct scpi_clk *clk = to_scpi_clk(hw); scpi_clk_set_rate() local
64 return clk->scpi_ops->clk_set_val(clk->id, rate); scpi_clk_set_rate()
74 static int __scpi_dvfs_round_rate(struct scpi_clk *clk, unsigned long rate) __scpi_dvfs_round_rate() argument
78 const struct scpi_opp *opp = clk->info->opps; __scpi_dvfs_round_rate()
80 for (idx = 0; idx < clk->info->count; idx++, opp++) { __scpi_dvfs_round_rate()
96 struct scpi_clk *clk = to_scpi_clk(hw); scpi_dvfs_recalc_rate() local
97 int idx = clk->scpi_ops->dvfs_get_idx(clk->id); scpi_dvfs_recalc_rate()
103 opp = clk->info->opps + idx; scpi_dvfs_recalc_rate()
110 struct scpi_clk *clk = to_scpi_clk(hw); scpi_dvfs_round_rate() local
112 return __scpi_dvfs_round_rate(clk, rate); scpi_dvfs_round_rate()
115 static int __scpi_find_dvfs_index(struct scpi_clk *clk, unsigned long rate) __scpi_find_dvfs_index() argument
117 int idx, max_opp = clk->info->count; __scpi_find_dvfs_index()
118 const struct scpi_opp *opp = clk->info->opps; __scpi_find_dvfs_index()
129 struct scpi_clk *clk = to_scpi_clk(hw); scpi_dvfs_set_rate() local
130 int ret = __scpi_find_dvfs_index(clk, rate); scpi_dvfs_set_rate()
134 return clk->scpi_ops->dvfs_set_idx(clk->id, (u8)ret); scpi_dvfs_set_rate()
149 static struct clk * scpi_clk_ops_init()
154 struct clk *clk; scpi_clk_ops_init() local
175 clk = devm_clk_register(dev, &sclk->hw); scpi_clk_ops_init()
176 if (!IS_ERR(clk) && max) scpi_clk_ops_init()
178 return clk; scpi_clk_ops_init()
182 struct scpi_clk **clk; member in struct:scpi_clk_data
186 static struct clk * scpi_of_clk_src_get()
194 sclk = clk_data->clk[count]; scpi_of_clk_src_get()
196 return sclk->hw.clk; scpi_of_clk_src_get()
205 struct clk **clks; scpi_clk_add()
220 clk_data->clk = devm_kcalloc(dev, count, sizeof(*clk_data->clk), scpi_clk_add()
222 if (!clk_data->clk) scpi_clk_add()
257 clk_data->clk[idx] = sclk; scpi_clk_add()
|
| H A D | clk.c | 9 * Standard functionality for the common clock API. See Documentation/clk.txt
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/clk/clk-conf.h>
27 #include "clk.h"
79 #include <trace/events/clk.h>
81 struct clk { struct
249 pr_warn("clk: Not disabling unused clocks\n"); clk_disable_unused()
275 const char *__clk_get_name(const struct clk *clk) __clk_get_name() argument
277 return !clk ? NULL : clk->core->name; __clk_get_name()
287 struct clk_hw *__clk_get_hw(struct clk *clk) __clk_get_hw() argument
289 return !clk ? NULL : clk->core->hw; __clk_get_hw()
331 /* search the 'proper' clk tree first */ clk_core_lookup()
373 unsigned int __clk_get_enable_count(struct clk *clk) __clk_get_enable_count() argument
375 return !clk ? 0 : clk->core->enable_count; __clk_get_enable_count()
413 unsigned long __clk_get_flags(struct clk *clk) __clk_get_flags() argument
415 return !clk ? 0 : clk->core->flags; __clk_get_flags()
435 bool __clk_is_enabled(struct clk *clk) __clk_is_enabled() argument
437 if (!clk) __clk_is_enabled()
440 return clk_core_is_enabled(clk->core); __clk_is_enabled()
516 struct clk *__clk_lookup(const char *name) __clk_lookup()
520 return !core ? NULL : core->hw->clk; __clk_lookup()
527 struct clk *clk_user; clk_core_get_boundaries()
566 /*** clk api ***/
594 * @clk: the clk being unprepared
597 * simple case, clk_unprepare can be used instead of clk_disable to gate a clk
598 * if the operation may sleep. One example is a clk which is accessed over
599 * I2c. In the complex case a clk gate operation may require a fast and a slow
603 void clk_unprepare(struct clk *clk) clk_unprepare() argument
605 if (IS_ERR_OR_NULL(clk)) clk_unprepare()
609 clk_core_unprepare(clk->core); clk_unprepare()
648 * @clk: the clk being prepared
651 * case, clk_prepare can be used instead of clk_enable to ungate a clk if the
652 * operation may sleep. One example is a clk which is accessed over I2c. In
653 * the complex case a clk ungate operation may require a fast and a slow part.
658 int clk_prepare(struct clk *clk) clk_prepare() argument
662 if (!clk) clk_prepare()
666 ret = clk_core_prepare(clk->core); clk_prepare()
698 * @clk: the clk being gated
702 * clk if the operation is fast and will never sleep. One example is a
703 * SoC-internal clk which is controlled via simple register writes. In the
704 * complex case a clk gate operation may require a fast and a slow part. It is
708 void clk_disable(struct clk *clk) clk_disable() argument
712 if (IS_ERR_OR_NULL(clk)) clk_disable()
716 clk_core_disable(clk->core); clk_disable()
758 * @clk: the clk being ungated
761 * simple case, clk_enable can be used instead of clk_prepare to ungate a clk
762 * if the operation will never sleep. One example is a SoC-internal clk which
763 * is controlled via simple register writes. In the complex case a clk ungate
769 int clk_enable(struct clk *clk) clk_enable() argument
774 if (!clk) clk_enable()
778 ret = clk_core_enable(clk->core); clk_enable()
860 * clk_round_rate - round the given rate for a clk
861 * @clk: the clk for which we are rounding a rate
864 * Takes in a rate as input and rounds it to a rate that the clk can actually
865 * use which is then returned. If clk doesn't support round_rate operation
868 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
873 if (!clk) clk_round_rate()
878 clk_core_get_boundaries(clk->core, &req.min_rate, &req.max_rate); clk_round_rate()
881 ret = clk_core_round_rate_nolock(clk->core, &req); clk_round_rate()
892 * __clk_notify - call clk notifier chain
893 * @core: clk that is changing rate
894 * @msg: clk notifier type (see include/linux/clk.h)
895 * @old_rate: old clk rate
896 * @new_rate: new clk rate
898 * Triggers a notifier call chain on the clk rate-change notification
899 * for 'clk'. Passes a pointer to the struct clk and the previous
916 if (cn->clk->core == core) { __clk_notify()
917 cnd.clk = cn->clk; __clk_notify()
928 * @core: first clk in the subtree
930 * Walks the subtree of clks starting with clk and recalculates accuracies as
931 * it goes. Note that if a clk does not implement the .recalc_accuracy
970 * clk_get_accuracy - return the accuracy of clk
971 * @clk: the clk whose accuracy is being returned
973 * Simply returns the cached accuracy of the clk, unless
976 * If clk is NULL then returns 0.
978 long clk_get_accuracy(struct clk *clk) clk_get_accuracy() argument
980 if (!clk) clk_get_accuracy()
983 return clk_core_get_accuracy(clk->core); clk_get_accuracy()
997 * @core: first clk in the subtree
998 * @msg: notification type (see include/linux/clk.h)
1000 * Walks the subtree of clks starting with clk and recalculates rates as it
1001 * goes. Note that if a clk does not implement the .recalc_rate callback then
1049 * clk_get_rate - return the rate of clk
1050 * @clk: the clk whose rate is being returned
1052 * Simply returns the cached rate of the clk, unless CLK_GET_RATE_NOCACHE flag
1054 * If clk is NULL then returns 0.
1056 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
1058 if (!clk) clk_get_rate()
1061 return clk_core_get_rate(clk->core); clk_get_rate()
1072 sizeof(struct clk *), GFP_KERNEL); clk_fetch_parent_index()
1168 /* update the clk tree topology */ __clk_set_parent_before()
1228 * @core: first clk in the subtree
1229 * @parent_rate: the "future" rate of clk's parent
1231 * Walks the subtree of clks starting with clk, speculating rates as it
1236 * subtree have subscribed to the notifications. Note that if a clk does not
1256 pr_debug("%s: clk notifier callback for clock %s aborted with error %d\n", __clk_speculate_rates()
1279 /* include clk in new parent's PRE_RATE_CHANGE notifications */ clk_calc_subtree()
1317 /* find the closest rate and parent clk/rate */ clk_calc_new_rates()
1371 pr_debug("%s: clk %s can not be parent of clk %s\n", clk_calc_new_rates()
1534 * clk_set_rate - specify a new rate for clk
1535 * @clk: the clk whose rate is being changed
1536 * @rate: the new rate for clk
1538 * In the simplest case clk_set_rate will only adjust the rate of clk.
1541 * propagate up to clk's parent; whether or not this happens depends on the
1542 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
1544 * *parent_rate comes back with a new rate for clk's parent then we propagate
1545 * up to clk's parent and set its rate. Upward propagation will continue
1546 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
1547 * .round_rate stops requesting changes to clk's parent_rate.
1554 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
1558 if (!clk) clk_set_rate()
1564 ret = clk_core_set_rate_nolock(clk->core, rate); clk_set_rate()
1574 * @clk: clock source
1580 int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max) clk_set_rate_range() argument
1584 if (!clk) clk_set_rate_range()
1588 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n", clk_set_rate_range()
1589 __func__, clk->core->name, clk->dev_id, clk->con_id, clk_set_rate_range()
1596 if (min != clk->min_rate || max != clk->max_rate) { clk_set_rate_range()
1597 clk->min_rate = min; clk_set_rate_range()
1598 clk->max_rate = max; clk_set_rate_range()
1599 ret = clk_core_set_rate_nolock(clk->core, clk->core->req_rate); clk_set_rate_range()
1610 * @clk: clock source
1615 int clk_set_min_rate(struct clk *clk, unsigned long rate) clk_set_min_rate() argument
1617 if (!clk) clk_set_min_rate()
1620 return clk_set_rate_range(clk, rate, clk->max_rate); clk_set_min_rate()
1626 * @clk: clock source
1631 int clk_set_max_rate(struct clk *clk, unsigned long rate) clk_set_max_rate() argument
1633 if (!clk) clk_set_max_rate()
1636 return clk_set_rate_range(clk, clk->min_rate, rate); clk_set_max_rate()
1641 * clk_get_parent - return the parent of a clk
1642 * @clk: the clk whose parent gets returned
1644 * Simply returns clk->parent. Returns NULL if clk is NULL.
1646 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
1648 struct clk *parent; clk_get_parent()
1650 if (!clk) clk_get_parent()
1654 /* TODO: Create a per-user clk and change callers to call clk_put */ clk_get_parent()
1655 parent = !clk->core->parent ? NULL : clk->core->parent->hw->clk; clk_get_parent()
1705 kcalloc(core->num_parents, sizeof(struct clk *), __clk_init_parent()
1732 * @clk: clock source
1738 * Returns true if @parent is a possible parent for @clk, false otherwise.
1740 bool clk_has_parent(struct clk *clk, struct clk *parent) clk_has_parent() argument
1746 if (!clk || !parent) clk_has_parent()
1749 core = clk->core; clk_has_parent()
1796 pr_debug("%s: clk %s can not be parent of clk %s\n", clk_core_set_parent()
1828 * clk_set_parent - switch the parent of a mux clk
1829 * @clk: the mux clk whose input we are switching
1830 * @parent: the new input to clk
1832 * Re-parent clk to use parent as its new input source. If clk is in
1833 * prepared state, the clk will get enabled for the duration of this call. If
1834 * that's not acceptable for a specific clk (Eg: the consumer can't handle
1836 * CLK_SET_PARENT_GATE flag to allow reparenting only when clk is unprepared.
1838 * After successfully changing clk's parent clk_set_parent will update the
1839 * clk topology, sysfs topology and propagate rate recalculation via
1844 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
1846 if (!clk) clk_set_parent()
1849 return clk_core_set_parent(clk->core, parent ? parent->core : NULL); clk_set_parent()
1855 * @clk: clock signal source
1873 int clk_set_phase(struct clk *clk, int degrees) clk_set_phase() argument
1877 if (!clk) clk_set_phase()
1887 trace_clk_set_phase(clk->core, degrees); clk_set_phase()
1889 if (clk->core->ops->set_phase) clk_set_phase()
1890 ret = clk->core->ops->set_phase(clk->core->hw, degrees); clk_set_phase()
1892 trace_clk_set_phase_complete(clk->core, degrees); clk_set_phase()
1895 clk->core->phase = degrees; clk_set_phase()
1916 * @clk: clock signal source
1921 int clk_get_phase(struct clk *clk) clk_get_phase() argument
1923 if (!clk) clk_get_phase()
1926 return clk_core_get_phase(clk->core); clk_get_phase()
1931 * clk_is_match - check if two clk's point to the same hardware clock
1932 * @p: clk compared against q
1933 * @q: clk compared against p
1935 * Returns true if the two struct clk pointers both point to the same hardware
1936 * clock node. Put differently, returns true if struct clk *p and struct clk *q
1941 bool clk_is_match(const struct clk *p, const struct clk *q) clk_is_match()
1943 /* trivial case: identical struct clk's or both NULL */ clk_is_match()
1947 /* true if clk->core pointers match. Avoid derefing garbage */ clk_is_match()
2173 * clk_debug_register - add a clk node to the debugfs clk directory
2174 * @core: the clk being added to the debugfs clk directory
2176 * Dynamically adds a clk to the debugfs clk directory if debugfs has been
2177 * initialized. Otherwise it bails out early since the debugfs clk directory
2198 * clk_debug_unregister - remove a clk node from the debugfs clk directory
2199 * @core: the clk being removed from the debugfs clk directory
2201 * Dynamically removes a clk and all its child nodes from the
2202 * debugfs clk directory if clk->dentry points to debugfs created by
2228 * clk_debug_init - lazily populate the debugfs clk directory
2232 * populates the debugfs clk directory once at boot-time when we know that
2241 rootdir = debugfs_create_dir("clk", NULL); clk_debug_init()
2288 * __clk_init - initialize the data structures in a struct clk
2289 * @dev: device initializing this clk, placeholder for now
2290 * @clk: clk being initialized
2295 static int __clk_init(struct device *dev, struct clk *clk_user) __clk_init()
2312 pr_debug("%s: clk %s already initialized\n", __clk_init()
2318 /* check that clk_ops are sane. See Documentation/clk.txt */ __clk_init()
2350 * Allocate an array of struct clk *'s to avoid unnecessary string __clk_init()
2351 * look-ups of clk's possible parents. This can fail for clocks passed __clk_init()
2360 core->parents = kcalloc(core->num_parents, sizeof(struct clk *), __clk_init()
2364 * clk_init'd; thus any access to clk->parents[] must check __clk_init()
2378 * parent has not yet been __clk_init'd then place clk in the orphan __clk_init()
2379 * list. If clk has set the CLK_IS_ROOT flag then place it in the root __clk_init()
2380 * clk list. __clk_init()
2382 * Every time a new clk is clk_init'd then we walk the list of orphan __clk_init()
2399 * Set clk's accuracy. The preferred method is to use __clk_init()
2414 * Set clk's phase. __clk_init()
2424 * Set clk's rate. The preferred method is to use .recalc_rate. For __clk_init()
2479 struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id, __clk_create_clk()
2482 struct clk *clk; __clk_create_clk() local
2486 return (struct clk *) hw; __clk_create_clk()
2488 clk = kzalloc(sizeof(*clk), GFP_KERNEL); __clk_create_clk()
2489 if (!clk) __clk_create_clk()
2492 clk->core = hw->core; __clk_create_clk()
2493 clk->dev_id = dev_id; __clk_create_clk()
2494 clk->con_id = con_id; __clk_create_clk()
2495 clk->max_rate = ULONG_MAX; __clk_create_clk()
2498 hlist_add_head(&clk->clks_node, &hw->core->clks); __clk_create_clk()
2501 return clk; __clk_create_clk()
2504 void __clk_free_clk(struct clk *clk) __clk_free_clk() argument
2507 hlist_del(&clk->clks_node); __clk_free_clk()
2510 kfree(clk); __clk_free_clk()
2519 * clock nodes. It returns a pointer to the newly allocated struct clk which
2524 struct clk *clk_register(struct device *dev, struct clk_hw *hw) clk_register()
2572 hw->clk = __clk_create_clk(hw, NULL, NULL); clk_register()
2573 if (IS_ERR(hw->clk)) { clk_register()
2574 ret = PTR_ERR(hw->clk); clk_register()
2578 ret = __clk_init(dev, hw->clk); clk_register()
2580 return hw->clk; clk_register()
2582 __clk_free_clk(hw->clk); clk_register()
2583 hw->clk = NULL; clk_register()
2618 * consumer calls clk_put() and the struct clk object is freed.
2652 * @clk: clock to unregister
2654 void clk_unregister(struct clk *clk) clk_unregister() argument
2658 if (!clk || WARN_ON_ONCE(IS_ERR(clk))) clk_unregister()
2661 clk_debug_unregister(clk->core); clk_unregister()
2665 if (clk->core->ops == &clk_nodrv_ops) { clk_unregister()
2667 clk->core->name); clk_unregister()
2675 clk->core->ops = &clk_nodrv_ops; clk_unregister()
2678 if (!hlist_empty(&clk->core->children)) { clk_unregister()
2683 hlist_for_each_entry_safe(child, t, &clk->core->children, clk_unregister()
2688 hlist_del_init(&clk->core->child_node); clk_unregister()
2690 if (clk->core->prepare_count) clk_unregister()
2692 __func__, clk->core->name); clk_unregister()
2693 kref_put(&clk->core->ref, __clk_release); clk_unregister()
2701 clk_unregister(*(struct clk **)res); devm_clk_release()
2713 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw) devm_clk_register()
2715 struct clk *clk; devm_clk_register() local
2716 struct clk **clkp; devm_clk_register()
2722 clk = clk_register(dev, hw); devm_clk_register()
2723 if (!IS_ERR(clk)) { devm_clk_register()
2724 *clkp = clk; devm_clk_register()
2730 return clk; devm_clk_register()
2736 struct clk *c = res; devm_clk_match()
2744 * @clk: clock to unregister
2750 void devm_clk_unregister(struct device *dev, struct clk *clk) devm_clk_unregister() argument
2752 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk)); devm_clk_unregister()
2759 int __clk_get(struct clk *clk) __clk_get() argument
2761 struct clk_core *core = !clk ? NULL : clk->core; __clk_get()
2772 void __clk_put(struct clk *clk) __clk_put() argument
2776 if (!clk || WARN_ON_ONCE(IS_ERR(clk))) __clk_put()
2781 hlist_del(&clk->clks_node); __clk_put()
2782 if (clk->min_rate > clk->core->req_rate || __clk_put()
2783 clk->max_rate < clk->core->req_rate) __clk_put()
2784 clk_core_set_rate_nolock(clk->core, clk->core->req_rate); __clk_put()
2786 owner = clk->core->owner; __clk_put()
2787 kref_put(&clk->core->ref, __clk_release); __clk_put()
2793 kfree(clk); __clk_put()
2796 /*** clk rate change notifiers ***/
2799 * clk_notifier_register - add a clk rate change notifier
2800 * @clk: struct clk * to watch
2803 * Request notification when clk's rate changes. This uses an SRCU
2806 * re-enter into the clk framework by calling any top-level clk APIs;
2819 int clk_notifier_register(struct clk *clk, struct notifier_block *nb) clk_notifier_register() argument
2824 if (!clk || !nb) clk_notifier_register()
2829 /* search the list of notifiers for this clk */ clk_notifier_register()
2831 if (cn->clk == clk) clk_notifier_register()
2834 /* if clk wasn't in the notifier list, allocate new clk_notifier */ clk_notifier_register()
2835 if (cn->clk != clk) { clk_notifier_register()
2840 cn->clk = clk; clk_notifier_register()
2848 clk->core->notifier_count++; clk_notifier_register()
2858 * clk_notifier_unregister - remove a clk rate change notifier
2859 * @clk: struct clk *
2862 * Request no further notification for changes to 'clk' and frees memory
2868 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb) clk_notifier_unregister() argument
2873 if (!clk || !nb) clk_notifier_unregister()
2879 if (cn->clk == clk) clk_notifier_unregister()
2882 if (cn->clk == clk) { clk_notifier_unregister()
2885 clk->core->notifier_count--; clk_notifier_unregister()
2909 * @get: Get clock callback. Returns NULL or a struct clk for the
2917 struct clk *(*get)(struct of_phandle_args *clkspec, void *data);
2927 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, of_clk_src_simple_get()
2934 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data) of_clk_src_onecell_get()
2955 struct clk *(*clk_src_get)(struct of_phandle_args *clkspec, of_clk_add_provider()
3004 struct clk *__of_clk_get_from_provider(struct of_phandle_args *clkspec, __of_clk_get_from_provider()
3008 struct clk *clk = ERR_PTR(-EPROBE_DEFER); __of_clk_get_from_provider() local
3017 clk = provider->get(clkspec, provider->data); __of_clk_get_from_provider()
3018 if (!IS_ERR(clk)) { __of_clk_get_from_provider()
3019 clk = __clk_create_clk(__clk_get_hw(clk), dev_id, __of_clk_get_from_provider()
3022 if (!IS_ERR(clk) && !__clk_get(clk)) { __of_clk_get_from_provider()
3023 __clk_free_clk(clk); __of_clk_get_from_provider()
3024 clk = ERR_PTR(-ENOENT); __of_clk_get_from_provider()
3032 return clk; __of_clk_get_from_provider()
3039 * This function looks up a struct clk from the registered list of clock
3043 struct clk *of_clk_get_from_provider(struct of_phandle_args *clkspec) of_clk_get_from_provider()
3063 struct clk *clk; of_clk_get_parent_name() local
3096 clk = of_clk_get_from_provider(&clkspec);
3097 if (IS_ERR(clk)) {
3103 clk_name = __clk_get_name(clk);
3104 clk_put(clk);
3151 struct clk *clk = of_clk_get(np, i); parent_ready() local
3154 if (!IS_ERR(clk)) { parent_ready()
3155 clk_put(clk); parent_ready()
3161 if (PTR_ERR(clk) == -EPROBE_DEFER) parent_ready()
|
| H A D | clk-gpio.c | 15 #include <linux/clk-provider.h>
38 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_gate_enable() local
40 gpiod_set_value(clk->gpiod, 1); clk_gpio_gate_enable()
47 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_gate_disable() local
49 gpiod_set_value(clk->gpiod, 0); clk_gpio_gate_disable()
54 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_gate_is_enabled() local
56 return gpiod_get_value(clk->gpiod); clk_gpio_gate_is_enabled()
76 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_mux_get_parent() local
78 return gpiod_get_value(clk->gpiod); clk_gpio_mux_get_parent()
83 struct clk_gpio *clk = to_clk_gpio(hw); clk_gpio_mux_set_parent() local
85 gpiod_set_value(clk->gpiod, index); clk_gpio_mux_set_parent()
97 static struct clk *clk_register_gpio(struct device *dev, const char *name, clk_register_gpio()
103 struct clk *clk; clk_register_gpio() local
145 clk = devm_clk_register(dev, &clk_gpio->hw); clk_register_gpio()
147 clk = clk_register(NULL, &clk_gpio->hw); clk_register_gpio()
149 if (!IS_ERR(clk)) clk_register_gpio()
150 return clk; clk_register_gpio()
157 return clk; clk_register_gpio()
169 struct clk *clk_register_gpio_gate(struct device *dev, const char *name, clk_register_gpio_gate()
190 struct clk *clk_register_gpio_mux(struct device *dev, const char *name, clk_register_gpio_mux()
216 struct clk *clk; member in struct:clk_gpio_delayed_register_data
217 struct clk *(*clk_register_get)(const char *name,
222 static struct clk *of_clk_gpio_delayed_register_get( of_clk_gpio_delayed_register_get()
226 struct clk *clk; of_clk_gpio_delayed_register_get() local
232 if (data->clk) { of_clk_gpio_delayed_register_get()
234 return data->clk; of_clk_gpio_delayed_register_get()
251 clk = data->clk_register_get(data->node->name, data->parent_names, of_clk_gpio_delayed_register_get()
253 if (IS_ERR(clk)) of_clk_gpio_delayed_register_get()
256 data->clk = clk; of_clk_gpio_delayed_register_get()
260 return clk; of_clk_gpio_delayed_register_get()
263 static struct clk *of_clk_gpio_gate_delayed_register_get(const char *name, of_clk_gpio_gate_delayed_register_get()
271 static struct clk *of_clk_gpio_mux_delayed_register_get(const char *name, of_clk_gpio_mux_delayed_register_get()
281 struct clk *(*clk_register_get)(const char *name, of_gpio_clk_setup()
|
| /linux-4.4.14/drivers/clk/spear/ |
| H A D | spear6xx_clock.c | 15 #include "clk.h"
118 struct clk *clk, *clk1; spear6xx_clk_init() local
120 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear6xx_clk_init()
124 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, CLK_IS_ROOT, spear6xx_clk_init()
126 clk_register_clkdev(clk, "osc_30m_clk", NULL); spear6xx_clk_init()
128 /* clock derived from 32 KHz osc clk */ spear6xx_clk_init()
129 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, spear6xx_clk_init()
131 clk_register_clkdev(clk, NULL, "rtc-spear"); spear6xx_clk_init()
133 /* clock derived from 30 MHz osc clk */ spear6xx_clk_init()
134 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, spear6xx_clk_init()
136 clk_register_clkdev(clk, "pll3_clk", NULL); spear6xx_clk_init()
138 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", spear6xx_clk_init()
141 clk_register_clkdev(clk, "vco1_clk", NULL); spear6xx_clk_init()
144 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk", spear6xx_clk_init()
147 clk_register_clkdev(clk, "vco2_clk", NULL); spear6xx_clk_init()
150 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1, spear6xx_clk_init()
152 clk_register_clkdev(clk, NULL, "wdt"); spear6xx_clk_init()
154 /* clock derived from pll1 clk */ spear6xx_clk_init()
155 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", spear6xx_clk_init()
157 clk_register_clkdev(clk, "cpu_clk", NULL); spear6xx_clk_init()
159 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", spear6xx_clk_init()
162 clk_register_clkdev(clk, "ahb_clk", NULL); spear6xx_clk_init()
164 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, spear6xx_clk_init()
167 clk_register_clkdev(clk, "uart_syn_clk", NULL); spear6xx_clk_init()
170 clk = clk_register_mux(NULL, "uart_mclk", uart_parents, spear6xx_clk_init()
174 clk_register_clkdev(clk, "uart_mclk", NULL); spear6xx_clk_init()
176 clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
178 clk_register_clkdev(clk, NULL, "d0000000.serial"); spear6xx_clk_init()
180 clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
182 clk_register_clkdev(clk, NULL, "d0080000.serial"); spear6xx_clk_init()
184 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", spear6xx_clk_init()
187 clk_register_clkdev(clk, "firda_syn_clk", NULL); spear6xx_clk_init()
190 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, spear6xx_clk_init()
194 clk_register_clkdev(clk, "firda_mclk", NULL); spear6xx_clk_init()
196 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, spear6xx_clk_init()
198 clk_register_clkdev(clk, NULL, "firda"); spear6xx_clk_init()
200 clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk", spear6xx_clk_init()
203 clk_register_clkdev(clk, "clcd_syn_clk", NULL); spear6xx_clk_init()
206 clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents, spear6xx_clk_init()
210 clk_register_clkdev(clk, "clcd_mclk", NULL); spear6xx_clk_init()
212 clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0, spear6xx_clk_init()
214 clk_register_clkdev(clk, NULL, "clcd"); spear6xx_clk_init()
217 clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, spear6xx_clk_init()
219 clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL); spear6xx_clk_init()
221 clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents, spear6xx_clk_init()
224 clk_register_clkdev(clk, NULL, "gpt0"); spear6xx_clk_init()
226 clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents, spear6xx_clk_init()
229 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear6xx_clk_init()
231 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, spear6xx_clk_init()
233 clk_register_clkdev(clk, NULL, "gpt1"); spear6xx_clk_init()
235 clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, spear6xx_clk_init()
237 clk_register_clkdev(clk, "gpt2_syn_clk", NULL); spear6xx_clk_init()
239 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, spear6xx_clk_init()
242 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear6xx_clk_init()
244 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, spear6xx_clk_init()
246 clk_register_clkdev(clk, NULL, "gpt2"); spear6xx_clk_init()
248 clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, spear6xx_clk_init()
250 clk_register_clkdev(clk, "gpt3_syn_clk", NULL); spear6xx_clk_init()
252 clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents, spear6xx_clk_init()
255 clk_register_clkdev(clk, "gpt3_mclk", NULL); spear6xx_clk_init()
257 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, spear6xx_clk_init()
259 clk_register_clkdev(clk, NULL, "gpt3"); spear6xx_clk_init()
261 /* clock derived from pll3 clk */ spear6xx_clk_init()
262 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, spear6xx_clk_init()
264 clk_register_clkdev(clk, NULL, "e1800000.ehci"); spear6xx_clk_init()
265 clk_register_clkdev(clk, NULL, "e1900000.ohci"); spear6xx_clk_init()
267 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, spear6xx_clk_init()
269 clk_register_clkdev(clk, NULL, "e2000000.ehci"); spear6xx_clk_init()
270 clk_register_clkdev(clk, NULL, "e2100000.ohci"); spear6xx_clk_init()
272 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
274 clk_register_clkdev(clk, NULL, "designware_udc"); spear6xx_clk_init()
276 /* clock derived from ahb clk */ spear6xx_clk_init()
277 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, spear6xx_clk_init()
279 clk_register_clkdev(clk, "ahbmult2_clk", NULL); spear6xx_clk_init()
281 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, spear6xx_clk_init()
284 clk_register_clkdev(clk, "ddr_clk", NULL); spear6xx_clk_init()
286 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", spear6xx_clk_init()
289 clk_register_clkdev(clk, "apb_clk", NULL); spear6xx_clk_init()
291 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
293 clk_register_clkdev(clk, NULL, "fc400000.dma"); spear6xx_clk_init()
295 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
297 clk_register_clkdev(clk, NULL, "d1800000.flash"); spear6xx_clk_init()
299 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
301 clk_register_clkdev(clk, NULL, "e0800000.ethernet"); spear6xx_clk_init()
303 clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
305 clk_register_clkdev(clk, NULL, "d0200000.i2c"); spear6xx_clk_init()
307 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
309 clk_register_clkdev(clk, NULL, "jpeg"); spear6xx_clk_init()
311 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
313 clk_register_clkdev(clk, NULL, "fc000000.flash"); spear6xx_clk_init()
315 /* clock derived from apb clk */ spear6xx_clk_init()
316 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
318 clk_register_clkdev(clk, NULL, "adc"); spear6xx_clk_init()
320 clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1); spear6xx_clk_init()
321 clk_register_clkdev(clk, NULL, "f0100000.gpio"); spear6xx_clk_init()
323 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
325 clk_register_clkdev(clk, NULL, "fc980000.gpio"); spear6xx_clk_init()
327 clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
329 clk_register_clkdev(clk, NULL, "d8100000.gpio"); spear6xx_clk_init()
331 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
333 clk_register_clkdev(clk, NULL, "ssp-pl022.0"); spear6xx_clk_init()
335 clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
337 clk_register_clkdev(clk, NULL, "ssp-pl022.1"); spear6xx_clk_init()
339 clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear6xx_clk_init()
341 clk_register_clkdev(clk, NULL, "ssp-pl022.2"); spear6xx_clk_init()
|
| H A D | spear3xx_clock.c | 12 #include <linux/clk.h>
18 #include "clk.h"
143 struct clk *clk; spear300_clk_init() local
145 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, spear300_clk_init()
147 clk_register_clkdev(clk, NULL, "60000000.clcd"); spear300_clk_init()
149 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, spear300_clk_init()
151 clk_register_clkdev(clk, NULL, "94000000.flash"); spear300_clk_init()
153 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, spear300_clk_init()
155 clk_register_clkdev(clk, NULL, "70000000.sdhci"); spear300_clk_init()
157 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, spear300_clk_init()
159 clk_register_clkdev(clk, NULL, "a9000000.gpio"); spear300_clk_init()
161 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, spear300_clk_init()
163 clk_register_clkdev(clk, NULL, "a0000000.kbd"); spear300_clk_init()
173 struct clk *clk; spear310_clk_init() local
175 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, spear310_clk_init()
177 clk_register_clkdev(clk, "emi", NULL); spear310_clk_init()
179 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, spear310_clk_init()
181 clk_register_clkdev(clk, NULL, "44000000.flash"); spear310_clk_init()
183 clk = clk_register_fixed_factor(NULL, "tdm_clk", "ras_ahb_clk", 0, 1, spear310_clk_init()
185 clk_register_clkdev(clk, NULL, "tdm"); spear310_clk_init()
187 clk = clk_register_fixed_factor(NULL, "uart1_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
189 clk_register_clkdev(clk, NULL, "b2000000.serial"); spear310_clk_init()
191 clk = clk_register_fixed_factor(NULL, "uart2_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
193 clk_register_clkdev(clk, NULL, "b2080000.serial"); spear310_clk_init()
195 clk = clk_register_fixed_factor(NULL, "uart3_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
197 clk_register_clkdev(clk, NULL, "b2100000.serial"); spear310_clk_init()
199 clk = clk_register_fixed_factor(NULL, "uart4_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
201 clk_register_clkdev(clk, NULL, "b2180000.serial"); spear310_clk_init()
203 clk = clk_register_fixed_factor(NULL, "uart5_clk", "ras_apb_clk", 0, 1, spear310_clk_init()
205 clk_register_clkdev(clk, NULL, "b2200000.serial"); spear310_clk_init()
249 struct clk *ras_apb_clk) spear320_clk_init()
251 struct clk *clk; spear320_clk_init() local
253 clk = clk_register_fixed_rate(NULL, "smii_125m_pad_clk", NULL, spear320_clk_init()
255 clk_register_clkdev(clk, "smii_125m_pad", NULL); spear320_clk_init()
257 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, spear320_clk_init()
259 clk_register_clkdev(clk, NULL, "90000000.clcd"); spear320_clk_init()
261 clk = clk_register_fixed_factor(NULL, "emi_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
263 clk_register_clkdev(clk, "emi", NULL); spear320_clk_init()
265 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
267 clk_register_clkdev(clk, NULL, "4c000000.flash"); spear320_clk_init()
269 clk = clk_register_fixed_factor(NULL, "i2c1_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
271 clk_register_clkdev(clk, NULL, "a7000000.i2c"); spear320_clk_init()
273 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
275 clk_register_clkdev(clk, NULL, "a8000000.pwm"); spear320_clk_init()
277 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
279 clk_register_clkdev(clk, NULL, "a5000000.spi"); spear320_clk_init()
281 clk = clk_register_fixed_factor(NULL, "ssp2_clk", "ras_ahb_clk", 0, 1, spear320_clk_init()
283 clk_register_clkdev(clk, NULL, "a6000000.spi"); spear320_clk_init()
285 clk = clk_register_fixed_factor(NULL, "can0_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
287 clk_register_clkdev(clk, NULL, "c_can_platform.0"); spear320_clk_init()
289 clk = clk_register_fixed_factor(NULL, "can1_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
291 clk_register_clkdev(clk, NULL, "c_can_platform.1"); spear320_clk_init()
293 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
295 clk_register_clkdev(clk, NULL, "a9400000.i2s"); spear320_clk_init()
297 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, spear320_clk_init()
302 clk_register_clkdev(clk, "i2s_ref_clk", NULL); spear320_clk_init()
304 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", spear320_clk_init()
307 clk_register_clkdev(clk, "i2s_sclk", NULL); spear320_clk_init()
309 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
311 clk_register_clkdev(clk, "hclk", "aa000000.eth"); spear320_clk_init()
313 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1, spear320_clk_init()
315 clk_register_clkdev(clk, "hclk", "ab000000.eth"); spear320_clk_init()
317 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, spear320_clk_init()
322 clk_register_clkdev(clk, NULL, "a9300000.serial"); spear320_clk_init()
324 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, spear320_clk_init()
329 clk_register_clkdev(clk, NULL, "70000000.sdhci"); spear320_clk_init()
331 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, spear320_clk_init()
335 clk_register_clkdev(clk, NULL, "smii_pclk"); spear320_clk_init()
337 clk = clk_register_fixed_factor(NULL, "smii_clk", "smii_pclk", 0, 1, 1); spear320_clk_init()
338 clk_register_clkdev(clk, NULL, "smii"); spear320_clk_init()
340 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, spear320_clk_init()
345 clk_register_clkdev(clk, NULL, "a3000000.serial"); spear320_clk_init()
347 clk_set_parent(clk, ras_apb_clk); spear320_clk_init()
349 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, spear320_clk_init()
354 clk_register_clkdev(clk, NULL, "a4000000.serial"); spear320_clk_init()
356 clk_set_parent(clk, ras_apb_clk); spear320_clk_init()
358 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, spear320_clk_init()
363 clk_register_clkdev(clk, NULL, "a9100000.serial"); spear320_clk_init()
365 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, spear320_clk_init()
370 clk_register_clkdev(clk, NULL, "a9200000.serial"); spear320_clk_init()
372 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, spear320_clk_init()
377 clk_register_clkdev(clk, NULL, "60000000.serial"); spear320_clk_init()
379 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, spear320_clk_init()
384 clk_register_clkdev(clk, NULL, "60100000.serial"); spear320_clk_init()
387 static inline void spear320_clk_init(void __iomem *sb, struct clk *rc) { } spear320_clk_init()
392 struct clk *clk, *clk1, *ras_apb_clk; spear3xx_clk_init() local
394 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear3xx_clk_init()
396 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear3xx_clk_init()
398 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, spear3xx_clk_init()
400 clk_register_clkdev(clk, "osc_24m_clk", NULL); spear3xx_clk_init()
402 /* clock derived from 32 KHz osc clk */ spear3xx_clk_init()
403 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, spear3xx_clk_init()
405 clk_register_clkdev(clk, NULL, "fc900000.rtc"); spear3xx_clk_init()
407 /* clock derived from 24 MHz osc clk */ spear3xx_clk_init()
408 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, spear3xx_clk_init()
410 clk_register_clkdev(clk, "pll3_clk", NULL); spear3xx_clk_init()
412 clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_24m_clk", 0, 1, spear3xx_clk_init()
414 clk_register_clkdev(clk, NULL, "fc880000.wdt"); spear3xx_clk_init()
416 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, spear3xx_clk_init()
419 clk_register_clkdev(clk, "vco1_clk", NULL); spear3xx_clk_init()
422 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, spear3xx_clk_init()
425 clk_register_clkdev(clk, "vco2_clk", NULL); spear3xx_clk_init()
428 /* clock derived from pll1 clk */ spear3xx_clk_init()
429 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", spear3xx_clk_init()
431 clk_register_clkdev(clk, "cpu_clk", NULL); spear3xx_clk_init()
433 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", spear3xx_clk_init()
436 clk_register_clkdev(clk, "ahb_clk", NULL); spear3xx_clk_init()
438 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0, spear3xx_clk_init()
441 clk_register_clkdev(clk, "uart_syn_clk", NULL); spear3xx_clk_init()
444 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, spear3xx_clk_init()
449 clk_register_clkdev(clk, "uart0_mclk", NULL); spear3xx_clk_init()
451 clk = clk_register_gate(NULL, "uart0", "uart0_mclk", spear3xx_clk_init()
454 clk_register_clkdev(clk, NULL, "d0000000.serial"); spear3xx_clk_init()
456 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, spear3xx_clk_init()
459 clk_register_clkdev(clk, "firda_syn_clk", NULL); spear3xx_clk_init()
462 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, spear3xx_clk_init()
467 clk_register_clkdev(clk, "firda_mclk", NULL); spear3xx_clk_init()
469 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", spear3xx_clk_init()
472 clk_register_clkdev(clk, NULL, "firda"); spear3xx_clk_init()
477 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, spear3xx_clk_init()
481 clk_register_clkdev(clk, NULL, "gpt0"); spear3xx_clk_init()
485 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, spear3xx_clk_init()
489 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear3xx_clk_init()
490 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", spear3xx_clk_init()
493 clk_register_clkdev(clk, NULL, "gpt1"); spear3xx_clk_init()
497 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, spear3xx_clk_init()
501 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear3xx_clk_init()
502 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", spear3xx_clk_init()
505 clk_register_clkdev(clk, NULL, "gpt2"); spear3xx_clk_init()
508 clk = clk_register_aux("gen0_syn_clk", "gen0_syn_gclk", "pll1_clk", spear3xx_clk_init()
511 clk_register_clkdev(clk, "gen0_syn_clk", NULL); spear3xx_clk_init()
514 clk = clk_register_aux("gen1_syn_clk", "gen1_syn_gclk", "pll1_clk", spear3xx_clk_init()
517 clk_register_clkdev(clk, "gen1_syn_clk", NULL); spear3xx_clk_init()
520 clk = clk_register_mux(NULL, "gen2_3_par_clk", gen2_3_parents, spear3xx_clk_init()
524 clk_register_clkdev(clk, "gen2_3_par_clk", NULL); spear3xx_clk_init()
526 clk = clk_register_aux("gen2_syn_clk", "gen2_syn_gclk", spear3xx_clk_init()
529 clk_register_clkdev(clk, "gen2_syn_clk", NULL); spear3xx_clk_init()
532 clk = clk_register_aux("gen3_syn_clk", "gen3_syn_gclk", spear3xx_clk_init()
535 clk_register_clkdev(clk, "gen3_syn_clk", NULL); spear3xx_clk_init()
538 /* clock derived from pll3 clk */ spear3xx_clk_init()
539 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
541 clk_register_clkdev(clk, NULL, "e1800000.ehci"); spear3xx_clk_init()
542 clk_register_clkdev(clk, NULL, "e1900000.ohci"); spear3xx_clk_init()
543 clk_register_clkdev(clk, NULL, "e2100000.ohci"); spear3xx_clk_init()
545 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, spear3xx_clk_init()
547 clk_register_clkdev(clk, "usbh.0_clk", NULL); spear3xx_clk_init()
549 clk = clk_register_fixed_factor(NULL, "usbh.1_clk", "usbh_clk", 0, 1, spear3xx_clk_init()
551 clk_register_clkdev(clk, "usbh.1_clk", NULL); spear3xx_clk_init()
553 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
555 clk_register_clkdev(clk, NULL, "e1100000.usbd"); spear3xx_clk_init()
557 /* clock derived from ahb clk */ spear3xx_clk_init()
558 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, spear3xx_clk_init()
560 clk_register_clkdev(clk, "ahbmult2_clk", NULL); spear3xx_clk_init()
562 clk = clk_register_mux(NULL, "ddr_clk", ddr_parents, spear3xx_clk_init()
565 clk_register_clkdev(clk, "ddr_clk", NULL); spear3xx_clk_init()
567 clk = clk_register_divider(NULL, "apb_clk", "ahb_clk", spear3xx_clk_init()
570 clk_register_clkdev(clk, "apb_clk", NULL); spear3xx_clk_init()
572 clk = clk_register_gate(NULL, "amem_clk", "ahb_clk", 0, AMEM_CLK_CFG, spear3xx_clk_init()
574 clk_register_clkdev(clk, "amem_clk", NULL); spear3xx_clk_init()
576 clk = clk_register_gate(NULL, "c3_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
578 clk_register_clkdev(clk, NULL, "c3_clk"); spear3xx_clk_init()
580 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
582 clk_register_clkdev(clk, NULL, "fc400000.dma"); spear3xx_clk_init()
584 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
586 clk_register_clkdev(clk, NULL, "e0800000.eth"); spear3xx_clk_init()
588 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
590 clk_register_clkdev(clk, NULL, "d0180000.i2c"); spear3xx_clk_init()
592 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
594 clk_register_clkdev(clk, NULL, "jpeg"); spear3xx_clk_init()
596 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
598 clk_register_clkdev(clk, NULL, "fc000000.flash"); spear3xx_clk_init()
600 /* clock derived from apb clk */ spear3xx_clk_init()
601 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
603 clk_register_clkdev(clk, NULL, "d0080000.adc"); spear3xx_clk_init()
605 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
607 clk_register_clkdev(clk, NULL, "fc980000.gpio"); spear3xx_clk_init()
609 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB, spear3xx_clk_init()
611 clk_register_clkdev(clk, NULL, "d0100000.spi"); spear3xx_clk_init()
613 /* RAS clk enable */ spear3xx_clk_init()
614 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, RAS_CLK_ENB, spear3xx_clk_init()
616 clk_register_clkdev(clk, "ras_ahb_clk", NULL); spear3xx_clk_init()
618 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, RAS_CLK_ENB, spear3xx_clk_init()
620 clk_register_clkdev(clk, "ras_apb_clk", NULL); spear3xx_clk_init()
621 ras_apb_clk = clk; spear3xx_clk_init()
623 clk = clk_register_gate(NULL, "ras_32k_clk", "osc_32k_clk", 0, spear3xx_clk_init()
625 clk_register_clkdev(clk, "ras_32k_clk", NULL); spear3xx_clk_init()
627 clk = clk_register_gate(NULL, "ras_24m_clk", "osc_24m_clk", 0, spear3xx_clk_init()
629 clk_register_clkdev(clk, "ras_24m_clk", NULL); spear3xx_clk_init()
631 clk = clk_register_gate(NULL, "ras_pll1_clk", "pll1_clk", 0, spear3xx_clk_init()
633 clk_register_clkdev(clk, "ras_pll1_clk", NULL); spear3xx_clk_init()
635 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, spear3xx_clk_init()
637 clk_register_clkdev(clk, "ras_pll2_clk", NULL); spear3xx_clk_init()
639 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, spear3xx_clk_init()
641 clk_register_clkdev(clk, "ras_pll3_clk", NULL); spear3xx_clk_init()
643 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", spear3xx_clk_init()
646 clk_register_clkdev(clk, "ras_syn0_gclk", NULL); spear3xx_clk_init()
648 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", spear3xx_clk_init()
651 clk_register_clkdev(clk, "ras_syn1_gclk", NULL); spear3xx_clk_init()
653 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", spear3xx_clk_init()
656 clk_register_clkdev(clk, "ras_syn2_gclk", NULL); spear3xx_clk_init()
658 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", spear3xx_clk_init()
661 clk_register_clkdev(clk, "ras_syn3_gclk", NULL); spear3xx_clk_init()
|
| H A D | spear1310_clock.c | 19 #include "clk.h"
265 /* For gmac phy input clk */
313 /* For parent clk = 49.152 MHz */
320 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
321 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
325 /* For parent clk = 49.152 MHz */
387 struct clk *clk, *clk1; spear1310_clk_init() local
389 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
391 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear1310_clk_init()
393 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
395 clk_register_clkdev(clk, "osc_24m_clk", NULL); spear1310_clk_init()
397 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
399 clk_register_clkdev(clk, "osc_25m_clk", NULL); spear1310_clk_init()
401 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
403 clk_register_clkdev(clk, "gmii_pad_clk", NULL); spear1310_clk_init()
405 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, spear1310_clk_init()
407 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); spear1310_clk_init()
409 /* clock derived from 32 KHz osc clk */ spear1310_clk_init()
410 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, spear1310_clk_init()
413 clk_register_clkdev(clk, NULL, "e0580000.rtc"); spear1310_clk_init()
415 /* clock derived from 24 or 25 MHz osc clk */ spear1310_clk_init()
417 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, spear1310_clk_init()
421 clk_register_clkdev(clk, "vco1_mclk", NULL); spear1310_clk_init()
422 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", spear1310_clk_init()
425 clk_register_clkdev(clk, "vco1_clk", NULL); spear1310_clk_init()
428 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, spear1310_clk_init()
432 clk_register_clkdev(clk, "vco2_mclk", NULL); spear1310_clk_init()
433 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", spear1310_clk_init()
436 clk_register_clkdev(clk, "vco2_clk", NULL); spear1310_clk_init()
439 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, spear1310_clk_init()
443 clk_register_clkdev(clk, "vco3_mclk", NULL); spear1310_clk_init()
444 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", spear1310_clk_init()
447 clk_register_clkdev(clk, "vco3_clk", NULL); spear1310_clk_init()
450 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", spear1310_clk_init()
453 clk_register_clkdev(clk, "vco4_clk", NULL); spear1310_clk_init()
456 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, spear1310_clk_init()
458 clk_register_clkdev(clk, "pll5_clk", NULL); spear1310_clk_init()
460 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, spear1310_clk_init()
462 clk_register_clkdev(clk, "pll6_clk", NULL); spear1310_clk_init()
465 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, spear1310_clk_init()
467 clk_register_clkdev(clk, "vco1div2_clk", NULL); spear1310_clk_init()
469 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, spear1310_clk_init()
471 clk_register_clkdev(clk, "vco1div4_clk", NULL); spear1310_clk_init()
473 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, spear1310_clk_init()
475 clk_register_clkdev(clk, "vco2div2_clk", NULL); spear1310_clk_init()
477 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, spear1310_clk_init()
479 clk_register_clkdev(clk, "vco3div2_clk", NULL); spear1310_clk_init()
484 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, spear1310_clk_init()
487 clk_register_clkdev(clk, NULL, "spear_thermal"); spear1310_clk_init()
489 /* clock derived from pll4 clk */ spear1310_clk_init()
490 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, spear1310_clk_init()
492 clk_register_clkdev(clk, "ddr_clk", NULL); spear1310_clk_init()
494 /* clock derived from pll1 clk */ spear1310_clk_init()
495 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", spear1310_clk_init()
497 clk_register_clkdev(clk, "cpu_clk", NULL); spear1310_clk_init()
499 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, spear1310_clk_init()
501 clk_register_clkdev(clk, NULL, "ec800620.wdt"); spear1310_clk_init()
503 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, spear1310_clk_init()
505 clk_register_clkdev(clk, NULL, "smp_twd"); spear1310_clk_init()
507 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, spear1310_clk_init()
509 clk_register_clkdev(clk, "ahb_clk", NULL); spear1310_clk_init()
511 clk = clk_register_fixed_factor(NULL, "apb_clk", "pll1_clk", 0, 1, spear1310_clk_init()
513 clk_register_clkdev(clk, "apb_clk", NULL); spear1310_clk_init()
516 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, spear1310_clk_init()
520 clk_register_clkdev(clk, "gpt0_mclk", NULL); spear1310_clk_init()
521 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, spear1310_clk_init()
524 clk_register_clkdev(clk, NULL, "gpt0"); spear1310_clk_init()
526 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, spear1310_clk_init()
530 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear1310_clk_init()
531 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, spear1310_clk_init()
534 clk_register_clkdev(clk, NULL, "gpt1"); spear1310_clk_init()
536 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, spear1310_clk_init()
540 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear1310_clk_init()
541 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, spear1310_clk_init()
544 clk_register_clkdev(clk, NULL, "gpt2"); spear1310_clk_init()
546 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, spear1310_clk_init()
550 clk_register_clkdev(clk, "gpt3_mclk", NULL); spear1310_clk_init()
551 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, spear1310_clk_init()
554 clk_register_clkdev(clk, NULL, "gpt3"); spear1310_clk_init()
557 clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "vco1div2_clk", spear1310_clk_init()
560 clk_register_clkdev(clk, "uart_syn_clk", NULL); spear1310_clk_init()
563 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, spear1310_clk_init()
568 clk_register_clkdev(clk, "uart0_mclk", NULL); spear1310_clk_init()
570 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", spear1310_clk_init()
573 clk_register_clkdev(clk, NULL, "e0000000.serial"); spear1310_clk_init()
575 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", spear1310_clk_init()
578 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); spear1310_clk_init()
581 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", spear1310_clk_init()
584 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); spear1310_clk_init()
586 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", spear1310_clk_init()
589 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); spear1310_clk_init()
592 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", spear1310_clk_init()
595 clk_register_clkdev(clk, NULL, "b2800000.cf"); spear1310_clk_init()
596 clk_register_clkdev(clk, NULL, "arasan_xd"); spear1310_clk_init()
598 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", spear1310_clk_init()
601 clk_register_clkdev(clk, "c3_syn_clk", NULL); spear1310_clk_init()
604 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, spear1310_clk_init()
609 clk_register_clkdev(clk, "c3_mclk", NULL); spear1310_clk_init()
611 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, spear1310_clk_init()
614 clk_register_clkdev(clk, NULL, "c3"); spear1310_clk_init()
617 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, spear1310_clk_init()
622 clk_register_clkdev(clk, "phy_input_mclk", NULL); spear1310_clk_init()
624 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", spear1310_clk_init()
627 clk_register_clkdev(clk, "phy_syn_clk", NULL); spear1310_clk_init()
630 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, spear1310_clk_init()
634 clk_register_clkdev(clk, "stmmacphy.0", NULL); spear1310_clk_init()
637 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, spear1310_clk_init()
642 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); spear1310_clk_init()
644 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, spear1310_clk_init()
647 clk_register_clkdev(clk, "clcd_syn_clk", NULL); spear1310_clk_init()
649 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, spear1310_clk_init()
654 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); spear1310_clk_init()
656 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, spear1310_clk_init()
659 clk_register_clkdev(clk, NULL, "e1000000.clcd"); spear1310_clk_init()
662 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, spear1310_clk_init()
666 clk_register_clkdev(clk, "i2s_src_mclk", NULL); spear1310_clk_init()
668 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, spear1310_clk_init()
671 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); spear1310_clk_init()
673 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, spear1310_clk_init()
678 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); spear1310_clk_init()
680 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, spear1310_clk_init()
683 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); spear1310_clk_init()
685 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", spear1310_clk_init()
689 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); spear1310_clk_init()
692 /* clock derived from ahb clk */ spear1310_clk_init()
693 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, spear1310_clk_init()
696 clk_register_clkdev(clk, NULL, "e0280000.i2c"); spear1310_clk_init()
698 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, spear1310_clk_init()
701 clk_register_clkdev(clk, NULL, "ea800000.dma"); spear1310_clk_init()
702 clk_register_clkdev(clk, NULL, "eb000000.dma"); spear1310_clk_init()
704 clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, spear1310_clk_init()
707 clk_register_clkdev(clk, NULL, "b2000000.jpeg"); spear1310_clk_init()
709 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, spear1310_clk_init()
712 clk_register_clkdev(clk, NULL, "e2000000.eth"); spear1310_clk_init()
714 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, spear1310_clk_init()
717 clk_register_clkdev(clk, NULL, "b0000000.flash"); spear1310_clk_init()
719 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, spear1310_clk_init()
722 clk_register_clkdev(clk, NULL, "ea000000.flash"); spear1310_clk_init()
724 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, spear1310_clk_init()
727 clk_register_clkdev(clk, NULL, "e4000000.ohci"); spear1310_clk_init()
728 clk_register_clkdev(clk, NULL, "e4800000.ehci"); spear1310_clk_init()
730 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, spear1310_clk_init()
733 clk_register_clkdev(clk, NULL, "e5000000.ohci"); spear1310_clk_init()
734 clk_register_clkdev(clk, NULL, "e5800000.ehci"); spear1310_clk_init()
736 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, spear1310_clk_init()
739 clk_register_clkdev(clk, NULL, "e3800000.otg"); spear1310_clk_init()
741 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, spear1310_clk_init()
744 clk_register_clkdev(clk, NULL, "b1000000.pcie"); spear1310_clk_init()
745 clk_register_clkdev(clk, NULL, "b1000000.ahci"); spear1310_clk_init()
747 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, spear1310_clk_init()
750 clk_register_clkdev(clk, NULL, "b1800000.pcie"); spear1310_clk_init()
751 clk_register_clkdev(clk, NULL, "b1800000.ahci"); spear1310_clk_init()
753 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, spear1310_clk_init()
756 clk_register_clkdev(clk, NULL, "b4000000.pcie"); spear1310_clk_init()
757 clk_register_clkdev(clk, NULL, "b4000000.ahci"); spear1310_clk_init()
759 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, spear1310_clk_init()
762 clk_register_clkdev(clk, "sysram0_clk", NULL); spear1310_clk_init()
764 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, spear1310_clk_init()
767 clk_register_clkdev(clk, "sysram1_clk", NULL); spear1310_clk_init()
769 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", spear1310_clk_init()
772 clk_register_clkdev(clk, "adc_syn_clk", NULL); spear1310_clk_init()
775 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", spear1310_clk_init()
778 clk_register_clkdev(clk, NULL, "e0080000.adc"); spear1310_clk_init()
780 /* clock derived from apb clk */ spear1310_clk_init()
781 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, spear1310_clk_init()
784 clk_register_clkdev(clk, NULL, "e0100000.spi"); spear1310_clk_init()
786 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, spear1310_clk_init()
789 clk_register_clkdev(clk, NULL, "e0600000.gpio"); spear1310_clk_init()
791 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, spear1310_clk_init()
794 clk_register_clkdev(clk, NULL, "e0680000.gpio"); spear1310_clk_init()
796 clk = clk_register_gate(NULL, "i2s0_clk", "apb_clk", 0, spear1310_clk_init()
799 clk_register_clkdev(clk, NULL, "e0180000.i2s"); spear1310_clk_init()
801 clk = clk_register_gate(NULL, "i2s1_clk", "apb_clk", 0, spear1310_clk_init()
804 clk_register_clkdev(clk, NULL, "e0200000.i2s"); spear1310_clk_init()
806 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, spear1310_clk_init()
809 clk_register_clkdev(clk, NULL, "e0300000.kbd"); spear1310_clk_init()
812 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, spear1310_clk_init()
817 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); spear1310_clk_init()
819 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, spear1310_clk_init()
824 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); spear1310_clk_init()
826 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, spear1310_clk_init()
829 clk_register_clkdev(clk, "gen_syn0_clk", NULL); spear1310_clk_init()
831 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, spear1310_clk_init()
834 clk_register_clkdev(clk, "gen_syn1_clk", NULL); spear1310_clk_init()
836 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, spear1310_clk_init()
839 clk_register_clkdev(clk, "gen_syn2_clk", NULL); spear1310_clk_init()
841 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, spear1310_clk_init()
844 clk_register_clkdev(clk, "gen_syn3_clk", NULL); spear1310_clk_init()
846 clk = clk_register_gate(NULL, "ras_osc_24m_clk", "osc_24m_clk", 0, spear1310_clk_init()
849 clk_register_clkdev(clk, "ras_osc_24m_clk", NULL); spear1310_clk_init()
851 clk = clk_register_gate(NULL, "ras_osc_25m_clk", "osc_25m_clk", 0, spear1310_clk_init()
854 clk_register_clkdev(clk, "ras_osc_25m_clk", NULL); spear1310_clk_init()
856 clk = clk_register_gate(NULL, "ras_osc_32k_clk", "osc_32k_clk", 0, spear1310_clk_init()
859 clk_register_clkdev(clk, "ras_osc_32k_clk", NULL); spear1310_clk_init()
861 clk = clk_register_gate(NULL, "ras_pll2_clk", "pll2_clk", 0, spear1310_clk_init()
864 clk_register_clkdev(clk, "ras_pll2_clk", NULL); spear1310_clk_init()
866 clk = clk_register_gate(NULL, "ras_pll3_clk", "pll3_clk", 0, spear1310_clk_init()
869 clk_register_clkdev(clk, "ras_pll3_clk", NULL); spear1310_clk_init()
871 clk = clk_register_gate(NULL, "ras_tx125_clk", "gmii_pad_clk", 0, spear1310_clk_init()
874 clk_register_clkdev(clk, "ras_tx125_clk", NULL); spear1310_clk_init()
876 clk = clk_register_fixed_rate(NULL, "ras_30m_fixed_clk", "pll5_clk", 0, spear1310_clk_init()
878 clk = clk_register_gate(NULL, "ras_30m_clk", "ras_30m_fixed_clk", 0, spear1310_clk_init()
881 clk_register_clkdev(clk, "ras_30m_clk", NULL); spear1310_clk_init()
883 clk = clk_register_fixed_rate(NULL, "ras_48m_fixed_clk", "pll5_clk", 0, spear1310_clk_init()
885 clk = clk_register_gate(NULL, "ras_48m_clk", "ras_48m_fixed_clk", 0, spear1310_clk_init()
888 clk_register_clkdev(clk, "ras_48m_clk", NULL); spear1310_clk_init()
890 clk = clk_register_gate(NULL, "ras_ahb_clk", "ahb_clk", 0, spear1310_clk_init()
893 clk_register_clkdev(clk, "ras_ahb_clk", NULL); spear1310_clk_init()
895 clk = clk_register_gate(NULL, "ras_apb_clk", "apb_clk", 0, spear1310_clk_init()
898 clk_register_clkdev(clk, "ras_apb_clk", NULL); spear1310_clk_init()
900 clk = clk_register_fixed_rate(NULL, "ras_plclk0_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
903 clk = clk_register_fixed_rate(NULL, "ras_tx50_clk", NULL, CLK_IS_ROOT, spear1310_clk_init()
906 clk = clk_register_gate(NULL, "can0_clk", "apb_clk", 0, spear1310_clk_init()
909 clk_register_clkdev(clk, NULL, "c_can_platform.0"); spear1310_clk_init()
911 clk = clk_register_gate(NULL, "can1_clk", "apb_clk", 0, spear1310_clk_init()
914 clk_register_clkdev(clk, NULL, "c_can_platform.1"); spear1310_clk_init()
916 clk = clk_register_gate(NULL, "ras_smii0_clk", "ras_ahb_clk", 0, spear1310_clk_init()
919 clk_register_clkdev(clk, NULL, "5c400000.eth"); spear1310_clk_init()
921 clk = clk_register_gate(NULL, "ras_smii1_clk", "ras_ahb_clk", 0, spear1310_clk_init()
924 clk_register_clkdev(clk, NULL, "5c500000.eth"); spear1310_clk_init()
926 clk = clk_register_gate(NULL, "ras_smii2_clk", "ras_ahb_clk", 0, spear1310_clk_init()
929 clk_register_clkdev(clk, NULL, "5c600000.eth"); spear1310_clk_init()
931 clk = clk_register_gate(NULL, "ras_rgmii_clk", "ras_ahb_clk", 0, spear1310_clk_init()
934 clk_register_clkdev(clk, NULL, "5c700000.eth"); spear1310_clk_init()
936 clk = clk_register_mux(NULL, "smii_rgmii_phy_mclk", spear1310_clk_init()
942 clk_register_clkdev(clk, "stmmacphy.1", NULL); spear1310_clk_init()
943 clk_register_clkdev(clk, "stmmacphy.2", NULL); spear1310_clk_init()
944 clk_register_clkdev(clk, "stmmacphy.4", NULL); spear1310_clk_init()
946 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, spear1310_clk_init()
950 clk_register_clkdev(clk, "stmmacphy.3", NULL); spear1310_clk_init()
952 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, spear1310_clk_init()
956 clk_register_clkdev(clk, "uart1_mclk", NULL); spear1310_clk_init()
958 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, spear1310_clk_init()
961 clk_register_clkdev(clk, NULL, "5c800000.serial"); spear1310_clk_init()
963 clk = clk_register_mux(NULL, "uart2_mclk", uart_parents, spear1310_clk_init()
967 clk_register_clkdev(clk, "uart2_mclk", NULL); spear1310_clk_init()
969 clk = clk_register_gate(NULL, "uart2_clk", "uart2_mclk", 0, spear1310_clk_init()
972 clk_register_clkdev(clk, NULL, "5c900000.serial"); spear1310_clk_init()
974 clk = clk_register_mux(NULL, "uart3_mclk", uart_parents, spear1310_clk_init()
978 clk_register_clkdev(clk, "uart3_mclk", NULL); spear1310_clk_init()
980 clk = clk_register_gate(NULL, "uart3_clk", "uart3_mclk", 0, spear1310_clk_init()
983 clk_register_clkdev(clk, NULL, "5ca00000.serial"); spear1310_clk_init()
985 clk = clk_register_mux(NULL, "uart4_mclk", uart_parents, spear1310_clk_init()
989 clk_register_clkdev(clk, "uart4_mclk", NULL); spear1310_clk_init()
991 clk = clk_register_gate(NULL, "uart4_clk", "uart4_mclk", 0, spear1310_clk_init()
994 clk_register_clkdev(clk, NULL, "5cb00000.serial"); spear1310_clk_init()
996 clk = clk_register_mux(NULL, "uart5_mclk", uart_parents, spear1310_clk_init()
1000 clk_register_clkdev(clk, "uart5_mclk", NULL); spear1310_clk_init()
1002 clk = clk_register_gate(NULL, "uart5_clk", "uart5_mclk", 0, spear1310_clk_init()
1005 clk_register_clkdev(clk, NULL, "5cc00000.serial"); spear1310_clk_init()
1007 clk = clk_register_mux(NULL, "i2c1_mclk", i2c_parents, spear1310_clk_init()
1011 clk_register_clkdev(clk, "i2c1_mclk", NULL); spear1310_clk_init()
1013 clk = clk_register_gate(NULL, "i2c1_clk", "i2c1_mclk", 0, spear1310_clk_init()
1016 clk_register_clkdev(clk, NULL, "5cd00000.i2c"); spear1310_clk_init()
1018 clk = clk_register_mux(NULL, "i2c2_mclk", i2c_parents, spear1310_clk_init()
1022 clk_register_clkdev(clk, "i2c2_mclk", NULL); spear1310_clk_init()
1024 clk = clk_register_gate(NULL, "i2c2_clk", "i2c2_mclk", 0, spear1310_clk_init()
1027 clk_register_clkdev(clk, NULL, "5ce00000.i2c"); spear1310_clk_init()
1029 clk = clk_register_mux(NULL, "i2c3_mclk", i2c_parents, spear1310_clk_init()
1033 clk_register_clkdev(clk, "i2c3_mclk", NULL); spear1310_clk_init()
1035 clk = clk_register_gate(NULL, "i2c3_clk", "i2c3_mclk", 0, spear1310_clk_init()
1038 clk_register_clkdev(clk, NULL, "5cf00000.i2c"); spear1310_clk_init()
1040 clk = clk_register_mux(NULL, "i2c4_mclk", i2c_parents, spear1310_clk_init()
1044 clk_register_clkdev(clk, "i2c4_mclk", NULL); spear1310_clk_init()
1046 clk = clk_register_gate(NULL, "i2c4_clk", "i2c4_mclk", 0, spear1310_clk_init()
1049 clk_register_clkdev(clk, NULL, "5d000000.i2c"); spear1310_clk_init()
1051 clk = clk_register_mux(NULL, "i2c5_mclk", i2c_parents, spear1310_clk_init()
1055 clk_register_clkdev(clk, "i2c5_mclk", NULL); spear1310_clk_init()
1057 clk = clk_register_gate(NULL, "i2c5_clk", "i2c5_mclk", 0, spear1310_clk_init()
1060 clk_register_clkdev(clk, NULL, "5d100000.i2c"); spear1310_clk_init()
1062 clk = clk_register_mux(NULL, "i2c6_mclk", i2c_parents, spear1310_clk_init()
1066 clk_register_clkdev(clk, "i2c6_mclk", NULL); spear1310_clk_init()
1068 clk = clk_register_gate(NULL, "i2c6_clk", "i2c6_mclk", 0, spear1310_clk_init()
1071 clk_register_clkdev(clk, NULL, "5d200000.i2c"); spear1310_clk_init()
1073 clk = clk_register_mux(NULL, "i2c7_mclk", i2c_parents, spear1310_clk_init()
1077 clk_register_clkdev(clk, "i2c7_mclk", NULL); spear1310_clk_init()
1079 clk = clk_register_gate(NULL, "i2c7_clk", "i2c7_mclk", 0, spear1310_clk_init()
1082 clk_register_clkdev(clk, NULL, "5d300000.i2c"); spear1310_clk_init()
1084 clk = clk_register_mux(NULL, "ssp1_mclk", ssp1_parents, spear1310_clk_init()
1088 clk_register_clkdev(clk, "ssp1_mclk", NULL); spear1310_clk_init()
1090 clk = clk_register_gate(NULL, "ssp1_clk", "ssp1_mclk", 0, spear1310_clk_init()
1093 clk_register_clkdev(clk, NULL, "5d400000.spi"); spear1310_clk_init()
1095 clk = clk_register_mux(NULL, "pci_mclk", pci_parents, spear1310_clk_init()
1099 clk_register_clkdev(clk, "pci_mclk", NULL); spear1310_clk_init()
1101 clk = clk_register_gate(NULL, "pci_clk", "pci_mclk", 0, spear1310_clk_init()
1104 clk_register_clkdev(clk, NULL, "pci"); spear1310_clk_init()
1106 clk = clk_register_mux(NULL, "tdm1_mclk", tdm_parents, spear1310_clk_init()
1110 clk_register_clkdev(clk, "tdm1_mclk", NULL); spear1310_clk_init()
1112 clk = clk_register_gate(NULL, "tdm1_clk", "tdm1_mclk", 0, spear1310_clk_init()
1115 clk_register_clkdev(clk, NULL, "tdm_hdlc.0"); spear1310_clk_init()
1117 clk = clk_register_mux(NULL, "tdm2_mclk", tdm_parents, spear1310_clk_init()
1121 clk_register_clkdev(clk, "tdm2_mclk", NULL); spear1310_clk_init()
1123 clk = clk_register_gate(NULL, "tdm2_clk", "tdm2_mclk", 0, spear1310_clk_init()
1126 clk_register_clkdev(clk, NULL, "tdm_hdlc.1"); spear1310_clk_init()
|
| H A D | spear1340_clock.c | 19 #include "clk.h"
294 /* For gmac phy input clk */
352 /* For parent clk = 49.152 MHz */
359 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
360 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
364 /* For parent clk = 49.152 MHz */
444 struct clk *clk, *clk1; spear1340_clk_init() local
446 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
448 clk_register_clkdev(clk, "osc_32k_clk", NULL); spear1340_clk_init()
450 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
452 clk_register_clkdev(clk, "osc_24m_clk", NULL); spear1340_clk_init()
454 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
456 clk_register_clkdev(clk, "osc_25m_clk", NULL); spear1340_clk_init()
458 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, CLK_IS_ROOT, spear1340_clk_init()
460 clk_register_clkdev(clk, "gmii_pad_clk", NULL); spear1340_clk_init()
462 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, spear1340_clk_init()
464 clk_register_clkdev(clk, "i2s_src_pad_clk", NULL); spear1340_clk_init()
466 /* clock derived from 32 KHz osc clk */ spear1340_clk_init()
467 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, spear1340_clk_init()
470 clk_register_clkdev(clk, NULL, "e0580000.rtc"); spear1340_clk_init()
472 /* clock derived from 24 or 25 MHz osc clk */ spear1340_clk_init()
474 clk = clk_register_mux(NULL, "vco1_mclk", vco_parents, spear1340_clk_init()
478 clk_register_clkdev(clk, "vco1_mclk", NULL); spear1340_clk_init()
479 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "vco1_mclk", 0, spear1340_clk_init()
482 clk_register_clkdev(clk, "vco1_clk", NULL); spear1340_clk_init()
485 clk = clk_register_mux(NULL, "vco2_mclk", vco_parents, spear1340_clk_init()
489 clk_register_clkdev(clk, "vco2_mclk", NULL); spear1340_clk_init()
490 clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "vco2_mclk", 0, spear1340_clk_init()
493 clk_register_clkdev(clk, "vco2_clk", NULL); spear1340_clk_init()
496 clk = clk_register_mux(NULL, "vco3_mclk", vco_parents, spear1340_clk_init()
500 clk_register_clkdev(clk, "vco3_mclk", NULL); spear1340_clk_init()
501 clk = clk_register_vco_pll("vco3_clk", "pll3_clk", NULL, "vco3_mclk", 0, spear1340_clk_init()
504 clk_register_clkdev(clk, "vco3_clk", NULL); spear1340_clk_init()
507 clk = clk_register_vco_pll("vco4_clk", "pll4_clk", NULL, "osc_24m_clk", spear1340_clk_init()
510 clk_register_clkdev(clk, "vco4_clk", NULL); spear1340_clk_init()
513 clk = clk_register_fixed_rate(NULL, "pll5_clk", "osc_24m_clk", 0, spear1340_clk_init()
515 clk_register_clkdev(clk, "pll5_clk", NULL); spear1340_clk_init()
517 clk = clk_register_fixed_rate(NULL, "pll6_clk", "osc_25m_clk", 0, spear1340_clk_init()
519 clk_register_clkdev(clk, "pll6_clk", NULL); spear1340_clk_init()
522 clk = clk_register_fixed_factor(NULL, "vco1div2_clk", "vco1_clk", 0, 1, spear1340_clk_init()
524 clk_register_clkdev(clk, "vco1div2_clk", NULL); spear1340_clk_init()
526 clk = clk_register_fixed_factor(NULL, "vco1div4_clk", "vco1_clk", 0, 1, spear1340_clk_init()
528 clk_register_clkdev(clk, "vco1div4_clk", NULL); spear1340_clk_init()
530 clk = clk_register_fixed_factor(NULL, "vco2div2_clk", "vco2_clk", 0, 1, spear1340_clk_init()
532 clk_register_clkdev(clk, "vco2div2_clk", NULL); spear1340_clk_init()
534 clk = clk_register_fixed_factor(NULL, "vco3div2_clk", "vco3_clk", 0, 1, spear1340_clk_init()
536 clk_register_clkdev(clk, "vco3div2_clk", NULL); spear1340_clk_init()
541 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, spear1340_clk_init()
544 clk_register_clkdev(clk, NULL, "e07008c4.thermal"); spear1340_clk_init()
546 /* clock derived from pll4 clk */ spear1340_clk_init()
547 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, spear1340_clk_init()
549 clk_register_clkdev(clk, "ddr_clk", NULL); spear1340_clk_init()
551 /* clock derived from pll1 clk */ spear1340_clk_init()
552 clk = clk_register_frac("sys_syn_clk", "vco1div2_clk", 0, spear1340_clk_init()
555 clk_register_clkdev(clk, "sys_syn_clk", NULL); spear1340_clk_init()
557 clk = clk_register_frac("amba_syn_clk", "vco1div2_clk", 0, spear1340_clk_init()
560 clk_register_clkdev(clk, "amba_syn_clk", NULL); spear1340_clk_init()
562 clk = clk_register_mux(NULL, "sys_mclk", sys_parents, spear1340_clk_init()
566 clk_register_clkdev(clk, "sys_mclk", NULL); spear1340_clk_init()
568 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, spear1340_clk_init()
570 clk_register_clkdev(clk, "cpu_clk", NULL); spear1340_clk_init()
572 clk = clk_register_fixed_factor(NULL, "cpu_div3_clk", "cpu_clk", 0, 1, spear1340_clk_init()
574 clk_register_clkdev(clk, "cpu_div3_clk", NULL); spear1340_clk_init()
576 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, spear1340_clk_init()
578 clk_register_clkdev(clk, NULL, "ec800620.wdt"); spear1340_clk_init()
580 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1, spear1340_clk_init()
582 clk_register_clkdev(clk, NULL, "smp_twd"); spear1340_clk_init()
584 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, spear1340_clk_init()
588 clk_register_clkdev(clk, "ahb_clk", NULL); spear1340_clk_init()
590 clk = clk_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, spear1340_clk_init()
592 clk_register_clkdev(clk, "apb_clk", NULL); spear1340_clk_init()
595 clk = clk_register_mux(NULL, "gpt0_mclk", gpt_parents, spear1340_clk_init()
599 clk_register_clkdev(clk, "gpt0_mclk", NULL); spear1340_clk_init()
600 clk = clk_register_gate(NULL, "gpt0_clk", "gpt0_mclk", 0, spear1340_clk_init()
603 clk_register_clkdev(clk, NULL, "gpt0"); spear1340_clk_init()
605 clk = clk_register_mux(NULL, "gpt1_mclk", gpt_parents, spear1340_clk_init()
609 clk_register_clkdev(clk, "gpt1_mclk", NULL); spear1340_clk_init()
610 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, spear1340_clk_init()
613 clk_register_clkdev(clk, NULL, "gpt1"); spear1340_clk_init()
615 clk = clk_register_mux(NULL, "gpt2_mclk", gpt_parents, spear1340_clk_init()
619 clk_register_clkdev(clk, "gpt2_mclk", NULL); spear1340_clk_init()
620 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, spear1340_clk_init()
623 clk_register_clkdev(clk, NULL, "gpt2"); spear1340_clk_init()
625 clk = clk_register_mux(NULL, "gpt3_mclk", gpt_parents, spear1340_clk_init()
629 clk_register_clkdev(clk, "gpt3_mclk", NULL); spear1340_clk_init()
630 clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0, spear1340_clk_init()
633 clk_register_clkdev(clk, NULL, "gpt3"); spear1340_clk_init()
636 clk = clk_register_aux("uart0_syn_clk", "uart0_syn_gclk", spear1340_clk_init()
639 clk_register_clkdev(clk, "uart0_syn_clk", NULL); spear1340_clk_init()
642 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, spear1340_clk_init()
647 clk_register_clkdev(clk, "uart0_mclk", NULL); spear1340_clk_init()
649 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", spear1340_clk_init()
652 clk_register_clkdev(clk, NULL, "e0000000.serial"); spear1340_clk_init()
654 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", spear1340_clk_init()
657 clk_register_clkdev(clk, "uart1_syn_clk", NULL); spear1340_clk_init()
660 clk = clk_register_mux(NULL, "uart1_mclk", uart1_parents, spear1340_clk_init()
664 clk_register_clkdev(clk, "uart1_mclk", NULL); spear1340_clk_init()
666 clk = clk_register_gate(NULL, "uart1_clk", "uart1_mclk", 0, spear1340_clk_init()
669 clk_register_clkdev(clk, NULL, "b4100000.serial"); spear1340_clk_init()
671 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", spear1340_clk_init()
674 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); spear1340_clk_init()
677 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", spear1340_clk_init()
680 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); spear1340_clk_init()
682 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", spear1340_clk_init()
685 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); spear1340_clk_init()
688 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", spear1340_clk_init()
691 clk_register_clkdev(clk, NULL, "b2800000.cf"); spear1340_clk_init()
692 clk_register_clkdev(clk, NULL, "arasan_xd"); spear1340_clk_init()
694 clk = clk_register_aux("c3_syn_clk", "c3_syn_gclk", "vco1div2_clk", 0, spear1340_clk_init()
697 clk_register_clkdev(clk, "c3_syn_clk", NULL); spear1340_clk_init()
700 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, spear1340_clk_init()
705 clk_register_clkdev(clk, "c3_mclk", NULL); spear1340_clk_init()
707 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT, spear1340_clk_init()
710 clk_register_clkdev(clk, NULL, "e1800000.c3"); spear1340_clk_init()
713 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, spear1340_clk_init()
718 clk_register_clkdev(clk, "phy_input_mclk", NULL); spear1340_clk_init()
720 clk = clk_register_aux("phy_syn_clk", "phy_syn_gclk", "phy_input_mclk", spear1340_clk_init()
723 clk_register_clkdev(clk, "phy_syn_clk", NULL); spear1340_clk_init()
726 clk = clk_register_mux(NULL, "phy_mclk", gmac_phy_parents, spear1340_clk_init()
730 clk_register_clkdev(clk, "stmmacphy.0", NULL); spear1340_clk_init()
733 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, spear1340_clk_init()
738 clk_register_clkdev(clk, "clcd_syn_mclk", NULL); spear1340_clk_init()
740 clk = clk_register_frac("clcd_syn_clk", "clcd_syn_mclk", 0, spear1340_clk_init()
743 clk_register_clkdev(clk, "clcd_syn_clk", NULL); spear1340_clk_init()
745 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, spear1340_clk_init()
750 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL); spear1340_clk_init()
752 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, spear1340_clk_init()
755 clk_register_clkdev(clk, NULL, "e1000000.clcd"); spear1340_clk_init()
758 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, spear1340_clk_init()
762 clk_register_clkdev(clk, "i2s_src_mclk", NULL); spear1340_clk_init()
764 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", spear1340_clk_init()
768 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); spear1340_clk_init()
770 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, spear1340_clk_init()
775 clk_register_clkdev(clk, "i2s_ref_mclk", NULL); spear1340_clk_init()
777 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, spear1340_clk_init()
780 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); spear1340_clk_init()
782 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", "i2s_ref_mclk", spear1340_clk_init()
786 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); spear1340_clk_init()
789 /* clock derived from ahb clk */ spear1340_clk_init()
790 clk = clk_register_gate(NULL, "i2c0_clk", "ahb_clk", 0, spear1340_clk_init()
793 clk_register_clkdev(clk, NULL, "e0280000.i2c"); spear1340_clk_init()
795 clk = clk_register_gate(NULL, "i2c1_clk", "ahb_clk", 0, spear1340_clk_init()
798 clk_register_clkdev(clk, NULL, "b4000000.i2c"); spear1340_clk_init()
800 clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, spear1340_clk_init()
803 clk_register_clkdev(clk, NULL, "ea800000.dma"); spear1340_clk_init()
804 clk_register_clkdev(clk, NULL, "eb000000.dma"); spear1340_clk_init()
806 clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, spear1340_clk_init()
809 clk_register_clkdev(clk, NULL, "e2000000.eth"); spear1340_clk_init()
811 clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, spear1340_clk_init()
814 clk_register_clkdev(clk, NULL, "b0000000.flash"); spear1340_clk_init()
816 clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, spear1340_clk_init()
819 clk_register_clkdev(clk, NULL, "ea000000.flash"); spear1340_clk_init()
821 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, spear1340_clk_init()
824 clk_register_clkdev(clk, NULL, "e4000000.ohci"); spear1340_clk_init()
825 clk_register_clkdev(clk, NULL, "e4800000.ehci"); spear1340_clk_init()
827 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, spear1340_clk_init()
830 clk_register_clkdev(clk, NULL, "e5000000.ohci"); spear1340_clk_init()
831 clk_register_clkdev(clk, NULL, "e5800000.ehci"); spear1340_clk_init()
833 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, spear1340_clk_init()
836 clk_register_clkdev(clk, NULL, "e3800000.otg"); spear1340_clk_init()
838 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, spear1340_clk_init()
841 clk_register_clkdev(clk, NULL, "b1000000.pcie"); spear1340_clk_init()
842 clk_register_clkdev(clk, NULL, "b1000000.ahci"); spear1340_clk_init()
844 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, spear1340_clk_init()
847 clk_register_clkdev(clk, "sysram0_clk", NULL); spear1340_clk_init()
849 clk = clk_register_gate(NULL, "sysram1_clk", "ahb_clk", 0, spear1340_clk_init()
852 clk_register_clkdev(clk, "sysram1_clk", NULL); spear1340_clk_init()
854 clk = clk_register_aux("adc_syn_clk", "adc_syn_gclk", "ahb_clk", spear1340_clk_init()
857 clk_register_clkdev(clk, "adc_syn_clk", NULL); spear1340_clk_init()
860 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", spear1340_clk_init()
863 clk_register_clkdev(clk, NULL, "e0080000.adc"); spear1340_clk_init()
865 /* clock derived from apb clk */ spear1340_clk_init()
866 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, spear1340_clk_init()
869 clk_register_clkdev(clk, NULL, "e0100000.spi"); spear1340_clk_init()
871 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, spear1340_clk_init()
874 clk_register_clkdev(clk, NULL, "e0600000.gpio"); spear1340_clk_init()
876 clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, spear1340_clk_init()
879 clk_register_clkdev(clk, NULL, "e0680000.gpio"); spear1340_clk_init()
881 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, spear1340_clk_init()
884 clk_register_clkdev(clk, NULL, "b2400000.i2s-play"); spear1340_clk_init()
886 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, spear1340_clk_init()
889 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec"); spear1340_clk_init()
891 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, spear1340_clk_init()
894 clk_register_clkdev(clk, NULL, "e0300000.kbd"); spear1340_clk_init()
897 clk = clk_register_mux(NULL, "gen_syn0_1_mclk", gen_synth0_1_parents, spear1340_clk_init()
902 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL); spear1340_clk_init()
904 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, spear1340_clk_init()
909 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL); spear1340_clk_init()
911 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0, spear1340_clk_init()
914 clk_register_clkdev(clk, "gen_syn0_clk", NULL); spear1340_clk_init()
916 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0, spear1340_clk_init()
919 clk_register_clkdev(clk, "gen_syn1_clk", NULL); spear1340_clk_init()
921 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0, spear1340_clk_init()
924 clk_register_clkdev(clk, "gen_syn2_clk", NULL); spear1340_clk_init()
926 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0, spear1340_clk_init()
929 clk_register_clkdev(clk, "gen_syn3_clk", NULL); spear1340_clk_init()
931 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", spear1340_clk_init()
934 clk_register_clkdev(clk, NULL, "mali"); spear1340_clk_init()
936 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, spear1340_clk_init()
939 clk_register_clkdev(clk, NULL, "spear_cec.0"); spear1340_clk_init()
941 clk = clk_register_gate(NULL, "cec1_clk", "ahb_clk", 0, spear1340_clk_init()
944 clk_register_clkdev(clk, NULL, "spear_cec.1"); spear1340_clk_init()
946 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, spear1340_clk_init()
951 clk_register_clkdev(clk, "spdif_out_mclk", NULL); spear1340_clk_init()
953 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", spear1340_clk_init()
956 clk_register_clkdev(clk, NULL, "d0000000.spdif-out"); spear1340_clk_init()
958 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, spear1340_clk_init()
963 clk_register_clkdev(clk, "spdif_in_mclk", NULL); spear1340_clk_init()
965 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", spear1340_clk_init()
968 clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); spear1340_clk_init()
970 clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0, spear1340_clk_init()
973 clk_register_clkdev(clk, NULL, "acp_clk"); spear1340_clk_init()
975 clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0, spear1340_clk_init()
978 clk_register_clkdev(clk, NULL, "e2800000.gpio"); spear1340_clk_init()
980 clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0, spear1340_clk_init()
983 clk_register_clkdev(clk, NULL, "video_dec"); spear1340_clk_init()
985 clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0, spear1340_clk_init()
988 clk_register_clkdev(clk, NULL, "video_enc"); spear1340_clk_init()
990 clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0, spear1340_clk_init()
993 clk_register_clkdev(clk, NULL, "spear_vip"); spear1340_clk_init()
995 clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0, spear1340_clk_init()
998 clk_register_clkdev(clk, NULL, "d0200000.cam0"); spear1340_clk_init()
1000 clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0, spear1340_clk_init()
1003 clk_register_clkdev(clk, NULL, "d0300000.cam1"); spear1340_clk_init()
1005 clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0, spear1340_clk_init()
1008 clk_register_clkdev(clk, NULL, "d0400000.cam2"); spear1340_clk_init()
1010 clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0, spear1340_clk_init()
1013 clk_register_clkdev(clk, NULL, "d0500000.cam3"); spear1340_clk_init()
1015 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0, spear1340_clk_init()
1018 clk_register_clkdev(clk, NULL, "e0180000.pwm"); spear1340_clk_init()
|
| /linux-4.4.14/arch/blackfin/include/asm/ |
| H A D | clocks.h | 51 #include <linux/clk.h>
54 unsigned long (*get_rate)(struct clk *clk);
55 unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
56 int (*set_rate)(struct clk *clk, unsigned long rate);
57 int (*enable)(struct clk *clk);
58 int (*disable)(struct clk *clk);
61 struct clk { struct
62 struct clk *parent;
|
| H A D | clkdev.h | 12 #define __clk_put(clk)
13 #define __clk_get(clk) ({ 1; })
|
| /linux-4.4.14/arch/sh/kernel/cpu/sh4/ |
| H A D | clock-sh4-202.c | 25 static unsigned long emi_clk_recalc(struct clk *clk) emi_clk_recalc() argument
28 return clk->parent->rate / frqcr3_divisors[idx]; emi_clk_recalc()
31 static inline int frqcr3_lookup(struct clk *clk, unsigned long rate) frqcr3_lookup() argument
33 int divisor = clk->parent->rate / rate; frqcr3_lookup()
48 static struct clk sh4202_emi_clk = {
53 static unsigned long femi_clk_recalc(struct clk *clk) femi_clk_recalc() argument
56 return clk->parent->rate / frqcr3_divisors[idx]; femi_clk_recalc()
63 static struct clk sh4202_femi_clk = {
68 static void shoc_clk_init(struct clk *clk) shoc_clk_init() argument
84 if (clk->ops->set_rate(clk, clk->parent->rate / divisor) == 0) shoc_clk_init()
91 static unsigned long shoc_clk_recalc(struct clk *clk) shoc_clk_recalc() argument
94 return clk->parent->rate / frqcr3_divisors[idx]; shoc_clk_recalc()
97 static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate) shoc_clk_verify_rate() argument
99 struct clk *bclk = clk_get(NULL, "bus_clk"); shoc_clk_verify_rate()
112 static int shoc_clk_set_rate(struct clk *clk, unsigned long rate) shoc_clk_set_rate() argument
118 if (shoc_clk_verify_rate(clk, rate) != 0) shoc_clk_set_rate()
121 tmp = frqcr3_lookup(clk, rate); shoc_clk_set_rate()
128 clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; shoc_clk_set_rate()
139 static struct clk sh4202_shoc_clk = {
144 static struct clk *sh4202_onchip_clocks[] = {
159 struct clk *clk; arch_clk_init() local
164 clk = clk_get(NULL, "master_clk"); arch_clk_init()
166 struct clk *clkp = sh4202_onchip_clocks[i]; arch_clk_init()
168 clkp->parent = clk; arch_clk_init()
172 clk_put(clk); arch_clk_init()
|
| H A D | clock-sh4.c | 29 static void master_clk_init(struct clk *clk) master_clk_init() argument
31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; master_clk_init()
38 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
41 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
48 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
51 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
58 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
61 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| /linux-4.4.14/arch/m68k/include/asm/ |
| H A D | mcfclk.h | 9 struct clk;
12 void (*enable)(struct clk *);
13 void (*disable)(struct clk *);
16 struct clk { struct
24 extern struct clk *mcf_clks[];
33 static struct clk __clk_##clk_bank##_##clk_slot = { \
40 void __clk_init_enabled(struct clk *);
41 void __clk_init_disabled(struct clk *);
44 static struct clk clk_##clk_ref = { \
|
| /linux-4.4.14/arch/mips/xilfpga/ |
| H A D | time.c | 12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
22 struct clk *clk; plat_time_init() local
33 clk = of_clk_get(np, 0); plat_time_init()
34 if (IS_ERR(clk)) { plat_time_init()
35 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); plat_time_init()
39 mips_hpt_frequency = clk_get_rate(clk) / 2; plat_time_init()
40 clk_put(clk); plat_time_init()
|
| /linux-4.4.14/arch/arm/plat-versatile/include/plat/ |
| H A D | clock.h | 7 long (*round)(struct clk *, unsigned long);
8 int (*set)(struct clk *, unsigned long);
9 void (*setvco)(struct clk *, struct icst_vco);
12 int icst_clk_set(struct clk *, unsigned long);
13 long icst_clk_round(struct clk *, unsigned long);
|
| /linux-4.4.14/arch/arm/mach-w90x900/ |
| H A D | clock.c | 19 #include <linux/clk.h>
32 int clk_enable(struct clk *clk) clk_enable() argument
37 if (clk->enabled++ == 0) clk_enable()
38 (clk->enable)(clk, 1); clk_enable()
45 void clk_disable(struct clk *clk) clk_disable() argument
49 WARN_ON(clk->enabled == 0); clk_disable()
52 if (--clk->enabled == 0) clk_disable()
53 (clk->enable)(clk, 0); clk_disable()
58 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
64 void nuc900_clk_enable(struct clk *clk, int enable) nuc900_clk_enable() argument
66 unsigned int clocks = clk->cken; nuc900_clk_enable()
79 void nuc900_subclk_enable(struct clk *clk, int enable) nuc900_subclk_enable() argument
81 unsigned int clocks = clk->cken; nuc900_subclk_enable()
|
| H A D | clock.h | 15 void nuc900_clk_enable(struct clk *clk, int enable);
16 void nuc900_subclk_enable(struct clk *clk, int enable);
18 struct clk { struct
21 void (*enable)(struct clk *, int enable);
25 struct clk clk_##_name = { \
31 struct clk clk_##_name = { \
39 .clk = _clk, \
|
| /linux-4.4.14/kernel/time/ |
| H A D | posix-clock.c | 35 struct posix_clock *clk = fp->private_data; get_posix_clock() local
37 down_read(&clk->rwsem); get_posix_clock()
39 if (!clk->zombie) get_posix_clock()
40 return clk; get_posix_clock()
42 up_read(&clk->rwsem); get_posix_clock()
47 static void put_posix_clock(struct posix_clock *clk) put_posix_clock() argument
49 up_read(&clk->rwsem); put_posix_clock()
55 struct posix_clock *clk = get_posix_clock(fp); posix_clock_read() local
58 if (!clk) posix_clock_read()
61 if (clk->ops.read) posix_clock_read()
62 err = clk->ops.read(clk, fp->f_flags, buf, count); posix_clock_read()
64 put_posix_clock(clk); posix_clock_read()
71 struct posix_clock *clk = get_posix_clock(fp); posix_clock_poll() local
74 if (!clk) posix_clock_poll()
77 if (clk->ops.poll) posix_clock_poll()
78 result = clk->ops.poll(clk, fp, wait); posix_clock_poll()
80 put_posix_clock(clk); posix_clock_poll()
87 struct posix_clock *clk = get_posix_clock(fp); posix_clock_fasync() local
90 if (!clk) posix_clock_fasync()
93 if (clk->ops.fasync) posix_clock_fasync()
94 err = clk->ops.fasync(clk, fd, fp, on); posix_clock_fasync()
96 put_posix_clock(clk); posix_clock_fasync()
103 struct posix_clock *clk = get_posix_clock(fp); posix_clock_mmap() local
106 if (!clk) posix_clock_mmap()
109 if (clk->ops.mmap) posix_clock_mmap()
110 err = clk->ops.mmap(clk, vma); posix_clock_mmap()
112 put_posix_clock(clk); posix_clock_mmap()
120 struct posix_clock *clk = get_posix_clock(fp); posix_clock_ioctl() local
123 if (!clk) posix_clock_ioctl()
126 if (clk->ops.ioctl) posix_clock_ioctl()
127 err = clk->ops.ioctl(clk, cmd, arg); posix_clock_ioctl()
129 put_posix_clock(clk); posix_clock_ioctl()
138 struct posix_clock *clk = get_posix_clock(fp); posix_clock_compat_ioctl() local
141 if (!clk) posix_clock_compat_ioctl()
144 if (clk->ops.ioctl) posix_clock_compat_ioctl()
145 err = clk->ops.ioctl(clk, cmd, arg); posix_clock_compat_ioctl()
147 put_posix_clock(clk); posix_clock_compat_ioctl()
156 struct posix_clock *clk = posix_clock_open() local
159 down_read(&clk->rwsem); posix_clock_open()
161 if (clk->zombie) { posix_clock_open()
165 if (clk->ops.open) posix_clock_open()
166 err = clk->ops.open(clk, fp->f_mode); posix_clock_open()
171 kref_get(&clk->kref); posix_clock_open()
172 fp->private_data = clk; posix_clock_open()
175 up_read(&clk->rwsem); posix_clock_open()
181 struct posix_clock *clk = fp->private_data; posix_clock_release() local
184 if (clk->ops.release) posix_clock_release()
185 err = clk->ops.release(clk); posix_clock_release()
187 kref_put(&clk->kref, delete_clock); posix_clock_release()
209 int posix_clock_register(struct posix_clock *clk, dev_t devid) posix_clock_register() argument
213 kref_init(&clk->kref); posix_clock_register()
214 init_rwsem(&clk->rwsem); posix_clock_register()
216 cdev_init(&clk->cdev, &posix_clock_file_operations); posix_clock_register()
217 clk->cdev.owner = clk->ops.owner; posix_clock_register()
218 err = cdev_add(&clk->cdev, devid, 1); posix_clock_register()
226 struct posix_clock *clk = container_of(kref, struct posix_clock, kref); delete_clock() local
228 if (clk->release) delete_clock()
229 clk->release(clk); delete_clock()
232 void posix_clock_unregister(struct posix_clock *clk) posix_clock_unregister() argument
234 cdev_del(&clk->cdev); posix_clock_unregister()
236 down_write(&clk->rwsem); posix_clock_unregister()
237 clk->zombie = true; posix_clock_unregister()
238 up_write(&clk->rwsem); posix_clock_unregister()
240 kref_put(&clk->kref, delete_clock); posix_clock_unregister()
246 struct posix_clock *clk; member in struct:posix_clock_desc
261 cd->clk = get_posix_clock(fp); get_clock_desc()
263 err = cd->clk ? 0 : -ENODEV; get_clock_desc()
272 put_posix_clock(cd->clk); put_clock_desc()
290 if (cd.clk->ops.clock_adjtime) pc_clock_adjtime()
291 err = cd.clk->ops.clock_adjtime(cd.clk, tx); pc_clock_adjtime()
309 if (cd.clk->ops.clock_gettime) pc_clock_gettime()
310 err = cd.clk->ops.clock_gettime(cd.clk, ts); pc_clock_gettime()
328 if (cd.clk->ops.clock_getres) pc_clock_getres()
329 err = cd.clk->ops.clock_getres(cd.clk, ts); pc_clock_getres()
352 if (cd.clk->ops.clock_settime) pc_clock_settime()
353 err = cd.clk->ops.clock_settime(cd.clk, ts); pc_clock_settime()
372 if (cd.clk->ops.timer_create) pc_timer_create()
373 err = cd.clk->ops.timer_create(cd.clk, kit); pc_timer_create()
392 if (cd.clk->ops.timer_delete) pc_timer_delete()
393 err = cd.clk->ops.timer_delete(cd.clk, kit); pc_timer_delete()
410 if (cd.clk->ops.timer_gettime) pc_timer_gettime()
411 cd.clk->ops.timer_gettime(cd.clk, kit, ts); pc_timer_gettime()
427 if (cd.clk->ops.timer_settime) pc_timer_settime()
428 err = cd.clk->ops.timer_settime(cd.clk, kit, flags, ts, old); pc_timer_settime()
|
| /linux-4.4.14/drivers/clk/pistachio/ |
| H A D | clk.c | 9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
16 #include "clk.h"
27 p->clk_data.clks = kcalloc(num_clks, sizeof(struct clk *), GFP_KERNEL); pistachio_clk_alloc_provider()
64 struct clk *clk; pistachio_clk_register_gate() local
68 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, pistachio_clk_register_gate()
72 p->clk_data.clks[gate[i].id] = clk; pistachio_clk_register_gate()
80 struct clk *clk; pistachio_clk_register_mux() local
84 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, pistachio_clk_register_mux()
90 p->clk_data.clks[mux[i].id] = clk; pistachio_clk_register_mux()
98 struct clk *clk; pistachio_clk_register_div() local
102 clk = clk_register_divider(NULL, div[i].name, div[i].parent, pistachio_clk_register_div()
106 p->clk_data.clks[div[i].id] = clk; pistachio_clk_register_div()
114 struct clk *clk; pistachio_clk_register_fixed_factor() local
118 clk = clk_register_fixed_factor(NULL, ff[i].name, ff[i].parent, pistachio_clk_register_fixed_factor()
120 p->clk_data.clks[ff[i].id] = clk; pistachio_clk_register_fixed_factor()
131 struct clk *clk = p->clk_data.clks[clk_ids[i]]; pistachio_clk_force_enable() local
133 if (IS_ERR(clk)) pistachio_clk_force_enable()
136 err = clk_prepare_enable(clk); pistachio_clk_force_enable()
139 __clk_get_name(clk), err); pistachio_clk_force_enable()
|
| /linux-4.4.14/drivers/gpu/drm/armada/ |
| H A D | armada_510.c | 10 #include <linux/clk.h>
20 struct clk *clk; armada510_crtc_init() local
22 clk = devm_clk_get(dev, "ext_ref_clk1"); armada510_crtc_init()
23 if (IS_ERR(clk)) armada510_crtc_init()
24 return PTR_ERR(clk) == -ENOENT ? -EPROBE_DEFER : PTR_ERR(clk); armada510_crtc_init()
26 dcrtc->extclk[0] = clk; armada510_crtc_init()
47 struct clk *clk = dcrtc->extclk[0]; armada510_crtc_compute_clock() local
53 if (IS_ERR(clk)) armada510_crtc_compute_clock()
54 return PTR_ERR(clk); armada510_crtc_compute_clock()
56 if (dcrtc->clk != clk) { armada510_crtc_compute_clock()
57 ret = clk_prepare_enable(clk); armada510_crtc_compute_clock()
60 dcrtc->clk = clk; armada510_crtc_compute_clock()
67 ref = clk_round_rate(clk, rate); armada510_crtc_compute_clock()
72 clk_set_rate(clk, ref); armada510_crtc_compute_clock()
|
| /linux-4.4.14/arch/arm/mach-versatile/include/mach/ |
| H A D | clkdev.h | 6 struct clk { struct
13 #define __clk_get(clk) ({ 1; })
14 #define __clk_put(clk) do { } while (0)
|
| /linux-4.4.14/drivers/clk/versatile/ |
| H A D | clk-realview.c | 12 #include <linux/clk-provider.h>
17 #include "clk-icst.h"
52 struct clk *clk; realview_clk_init() local
55 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); realview_clk_init()
56 clk_register_clkdev(clk, "apb_pclk", NULL); realview_clk_init()
59 clk = clk_register_fixed_rate(NULL, "clk24mhz", NULL, CLK_IS_ROOT, realview_clk_init()
61 clk_register_clkdev(clk, NULL, "dev:uart0"); realview_clk_init()
62 clk_register_clkdev(clk, NULL, "dev:uart1"); realview_clk_init()
63 clk_register_clkdev(clk, NULL, "dev:uart2"); realview_clk_init()
64 clk_register_clkdev(clk, NULL, "fpga:kmi0"); realview_clk_init()
65 clk_register_clkdev(clk, NULL, "fpga:kmi1"); realview_clk_init()
66 clk_register_clkdev(clk, NULL, "fpga:mmc0"); realview_clk_init()
67 clk_register_clkdev(clk, NULL, "dev:ssp0"); realview_clk_init()
73 clk_register_clkdev(clk, NULL, "dev:uart3"); realview_clk_init()
74 clk_register_clkdev(clk, NULL, "dev:uart4"); realview_clk_init()
76 clk_register_clkdev(clk, NULL, "fpga:uart3"); realview_clk_init()
80 clk = clk_register_fixed_rate(NULL, "clk1mhz", NULL, CLK_IS_ROOT, realview_clk_init()
82 clk_register_clkdev(clk, NULL, "sp804"); realview_clk_init()
86 clk = icst_clk_register(NULL, &realview_osc0_desc, realview_clk_init()
89 clk = icst_clk_register(NULL, &realview_osc4_desc, realview_clk_init()
92 clk_register_clkdev(clk, NULL, "dev:clcd"); realview_clk_init()
93 clk_register_clkdev(clk, NULL, "issp:clcd"); realview_clk_init()
|
| H A D | clk-impd1.c | 9 #include <linux/clk-provider.h>
13 #include <linux/platform_data/clk-integrator.h>
15 #include "clk-icst.h"
23 struct clk *pclk;
25 struct clk *vco1clk;
27 struct clk *vco2clk;
28 struct clk *mmciclk;
30 struct clk *uartclk;
32 struct clk *spiclk;
34 struct clk *scclk;
89 struct clk *clk; integrator_impd1_clk_init() local
90 struct clk *pclk; integrator_impd1_clk_init()
106 clk = icst_clk_register(NULL, &impd1_icst1_desc, imc->vco1name, NULL, integrator_impd1_clk_init()
108 imc->vco1clk = clk; integrator_impd1_clk_init()
110 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:01000", id); integrator_impd1_clk_init()
114 clk = icst_clk_register(NULL, &impd1_icst2_desc, imc->vco2name, NULL, integrator_impd1_clk_init()
116 imc->vco2clk = clk; integrator_impd1_clk_init()
120 imc->clks[3] = clkdev_alloc(clk, NULL, "lm%x:00700", id); integrator_impd1_clk_init()
124 clk = clk_register_fixed_factor(NULL, imc->uartname, imc->vco2name, integrator_impd1_clk_init()
126 imc->uartclk = clk; integrator_impd1_clk_init()
128 imc->clks[5] = clkdev_alloc(clk, NULL, "lm%x:00100", id); integrator_impd1_clk_init()
130 imc->clks[7] = clkdev_alloc(clk, NULL, "lm%x:00200", id); integrator_impd1_clk_init()
134 clk = clk_register_fixed_factor(NULL, imc->spiname, imc->vco2name, integrator_impd1_clk_init()
137 imc->clks[9] = clkdev_alloc(clk, NULL, "lm%x:00300", id); integrator_impd1_clk_init()
146 clk = clk_register_fixed_factor(NULL, imc->scname, imc->vco2name, integrator_impd1_clk_init()
148 imc->scclk = clk; integrator_impd1_clk_init()
150 imc->clks[14] = clkdev_alloc(clk, NULL, "lm%x:00600", id); integrator_impd1_clk_init()
|
| /linux-4.4.14/arch/sh/kernel/cpu/sh4a/ |
| H A D | clock-sh7780.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
27 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003]; master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
37 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
54 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
57 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
77 static unsigned long shyway_clk_recalc(struct clk *clk) shyway_clk_recalc() argument
80 return clk->parent->rate / cfc_divisors[idx]; shyway_clk_recalc()
87 static struct clk sh7780_shyway_clk = {
96 static struct clk *sh7780_onchip_clocks[] = {
107 struct clk *clk; arch_clk_init() local
112 clk = clk_get(NULL, "master_clk"); arch_clk_init()
114 struct clk *clkp = sh7780_onchip_clocks[i]; arch_clk_init()
116 clkp->parent = clk; arch_clk_init()
120 clk_put(clk); arch_clk_init()
|
| H A D | clock-sh7763.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
27 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; master_clk_init()
34 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
37 return clk->parent->rate / p0fc_divisors[idx]; module_clk_recalc()
44 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
47 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
71 static unsigned long shyway_clk_recalc(struct clk *clk) shyway_clk_recalc() argument
74 return clk->parent->rate / cfc_divisors[idx]; shyway_clk_recalc()
81 static struct clk sh7763_shyway_clk = {
90 static struct clk *sh7763_onchip_clocks[] = {
101 struct clk *clk; arch_clk_init() local
106 clk = clk_get(NULL, "master_clk"); arch_clk_init()
108 struct clk *clkp = sh7763_onchip_clocks[i]; arch_clk_init()
110 clkp->parent = clk; arch_clk_init()
114 clk_put(clk); arch_clk_init()
|
| H A D | clock-sh7770.c | 22 static void master_clk_init(struct clk *clk) master_clk_init() argument
24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f]; master_clk_init()
31 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
34 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
41 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
44 return clk->parent->rate / bfc_divisors[idx]; bus_clk_recalc()
51 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
54 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| /linux-4.4.14/arch/mips/bcm63xx/ |
| H A D | clk.c | 12 #include <linux/clk.h>
19 struct clk { struct
20 void (*set)(struct clk *, int);
29 static void clk_enable_unlocked(struct clk *clk) clk_enable_unlocked() argument
31 if (clk->set && (clk->usage++) == 0) clk_enable_unlocked()
32 clk->set(clk, 1); clk_enable_unlocked()
35 static void clk_disable_unlocked(struct clk *clk) clk_disable_unlocked() argument
37 if (clk->set && (--clk->usage) == 0) clk_disable_unlocked()
38 clk->set(clk, 0); clk_disable_unlocked()
56 static void enet_misc_set(struct clk *clk, int enable) enet_misc_set() argument
72 static struct clk clk_enet_misc = {
80 static void enetx_set(struct clk *clk, int enable) enetx_set() argument
90 if (clk->id == 0) enetx_set()
98 static struct clk clk_enet0 = {
103 static struct clk clk_enet1 = {
111 static void ephy_set(struct clk *clk, int enable) ephy_set() argument
118 static struct clk clk_ephy = {
125 static void enetsw_set(struct clk *clk, int enable) enetsw_set() argument
148 static struct clk clk_enetsw = {
155 static void pcm_set(struct clk *clk, int enable) pcm_set() argument
163 static struct clk clk_pcm = {
170 static void usbh_set(struct clk *clk, int enable) usbh_set() argument
182 static struct clk clk_usbh = {
189 static void usbd_set(struct clk *clk, int enable) usbd_set() argument
199 static struct clk clk_usbd = {
206 static void spi_set(struct clk *clk, int enable) spi_set() argument
224 static struct clk clk_spi = {
231 static void hsspi_set(struct clk *clk, int enable) hsspi_set() argument
245 static struct clk clk_hsspi = {
253 static void xtm_set(struct clk *clk, int enable) xtm_set() argument
271 static struct clk clk_xtm = {
278 static void ipsec_set(struct clk *clk, int enable) ipsec_set() argument
286 static struct clk clk_ipsec = {
294 static void pcie_set(struct clk *clk, int enable) pcie_set() argument
302 static struct clk clk_pcie = {
309 static struct clk clk_periph = {
317 int clk_enable(struct clk *clk) clk_enable() argument
320 clk_enable_unlocked(clk); clk_enable()
327 void clk_disable(struct clk *clk) clk_disable() argument
330 clk_disable_unlocked(clk); clk_disable()
336 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
338 return clk->rate; clk_get_rate()
343 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
349 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
355 struct clk *clk_get(struct device *dev, const char *id) clk_get()
388 void clk_put(struct clk *clk) clk_put() argument
|
| /linux-4.4.14/arch/sh/kernel/ |
| H A D | localtimer.c | 35 struct clock_event_device *clk = this_cpu_ptr(&local_clockevent); local_timer_interrupt() local
38 clk->event_handler(clk); local_timer_interrupt()
44 struct clock_event_device *clk = &per_cpu(local_clockevent, cpu); local_timer_setup() local
46 clk->name = "dummy_timer"; local_timer_setup()
47 clk->features = CLOCK_EVT_FEAT_ONESHOT | local_timer_setup()
50 clk->rating = 400; local_timer_setup()
51 clk->mult = 1; local_timer_setup()
52 clk->broadcast = smp_timer_broadcast; local_timer_setup()
53 clk->cpumask = cpumask_of(cpu); local_timer_setup()
55 clockevents_register_device(clk); local_timer_setup()
|
| /linux-4.4.14/arch/arm/mach-ep93xx/ |
| H A D | clock.c | 16 #include <linux/clk.h>
30 struct clk { struct
31 struct clk *parent;
38 unsigned long (*get_rate)(struct clk *clk);
39 int (*set_rate)(struct clk *clk, unsigned long rate);
43 static unsigned long get_uart_rate(struct clk *clk);
45 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
46 static int set_div_rate(struct clk *clk, unsigned long rate);
47 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
48 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
50 static struct clk clk_xtali = {
53 static struct clk clk_uart1 = {
60 static struct clk clk_uart2 = {
67 static struct clk clk_uart3 = {
74 static struct clk clk_pll1 = {
77 static struct clk clk_f = {
80 static struct clk clk_h = {
83 static struct clk clk_p = {
86 static struct clk clk_pll2 = {
89 static struct clk clk_usb_host = {
94 static struct clk clk_keypad = {
101 static struct clk clk_spi = {
105 static struct clk clk_pwm = {
110 static struct clk clk_video = {
117 static struct clk clk_i2s_mclk = {
124 static struct clk clk_i2s_sclk = {
132 static struct clk clk_i2s_lrclk = {
141 static struct clk clk_m2p0 = {
146 static struct clk clk_m2p1 = {
151 static struct clk clk_m2p2 = {
156 static struct clk clk_m2p3 = {
161 static struct clk clk_m2p4 = {
166 static struct clk clk_m2p5 = {
171 static struct clk clk_m2p6 = {
176 static struct clk clk_m2p7 = {
181 static struct clk clk_m2p8 = {
186 static struct clk clk_m2p9 = {
191 static struct clk clk_m2m0 = {
196 static struct clk clk_m2m1 = {
203 { .dev_id = dev, .con_id = con, .clk = ck }
239 static void __clk_enable(struct clk *clk) __clk_enable() argument
241 if (!clk->users++) { __clk_enable()
242 if (clk->parent) __clk_enable()
243 __clk_enable(clk->parent); __clk_enable()
245 if (clk->enable_reg) { __clk_enable()
248 v = __raw_readl(clk->enable_reg); __clk_enable()
249 v |= clk->enable_mask; __clk_enable()
250 if (clk->sw_locked) __clk_enable()
251 ep93xx_syscon_swlocked_write(v, clk->enable_reg); __clk_enable()
253 __raw_writel(v, clk->enable_reg); __clk_enable()
258 int clk_enable(struct clk *clk) clk_enable() argument
262 if (!clk) clk_enable()
266 __clk_enable(clk); clk_enable()
273 static void __clk_disable(struct clk *clk) __clk_disable() argument
275 if (!--clk->users) { __clk_disable()
276 if (clk->enable_reg) { __clk_disable()
279 v = __raw_readl(clk->enable_reg); __clk_disable()
280 v &= ~clk->enable_mask; __clk_disable()
281 if (clk->sw_locked) __clk_disable()
282 ep93xx_syscon_swlocked_write(v, clk->enable_reg); __clk_disable()
284 __raw_writel(v, clk->enable_reg); __clk_disable()
287 if (clk->parent) __clk_disable()
288 __clk_disable(clk->parent); __clk_disable()
292 void clk_disable(struct clk *clk) clk_disable() argument
296 if (!clk) clk_disable()
300 __clk_disable(clk); clk_disable()
305 static unsigned long get_uart_rate(struct clk *clk) get_uart_rate() argument
307 unsigned long rate = clk_get_rate(clk->parent); get_uart_rate()
317 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
319 if (clk->get_rate) clk_get_rate()
320 return clk->get_rate(clk); clk_get_rate()
322 return clk->rate; clk_get_rate()
326 static int set_keytchclk_rate(struct clk *clk, unsigned long rate) set_keytchclk_rate() argument
331 val = __raw_readl(clk->enable_reg); set_keytchclk_rate()
340 div_bit = clk->enable_mask >> 15; set_keytchclk_rate()
349 ep93xx_syscon_swlocked_write(val, clk->enable_reg); set_keytchclk_rate()
350 clk->rate = rate; set_keytchclk_rate()
354 static int calc_clk_div(struct clk *clk, unsigned long rate, calc_clk_div() argument
357 struct clk *mclk; calc_clk_div()
396 clk->parent = mclk; calc_clk_div()
397 clk->rate = actual_rate; calc_clk_div()
410 static int set_div_rate(struct clk *clk, unsigned long rate) set_div_rate() argument
415 err = calc_clk_div(clk, rate, &psel, &esel, &pdiv, &div); set_div_rate()
420 val = __raw_readl(clk->enable_reg); set_div_rate()
427 ep93xx_syscon_swlocked_write(val, clk->enable_reg); set_div_rate()
431 static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate) set_i2s_sclk_rate() argument
433 unsigned val = __raw_readl(clk->enable_reg); set_i2s_sclk_rate()
437 clk->enable_reg); set_i2s_sclk_rate()
440 clk->enable_reg); set_i2s_sclk_rate()
448 static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate) set_i2s_lrclk_rate() argument
450 unsigned val = __raw_readl(clk->enable_reg) & set_i2s_lrclk_rate()
455 clk->enable_reg); set_i2s_lrclk_rate()
458 clk->enable_reg); set_i2s_lrclk_rate()
461 clk->enable_reg); set_i2s_lrclk_rate()
469 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
471 if (clk->set_rate) clk_set_rate()
472 return clk->set_rate(clk, rate); clk_set_rate()
|
| /linux-4.4.14/drivers/cpufreq/ |
| H A D | ls1x-cpufreq.c | 11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
25 struct clk *clk; /* CPU clk */ member in struct:__anon3808
26 struct clk *mux_clk; /* MUX of CPU clk */
27 struct clk *pll_clk; /* PLL clk */
28 struct clk *osc_clk; /* OSC clk */
55 * The procedure of reconfiguring CPU clk is as below. ls1x_cpufreq_target()
57 * - Reparent CPU clk to OSC clk ls1x_cpufreq_target()
60 * - Reparent CPU clk back to CPU DIV clk ls1x_cpufreq_target()
64 clk_set_parent(policy->clk, ls1x_cpufreq.osc_clk); ls1x_cpufreq_target()
70 clk_set_parent(policy->clk, ls1x_cpufreq.mux_clk); ls1x_cpufreq_target()
105 policy->clk = ls1x_cpufreq.clk; ls1x_cpufreq_init()
142 struct clk *clk; ls1x_cpufreq_probe() local
150 clk = devm_clk_get(&pdev->dev, pdata->clk_name); ls1x_cpufreq_probe()
151 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
154 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
157 ls1x_cpufreq.clk = clk; ls1x_cpufreq_probe()
159 clk = clk_get_parent(clk); ls1x_cpufreq_probe()
160 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
162 __clk_get_name(ls1x_cpufreq.clk)); ls1x_cpufreq_probe()
163 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
166 ls1x_cpufreq.mux_clk = clk; ls1x_cpufreq_probe()
168 clk = clk_get_parent(clk); ls1x_cpufreq_probe()
169 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
172 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
175 ls1x_cpufreq.pll_clk = clk; ls1x_cpufreq_probe()
177 clk = devm_clk_get(&pdev->dev, pdata->osc_clk_name); ls1x_cpufreq_probe()
178 if (IS_ERR(clk)) { ls1x_cpufreq_probe()
181 ret = PTR_ERR(clk); ls1x_cpufreq_probe()
184 ls1x_cpufreq.osc_clk = clk; ls1x_cpufreq_probe()
|
| /linux-4.4.14/arch/mips/lantiq/xway/ |
| H A D | clk.c | 12 #include <linux/clk.h>
20 #include "../clk.h"
59 unsigned long clk; ltq_danube_pp32_hz() local
63 clk = CLOCK_240M; ltq_danube_pp32_hz()
66 clk = CLOCK_222M; ltq_danube_pp32_hz()
69 clk = CLOCK_133M; ltq_danube_pp32_hz()
72 clk = CLOCK_266M; ltq_danube_pp32_hz()
76 return clk; ltq_danube_pp32_hz()
107 unsigned long clk; ltq_vr9_cpu_hz() local
113 clk = CLOCK_600M; ltq_vr9_cpu_hz()
116 clk = CLOCK_500M; ltq_vr9_cpu_hz()
119 clk = CLOCK_393M; ltq_vr9_cpu_hz()
122 clk = CLOCK_333M; ltq_vr9_cpu_hz()
126 clk = CLOCK_196_608M; ltq_vr9_cpu_hz()
129 clk = CLOCK_167M; ltq_vr9_cpu_hz()
134 clk = CLOCK_125M; ltq_vr9_cpu_hz()
137 clk = 0; ltq_vr9_cpu_hz()
141 return clk; ltq_vr9_cpu_hz()
147 unsigned long clk; ltq_vr9_fpi_hz() local
155 clk = cpu_clk; ltq_vr9_fpi_hz()
159 clk = cpu_clk / 2; ltq_vr9_fpi_hz()
163 clk = (cpu_clk * 2) / 5; ltq_vr9_fpi_hz()
167 clk = cpu_clk / 3; ltq_vr9_fpi_hz()
170 clk = 0; ltq_vr9_fpi_hz()
174 return clk; ltq_vr9_fpi_hz()
180 unsigned long clk; ltq_vr9_pp32_hz() local
184 clk = CLOCK_500M; ltq_vr9_pp32_hz()
187 clk = CLOCK_432M; ltq_vr9_pp32_hz()
190 clk = CLOCK_288M; ltq_vr9_pp32_hz()
193 clk = CLOCK_500M; ltq_vr9_pp32_hz()
197 return clk; ltq_vr9_pp32_hz()
252 unsigned long clk; ltq_ar10_pp32_hz() local
256 clk = CLOCK_250M; ltq_ar10_pp32_hz()
259 clk = CLOCK_400M; ltq_ar10_pp32_hz()
262 clk = CLOCK_250M; ltq_ar10_pp32_hz()
266 return clk; ltq_ar10_pp32_hz()
336 unsigned long clk; ltq_grx390_pp32_hz() local
340 clk = CLOCK_250M; ltq_grx390_pp32_hz()
343 clk = CLOCK_432M; ltq_grx390_pp32_hz()
346 clk = CLOCK_400M; ltq_grx390_pp32_hz()
349 clk = CLOCK_250M; ltq_grx390_pp32_hz()
352 return clk; ltq_grx390_pp32_hz()
|
| H A D | Makefile | 1 obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o dcdc.o
|
| H A D | gptu.c | 17 #include "../clk.h"
96 static int gptu_enable(struct clk *clk) gptu_enable() argument
98 int ret = request_irq(irqres[clk->bits].start, timer_irq_handler, gptu_enable()
106 GPTU_CON(clk->bits)); gptu_enable()
107 gptu_w32(1, GPTU_RLD(clk->bits)); gptu_enable()
108 gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN); gptu_enable()
109 gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits)); gptu_enable()
113 static void gptu_disable(struct clk *clk) gptu_disable() argument
115 gptu_w32(0, GPTU_RUN(clk->bits)); gptu_disable()
116 gptu_w32(0, GPTU_CON(clk->bits)); gptu_disable()
117 gptu_w32(0, GPTU_RLD(clk->bits)); gptu_disable()
118 gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN); gptu_disable()
119 free_irq(irqres[clk->bits].start, NULL); gptu_disable()
125 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_gptu() local
127 clk->cl.dev_id = dev_name(dev); clkdev_add_gptu()
128 clk->cl.con_id = con; clkdev_add_gptu()
129 clk->cl.clk = clk; clkdev_add_gptu()
130 clk->enable = gptu_enable; clkdev_add_gptu()
131 clk->disable = gptu_disable; clkdev_add_gptu()
132 clk->bits = timer; clkdev_add_gptu()
133 clkdev_add(&clk->cl); clkdev_add_gptu()
138 struct clk *clk; gptu_probe() local
154 clk = clk_get(&pdev->dev, NULL); gptu_probe()
155 if (IS_ERR(clk)) { gptu_probe()
159 clk_enable(clk); gptu_probe()
168 clk_disable(clk); gptu_probe()
169 clk_put(clk); gptu_probe()
|
| H A D | sysctrl.c | 20 #include "../clk.h"
196 static int cgu_enable(struct clk *clk) cgu_enable() argument
198 ltq_cgu_w32(ltq_cgu_r32(ifccr) | clk->bits, ifccr); cgu_enable()
203 static void cgu_disable(struct clk *clk) cgu_disable() argument
205 ltq_cgu_w32(ltq_cgu_r32(ifccr) & ~clk->bits, ifccr); cgu_disable()
209 static int pmu_enable(struct clk *clk) pmu_enable() argument
215 pmu_w32(clk->bits, PWDCR_EN_XRX(clk->module)); pmu_enable()
217 (!(pmu_r32(PWDSR_XRX(clk->module)) & clk->bits))); pmu_enable()
221 pmu_w32(pmu_r32(PWDCR(clk->module)) & ~clk->bits, pmu_enable()
222 PWDCR(clk->module)); pmu_enable()
224 (pmu_r32(PWDSR(clk->module)) & clk->bits)); pmu_enable()
235 static void pmu_disable(struct clk *clk) pmu_disable() argument
241 pmu_w32(clk->bits, PWDCR_DIS_XRX(clk->module)); pmu_disable()
243 (pmu_r32(PWDSR_XRX(clk->module)) & clk->bits)); pmu_disable()
246 pmu_w32(pmu_r32(PWDCR(clk->module)) | clk->bits, pmu_disable()
247 PWDCR(clk->module)); pmu_disable()
249 (!(pmu_r32(PWDSR(clk->module)) & clk->bits))); pmu_disable()
258 static int pci_enable(struct clk *clk) pci_enable() argument
265 if (clk->rate == CLOCK_33M) pci_enable()
271 if (clk->rate == CLOCK_33M) pci_enable()
277 pmu_enable(clk); pci_enable()
282 static int pci_ext_enable(struct clk *clk) pci_ext_enable() argument
290 static void pci_ext_disable(struct clk *clk) pci_ext_disable() argument
307 static int clkout_enable(struct clk *clk) clkout_enable() argument
313 if (clk->rates[i] == clk->rate) { clkout_enable()
314 int shift = 14 - (2 * clk->module); clkout_enable()
315 int enable = 7 - clk->module; clkout_enable()
332 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_pmu() local
334 clk->cl.dev_id = dev; clkdev_add_pmu()
335 clk->cl.con_id = con; clkdev_add_pmu()
336 clk->cl.clk = clk; clkdev_add_pmu()
337 clk->enable = pmu_enable; clkdev_add_pmu()
338 clk->disable = pmu_disable; clkdev_add_pmu()
339 clk->module = module; clkdev_add_pmu()
340 clk->bits = bits; clkdev_add_pmu()
346 pmu_disable(clk); clkdev_add_pmu()
348 clkdev_add(&clk->cl); clkdev_add_pmu()
355 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_cgu() local
357 clk->cl.dev_id = dev; clkdev_add_cgu()
358 clk->cl.con_id = con; clkdev_add_cgu()
359 clk->cl.clk = clk; clkdev_add_cgu()
360 clk->enable = cgu_enable; clkdev_add_cgu()
361 clk->disable = cgu_disable; clkdev_add_cgu()
362 clk->bits = bits; clkdev_add_cgu()
363 clkdev_add(&clk->cl); clkdev_add_cgu()
371 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_pci() local
372 struct clk *clk_ext = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_pci()
375 clk->cl.dev_id = "17000000.pci"; clkdev_add_pci()
376 clk->cl.con_id = NULL; clkdev_add_pci()
377 clk->cl.clk = clk; clkdev_add_pci()
378 clk->rate = CLOCK_33M; clkdev_add_pci()
379 clk->rates = valid_pci_rates; clkdev_add_pci()
380 clk->enable = pci_enable; clkdev_add_pci()
381 clk->disable = pmu_disable; clkdev_add_pci()
382 clk->module = 0; clkdev_add_pci()
383 clk->bits = PMU_PCI; clkdev_add_pci()
384 clkdev_add(&clk->cl); clkdev_add_pci()
389 clk_ext->cl.clk = clk_ext; clkdev_add_pci()
408 struct clk *clk; clkdev_add_clkout() local
414 clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_clkout()
415 clk->cl.dev_id = "1f103000.cgu"; clkdev_add_clkout()
416 clk->cl.con_id = name; clkdev_add_clkout()
417 clk->cl.clk = clk; clkdev_add_clkout()
418 clk->rate = 0; clkdev_add_clkout()
419 clk->rates = valid_clkout_rates[i]; clkdev_add_clkout()
420 clk->enable = clkout_enable; clkdev_add_clkout()
421 clk->module = i; clkdev_add_clkout()
422 clkdev_add(&clk->cl); clkdev_add_clkout()
|
| /linux-4.4.14/arch/mips/lantiq/falcon/ |
| H A D | sysctrl.c | 18 #include "../clk.h"
82 static inline void sysctl_wait(struct clk *clk, sysctl_wait() argument
87 do {} while (--err && ((sysctl_r32(clk->module, reg) sysctl_wait()
88 & clk->bits) != test)); sysctl_wait()
91 clk->module, clk->bits, test, sysctl_wait()
92 sysctl_r32(clk->module, reg) & clk->bits); sysctl_wait()
95 static int sysctl_activate(struct clk *clk) sysctl_activate() argument
97 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); sysctl_activate()
98 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_activate()
99 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); sysctl_activate()
103 static void sysctl_deactivate(struct clk *clk) sysctl_deactivate() argument
105 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); sysctl_deactivate()
106 sysctl_w32(clk->module, clk->bits, SYSCTL_DEACT); sysctl_deactivate()
107 sysctl_wait(clk, 0, SYSCTL_ACTS); sysctl_deactivate()
110 static int sysctl_clken(struct clk *clk) sysctl_clken() argument
112 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKEN); sysctl_clken()
113 sysctl_w32(clk->module, clk->bits, SYSCTL_ACT); sysctl_clken()
114 sysctl_wait(clk, clk->bits, SYSCTL_CLKS); sysctl_clken()
118 static void sysctl_clkdis(struct clk *clk) sysctl_clkdis() argument
120 sysctl_w32(clk->module, clk->bits, SYSCTL_CLKCLR); sysctl_clkdis()
121 sysctl_wait(clk, 0, SYSCTL_CLKS); sysctl_clkdis()
124 static void sysctl_reboot(struct clk *clk) sysctl_reboot() argument
129 act = sysctl_r32(clk->module, SYSCTL_ACT); sysctl_reboot()
130 bits = ~act & clk->bits; sysctl_reboot()
132 sysctl_w32(clk->module, bits, SYSCTL_CLKEN); sysctl_reboot()
133 sysctl_w32(clk->module, bits, SYSCTL_ACT); sysctl_reboot()
134 sysctl_wait(clk, bits, SYSCTL_ACTS); sysctl_reboot()
136 sysctl_w32(clk->module, act & clk->bits, SYSCTL_RBT); sysctl_reboot()
137 sysctl_wait(clk, clk->bits, SYSCTL_ACTS); sysctl_reboot()
170 struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL); clkdev_add_sys() local
172 clk->cl.dev_id = dev; clkdev_add_sys()
173 clk->cl.con_id = NULL; clkdev_add_sys()
174 clk->cl.clk = clk; clkdev_add_sys()
175 clk->module = module; clkdev_add_sys()
176 clk->bits = bits; clkdev_add_sys()
177 clk->activate = sysctl_activate; clkdev_add_sys()
178 clk->deactivate = sysctl_deactivate; clkdev_add_sys()
179 clk->enable = sysctl_clken; clkdev_add_sys()
180 clk->disable = sysctl_clkdis; clkdev_add_sys()
181 clk->reboot = sysctl_reboot; clkdev_add_sys()
182 clkdev_add(&clk->cl); clkdev_add_sys()
|
| /linux-4.4.14/include/asm-generic/ |
| H A D | clkdev.h | 11 * Helper for the clk API to assist looking up a struct clk.
19 struct clk;
21 static inline int __clk_get(struct clk *clk) { return 1; } __clk_put() argument
22 static inline void __clk_put(struct clk *clk) { } __clk_put() argument
|
| /linux-4.4.14/drivers/clk/tegra/ |
| H A D | clk-tegra-fixed.c | 18 #include <linux/clk-provider.h>
23 #include <linux/clk/tegra.h>
25 #include "clk.h"
26 #include "clk-id.h"
37 struct clk *clk, *osc; tegra_osc_clk_init() local
38 struct clk **dt_clk; tegra_osc_clk_init()
62 clk = clk_register_fixed_factor(NULL, "clk_m", "osc", tegra_osc_clk_init()
64 *dt_clk = clk; tegra_osc_clk_init()
73 clk = clk_register_fixed_factor(NULL, "pll_ref", "osc", tegra_osc_clk_init()
75 *dt_clk = clk; tegra_osc_clk_init()
85 struct clk *clk; tegra_fixed_clk_init() local
86 struct clk **dt_clk; tegra_fixed_clk_init()
91 clk = clk_register_fixed_rate(NULL, "clk_32k", NULL, tegra_fixed_clk_init()
93 *dt_clk = clk; tegra_fixed_clk_init()
99 clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m", tegra_fixed_clk_init()
101 *dt_clk = clk; tegra_fixed_clk_init()
107 clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m", tegra_fixed_clk_init()
109 *dt_clk = clk; tegra_fixed_clk_init()
|
| H A D | clk-tegra-super-gen4.c | 18 #include <linux/clk-provider.h>
23 #include <linux/clk/tegra.h>
25 #include "clk.h"
26 #include "clk-id.h"
57 struct clk *clk; tegra_sclk_init() local
58 struct clk **dt_clk; tegra_sclk_init()
63 clk = tegra_clk_register_super_mux("sclk", sclk_parents, tegra_sclk_init()
68 *dt_clk = clk; tegra_sclk_init()
74 clk = clk_register_divider(NULL, "hclk_div", "sclk", 0, tegra_sclk_init()
77 clk = clk_register_gate(NULL, "hclk", "hclk_div", tegra_sclk_init()
81 *dt_clk = clk; tegra_sclk_init()
89 clk = clk_register_divider(NULL, "pclk_div", "hclk", 0, tegra_sclk_init()
92 clk = clk_register_gate(NULL, "pclk", "pclk_div", CLK_SET_RATE_PARENT | tegra_sclk_init()
95 *dt_clk = clk; tegra_sclk_init()
103 struct clk *clk; tegra_super_clk_gen4_init() local
104 struct clk **dt_clk; tegra_super_clk_gen4_init()
109 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, tegra_super_clk_gen4_init()
114 *dt_clk = clk; tegra_super_clk_gen4_init()
120 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents, tegra_super_clk_gen4_init()
125 *dt_clk = clk; tegra_super_clk_gen4_init()
136 clk = tegra_clk_register_pllxc("pll_x", "pll_ref", clk_base, tegra_super_clk_gen4_init()
138 *dt_clk = clk; tegra_super_clk_gen4_init()
145 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x", tegra_super_clk_gen4_init()
147 *dt_clk = clk; tegra_super_clk_gen4_init()
|
| H A D | clk-tegra-pmc.c | 18 #include <linux/clk-provider.h>
24 #include <linux/clk/tegra.h>
26 #include "clk.h"
27 #include "clk-id.h"
84 struct clk *clk; tegra_pmc_clk_init() local
85 struct clk **dt_clk; tegra_pmc_clk_init()
97 clk = clk_register_mux(NULL, data->mux_name, data->parents, tegra_pmc_clk_init()
101 *dt_clk = clk; tegra_pmc_clk_init()
108 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, tegra_pmc_clk_init()
111 *dt_clk = clk; tegra_pmc_clk_init()
112 clk_register_clkdev(clk, data->dev_name, data->gate_name); tegra_pmc_clk_init()
117 clk = clk_register_gate(NULL, "blink_override", "clk_32k", 0, tegra_pmc_clk_init()
125 clk = clk_register_gate(NULL, "blink", "blink_override", 0, tegra_pmc_clk_init()
128 clk_register_clkdev(clk, "blink", NULL); tegra_pmc_clk_init()
129 *dt_clk = clk; tegra_pmc_clk_init()
|
| H A D | clk-tegra-audio.c | 18 #include <linux/clk-provider.h>
23 #include <linux/clk/tegra.h>
25 #include "clk.h"
26 #include "clk-id.h"
131 struct clk *clk; tegra_audio_clk_init() local
132 struct clk **dt_clk; tegra_audio_clk_init()
146 clk = tegra_clk_register_pll(info->name, info->parent, tegra_audio_clk_init()
149 *dt_clk = clk; tegra_audio_clk_init()
156 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a", tegra_audio_clk_init()
159 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div", tegra_audio_clk_init()
162 *dt_clk = clk; tegra_audio_clk_init()
174 clk = tegra_clk_register_sync_source(data->name, tegra_audio_clk_init()
176 *dt_clk = clk; tegra_audio_clk_init()
187 clk = clk_register_mux(NULL, data->mux_name, mux_audio_sync_clk, tegra_audio_clk_init()
192 *dt_clk = clk; tegra_audio_clk_init()
198 clk = clk_register_gate(NULL, data->gate_name, data->mux_name, tegra_audio_clk_init()
201 *dt_clk = clk; tegra_audio_clk_init()
212 clk = clk_register_fixed_factor(NULL, data->name_2x, tegra_audio_clk_init()
214 clk = tegra_clk_register_divider(data->div_name, tegra_audio_clk_init()
218 clk = tegra_clk_register_periph_gate(data->gate_name, tegra_audio_clk_init()
222 *dt_clk = clk; tegra_audio_clk_init()
|
| /linux-4.4.14/drivers/clk/mediatek/ |
| H A D | clk-mtk.c | 24 #include "clk-mtk.h"
25 #include "clk-gate.h"
56 struct clk *clk; mtk_clk_register_fixed_clks() local
61 clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, mtk_clk_register_fixed_clks()
64 if (IS_ERR(clk)) { mtk_clk_register_fixed_clks()
65 pr_err("Failed to register clk %s: %ld\n", mtk_clk_register_fixed_clks()
66 rc->name, PTR_ERR(clk)); mtk_clk_register_fixed_clks()
71 clk_data->clks[rc->id] = clk; mtk_clk_register_fixed_clks()
79 struct clk *clk; mtk_clk_register_factors() local
84 clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name, mtk_clk_register_factors()
87 if (IS_ERR(clk)) { mtk_clk_register_factors()
88 pr_err("Failed to register clk %s: %ld\n", mtk_clk_register_factors()
89 ff->name, PTR_ERR(clk)); mtk_clk_register_factors()
94 clk_data->clks[ff->id] = clk; mtk_clk_register_factors()
103 struct clk *clk; mtk_clk_register_gates() local
119 clk = mtk_clk_register_gate(gate->name, gate->parent_name, mtk_clk_register_gates()
126 if (IS_ERR(clk)) { mtk_clk_register_gates()
127 pr_err("Failed to register clk %s: %ld\n", mtk_clk_register_gates()
128 gate->name, PTR_ERR(clk)); mtk_clk_register_gates()
132 clk_data->clks[gate->id] = clk; mtk_clk_register_gates()
138 struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc, mtk_clk_register_composite()
141 struct clk *clk; mtk_clk_register_composite() local
205 clk = clk_register_composite(NULL, mc->name, parent_names, num_parents, mtk_clk_register_composite()
211 if (IS_ERR(clk)) { mtk_clk_register_composite()
216 return clk; mtk_clk_register_composite()
227 struct clk *clk; mtk_clk_register_composites() local
233 clk = mtk_clk_register_composite(mc, base, lock); mtk_clk_register_composites()
235 if (IS_ERR(clk)) { mtk_clk_register_composites()
236 pr_err("Failed to register clk %s: %ld\n", mtk_clk_register_composites()
237 mc->name, PTR_ERR(clk)); mtk_clk_register_composites()
242 clk_data->clks[mc->id] = clk; mtk_clk_register_composites()
|
| /linux-4.4.14/drivers/clk/meson/ |
| H A D | clkc.c | 18 #include <linux/clk-provider.h>
26 static struct clk **clks;
29 struct clk ** __init meson_clk_init(struct device_node *np, meson_clk_init()
43 static void meson_clk_add_lookup(struct clk *clk, unsigned int id) meson_clk_add_lookup() argument
46 clks[id] = clk; meson_clk_add_lookup()
49 static struct clk * __init meson_clk_register_composite()
53 struct clk *clk; meson_clk_register_composite() local
81 clk = ERR_PTR(-ENOMEM); meson_clk_register_composite()
97 clk = ERR_PTR(-ENOMEM); meson_clk_register_composite()
108 clk = clk_register_composite(NULL, clk_conf->clk_name, meson_clk_register_composite()
115 if (IS_ERR(clk)) meson_clk_register_composite()
118 return clk; meson_clk_register_composite()
125 return clk; meson_clk_register_composite()
128 static struct clk * __init meson_clk_register_fixed_factor()
132 struct clk *clk; meson_clk_register_fixed_factor() local
161 clk = clk_register_fixed_factor(NULL, meson_clk_register_fixed_factor()
167 return clk; meson_clk_register_fixed_factor()
170 static struct clk * __init meson_clk_register_fixed_rate()
174 struct clk *clk; meson_clk_register_fixed_rate() local
191 clk = clk_register_fixed_rate(NULL, meson_clk_register_fixed_rate()
197 return clk; meson_clk_register_fixed_rate()
205 struct clk *clk = NULL; meson_clk_register_clks() local
212 clk = meson_clk_register_fixed_rate(clk_conf, meson_clk_register_clks()
216 clk = meson_clk_register_fixed_factor(clk_conf, meson_clk_register_clks()
220 clk = meson_clk_register_composite(clk_conf, meson_clk_register_clks()
224 clk = meson_clk_register_cpu(clk_conf, clk_base, meson_clk_register_clks()
228 clk = meson_clk_register_pll(clk_conf, clk_base, meson_clk_register_clks()
232 clk = NULL; meson_clk_register_clks()
235 if (!clk) { meson_clk_register_clks()
241 if (IS_ERR(clk)) { meson_clk_register_clks()
247 meson_clk_add_lookup(clk, clk_conf->clk_id); meson_clk_register_clks()
|
| /linux-4.4.14/arch/mips/pistachio/ |
| H A D | time.c | 11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
39 struct clk *clk; plat_time_init() local
50 clk = of_clk_get(np, 0); plat_time_init()
51 if (IS_ERR(clk)) { plat_time_init()
52 pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk)); plat_time_init()
56 mips_hpt_frequency = clk_get_rate(clk) / 2; plat_time_init()
57 clk_put(clk); plat_time_init()
|
| /linux-4.4.14/include/media/ |
| H A D | v4l2-clk.h | 25 struct clk;
33 struct clk *clk; member in struct:v4l2_clk
39 int (*enable)(struct v4l2_clk *clk);
40 void (*disable)(struct v4l2_clk *clk);
41 unsigned long (*get_rate)(struct v4l2_clk *clk);
42 int (*set_rate)(struct v4l2_clk *clk, unsigned long);
48 void v4l2_clk_unregister(struct v4l2_clk *clk);
50 void v4l2_clk_put(struct v4l2_clk *clk);
51 int v4l2_clk_enable(struct v4l2_clk *clk);
52 void v4l2_clk_disable(struct v4l2_clk *clk);
53 unsigned long v4l2_clk_get_rate(struct v4l2_clk *clk);
54 int v4l2_clk_set_rate(struct v4l2_clk *clk, unsigned long rate);
60 void v4l2_clk_unregister_fixed(struct v4l2_clk *clk);
|
| /linux-4.4.14/drivers/clk/bcm/ |
| H A D | clk-iproc-asiu.c | 16 #include <linux/clk-provider.h>
23 #include "clk-iproc.h"
48 struct iproc_asiu_clk *clk = to_asiu_clk(hw); iproc_asiu_clk_enable() local
49 struct iproc_asiu *asiu = clk->asiu; iproc_asiu_clk_enable()
53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); iproc_asiu_clk_enable()
57 val |= (1 << clk->gate.en_shift); iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); iproc_asiu_clk_enable()
65 struct iproc_asiu_clk *clk = to_asiu_clk(hw); iproc_asiu_clk_disable() local
66 struct iproc_asiu *asiu = clk->asiu; iproc_asiu_clk_disable()
70 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) iproc_asiu_clk_disable()
73 val = readl(asiu->gate_base + clk->gate.offset); iproc_asiu_clk_disable()
74 val &= ~(1 << clk->gate.en_shift); iproc_asiu_clk_disable()
75 writel(val, asiu->gate_base + clk->gate.offset); iproc_asiu_clk_disable()
81 struct iproc_asiu_clk *clk = to_asiu_clk(hw); iproc_asiu_clk_recalc_rate() local
82 struct iproc_asiu *asiu = clk->asiu; iproc_asiu_clk_recalc_rate()
87 clk->rate = 0; iproc_asiu_clk_recalc_rate()
92 val = readl(asiu->div_base + clk->div.offset); iproc_asiu_clk_recalc_rate()
93 if ((val & (1 << clk->div.en_shift)) == 0) { iproc_asiu_clk_recalc_rate()
94 clk->rate = parent_rate; iproc_asiu_clk_recalc_rate()
99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); iproc_asiu_clk_recalc_rate()
101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); iproc_asiu_clk_recalc_rate()
104 clk->rate = parent_rate / (div_h + div_l); iproc_asiu_clk_recalc_rate()
106 __func__, clk->rate, parent_rate, div_h, div_l); iproc_asiu_clk_recalc_rate()
108 return clk->rate; iproc_asiu_clk_recalc_rate()
132 struct iproc_asiu_clk *clk = to_asiu_clk(hw); iproc_asiu_clk_set_rate() local
133 struct iproc_asiu *asiu = clk->asiu; iproc_asiu_clk_set_rate()
142 val = readl(asiu->div_base + clk->div.offset); iproc_asiu_clk_set_rate()
143 val &= ~(1 << clk->div.en_shift); iproc_asiu_clk_set_rate()
144 writel(val, asiu->div_base + clk->div.offset); iproc_asiu_clk_set_rate()
156 val = readl(asiu->div_base + clk->div.offset); iproc_asiu_clk_set_rate()
157 val |= 1 << clk->div.en_shift; iproc_asiu_clk_set_rate()
159 val &= ~(bit_mask(clk->div.high_width) iproc_asiu_clk_set_rate()
160 << clk->div.high_shift); iproc_asiu_clk_set_rate()
161 val |= div_h << clk->div.high_shift; iproc_asiu_clk_set_rate()
163 val &= ~(bit_mask(clk->div.high_width) iproc_asiu_clk_set_rate()
164 << clk->div.high_shift); iproc_asiu_clk_set_rate()
167 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); iproc_asiu_clk_set_rate()
168 val |= div_l << clk->div.low_shift; iproc_asiu_clk_set_rate()
170 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); iproc_asiu_clk_set_rate()
172 writel(val, asiu->div_base + clk->div.offset); iproc_asiu_clk_set_rate()
220 struct clk *clk; iproc_asiu_setup() local
243 clk = clk_register(NULL, &asiu_clk->hw); iproc_asiu_setup()
244 if (WARN_ON(IS_ERR(clk))) iproc_asiu_setup()
246 asiu->clk_data.clks[i] = clk; iproc_asiu_setup()
|
| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| H A D | rockchip,rk808.h | 2 * This header provides constants clk index RK808 pmic clkout
|
| H A D | stih415-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| H A D | stih416-clks.h | 2 * This header provides constants clk index STMicroelectronics
|
| /linux-4.4.14/drivers/rtc/ |
| H A D | rtc-sa1100.h | 6 struct clk;
18 struct clk *clk; member in struct:sa1100_rtc
|
| H A D | rtc-coh901331.c | 12 #include <linux/clk.h>
45 struct clk *clk; member in struct:coh901331_port
57 clk_enable(rtap->clk); coh901331_interrupt()
68 clk_disable(rtap->clk); coh901331_interrupt()
80 clk_enable(rtap->clk); coh901331_read_time()
84 clk_disable(rtap->clk); coh901331_read_time()
87 clk_disable(rtap->clk); coh901331_read_time()
95 clk_enable(rtap->clk); coh901331_set_mmss()
97 clk_disable(rtap->clk); coh901331_set_mmss()
106 clk_enable(rtap->clk); coh901331_read_alarm()
110 clk_disable(rtap->clk); coh901331_read_alarm()
121 clk_enable(rtap->clk); coh901331_set_alarm()
124 clk_disable(rtap->clk); coh901331_set_alarm()
133 clk_enable(rtap->clk); coh901331_alarm_irq_enable()
138 clk_disable(rtap->clk); coh901331_alarm_irq_enable()
156 clk_unprepare(rtap->clk); coh901331_remove()
183 rtap->clk = devm_clk_get(&pdev->dev, NULL); coh901331_probe()
184 if (IS_ERR(rtap->clk)) { coh901331_probe()
185 ret = PTR_ERR(rtap->clk); coh901331_probe()
191 ret = clk_prepare_enable(rtap->clk); coh901331_probe()
196 clk_disable(rtap->clk); coh901331_probe()
209 clk_unprepare(rtap->clk); coh901331_probe()
226 clk_enable(rtap->clk); coh901331_suspend()
229 clk_disable(rtap->clk); coh901331_suspend()
231 clk_unprepare(rtap->clk); coh901331_suspend()
239 clk_prepare(rtap->clk); coh901331_resume()
243 clk_enable(rtap->clk); coh901331_resume()
245 clk_disable(rtap->clk); coh901331_resume()
257 clk_enable(rtap->clk); coh901331_shutdown()
259 clk_disable_unprepare(rtap->clk); coh901331_shutdown()
|
| /linux-4.4.14/arch/sh/kernel/cpu/sh2a/ |
| H A D | clock-sh7201.c | 27 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate = 10000000 * pll2_mult * master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
40 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
47 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
50 return clk->parent->rate / pfc_divisors[idx]; bus_clk_recalc()
57 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
60 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7206.c | 27 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
39 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
48 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7203.c | 30 static void master_clk_init(struct clk *clk) master_clk_init() argument
32 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; master_clk_init()
39 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
52 return clk->parent->rate / pfc_divisors[idx-2]; bus_clk_recalc()
|
| /linux-4.4.14/arch/sh/kernel/cpu/sh3/ |
| H A D | clock-sh3.c | 29 static void master_clk_init(struct clk *clk) master_clk_init() argument
34 clk->rate *= pfc_divisors[idx]; master_clk_init()
41 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
46 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
53 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
58 return clk->parent->rate / stc_multipliers[idx]; bus_clk_recalc()
65 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
70 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7705.c | 33 static void master_clk_init(struct clk *clk) master_clk_init() argument
35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; master_clk_init()
42 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
45 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
52 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
55 return clk->parent->rate / stc_multipliers[idx]; bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
65 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7706.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
54 return clk->parent->rate / stc_multipliers[idx]; bus_clk_recalc()
61 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
66 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7709.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
30 clk->rate *= pfc_divisors[idx]; master_clk_init()
37 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
42 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
49 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
55 return clk->parent->rate * stc_multipliers[idx]; bus_clk_recalc()
62 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
67 return clk->parent->rate / ifc_divisors[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7710.c | 27 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
39 return clk->parent->rate / md_table[idx]; module_clk_recalc()
46 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
49 return clk->parent->rate / md_table[idx]; bus_clk_recalc()
56 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
59 return clk->parent->rate / md_table[idx]; cpu_clk_recalc()
|
| H A D | clock-sh7712.c | 24 static void master_clk_init(struct clk *clk) master_clk_init() argument
29 clk->rate *= multipliers[idx]; master_clk_init()
36 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
41 return clk->parent->rate / divisors[idx]; module_clk_recalc()
48 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
53 return clk->parent->rate / divisors[idx]; cpu_clk_recalc()
|
| /linux-4.4.14/arch/sh/kernel/cpu/sh5/ |
| H A D | clock-sh5.c | 25 static void master_clk_init(struct clk *clk) master_clk_init() argument
28 clk->rate *= ifc_table[idx]; master_clk_init()
35 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
38 return clk->parent->rate / ifc_table[idx]; module_clk_recalc()
45 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
48 return clk->parent->rate / ifc_table[idx]; bus_clk_recalc()
55 static unsigned long cpu_clk_recalc(struct clk *clk) cpu_clk_recalc() argument
58 return clk->parent->rate / ifc_table[idx]; cpu_clk_recalc()
|
| /linux-4.4.14/arch/arm/mach-omap2/ |
| H A D | clock3xxx.h | 12 int omap3_core_dpll_m2_set_rate(struct clk_hw *clk, unsigned long rate,
15 extern struct clk *sdrc_ick_p;
16 extern struct clk *arm_fck_p;
|
| H A D | omap_hwmod_33xx_43xx_interconnect_data.c | 25 .clk = "dpll_mpu_m2_ck",
33 .clk = "l3s_gclk",
41 .clk = "l3s_gclk",
49 .clk = "l3s_gclk",
57 .clk = "l3s_gclk",
65 .clk = "dpll_mpu_m2_ck",
73 .clk = "l3s_gclk",
81 .clk = "l3_gclk",
89 .clk = "dpll_core_m4_ck",
97 .clk = "dpll_core_m4_ck",
105 .clk = "clkdiv32k_ick",
113 .clk = "l4ls_gclk",
121 .clk = "l4ls_gclk",
129 .clk = "l4ls_gclk",
137 .clk = "l4ls_gclk",
145 .clk = "l4ls_gclk",
158 .clk = "l4ls_gclk",
174 .clk = "l4ls_gclk",
182 .clk = "l4ls_gclk",
189 .clk = "l4ls_gclk",
196 .clk = "l4ls_gclk",
213 .clk = "l4ls_gclk",
221 .clk = "l4ls_gclk",
228 .clk = "l4ls_gclk",
235 .clk = "l4ls_gclk",
251 .clk = "l4ls_gclk",
259 .clk = "l4ls_gclk",
266 .clk = "l4ls_gclk",
273 .clk = "l4ls_gclk",
281 .clk = "l3s_gclk",
289 .clk = "l4ls_gclk",
296 .clk = "l4ls_gclk",
304 .clk = "l4ls_gclk",
312 .clk = "l4ls_gclk",
329 .clk = "l4ls_gclk",
347 .clk = "l4ls_gclk",
365 .clk = "l4ls_gclk",
383 .clk = "l4ls_gclk",
401 .clk = "l3s_gclk",
410 .clk = "l4ls_gclk",
418 .clk = "l4ls_gclk",
426 .clk = "l4ls_gclk",
434 .clk = "l4ls_gclk",
442 .clk = "l4ls_gclk",
450 .clk = "l4ls_gclk",
458 .clk = "l4ls_gclk",
466 .clk = "l4ls_gclk",
474 .clk = "l3_gclk",
491 .clk = "l3_gclk",
509 .clk = "l3_gclk",
527 .clk = "l3_gclk",
536 .clk = "l4ls_gclk",
544 .clk = "l4ls_gclk",
552 .clk = "l4ls_gclk",
560 .clk = "l4ls_gclk",
568 .clk = "l4ls_gclk",
592 .clk = "sha0_fck",
610 .clk = "aes0_fck",
|
| H A D | clkt2xxx_dpll.c | 14 #include <linux/clk.h>
25 * @clk: struct clk * of the DPLL to operate on
32 static void _allow_idle(struct clk_hw_omap *clk) _allow_idle() argument
34 if (!clk || !clk->dpll_data) _allow_idle()
42 * @clk: struct clk * of the DPLL to operate on
46 static void _deny_idle(struct clk_hw_omap *clk) _deny_idle() argument
48 if (!clk || !clk->dpll_data) _deny_idle()
|
| H A D | omap_hwmod_2xxx_interconnect_data.c | 65 .clk = "uart1_ick",
73 .clk = "uart2_ick",
81 .clk = "uart3_ick",
89 .clk = "mcspi1_ick",
97 .clk = "mcspi2_ick",
105 .clk = "gpt2_ick",
113 .clk = "gpt3_ick",
121 .clk = "gpt4_ick",
129 .clk = "gpt5_ick",
137 .clk = "gpt6_ick",
145 .clk = "gpt7_ick",
153 .clk = "gpt8_ick",
161 .clk = "gpt9_ick",
169 .clk = "gpt10_ick",
177 .clk = "gpt11_ick",
185 .clk = "gpt12_ick",
193 .clk = "dss_ick",
208 .clk = "dss_ick",
223 .clk = "dss_ick",
238 .clk = "dss_ick",
254 .clk = "rng_ick",
262 .clk = "sha_ick",
270 .clk = "aes_ick",
|
| /linux-4.4.14/drivers/clk/hisilicon/ |
| H A D | clk-hix5hd2.c | 14 #include "clk.h"
174 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_ether_prepare() local
177 val = readl_relaxed(clk->ctrl_reg); clk_ether_prepare()
178 val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask; clk_ether_prepare()
179 writel_relaxed(val, clk->ctrl_reg); clk_ether_prepare()
180 val &= ~(clk->ctrl_rst_mask); clk_ether_prepare()
181 writel_relaxed(val, clk->ctrl_reg); clk_ether_prepare()
183 val = readl_relaxed(clk->phy_reg); clk_ether_prepare()
184 val |= clk->phy_clk_mask; clk_ether_prepare()
185 val &= ~(clk->phy_rst_mask); clk_ether_prepare()
186 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
189 val &= ~(clk->phy_clk_mask); clk_ether_prepare()
190 val |= clk->phy_rst_mask; clk_ether_prepare()
191 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
194 val |= clk->phy_clk_mask; clk_ether_prepare()
195 val &= ~(clk->phy_rst_mask); clk_ether_prepare()
196 writel_relaxed(val, clk->phy_reg); clk_ether_prepare()
203 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_ether_unprepare() local
206 val = readl_relaxed(clk->ctrl_reg); clk_ether_unprepare()
207 val &= ~(clk->ctrl_clk_mask); clk_ether_unprepare()
208 writel_relaxed(val, clk->ctrl_reg); clk_ether_unprepare()
218 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_complex_enable() local
221 val = readl_relaxed(clk->ctrl_reg); clk_complex_enable()
222 val |= clk->ctrl_clk_mask; clk_complex_enable()
223 val &= ~(clk->ctrl_rst_mask); clk_complex_enable()
224 writel_relaxed(val, clk->ctrl_reg); clk_complex_enable()
226 val = readl_relaxed(clk->phy_reg); clk_complex_enable()
227 val |= clk->phy_clk_mask; clk_complex_enable()
228 val &= ~(clk->phy_rst_mask); clk_complex_enable()
229 writel_relaxed(val, clk->phy_reg); clk_complex_enable()
236 struct hix5hd2_clk_complex *clk = to_complex_clk(hw); clk_complex_disable() local
239 val = readl_relaxed(clk->ctrl_reg); clk_complex_disable()
240 val |= clk->ctrl_rst_mask; clk_complex_disable()
241 val &= ~(clk->ctrl_clk_mask); clk_complex_disable()
242 writel_relaxed(val, clk->ctrl_reg); clk_complex_disable()
244 val = readl_relaxed(clk->phy_reg); clk_complex_disable()
245 val |= clk->phy_rst_mask; clk_complex_disable()
246 val &= ~(clk->phy_clk_mask); clk_complex_disable()
247 writel_relaxed(val, clk->phy_reg); clk_complex_disable()
264 struct clk *clk; hix5hd2_clk_register_complex() local
290 clk = clk_register(NULL, &p_clk->hw); hix5hd2_clk_register_complex()
291 if (IS_ERR(clk)) { hix5hd2_clk_register_complex()
298 data->clk_data.clks[clks[i].id] = clk; hix5hd2_clk_register_complex()
|
| H A D | clk.c | 28 #include <linux/clk-provider.h>
36 #include "clk.h"
44 struct clk **clk_table; hisi_clk_init()
60 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL); hisi_clk_init()
78 struct clk *clk; hisi_clk_register_fixed_rate() local
82 clk = clk_register_fixed_rate(NULL, clks[i].name, hisi_clk_register_fixed_rate()
86 if (IS_ERR(clk)) { hisi_clk_register_fixed_rate()
91 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_fixed_rate()
99 struct clk *clk; hisi_clk_register_fixed_factor() local
103 clk = clk_register_fixed_factor(NULL, clks[i].name, hisi_clk_register_fixed_factor()
107 if (IS_ERR(clk)) { hisi_clk_register_fixed_factor()
112 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_fixed_factor()
119 struct clk *clk; hisi_clk_register_mux() local
126 clk = clk_register_mux_table(NULL, clks[i].name, hisi_clk_register_mux()
132 if (IS_ERR(clk)) { hisi_clk_register_mux()
139 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_mux()
141 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_mux()
148 struct clk *clk; hisi_clk_register_divider() local
153 clk = clk_register_divider_table(NULL, clks[i].name, hisi_clk_register_divider()
161 if (IS_ERR(clk)) { hisi_clk_register_divider()
168 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_divider()
170 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_divider()
177 struct clk *clk; hisi_clk_register_gate() local
182 clk = clk_register_gate(NULL, clks[i].name, hisi_clk_register_gate()
189 if (IS_ERR(clk)) { hisi_clk_register_gate()
196 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_gate()
198 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_gate()
205 struct clk *clk; hisi_clk_register_gate_sep() local
210 clk = hisi_register_clkgate_sep(NULL, clks[i].name, hisi_clk_register_gate_sep()
217 if (IS_ERR(clk)) { hisi_clk_register_gate_sep()
224 clk_register_clkdev(clk, clks[i].alias, NULL); hisi_clk_register_gate_sep()
226 data->clk_data.clks[clks[i].id] = clk; hisi_clk_register_gate_sep()
233 struct clk *clk; hi6220_clk_register_divider() local
238 clk = hi6220_register_clkdiv(NULL, clks[i].name, hi6220_clk_register_divider()
246 if (IS_ERR(clk)) { hi6220_clk_register_divider()
253 clk_register_clkdev(clk, clks[i].alias, NULL); hi6220_clk_register_divider()
255 data->clk_data.clks[clks[i].id] = clk; hi6220_clk_register_divider()
|
| /linux-4.4.14/arch/sh/kernel/cpu/ |
| H A D | clock-cpg.c | 1 #include <linux/clk.h>
8 static struct clk master_clk = {
13 static struct clk peripheral_clk = {
18 static struct clk bus_clk = {
23 static struct clk cpu_clk = {
31 static struct clk *onchip_clocks[] = {
51 struct clk *clk = onchip_clocks[i]; cpg_clk_init() local
52 arch_init_clk_ops(&clk->ops, i); cpg_clk_init()
53 if (clk->ops) cpg_clk_init()
54 ret |= clk_register(clk); cpg_clk_init()
|
| /linux-4.4.14/drivers/clk/h8300/ |
| H A D | clk-div.c | 7 #include <linux/clk-provider.h>
17 struct clk *clk; h8300_div_clk_setup() local
41 clk = clk_register_divider(NULL, clk_name, parent_name, h8300_div_clk_setup()
44 if (!IS_ERR(clk)) { h8300_div_clk_setup()
45 of_clk_add_provider(node, of_clk_src_simple_get, clk); h8300_div_clk_setup()
49 __func__, clk_name, PTR_ERR(clk)); h8300_div_clk_setup()
|
| /linux-4.4.14/drivers/clk/sunxi/ |
| H A D | clk-a10-codec.c | 17 #include <linux/clk-provider.h>
25 struct clk *clk; sun4i_codec_clk_setup() local
36 clk = clk_register_gate(NULL, clk_name, parent_name, sun4i_codec_clk_setup()
40 if (!IS_ERR(clk)) sun4i_codec_clk_setup()
41 of_clk_add_provider(node, of_clk_src_simple_get, clk); sun4i_codec_clk_setup()
43 CLK_OF_DECLARE(sun4i_codec, "allwinner,sun4i-a10-codec-clk",
|
| H A D | clk-simple-gates.c | 17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
54 clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL); sunxi_simple_gates_setup()
101 CLK_OF_DECLARE(sun4i_a10_apb0, "allwinner,sun4i-a10-apb0-gates-clk",
103 CLK_OF_DECLARE(sun4i_a10_apb1, "allwinner,sun4i-a10-apb1-gates-clk",
105 CLK_OF_DECLARE(sun4i_a10_axi, "allwinner,sun4i-a10-axi-gates-clk",
107 CLK_OF_DECLARE(sun5i_a10s_apb0, "allwinner,sun5i-a10s-apb0-gates-clk",
109 CLK_OF_DECLARE(sun5i_a10s_apb1, "allwinner,sun5i-a10s-apb1-gates-clk",
111 CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk",
113 CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk",
115 CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk",
117 CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk",
119 CLK_OF_DECLARE(sun6i_a31_apb2, "allwinner,sun6i-a31-apb2-gates-clk",
121 CLK_OF_DECLARE(sun7i_a20_apb0, "allwinner,sun7i-a20-apb0-gates-clk",
123 CLK_OF_DECLARE(sun7i_a20_apb1, "allwinner,sun7i-a20-apb1-gates-clk",
125 CLK_OF_DECLARE(sun8i_a23_ahb1, "allwinner,sun8i-a23-ahb1-gates-clk",
127 CLK_OF_DECLARE(sun8i_a23_apb1, "allwinner,sun8i-a23-apb1-gates-clk",
129 CLK_OF_DECLARE(sun8i_a23_apb2, "allwinner,sun8i-a23-apb2-gates-clk",
131 CLK_OF_DECLARE(sun8i_a33_ahb1, "allwinner,sun8i-a33-ahb1-gates-clk",
133 CLK_OF_DECLARE(sun9i_a80_ahb0, "allwinner,sun9i-a80-ahb0-gates-clk",
135 CLK_OF_DECLARE(sun9i_a80_ahb1, "allwinner,sun9i-a80-ahb1-gates-clk",
137 CLK_OF_DECLARE(sun9i_a80_ahb2, "allwinner,sun9i-a80-ahb2-gates-clk",
139 CLK_OF_DECLARE(sun9i_a80_apb0, "allwinner,sun9i-a80-apb0-gates-clk",
141 CLK_OF_DECLARE(sun9i_a80_apb1, "allwinner,sun9i-a80-apb1-gates-clk",
153 CLK_OF_DECLARE(sun4i_a10_ahb, "allwinner,sun4i-a10-ahb-gates-clk",
155 CLK_OF_DECLARE(sun5i_a10s_ahb, "allwinner,sun5i-a10s-ahb-gates-clk",
157 CLK_OF_DECLARE(sun5i_a13_ahb, "allwinner,sun5i-a13-ahb-gates-clk",
159 CLK_OF_DECLARE(sun7i_a20_ahb, "allwinner,sun7i-a20-ahb-gates-clk",
|
| H A D | clk-sun6i-apb0.c | 11 #include <linux/clk-provider.h>
17 * The APB0 clk has a configurable divisor.
38 struct clk *clk; sun6i_a31_apb0_clk_probe() local
51 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, sun6i_a31_apb0_clk_probe()
54 if (IS_ERR(clk)) sun6i_a31_apb0_clk_probe()
55 return PTR_ERR(clk); sun6i_a31_apb0_clk_probe()
57 return of_clk_add_provider(np, of_clk_src_simple_get, clk); sun6i_a31_apb0_clk_probe()
61 { .compatible = "allwinner,sun6i-a31-apb0-clk" },
68 .name = "sun6i-a31-apb0-clk",
|
| H A D | clk-sun8i-apb0.c | 9 * Based on clk-sun6i-apb0.c
17 #include <linux/clk-provider.h>
29 struct clk *clk; sun8i_a23_apb0_clk_probe() local
43 clk = clk_register_divider(&pdev->dev, clk_name, clk_parent, 0, reg, sun8i_a23_apb0_clk_probe()
45 if (IS_ERR(clk)) sun8i_a23_apb0_clk_probe()
46 return PTR_ERR(clk); sun8i_a23_apb0_clk_probe()
48 return of_clk_add_provider(np, of_clk_src_simple_get, clk); sun8i_a23_apb0_clk_probe()
52 { .compatible = "allwinner,sun8i-a23-apb0-clk" },
59 .name = "sun8i-a23-apb0-clk",
|
| H A D | clk-a10-hosc.c | 17 #include <linux/clk-provider.h>
28 struct clk *clk; sun4i_osc_clk_setup() local
53 clk = clk_register_composite(NULL, clk_name, sun4i_osc_clk_setup()
60 if (IS_ERR(clk)) sun4i_osc_clk_setup()
63 of_clk_add_provider(node, of_clk_src_simple_get, clk); sun4i_osc_clk_setup()
64 clk_register_clkdev(clk, clk_name, NULL); sun4i_osc_clk_setup()
73 CLK_OF_DECLARE(sun4i_osc, "allwinner,sun4i-a10-osc-clk", sun4i_osc_clk_setup);
|
| H A D | clk-sun6i-ar100.c | 11 #include <linux/clk-provider.h>
39 struct ar100_clk *clk = to_ar100_clk(hw); ar100_recalc_rate() local
40 u32 val = readl(clk->reg); ar100_recalc_rate()
68 * The AR100 clk contains 2 divisors: ar100_determine_rate()
118 struct ar100_clk *clk = to_ar100_clk(hw); ar100_set_parent() local
119 u32 val = readl(clk->reg); ar100_set_parent()
126 writel(val, clk->reg); ar100_set_parent()
133 struct ar100_clk *clk = to_ar100_clk(hw); ar100_get_parent() local
134 return (readl(clk->reg) >> SUN6I_AR100_MUX_SHIFT) & ar100_get_parent()
142 struct ar100_clk *clk = to_ar100_clk(hw); ar100_set_rate() local
143 u32 val = readl(clk->reg); ar100_set_rate()
162 writel(val, clk->reg); ar100_set_rate()
183 struct clk *clk; sun6i_a31_ar100_clk_probe() local
211 clk = clk_register(&pdev->dev, &ar100->hw); sun6i_a31_ar100_clk_probe()
212 if (IS_ERR(clk)) sun6i_a31_ar100_clk_probe()
213 return PTR_ERR(clk); sun6i_a31_ar100_clk_probe()
215 return of_clk_add_provider(np, of_clk_src_simple_get, clk); sun6i_a31_ar100_clk_probe()
219 { .compatible = "allwinner,sun6i-a31-ar100-clk" },
226 .name = "sun6i-a31-ar100-clk",
|
| /linux-4.4.14/arch/arm/mach-lpc32xx/ |
| H A D | clock.h | 22 struct clk { struct
24 struct clk *parent;
28 int (*set_rate) (struct clk *, unsigned long);
29 unsigned long (*round_rate) (struct clk *, unsigned long);
30 unsigned long (*get_rate) (struct clk *clk);
31 int (*enable) (struct clk *, int);
|
| H A D | clock.c | 92 #include <linux/clk.h>
106 static struct clk clk_armpll;
107 static struct clk clk_usbpll;
114 static unsigned long local_return_parent_rate(struct clk *clk) local_return_parent_rate() argument
120 while (clk->rate == 0) local_return_parent_rate()
121 clk = clk->parent; local_return_parent_rate()
123 return clk->rate; local_return_parent_rate()
127 static struct clk osc_32KHz = {
132 static int local_pll397_enable(struct clk *clk, int enable) local_pll397_enable() argument
161 static int local_oscmain_enable(struct clk *clk, int enable) local_oscmain_enable() argument
190 static struct clk osc_pll397 = {
197 static struct clk osc_main = {
203 static struct clk clk_sys;
367 static struct clk clk_armpll = {
387 static int local_usbpll_enable(struct clk *clk, int enable) local_usbpll_enable() argument
451 static unsigned long local_usbpll_round_rate(struct clk *clk, local_usbpll_round_rate() argument
463 clkin = clk->get_rate(clk); local_usbpll_round_rate()
475 static int local_usbpll_set_rate(struct clk *clk, unsigned long rate) local_usbpll_set_rate() argument
487 clkin = clk->get_rate(clk->parent); local_usbpll_set_rate()
499 local_usbpll_enable(clk, 0); local_usbpll_set_rate()
510 ret = local_usbpll_enable(clk, 1); local_usbpll_set_rate()
512 clk->rate = clk_check_pll_setup(clkin, &pllsetup); local_usbpll_set_rate()
517 static struct clk clk_usbpll = {
533 static struct clk clk_hclk = {
538 static struct clk clk_pclk = {
543 static int local_onoff_enable(struct clk *clk, int enable) local_onoff_enable() argument
547 tmp = __raw_readl(clk->enable_reg); local_onoff_enable()
550 tmp &= ~clk->enable_mask; local_onoff_enable()
552 tmp |= clk->enable_mask; local_onoff_enable()
554 __raw_writel(tmp, clk->enable_reg); local_onoff_enable()
560 static struct clk clk_timer0 = {
567 static struct clk clk_timer1 = {
574 static struct clk clk_timer2 = {
581 static struct clk clk_timer3 = {
588 static struct clk clk_mpwm = {
595 static struct clk clk_wdt = {
602 static struct clk clk_vfp9 = {
609 static struct clk clk_dma = {
617 static struct clk clk_pwm = {
630 static struct clk clk_uart3 = {
638 static struct clk clk_uart4 = {
646 static struct clk clk_uart5 = {
654 static struct clk clk_uart6 = {
662 static struct clk clk_i2c0 = {
670 static struct clk clk_i2c1 = {
678 static struct clk clk_i2c2 = {
686 static struct clk clk_ssp0 = {
694 static struct clk clk_ssp1 = {
702 static struct clk clk_kscan = {
710 static struct clk clk_nand = {
719 static struct clk clk_nand_mlc = {
729 static struct clk clk_i2s0 = {
737 static struct clk clk_i2s1 = {
746 static struct clk clk_net = {
756 static struct clk clk_rtc = {
762 static int local_usb_enable(struct clk *clk, int enable) local_usb_enable() argument
773 return local_onoff_enable(clk, enable); local_usb_enable()
776 static struct clk clk_usbd = {
787 static int local_usb_otg_enable(struct clk *clk, int enable) local_usb_otg_enable() argument
792 __raw_writel(clk->enable_mask, clk->enable_reg); local_usb_otg_enable()
795 clk->enable_mask) != clk->enable_mask) && (to > 0)) local_usb_otg_enable()
798 __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg); local_usb_otg_enable()
811 static struct clk clk_usb_otg_dev = {
822 static struct clk clk_usb_otg_host = {
833 static int tsc_onoff_enable(struct clk *clk, int enable) tsc_onoff_enable() argument
843 __raw_writel(0, clk->enable_reg); tsc_onoff_enable()
845 __raw_writel(clk->enable_mask, clk->enable_reg); tsc_onoff_enable()
850 static struct clk clk_tsc = {
858 static int adc_onoff_enable(struct clk *clk, int enable) adc_onoff_enable() argument
870 divider = clk->get_rate(clk) / 4500000 + 1; adc_onoff_enable()
875 clk->rate = clk->get_rate(clk->parent) / divider; adc_onoff_enable()
878 __raw_writel(0, clk->enable_reg); adc_onoff_enable()
880 __raw_writel(clk->enable_mask, clk->enable_reg); adc_onoff_enable()
885 static struct clk clk_adc = {
893 static int mmc_onoff_enable(struct clk *clk, int enable) mmc_onoff_enable() argument
915 static unsigned long mmc_get_rate(struct clk *clk) mmc_get_rate() argument
927 rate = clk->parent->get_rate(clk->parent); mmc_get_rate()
938 static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate) mmc_round_rate() argument
943 prate = clk->parent->get_rate(clk->parent); mmc_round_rate()
955 static int mmc_set_rate(struct clk *clk, unsigned long rate) mmc_set_rate() argument
958 unsigned long prate, div, crate = mmc_round_rate(clk, rate); mmc_set_rate()
960 prate = clk->parent->get_rate(clk->parent); mmc_set_rate()
974 static struct clk clk_mmc = {
984 static unsigned long clcd_get_rate(struct clk *clk) clcd_get_rate() argument
995 rate = clk->parent->get_rate(clk->parent); clcd_get_rate()
1007 static int clcd_set_rate(struct clk *clk, unsigned long rate) clcd_set_rate() argument
1017 prate = clk->parent->get_rate(clk->parent); clcd_set_rate()
1038 static unsigned long clcd_round_rate(struct clk *clk, unsigned long rate) clcd_round_rate() argument
1042 prate = clk->parent->get_rate(clk->parent); clcd_round_rate()
1057 static struct clk clk_lcd = {
1067 static void local_clk_disable(struct clk *clk) local_clk_disable() argument
1070 if (clk->usecount > 0) { local_clk_disable()
1071 clk->usecount--; local_clk_disable()
1074 if ((clk->usecount == 0) && (clk->enable)) local_clk_disable()
1075 clk->enable(clk, 0); local_clk_disable()
1078 if (clk->parent) local_clk_disable()
1079 local_clk_disable(clk->parent); local_clk_disable()
1083 static int local_clk_enable(struct clk *clk) local_clk_enable() argument
1088 if (clk->parent) local_clk_enable()
1089 ret = local_clk_enable(clk->parent); local_clk_enable()
1093 if ((clk->usecount == 0) && (clk->enable)) local_clk_enable()
1094 ret = clk->enable(clk, 1); local_clk_enable()
1097 clk->usecount++; local_clk_enable()
1098 else if (clk->parent) local_clk_enable()
1099 local_clk_disable(clk->parent); local_clk_enable()
1108 int clk_enable(struct clk *clk) clk_enable() argument
1114 ret = local_clk_enable(clk); clk_enable()
1124 void clk_disable(struct clk *clk) clk_disable() argument
1129 local_clk_disable(clk); clk_disable()
1137 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
1139 return clk->get_rate(clk); clk_get_rate()
1146 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
1155 if (clk->set_rate) clk_set_rate()
1156 ret = clk->set_rate(clk, rate); clk_set_rate()
1165 long clk_round_rate(struct clk *clk, unsigned long rate) clk_round_rate() argument
1167 if (clk->round_rate) clk_round_rate()
1168 rate = clk->round_rate(clk, rate); clk_round_rate()
1170 rate = clk->get_rate(clk); clk_round_rate()
1179 int clk_set_parent(struct clk *clk, struct clk *parent) clk_set_parent() argument
1189 struct clk *clk_get_parent(struct clk *clk) clk_get_parent() argument
1191 return clk->parent; clk_get_parent()
|
| /linux-4.4.14/drivers/clk/pxa/ |
| H A D | clk-pxa.c | 13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
19 #include "clk-pxa.h"
23 static struct clk *pxa_clocks[CLK_MAX];
72 const char *dev_id, struct clk *clk) clkdev_pxa_register()
74 if (!IS_ERR(clk) && (ckid != CLK_NONE)) clkdev_pxa_register()
75 pxa_clocks[ckid] = clk; clkdev_pxa_register()
76 if (!IS_ERR(clk)) clkdev_pxa_register()
77 clk_register_clkdev(clk, con_id, dev_id); clkdev_pxa_register()
84 struct clk *clk; clk_pxa_cken_init() local
93 clk = clk_register_composite(NULL, clks[i].name, clk_pxa_cken_init()
100 clks[i].dev_id, clk); clk_pxa_cken_init()
71 clkdev_pxa_register(int ckid, const char *con_id, const char *dev_id, struct clk *clk) clkdev_pxa_register() argument
|
| /linux-4.4.14/drivers/clk/at91/ |
| H A D | clk-slow.c | 2 * drivers/clk/at91/clk-slow.c
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
17 #include <linux/clk/at91_pmc.h>
75 static struct clk *slow_clk;
123 static struct clk * __init at91_clk_register_slow_osc()
131 struct clk *clk = NULL; at91_clk_register_slow_osc() local
155 clk = clk_register(NULL, &osc->hw); at91_clk_register_slow_osc()
156 if (IS_ERR(clk)) at91_clk_register_slow_osc()
159 return clk; at91_clk_register_slow_osc()
165 struct clk *clk; of_at91sam9x5_clk_slow_osc_setup() local
176 clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup, of_at91sam9x5_clk_slow_osc_setup()
178 if (IS_ERR(clk)) of_at91sam9x5_clk_slow_osc_setup()
181 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_slow_osc_setup()
235 static struct clk * __init at91_clk_register_slow_rc_osc()
243 struct clk *clk = NULL; at91_clk_register_slow_rc_osc() local
265 clk = clk_register(NULL, &osc->hw); at91_clk_register_slow_rc_osc()
266 if (IS_ERR(clk)) at91_clk_register_slow_rc_osc()
269 return clk; at91_clk_register_slow_rc_osc()
275 struct clk *clk; of_at91sam9x5_clk_slow_rc_osc_setup() local
286 clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, accuracy, of_at91sam9x5_clk_slow_rc_osc_setup()
288 if (IS_ERR(clk)) of_at91sam9x5_clk_slow_rc_osc_setup()
291 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_slow_rc_osc_setup()
333 static struct clk * __init at91_clk_register_sam9x5_slow()
340 struct clk *clk = NULL; at91_clk_register_sam9x5_slow() local
360 clk = clk_register(NULL, &slowck->hw); at91_clk_register_sam9x5_slow()
361 if (IS_ERR(clk)) at91_clk_register_sam9x5_slow()
364 slow_clk = clk; at91_clk_register_sam9x5_slow()
366 return clk; at91_clk_register_sam9x5_slow()
372 struct clk *clk; of_at91sam9x5_clk_slow_setup() local
385 clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names, of_at91sam9x5_clk_slow_setup()
387 if (IS_ERR(clk)) of_at91sam9x5_clk_slow_setup()
390 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_slow_setup()
404 static struct clk * __init at91_clk_register_sam9260_slow()
411 struct clk *clk = NULL; at91_clk_register_sam9260_slow() local
433 clk = clk_register(NULL, &slowck->hw); at91_clk_register_sam9260_slow()
434 if (IS_ERR(clk)) at91_clk_register_sam9260_slow()
437 slow_clk = clk; at91_clk_register_sam9260_slow()
439 return clk; at91_clk_register_sam9260_slow()
445 struct clk *clk; of_at91sam9260_clk_slow_setup() local
458 clk = at91_clk_register_sam9260_slow(pmc, name, parent_names, of_at91sam9260_clk_slow_setup()
460 if (IS_ERR(clk)) of_at91sam9260_clk_slow_setup()
463 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9260_clk_slow_setup()
467 * FIXME: All slow clk users are not properly claiming it (get + prepare +
|
| H A D | clk-usb.c | 11 #include <linux/clk-provider.h>
13 #include <linux/clk/at91_pmc.h>
199 static struct clk * __init at91sam9x5_clk_register_usb()
204 struct clk *clk = NULL; at91sam9x5_clk_register_usb() local
221 clk = clk_register(NULL, &usb->hw); at91sam9x5_clk_register_usb()
222 if (IS_ERR(clk)) at91sam9x5_clk_register_usb()
225 return clk; at91sam9x5_clk_register_usb()
228 static struct clk * __init at91sam9n12_clk_register_usb()
233 struct clk *clk = NULL; at91sam9n12_clk_register_usb() local
249 clk = clk_register(NULL, &usb->hw); at91sam9n12_clk_register_usb()
250 if (IS_ERR(clk)) at91sam9n12_clk_register_usb()
253 return clk; at91sam9n12_clk_register_usb()
343 static struct clk * __init at91rm9200_clk_register_usb()
348 struct clk *clk = NULL; at91rm9200_clk_register_usb() local
365 clk = clk_register(NULL, &usb->hw); at91rm9200_clk_register_usb()
366 if (IS_ERR(clk)) at91rm9200_clk_register_usb()
369 return clk; at91rm9200_clk_register_usb()
375 struct clk *clk; of_at91sam9x5_clk_usb_setup() local
388 clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents); of_at91sam9x5_clk_usb_setup()
389 if (IS_ERR(clk)) of_at91sam9x5_clk_usb_setup()
392 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9x5_clk_usb_setup()
398 struct clk *clk; of_at91sam9n12_clk_usb_setup() local
408 clk = at91sam9n12_clk_register_usb(pmc, name, parent_name); of_at91sam9n12_clk_usb_setup()
409 if (IS_ERR(clk)) of_at91sam9n12_clk_usb_setup()
412 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91sam9n12_clk_usb_setup()
418 struct clk *clk; of_at91rm9200_clk_usb_setup() local
427 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4); of_at91rm9200_clk_usb_setup()
433 clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors); of_at91rm9200_clk_usb_setup()
434 if (IS_ERR(clk)) of_at91rm9200_clk_usb_setup()
437 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91rm9200_clk_usb_setup()
|
| H A D | clk-utmi.c | 11 #include <linux/clk-provider.h>
13 #include <linux/clk/at91_pmc.h>
84 /* UTMI clk is a fixed clk multiplier */ clk_utmi_recalc_rate()
95 static struct clk * __init at91_clk_register_utmi()
101 struct clk *clk = NULL; at91_clk_register_utmi() local
120 IRQF_TRIGGER_HIGH, "clk-utmi", utmi); at91_clk_register_utmi()
126 clk = clk_register(NULL, &utmi->hw); at91_clk_register_utmi()
127 if (IS_ERR(clk)) { at91_clk_register_utmi()
132 return clk; at91_clk_register_utmi()
139 struct clk *clk; of_at91_clk_utmi_setup() local
151 clk = at91_clk_register_utmi(pmc, irq, name, parent_name); of_at91_clk_utmi_setup()
152 if (IS_ERR(clk)) of_at91_clk_utmi_setup()
155 of_clk_add_provider(np, of_clk_src_simple_get, clk); of_at91_clk_utmi_setup()
|
| H A D | sckc.c | 2 * drivers/clk/at91/sckc.c
13 #include <linux/clk-provider.h>
24 .compatible = "atmel,at91sam9x5-clk-slow-osc",
28 .compatible = "atmel,at91sam9x5-clk-slow-rc-osc",
32 .compatible = "atmel,at91sam9x5-clk-slow",
|
| /linux-4.4.14/drivers/clocksource/ |
| H A D | armv7m_systick.c | 12 #include <linux/clk.h>
26 struct clk *clk = NULL; system_timer_of_register() local
39 clk = of_clk_get(np, 0); system_timer_of_register()
40 if (IS_ERR(clk)) system_timer_of_register()
43 ret = clk_prepare_enable(clk); system_timer_of_register()
47 rate = clk_get_rate(clk); system_timer_of_register()
59 if (clk) system_timer_of_register()
70 clk_disable_unprepare(clk); system_timer_of_register()
72 clk_put(clk); system_timer_of_register()
|
| H A D | clksrc_st_lpc.c | 15 #include <linux/clk.h>
30 struct clk *clk; member in struct:st_clksrc_ddata
54 rate = clk_get_rate(ddata.clk); st_clksrc_init()
71 struct clk *clk; st_clksrc_setup_clk() local
73 clk = of_clk_get(np, 0); st_clksrc_setup_clk()
74 if (IS_ERR(clk)) { st_clksrc_setup_clk()
76 return PTR_ERR(clk); st_clksrc_setup_clk()
79 if (clk_prepare_enable(clk)) { st_clksrc_setup_clk()
84 if (!clk_get_rate(clk)) { st_clksrc_setup_clk()
86 clk_disable_unprepare(clk); st_clksrc_setup_clk()
90 ddata.clk = clk; st_clksrc_setup_clk()
122 clk_disable_unprepare(ddata.clk); st_clksrc_of_register()
123 clk_put(ddata.clk); st_clksrc_of_register()
129 clk_get_rate(ddata.clk)); st_clksrc_of_register()
|
| H A D | tango_xtal.c | 7 #include <linux/clk.h>
37 struct clk *clk; tango_clocksource_init() local
46 clk = of_clk_get(np, 0); tango_clocksource_init()
47 if (IS_ERR(clk)) { tango_clocksource_init()
52 xtal_freq = clk_get_rate(clk); tango_clocksource_init()
|
| H A D | timer-sp804.c | 21 #include <linux/clk.h>
37 static long __init sp804_get_clock_rate(struct clk *clk) sp804_get_clock_rate() argument
42 err = clk_prepare(clk); sp804_get_clock_rate()
45 clk_put(clk); sp804_get_clock_rate()
49 err = clk_enable(clk); sp804_get_clock_rate()
52 clk_unprepare(clk); sp804_get_clock_rate()
53 clk_put(clk); sp804_get_clock_rate()
57 rate = clk_get_rate(clk); sp804_get_clock_rate()
60 clk_disable(clk); sp804_get_clock_rate()
61 clk_unprepare(clk); sp804_get_clock_rate()
62 clk_put(clk); sp804_get_clock_rate()
82 struct clk *clk, __sp804_clocksource_and_sched_clock_init()
87 if (!clk) { __sp804_clocksource_and_sched_clock_init()
88 clk = clk_get_sys("sp804", name); __sp804_clocksource_and_sched_clock_init()
89 if (IS_ERR(clk)) { __sp804_clocksource_and_sched_clock_init()
91 (int)PTR_ERR(clk)); __sp804_clocksource_and_sched_clock_init()
96 rate = sp804_get_clock_rate(clk); __sp804_clocksource_and_sched_clock_init()
189 void __init __sp804_clockevents_init(void __iomem *base, unsigned int irq, struct clk *clk, const char *name) __sp804_clockevents_init() argument
194 if (!clk) __sp804_clockevents_init()
195 clk = clk_get_sys("sp804", name); __sp804_clockevents_init()
196 if (IS_ERR(clk)) { __sp804_clockevents_init()
198 (int)PTR_ERR(clk)); __sp804_clockevents_init()
202 rate = sp804_get_clock_rate(clk); __sp804_clockevents_init()
224 struct clk *clk1, *clk2; sp804_of_init()
280 struct clk *clk; integrator_cp_of_init() local
285 clk = of_clk_get(np, 0); integrator_cp_of_init()
286 if (WARN_ON(IS_ERR(clk))) integrator_cp_of_init()
296 __sp804_clocksource_and_sched_clock_init(base, name, clk, 0); integrator_cp_of_init()
302 __sp804_clockevents_init(base, irq, clk, name); integrator_cp_of_init()
80 __sp804_clocksource_and_sched_clock_init(void __iomem *base, const char *name, struct clk *clk, int use_sched_clock) __sp804_clocksource_and_sched_clock_init() argument
|
| /linux-4.4.14/drivers/clk/mxs/ |
| H A D | clk.h | 15 struct clk;
17 #include <linux/clk-provider.h>
27 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
30 struct clk *mxs_clk_ref(const char *name, const char *parent_name,
33 struct clk *mxs_clk_div(const char *name, const char *parent_name,
36 struct clk *mxs_clk_frac(const char *name, const char *parent_name,
39 static inline struct clk *mxs_clk_fixed(const char *name, int rate) mxs_clk_fixed()
44 static inline struct clk *mxs_clk_gate(const char *name, mxs_clk_gate()
52 static inline struct clk *mxs_clk_mux(const char *name, void __iomem *reg, mxs_clk_mux()
60 static inline struct clk *mxs_clk_fixed_factor(const char *name, mxs_clk_fixed_factor()
|
| /linux-4.4.14/drivers/clk/samsung/ |
| H A D | clk.c | 16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
21 #include "clk.h"
63 struct clk **clk_table; samsung_clk_init()
70 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); samsung_clk_init()
91 panic("could not register clk provider\n"); samsung_clk_of_add_provider()
96 void samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk *clk, samsung_clk_add_lookup() argument
100 ctx->clk_data.clks[id] = clk; samsung_clk_add_lookup()
108 struct clk *clk; samsung_clk_register_alias() local
123 clk = ctx->clk_data.clks[list->id]; samsung_clk_register_alias()
124 if (!clk) { samsung_clk_register_alias()
130 ret = clk_register_clkdev(clk, list->alias, list->dev_name); samsung_clk_register_alias()
142 struct clk *clk; samsung_clk_register_fixed_rate() local
146 clk = clk_register_fixed_rate(NULL, list->name, samsung_clk_register_fixed_rate()
148 if (IS_ERR(clk)) { samsung_clk_register_fixed_rate()
154 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_fixed_rate()
160 ret = clk_register_clkdev(clk, list->name, NULL); samsung_clk_register_fixed_rate()
171 struct clk *clk; samsung_clk_register_fixed_factor() local
175 clk = clk_register_fixed_factor(NULL, list->name, samsung_clk_register_fixed_factor()
177 if (IS_ERR(clk)) { samsung_clk_register_fixed_factor()
183 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_fixed_factor()
192 struct clk *clk; samsung_clk_register_mux() local
196 clk = clk_register_mux(NULL, list->name, list->parent_names, samsung_clk_register_mux()
200 if (IS_ERR(clk)) { samsung_clk_register_mux()
206 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_mux()
210 ret = clk_register_clkdev(clk, list->alias, samsung_clk_register_mux()
224 struct clk *clk; samsung_clk_register_div() local
229 clk = clk_register_divider_table(NULL, list->name, samsung_clk_register_div()
235 clk = clk_register_divider(NULL, list->name, samsung_clk_register_div()
239 if (IS_ERR(clk)) { samsung_clk_register_div()
245 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_div()
249 ret = clk_register_clkdev(clk, list->alias, samsung_clk_register_div()
263 struct clk *clk; samsung_clk_register_gate() local
267 clk = clk_register_gate(NULL, list->name, list->parent_name, samsung_clk_register_gate()
270 if (IS_ERR(clk)) { samsung_clk_register_gate()
278 ret = clk_register_clkdev(clk, list->alias, samsung_clk_register_gate()
285 samsung_clk_add_lookup(ctx, clk, list->id); samsung_clk_register_gate()
313 struct clk *clk; _get_rate() local
315 clk = __clk_lookup(clk_name); _get_rate()
316 if (!clk) { _get_rate()
321 return clk_get_rate(clk); _get_rate()
|
| /linux-4.4.14/drivers/clk/rockchip/ |
| H A D | clk.c | 7 * samsung/clk.c
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
29 #include "clk.h"
41 static struct clk *rockchip_clk_register_branch(const char *name, rockchip_clk_register_branch()
49 struct clk *clk; rockchip_clk_register_branch() local
98 clk = clk_register_composite(NULL, name, parent_names, num_parents, rockchip_clk_register_branch()
104 return clk; rockchip_clk_register_branch()
112 static struct clk *rockchip_clk_register_frac_branch(const char *name, rockchip_clk_register_frac_branch()
118 struct clk *clk; rockchip_clk_register_frac_branch() local
153 clk = clk_register_composite(NULL, name, parent_names, num_parents, rockchip_clk_register_frac_branch()
159 return clk; rockchip_clk_register_frac_branch()
163 static struct clk **clk_table;
176 clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL); rockchip_clk_init()
192 void rockchip_clk_add_lookup(struct clk *clk, unsigned int id) rockchip_clk_add_lookup() argument
195 clk_table[id] = clk; rockchip_clk_add_lookup()
201 struct clk *clk; rockchip_clk_register_plls() local
205 clk = rockchip_clk_register_pll(list->type, list->name, rockchip_clk_register_plls()
211 if (IS_ERR(clk)) { rockchip_clk_register_plls()
217 rockchip_clk_add_lookup(clk, list->id); rockchip_clk_register_plls()
225 struct clk *clk = NULL; rockchip_clk_register_branches() local
235 clk = clk_register_mux(NULL, list->name, rockchip_clk_register_branches()
243 clk = clk_register_divider_table(NULL, rockchip_clk_register_branches()
250 clk = clk_register_divider(NULL, list->name, rockchip_clk_register_branches()
257 clk = rockchip_clk_register_frac_branch(list->name, rockchip_clk_register_branches()
266 clk = clk_register_gate(NULL, list->name, rockchip_clk_register_branches()
272 clk = rockchip_clk_register_branch(list->name, rockchip_clk_register_branches()
282 clk = rockchip_clk_register_mmc( rockchip_clk_register_branches()
290 clk = rockchip_clk_register_inverter( rockchip_clk_register_branches()
299 if (!clk) { rockchip_clk_register_branches()
305 if (IS_ERR(clk)) { rockchip_clk_register_branches()
307 __func__, list->name, PTR_ERR(clk)); rockchip_clk_register_branches()
311 rockchip_clk_add_lookup(clk, list->id); rockchip_clk_register_branches()
322 struct clk *clk; rockchip_clk_register_armclk() local
324 clk = rockchip_clk_register_cpuclk(name, parent_names, num_parents, rockchip_clk_register_armclk()
327 if (IS_ERR(clk)) { rockchip_clk_register_armclk()
329 __func__, name, PTR_ERR(clk)); rockchip_clk_register_armclk()
333 rockchip_clk_add_lookup(clk, lookup_id); rockchip_clk_register_armclk()
343 struct clk *clk = __clk_lookup(clocks[i]); rockchip_clk_protect_critical() local
345 if (clk) rockchip_clk_protect_critical()
346 clk_prepare_enable(clk); rockchip_clk_protect_critical()
|
| /linux-4.4.14/include/clocksource/ |
| H A D | timer-sp804.h | 4 struct clk;
7 const char *, struct clk *, int);
9 struct clk *, const char *);
|
| /linux-4.4.14/arch/mips/include/asm/mach-lantiq/ |
| H A D | lantiq.h | 13 #include <linux/clk.h>
40 extern int clk_activate(struct clk *clk);
41 extern void clk_deactivate(struct clk *clk);
42 extern struct clk *clk_get_cpu(void);
43 extern struct clk *clk_get_fpi(void);
44 extern struct clk *clk_get_io(void);
45 extern struct clk *clk_get_ppe(void);
|
| /linux-4.4.14/arch/sh/include/asm/ |
| H A D | clkdev.h | 8 * Helper for the clk API to assist looking up a struct clk.
29 #define __clk_put(clk)
30 #define __clk_get(clk) ({ 1; })
|
| /linux-4.4.14/arch/sh/kernel/cpu/sh2/ |
| H A D | clock-sh7619.c | 26 static void master_clk_init(struct clk *clk) master_clk_init() argument
28 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; master_clk_init()
35 static unsigned long module_clk_recalc(struct clk *clk) module_clk_recalc() argument
38 return clk->parent->rate / pfc_divisors[idx]; module_clk_recalc()
45 static unsigned long bus_clk_recalc(struct clk *clk) bus_clk_recalc() argument
47 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; bus_clk_recalc()
|
| /linux-4.4.14/arch/arm/include/asm/ |
| H A D | clkdev.h | 10 * Helper for the clk API to assist looking up a struct clk.
21 #define __clk_get(clk) ({ 1; })
22 #define __clk_put(clk) do { } while (0)
|
| /linux-4.4.14/drivers/usb/host/ |
| H A D | ehci-st.c | 15 #include <linux/clk.h>
35 struct clk *clks[USB_MAX_CLKS];
36 struct clk *clk48;
71 int clk, ret; st_ehci_platform_power_on() local
89 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { st_ehci_platform_power_on()
90 ret = clk_prepare_enable(priv->clks[clk]); st_ehci_platform_power_on()
108 while (--clk >= 0) st_ehci_platform_power_on()
109 clk_disable_unprepare(priv->clks[clk]); st_ehci_platform_power_on()
122 int clk; st_ehci_platform_power_off() local
132 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) st_ehci_platform_power_off()
133 if (priv->clks[clk]) st_ehci_platform_power_off()
134 clk_disable_unprepare(priv->clks[clk]); st_ehci_platform_power_off()
158 int err, irq, clk = 0; st_ehci_platform_probe() local
190 for (clk = 0; clk < USB_MAX_CLKS; clk++) { st_ehci_platform_probe()
191 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); st_ehci_platform_probe()
192 if (IS_ERR(priv->clks[clk])) { st_ehci_platform_probe()
193 err = PTR_ERR(priv->clks[clk]); st_ehci_platform_probe()
196 priv->clks[clk] = NULL; st_ehci_platform_probe()
205 dev_info(&dev->dev, "48MHz clk not found\n"); st_ehci_platform_probe()
250 while (--clk >= 0) st_ehci_platform_probe()
251 clk_put(priv->clks[clk]); st_ehci_platform_probe()
266 int clk; st_ehci_platform_remove() local
273 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) st_ehci_platform_remove()
274 clk_put(priv->clks[clk]); st_ehci_platform_remove()
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| H A D | ohci-st.c | 15 #include <linux/clk.h>
34 struct clk *clks[USB_MAX_CLKS];
35 struct clk *clk48;
52 int clk, ret; st_ohci_platform_power_on() local
70 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { st_ohci_platform_power_on()
71 ret = clk_prepare_enable(priv->clks[clk]); st_ohci_platform_power_on()
89 while (--clk >= 0) st_ohci_platform_power_on()
90 clk_disable_unprepare(priv->clks[clk]); st_ohci_platform_power_on()
104 int clk; st_ohci_platform_power_off() local
114 for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) st_ohci_platform_power_off()
115 if (priv->clks[clk]) st_ohci_platform_power_off()
116 clk_disable_unprepare(priv->clks[clk]); st_ohci_platform_power_off()
139 int err, irq, clk = 0; st_ohci_platform_probe() local
172 for (clk = 0; clk < USB_MAX_CLKS; clk++) { st_ohci_platform_probe()
173 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); st_ohci_platform_probe()
174 if (IS_ERR(priv->clks[clk])) { st_ohci_platform_probe()
175 err = PTR_ERR(priv->clks[clk]); st_ohci_platform_probe()
178 priv->clks[clk] = NULL; st_ohci_platform_probe()
187 dev_info(&dev->dev, "48MHz clk not found\n"); st_ohci_platform_probe()
232 while (--clk >= 0) st_ohci_platform_probe()
233 clk_put(priv->clks[clk]); st_ohci_platform_probe()
248 int clk; st_ohci_platform_remove() local
256 for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) st_ohci_platform_remove()
257 clk_put(priv->clks[clk]); st_ohci_platform_remove()
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| H A D | ohci-platform.c | 18 #include <linux/clk.h>
39 struct clk *clks[OHCI_MAX_CLKS];
51 int clk, ret, phy_num; ohci_platform_power_on() local
53 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) { ohci_platform_power_on()
54 ret = clk_prepare_enable(priv->clks[clk]); ohci_platform_power_on()
78 while (--clk >= 0) ohci_platform_power_on()
79 clk_disable_unprepare(priv->clks[clk]); ohci_platform_power_on()
88 int clk, phy_num; ohci_platform_power_off() local
95 for (clk = OHCI_MAX_CLKS - 1; clk >= 0; clk--) ohci_platform_power_off()
96 if (priv->clks[clk]) ohci_platform_power_off()
97 clk_disable_unprepare(priv->clks[clk]); ohci_platform_power_off()
120 int err, irq, phy_num, clk = 0; ohci_platform_probe() local
188 for (clk = 0; clk < OHCI_MAX_CLKS; clk++) { ohci_platform_probe()
189 priv->clks[clk] = of_clk_get(dev->dev.of_node, clk); ohci_platform_probe()
190 if (IS_ERR(priv->clks[clk])) { ohci_platform_probe()
191 err = PTR_ERR(priv->clks[clk]); ohci_platform_probe()
194 priv->clks[clk] = NULL; ohci_platform_probe()
271 while (--clk >= 0) ohci_platform_probe()
272 clk_put(priv->clks[clk]); ohci_platform_probe()
287 int clk; ohci_platform_remove() local
297 for (clk = 0; clk < OHCI_MAX_CLKS && priv->clks[clk]; clk++) ohci_platform_remove()
298 clk_put(priv->clks[clk]); ohci_platform_remove()
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| /linux-4.4.14/arch/unicore32/kernel/ |
| H A D | clock.c | 20 #include <linux/clk.h>
30 struct clk { struct
36 static struct clk clk_ost_clk = {
41 static struct clk clk_mclk_clk = {
45 static struct clk clk_bclk32_clk = {
49 static struct clk clk_ddr_clk = {
53 static struct clk clk_vga_clk = {
60 struct clk *clk_get(struct device *dev, const char *id) clk_get()
62 struct clk *p, *clk = ERR_PTR(-ENOENT); clk_get() local
67 clk = p; clk_get()
73 return clk; clk_get()
77 void clk_put(struct clk *clk) clk_put() argument
82 int clk_enable(struct clk *clk) clk_enable() argument
88 void clk_disable(struct clk *clk) clk_disable() argument
93 unsigned long clk_get_rate(struct clk *clk) clk_get_rate() argument
95 return clk->rate; clk_get_rate()
136 int clk_set_rate(struct clk *clk, unsigned long rate) clk_set_rate() argument
138 if (clk == &clk_vga_clk) { clk_set_rate()
181 if (clk == &clk_mclk_clk) { clk_set_rate()
217 int clk_register(struct clk *clk) clk_register() argument
220 list_add(&clk->node, &clocks); clk_register()
222 printk(KERN_DEFAULT "PKUnity PM: %s %lu.%02luM\n", clk->name, clk_register()
223 (clk->rate)/1000000, (clk->rate)/10000 % 100); clk_register()
228 void clk_unregister(struct clk *clk) clk_unregister() argument
231 list_del(&clk->node); clk_unregister()
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| /linux-4.4.14/drivers/memory/ |
| H A D | atmel-sdramc.c | 20 #include <linux/clk.h>
57 struct clk *clk; atmel_ramc_probe() local
63 clk = devm_clk_get(&pdev->dev, "ddrck"); atmel_ramc_probe()
64 if (IS_ERR(clk)) atmel_ramc_probe()
65 return PTR_ERR(clk); atmel_ramc_probe()
66 clk_prepare_enable(clk); atmel_ramc_probe()
70 clk = devm_clk_get(&pdev->dev, "mpddr"); atmel_ramc_probe()
71 if (IS_ERR(clk)) { atmel_ramc_probe()
73 return PTR_ERR(clk); atmel_ramc_probe()
75 clk_prepare_enable(clk); atmel_ramc_probe()
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| /linux-4.4.14/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-cgu.c | 11 #include <linux/clk-provider.h>
417 /* Power down PLL, disable clk output and dividers */ lpc18xx_pll0_set_rate()
533 static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk, lpc18xx_cgu_register_div() argument
537 const char *name = clk_src_names[clk->clk_id]; lpc18xx_cgu_register_div()
540 clk->div.reg = reg; lpc18xx_cgu_register_div()
541 clk->mux.reg = reg; lpc18xx_cgu_register_div()
542 clk->gate.reg = reg; lpc18xx_cgu_register_div()
544 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); lpc18xx_cgu_register_div()
546 return clk_register_composite(NULL, name, parents, clk->n_parents, lpc18xx_cgu_register_div()
547 &clk->mux.hw, &clk_mux_ops, lpc18xx_cgu_register_div()
548 &clk->div.hw, &clk_divider_ops, lpc18xx_cgu_register_div()
549 &clk->gate.hw, &lpc18xx_gate_ops, 0); lpc18xx_cgu_register_div()
553 static struct clk *lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk, lpc18xx_register_base_clk() argument
557 const char *name = clk_base_names[clk->clk_id]; lpc18xx_register_base_clk()
560 if (clk->n_parents == 0) lpc18xx_register_base_clk()
563 clk->mux.reg = reg; lpc18xx_register_base_clk()
564 clk->gate.reg = reg; lpc18xx_register_base_clk()
566 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); lpc18xx_register_base_clk()
570 return clk_register_composite(NULL, name, parents, clk->n_parents, lpc18xx_register_base_clk()
571 &clk->mux.hw, &clk_mux_ops, lpc18xx_register_base_clk()
574 return clk_register_composite(NULL, name, parents, clk->n_parents, lpc18xx_register_base_clk()
575 &clk->mux.hw, &clk_mux_ops, lpc18xx_register_base_clk()
577 &clk->gate.hw, &lpc18xx_gate_ops, 0); lpc18xx_register_base_clk()
581 static struct clk *lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk, lpc18xx_cgu_register_pll() argument
584 const char *name = clk_src_names[clk->clk_id]; lpc18xx_cgu_register_pll()
587 clk->pll.reg = base; lpc18xx_cgu_register_pll()
588 clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; lpc18xx_cgu_register_pll()
589 clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; lpc18xx_cgu_register_pll()
591 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); lpc18xx_cgu_register_pll()
593 return clk_register_composite(NULL, name, parents, clk->n_parents, lpc18xx_cgu_register_pll()
594 &clk->mux.hw, &clk_mux_ops, lpc18xx_cgu_register_pll()
595 &clk->pll.hw, clk->pll_ops, lpc18xx_cgu_register_pll()
596 &clk->gate.hw, &lpc18xx_gate_ops, 0); lpc18xx_cgu_register_pll()
603 struct clk *clk; lpc18xx_cgu_register_source_clks() local
607 clk = clk_register_fixed_rate(NULL, clk_src_names[CLK_SRC_IRC], lpc18xx_cgu_register_source_clks()
609 if (IS_ERR(clk)) lpc18xx_cgu_register_source_clks()
610 pr_warn("%s: failed to register irc clk\n", __func__); lpc18xx_cgu_register_source_clks()
614 clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0], lpc18xx_cgu_register_source_clks()
617 if (IS_ERR(clk)) lpc18xx_cgu_register_source_clks()
618 pr_warn("%s: failed to register osc clk\n", __func__); lpc18xx_cgu_register_source_clks()
622 clk = lpc18xx_cgu_register_pll(&lpc18xx_cgu_src_clk_plls[i], lpc18xx_cgu_register_source_clks()
624 if (IS_ERR(clk)) lpc18xx_cgu_register_source_clks()
630 clk = lpc18xx_cgu_register_div(&lpc18xx_cgu_src_clk_divs[i], lpc18xx_cgu_register_source_clks()
632 if (IS_ERR(clk)) lpc18xx_cgu_register_source_clks()
637 static struct clk *clk_base[BASE_CLK_MAX];
651 pr_warn("%s: register base clk %d failed\n", __func__, i); lpc18xx_cgu_register_base_clks()
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