Searched refs:REG_WR (Results 1 - 104 of 104) sorted by relevance

/linux-4.1.27/arch/cris/arch-v32/mm/
H A Dl2cache.c19 REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl); l2cache_init()
25 REG_WR(l2cache, regi_l2cache, rw_cfg, cfg); l2cache_init()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Ddma.h78 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
84 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
90 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
96 REG_WR( dma, inst, rw_cfg, c); } while( 0 )
103 REG_WR(dma, inst, rw_stream_cmd, __x); \
125 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
H A Dirq_nmi_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dstrcop_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dconfig_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Drt_trace_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Data_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dbif_slave_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dmarb_bp_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dmarb_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
282 #ifndef REG_WR
283 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dbif_core_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Deth_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dextmem_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dser_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dsser_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dbif_dma_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Ddma_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_init_ops.h55 REG_WR(bp, addr + i*4, data[i]); bnx2x_init_str_wr()
263 REG_WR(bp, addr, op->write.val); bnx2x_init_block()
495 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); bnx2x_init_pxp_arb()
496 REG_WR(bp, read_arb_addr[i].add, bnx2x_init_pxp_arb()
498 REG_WR(bp, read_arb_addr[i].ubound, bnx2x_init_pxp_arb()
506 REG_WR(bp, write_arb_addr[i].l, bnx2x_init_pxp_arb()
509 REG_WR(bp, write_arb_addr[i].add, bnx2x_init_pxp_arb()
512 REG_WR(bp, write_arb_addr[i].ubound, bnx2x_init_pxp_arb()
517 REG_WR(bp, write_arb_addr[i].l, bnx2x_init_pxp_arb()
521 REG_WR(bp, write_arb_addr[i].add, bnx2x_init_pxp_arb()
525 REG_WR(bp, write_arb_addr[i].ubound, bnx2x_init_pxp_arb()
533 REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val); bnx2x_init_pxp_arb()
538 REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val); bnx2x_init_pxp_arb()
540 REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order); bnx2x_init_pxp_arb()
541 REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order); bnx2x_init_pxp_arb()
542 REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order); bnx2x_init_pxp_arb()
543 REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order); bnx2x_init_pxp_arb()
546 REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00); bnx2x_init_pxp_arb()
549 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); bnx2x_init_pxp_arb()
551 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); bnx2x_init_pxp_arb()
553 REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); bnx2x_init_pxp_arb()
565 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val); bnx2x_init_pxp_arb()
568 REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); bnx2x_init_pxp_arb()
571 REG_WR(bp, PXP2_REG_WR_HC_MPS, val); bnx2x_init_pxp_arb()
572 REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); bnx2x_init_pxp_arb()
573 REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); bnx2x_init_pxp_arb()
574 REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); bnx2x_init_pxp_arb()
575 REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); bnx2x_init_pxp_arb()
576 REG_WR(bp, PXP2_REG_WR_QM_MPS, val); bnx2x_init_pxp_arb()
577 REG_WR(bp, PXP2_REG_WR_TM_MPS, val); bnx2x_init_pxp_arb()
578 REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); bnx2x_init_pxp_arb()
579 REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); bnx2x_init_pxp_arb()
580 REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); bnx2x_init_pxp_arb()
588 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20); bnx2x_init_pxp_arb()
733 REG_WR(bp, start_reg + BP_FUNC(bp)*4, bnx2x_ilt_boundry_init_op()
755 REG_WR(bp, start_reg, (ilt_start + ilt_cli->start)); bnx2x_ilt_boundry_init_op()
756 REG_WR(bp, end_reg, (ilt_start + ilt_cli->end)); bnx2x_ilt_boundry_init_op()
822 REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12)); bnx2x_ilt_init_client_psz()
863 REG_WR(bp, QM_REG_CONNNUM_0 + port*4, bnx2x_qm_init_cid_count()
878 REG_WR(bp, base_reg + i*4, bnx2x_qm_set_ptr_table()
923 REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count); bnx2x_src_init_t2()
H A Dbnx2x_main.c299 REG_WR(bp, addr, U64_LO(mapping)); __storm_memset_dma_mapping()
300 REG_WR(bp, addr + 4, U64_HI(mapping)); __storm_memset_dma_mapping()
459 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); bnx2x_post_dmae()
461 REG_WR(bp, dmae_reg_go_c[idx], 1); bnx2x_post_dmae()
848 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); bnx2x_hc_int_disable()
866 REG_WR(bp, addr, val); bnx2x_hc_int_disable()
884 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); bnx2x_igu_int_disable()
1397 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); bnx2x_send_final_clnup()
1407 REG_WR(bp, comp_addr, 0); bnx2x_send_final_clnup()
1504 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); bnx2x_pf_flr_clnup()
1536 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); bnx2x_pf_flr_clnup()
1572 REG_WR(bp, addr, val); bnx2x_hc_int_enable()
1579 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); bnx2x_hc_int_enable()
1585 REG_WR(bp, addr, val); bnx2x_hc_int_enable()
1602 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); bnx2x_hc_int_enable()
1603 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); bnx2x_hc_int_enable()
1641 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); bnx2x_igu_int_enable()
1650 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); bnx2x_igu_int_enable()
1666 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); bnx2x_igu_int_enable()
1667 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); bnx2x_igu_int_enable()
1739 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); bnx2x_trylock_hw_lock()
2014 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); bnx2x_acquire_hw_lock()
2059 REG_WR(bp, hw_lock_control_reg, resource_bit); bnx2x_release_hw_lock()
2141 REG_WR(bp, MISC_REG_GPIO, gpio_reg); bnx2x_set_gpio()
2187 REG_WR(bp, MISC_REG_GPIO, gpio_reg); bnx2x_set_mult_gpio()
2236 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); bnx2x_set_gpio_int()
2281 REG_WR(bp, MISC_REG_SPIO, spio_reg); bnx2x_set_spio()
2333 REG_WR(bp, BAR_USTRORM_INTMEM + bnx2x_init_dropless_fc()
2831 REG_WR(bp, addr_to_write + i*sizeof(u32), bnx2x_handle_afex_cmd()
2934 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, bnx2x_handle_update_svid_cmd()
2982 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); bnx2x_pmf_update()
2983 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); bnx2x_pmf_update()
2985 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); bnx2x_pmf_update()
2986 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); bnx2x_pmf_update()
3070 REG_WR(bp, XSEM_REG_FAST_MEMORY + bnx2x_func_init()
3289 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + bnx2x_pf_init()
3294 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + bnx2x_pf_init()
3347 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); bnx2x_e1h_disable()
3355 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); bnx2x_e1h_enable()
3919 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); bnx2x_acquire_alr()
3937 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); bnx2x_release_alr()
3990 REG_WR(bp, aeu_addr, aeu_mask); bnx2x_attn_int_asserted()
4009 REG_WR(bp, nig_int_mask_addr, 0); bnx2x_attn_int_asserted()
4031 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); bnx2x_attn_int_asserted()
4035 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); bnx2x_attn_int_asserted()
4039 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); bnx2x_attn_int_asserted()
4044 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); bnx2x_attn_int_asserted()
4048 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); bnx2x_attn_int_asserted()
4052 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); bnx2x_attn_int_asserted()
4066 REG_WR(bp, reg_addr, asserted); bnx2x_attn_int_asserted()
4085 REG_WR(bp, nig_int_mask_addr, nig_mask); bnx2x_attn_int_asserted()
4128 REG_WR(bp, reg_offset, val); bnx2x_attn_int_deasserted0()
4147 REG_WR(bp, reg_offset, val); bnx2x_attn_int_deasserted0()
4178 REG_WR(bp, reg_offset, val); bnx2x_attn_int_deasserted1()
4222 REG_WR(bp, reg_offset, val); bnx2x_attn_int_deasserted2()
4239 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); bnx2x_attn_int_deasserted3()
4299 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); bnx2x_attn_int_deasserted3()
4300 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); bnx2x_attn_int_deasserted3()
4301 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); bnx2x_attn_int_deasserted3()
4302 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); bnx2x_attn_int_deasserted3()
4308 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); bnx2x_attn_int_deasserted3()
4327 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); bnx2x_attn_int_deasserted3()
4365 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); bnx2x_set_reset_global()
4379 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); bnx2x_clear_reset_global()
4411 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); bnx2x_set_reset_done()
4431 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); bnx2x_set_reset_in_progress()
4479 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); bnx2x_set_pf_load()
4516 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); bnx2x_clear_pf_load()
4874 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, bnx2x_check_blocks_with_parity3()
5133 REG_WR(bp, reg_addr, val); bnx2x_attn_int_deasserted()
5149 REG_WR(bp, reg_addr, aeu_mask); bnx2x_attn_int_deasserted()
5779 REG_WR(bp, addr + i, fill); bnx2x_fill()
5793 REG_WR(bp, BAR_CSTRORM_INTMEM + bnx2x_wr_fp_sb_data()
5838 REG_WR(bp, BAR_CSTRORM_INTMEM + bnx2x_wr_sp_sb_data()
6033 REG_WR(bp, reg_offset, U64_LO(section)); bnx2x_init_def_sb()
6034 REG_WR(bp, reg_offset + 4, U64_HI(section)); bnx2x_init_def_sb()
6036 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); bnx2x_init_def_sb()
6037 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); bnx2x_init_def_sb()
6245 REG_WR(bp, BAR_USTRORM_INTMEM + bnx2x_init_internal_common()
6641 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); bnx2x_int_mem_test()
6642 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); bnx2x_int_mem_test()
6643 REG_WR(bp, CFC_REG_DEBUG0, 0x1); bnx2x_int_mem_test()
6644 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); bnx2x_int_mem_test()
6647 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); bnx2x_int_mem_test()
6686 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); bnx2x_int_mem_test()
6688 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); bnx2x_int_mem_test()
6696 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); bnx2x_int_mem_test()
6697 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); bnx2x_int_mem_test()
6698 REG_WR(bp, CFC_REG_DEBUG0, 0x1); bnx2x_int_mem_test()
6699 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); bnx2x_int_mem_test()
6702 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); bnx2x_int_mem_test()
6732 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); bnx2x_int_mem_test()
6751 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); bnx2x_int_mem_test()
6753 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); bnx2x_int_mem_test()
6759 REG_WR(bp, PRS_REG_NIC_MODE, 1); bnx2x_int_mem_test()
6762 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); bnx2x_int_mem_test()
6763 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); bnx2x_int_mem_test()
6764 REG_WR(bp, CFC_REG_DEBUG0, 0x0); bnx2x_int_mem_test()
6765 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); bnx2x_int_mem_test()
6776 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); bnx2x_enable_blocks_attention()
6778 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); bnx2x_enable_blocks_attention()
6780 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); bnx2x_enable_blocks_attention()
6781 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); bnx2x_enable_blocks_attention()
6782 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); bnx2x_enable_blocks_attention()
6789 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); bnx2x_enable_blocks_attention()
6790 REG_WR(bp, QM_REG_QM_INT_MASK, 0); bnx2x_enable_blocks_attention()
6791 REG_WR(bp, TM_REG_TM_INT_MASK, 0); bnx2x_enable_blocks_attention()
6792 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); bnx2x_enable_blocks_attention()
6793 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); bnx2x_enable_blocks_attention()
6794 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); bnx2x_enable_blocks_attention()
6795 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */ bnx2x_enable_blocks_attention()
6796 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */ bnx2x_enable_blocks_attention()
6797 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); bnx2x_enable_blocks_attention()
6798 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); bnx2x_enable_blocks_attention()
6799 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); bnx2x_enable_blocks_attention()
6800 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */ bnx2x_enable_blocks_attention()
6801 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */ bnx2x_enable_blocks_attention()
6802 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); bnx2x_enable_blocks_attention()
6803 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); bnx2x_enable_blocks_attention()
6804 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); bnx2x_enable_blocks_attention()
6805 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); bnx2x_enable_blocks_attention()
6806 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */ bnx2x_enable_blocks_attention()
6807 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */ bnx2x_enable_blocks_attention()
6815 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); bnx2x_enable_blocks_attention()
6817 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); bnx2x_enable_blocks_attention()
6818 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); bnx2x_enable_blocks_attention()
6819 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); bnx2x_enable_blocks_attention()
6820 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */ bnx2x_enable_blocks_attention()
6824 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); bnx2x_enable_blocks_attention()
6826 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); bnx2x_enable_blocks_attention()
6827 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); bnx2x_enable_blocks_attention()
6828 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */ bnx2x_enable_blocks_attention()
6829 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ bnx2x_enable_blocks_attention()
6837 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, bnx2x_reset_common()
6845 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); bnx2x_reset_common()
6914 REG_WR(bp, MISC_REG_SPIO_INT, val); bnx2x_setup_fan_failure_detection()
6919 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); bnx2x_setup_fan_failure_detection()
6927 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); bnx2x_pf_disable()
6928 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); bnx2x_pf_disable()
6929 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); bnx2x_pf_disable()
6955 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); bnx2x_config_endianity()
6956 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); bnx2x_config_endianity()
6957 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); bnx2x_config_endianity()
6958 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); bnx2x_config_endianity()
6959 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); bnx2x_config_endianity()
6962 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); bnx2x_config_endianity()
6964 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); bnx2x_config_endianity()
6965 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); bnx2x_config_endianity()
6966 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); bnx2x_config_endianity()
6967 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); bnx2x_config_endianity()
7002 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); bnx2x_init_hw_common()
7009 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); bnx2x_init_hw_common()
7028 REG_WR(bp, bnx2x_init_hw_common()
7045 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); bnx2x_init_hw_common()
7054 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); bnx2x_init_hw_common()
7090 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); bnx2x_init_hw_common()
7091 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); bnx2x_init_hw_common()
7092 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); bnx2x_init_hw_common()
7163 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); bnx2x_init_hw_common()
7164 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); bnx2x_init_hw_common()
7165 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); bnx2x_init_hw_common()
7168 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); bnx2x_init_hw_common()
7169 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); bnx2x_init_hw_common()
7217 REG_WR(bp, QM_REG_SOFT_RESET, 1); bnx2x_init_hw_common()
7218 REG_WR(bp, QM_REG_SOFT_RESET, 0); bnx2x_init_hw_common()
7227 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); bnx2x_init_hw_common()
7232 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); bnx2x_init_hw_common()
7235 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); bnx2x_init_hw_common()
7242 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); bnx2x_init_hw_common()
7243 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); bnx2x_init_hw_common()
7244 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); bnx2x_init_hw_common()
7245 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); bnx2x_init_hw_common()
7246 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); bnx2x_init_hw_common()
7251 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, bnx2x_init_hw_common()
7263 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, bnx2x_init_hw_common()
7266 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, bnx2x_init_hw_common()
7279 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, bnx2x_init_hw_common()
7281 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, bnx2x_init_hw_common()
7293 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); bnx2x_init_hw_common()
7294 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); bnx2x_init_hw_common()
7295 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); bnx2x_init_hw_common()
7296 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); bnx2x_init_hw_common()
7297 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); bnx2x_init_hw_common()
7299 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, bnx2x_init_hw_common()
7304 REG_WR(bp, SRC_REG_SOFT_RST, 1); bnx2x_init_hw_common()
7309 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); bnx2x_init_hw_common()
7310 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); bnx2x_init_hw_common()
7311 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); bnx2x_init_hw_common()
7312 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); bnx2x_init_hw_common()
7313 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); bnx2x_init_hw_common()
7314 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); bnx2x_init_hw_common()
7315 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); bnx2x_init_hw_common()
7316 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); bnx2x_init_hw_common()
7317 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); bnx2x_init_hw_common()
7318 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); bnx2x_init_hw_common()
7320 REG_WR(bp, SRC_REG_SOFT_RST, 0); bnx2x_init_hw_common()
7330 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); bnx2x_init_hw_common()
7333 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); bnx2x_init_hw_common()
7335 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); bnx2x_init_hw_common()
7338 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); bnx2x_init_hw_common()
7343 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); bnx2x_init_hw_common()
7349 REG_WR(bp, 0x2814, 0xffffffff); bnx2x_init_hw_common()
7350 REG_WR(bp, 0x3820, 0xffffffff); bnx2x_init_hw_common()
7353 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, bnx2x_init_hw_common()
7356 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, bnx2x_init_hw_common()
7360 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, bnx2x_init_hw_common()
7370 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); bnx2x_init_hw_common()
7374 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); bnx2x_init_hw_common()
7395 REG_WR(bp, CFC_REG_DEBUG0, 0); bnx2x_init_hw_common()
7455 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); bnx2x_init_hw_port()
7467 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); bnx2x_init_hw_port()
7484 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); bnx2x_init_hw_port()
7485 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); bnx2x_init_hw_port()
7508 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); bnx2x_init_hw_port()
7509 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); bnx2x_init_hw_port()
7513 REG_WR(bp, (BP_PORT(bp) ? bnx2x_init_hw_port()
7521 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7524 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7527 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7535 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7559 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); bnx2x_init_hw_port()
7562 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); bnx2x_init_hw_port()
7564 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); bnx2x_init_hw_port()
7567 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); bnx2x_init_hw_port()
7569 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); bnx2x_init_hw_port()
7579 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); bnx2x_init_hw_port()
7580 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); bnx2x_init_hw_port()
7594 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); bnx2x_init_hw_port()
7598 REG_WR(bp, reg, bnx2x_init_hw_port()
7603 REG_WR(bp, reg, bnx2x_init_hw_port()
7614 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7618 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7624 REG_WR(bp, BP_PORT(bp) ? bnx2x_init_hw_port()
7629 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); bnx2x_init_hw_port()
7633 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, bnx2x_init_hw_port()
7648 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : bnx2x_init_hw_port()
7652 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); bnx2x_init_hw_port()
7653 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); bnx2x_init_hw_port()
7654 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); bnx2x_init_hw_port()
7665 REG_WR(bp, reg_addr, val); bnx2x_init_hw_port()
7711 REG_WR(bp, igu_addr_data, data); bnx2x_igu_clear_sb_gen()
7716 REG_WR(bp, igu_addr_ctl, ctl); bnx2x_igu_clear_sb_gen()
7748 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); bnx2x_init_searcher()
7788 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : bnx2x_reset_nic_mode()
7796 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + bnx2x_reset_nic_mode()
7803 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : bnx2x_reset_nic_mode()
7818 REG_WR(bp, PRS_REG_NIC_MODE, 0); bnx2x_reset_nic_mode()
7824 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : bnx2x_reset_nic_mode()
7827 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + bnx2x_reset_nic_mode()
7835 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : bnx2x_reset_nic_mode()
7879 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, bnx2x_clean_pglue_errors()
7910 REG_WR(bp, addr, val); bnx2x_init_hw_func()
7938 REG_WR(bp, PRS_REG_NIC_MODE, 0); bnx2x_init_hw_func()
7942 REG_WR(bp, PRS_REG_NIC_MODE, 1); bnx2x_init_hw_func()
7966 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); bnx2x_init_hw_func()
7968 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); bnx2x_init_hw_func()
7992 REG_WR(bp, QM_REG_PF_EN, 1); bnx2x_init_hw_func()
7995 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); bnx2x_init_hw_func()
7996 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); bnx2x_init_hw_func()
7997 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); bnx2x_init_hw_func()
7998 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); bnx2x_init_hw_func()
8004 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ bnx2x_init_hw_func()
8018 REG_WR(bp, PBF_REG_DISABLE_PF, 0); bnx2x_init_hw_func()
8025 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); bnx2x_init_hw_func()
8029 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); bnx2x_init_hw_func()
8030 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, bnx2x_init_hw_func()
8040 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); bnx2x_init_hw_func()
8042 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); bnx2x_init_hw_func()
8043 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); bnx2x_init_hw_func()
8050 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); bnx2x_init_hw_func()
8053 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); bnx2x_init_hw_func()
8054 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); bnx2x_init_hw_func()
8091 REG_WR(bp, addr, 0); bnx2x_init_hw_func()
8121 REG_WR(bp, addr, 0); bnx2x_init_hw_func()
8145 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); bnx2x_init_hw_func()
8146 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); bnx2x_init_hw_func()
8147 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); bnx2x_init_hw_func()
8148 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); bnx2x_init_hw_func()
8149 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); bnx2x_init_hw_func()
8150 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); bnx2x_init_hw_func()
8155 REG_WR(bp, 0x2114, 0xffffffff); bnx2x_init_hw_func()
8156 REG_WR(bp, 0x2120, 0xffffffff); bnx2x_init_hw_func()
8882 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8887 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8888 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8890 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8891 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8896 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8939 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); bnx2x_reset_port()
8942 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); bnx2x_reset_port()
8944 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : bnx2x_reset_port()
8948 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); bnx2x_reset_port()
9166 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : bnx2x_disable_ptp()
9170 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : bnx2x_disable_ptp()
9172 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : bnx2x_disable_ptp()
9174 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : bnx2x_disable_ptp()
9176 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : bnx2x_disable_ptp()
9180 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : bnx2x_disable_ptp()
9241 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9361 REG_WR(bp, addr, val); bnx2x_disable_close_the_gate()
9366 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); bnx2x_disable_close_the_gate()
9378 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); bnx2x_set_234_gates()
9380 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); bnx2x_set_234_gates()
9387 REG_WR(bp, HC_REG_CONFIG_1, bnx2x_set_234_gates()
9392 REG_WR(bp, HC_REG_CONFIG_0, bnx2x_set_234_gates()
9399 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, bnx2x_set_234_gates()
9460 REG_WR(bp, shmem + validity_offset, 0); bnx2x_reset_mcp_prep()
9520 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); bnx2x_pxp_prep()
9521 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); bnx2x_pxp_prep()
9615 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_process_kill_chip_reset()
9618 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, bnx2x_process_kill_chip_reset()
9624 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, bnx2x_process_kill_chip_reset()
9630 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); bnx2x_process_kill_chip_reset()
9712 REG_WR(bp, MISC_REG_UNPREPARED, 0); bnx2x_process_kill()
9738 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); bnx2x_process_kill()
10172 REG_WR(bp, vals->umac_addr[port], 0); bnx2x_prev_unload_close_umac()
10212 REG_WR(bp, vals->bmac_addr, wb_data[0]); bnx2x_prev_unload_close_mac()
10213 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); bnx2x_prev_unload_close_mac()
10218 REG_WR(bp, vals->emac_addr, 0); bnx2x_prev_unload_close_mac()
10225 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, bnx2x_prev_unload_close_mac()
10227 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, bnx2x_prev_unload_close_mac()
10231 REG_WR(bp, vals->xmac_addr, 0); bnx2x_prev_unload_close_mac()
10288 REG_WR(bp, addr, tmp_reg); bnx2x_prev_unload_undi_inc()
10544 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); bnx2x_prev_unload_common()
10550 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); bnx2x_prev_unload_common()
10584 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); bnx2x_prev_unload_common()
10586 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); bnx2x_prev_unload_common()
10588 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); bnx2x_prev_unload_common()
10590 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); bnx2x_prev_unload_common()
10592 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); bnx2x_prev_unload_common()
10593 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); bnx2x_prev_unload_common()
10625 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, bnx2x_prev_unload()
10630 REG_WR(bp, hw_lock_reg, 0xffffffff); bnx2x_prev_unload()
11695 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); bnx2x_get_hwinfo()
11696 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); bnx2x_get_hwinfo()
12755 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); bnx2x_init_dev()
12756 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); bnx2x_init_dev()
12757 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); bnx2x_init_dev()
12758 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); bnx2x_init_dev()
12761 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); bnx2x_init_dev()
12762 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); bnx2x_init_dev()
12763 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); bnx2x_init_dev()
12764 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); bnx2x_init_dev()
12772 REG_WR(bp, bnx2x_init_dev()
13945 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); bnx2x_notify_link_changed()
14323 REG_WR(bp, scratch_offset + i, bnx2x_drv_ctl()
14552 REG_WR(bp, pretend_reg, pretend_func_val); bnx2x_pretend_func()
14576 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : bnx2x_ptp_task()
14607 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : bnx2x_set_rx_ts()
14708 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : bnx2x_configure_ptp_filters()
14710 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : bnx2x_configure_ptp_filters()
14730 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : bnx2x_configure_ptp_filters()
14732 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : bnx2x_configure_ptp_filters()
14740 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : bnx2x_configure_ptp_filters()
14742 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : bnx2x_configure_ptp_filters()
14750 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : bnx2x_configure_ptp_filters()
14752 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : bnx2x_configure_ptp_filters()
14761 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : bnx2x_configure_ptp_filters()
14763 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : bnx2x_configure_ptp_filters()
14774 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : bnx2x_configure_ptp_filters()
14819 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : bnx2x_configure_ptp()
14821 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : bnx2x_configure_ptp()
14823 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : bnx2x_configure_ptp()
14825 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : bnx2x_configure_ptp()
14829 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : bnx2x_configure_ptp()
14833 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : bnx2x_configure_ptp()
14849 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : bnx2x_configure_ptp()
14851 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : bnx2x_configure_ptp()
H A Dbnx2x_link.c229 REG_WR(bp, reg, val); bnx2x_bits_en()
238 REG_WR(bp, reg, val); bnx2x_bits_dis()
266 REG_WR(bp, params->lfa_base + bnx2x_check_lfa()
385 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); bnx2x_get_epio()
407 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); bnx2x_set_epio()
411 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); bnx2x_set_epio()
458 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); bnx2x_ets_e2e3a0_disabled()
467 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); bnx2x_ets_e2e3a0_disabled()
473 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); bnx2x_ets_e2e3a0_disabled()
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); bnx2x_ets_e2e3a0_disabled()
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); bnx2x_ets_e2e3a0_disabled()
482 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); bnx2x_ets_e2e3a0_disabled()
483 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); bnx2x_ets_e2e3a0_disabled()
489 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); bnx2x_ets_e2e3a0_disabled()
490 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); bnx2x_ets_e2e3a0_disabled()
492 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); bnx2x_ets_e2e3a0_disabled()
493 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); bnx2x_ets_e2e3a0_disabled()
495 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); bnx2x_ets_e2e3a0_disabled()
543 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : bnx2x_ets_e3b0_set_credit_upper_bound_nig()
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : bnx2x_ets_e3b0_set_credit_upper_bound_nig()
551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : bnx2x_ets_e3b0_set_credit_upper_bound_nig()
557 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, bnx2x_ets_e3b0_set_credit_upper_bound_nig()
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, bnx2x_ets_e3b0_set_credit_upper_bound_nig()
561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, bnx2x_ets_e3b0_set_credit_upper_bound_nig()
585 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); bnx2x_ets_e3b0_nig_disabled()
586 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); bnx2x_ets_e3b0_nig_disabled()
588 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); bnx2x_ets_e3b0_nig_disabled()
589 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); bnx2x_ets_e3b0_nig_disabled()
594 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : bnx2x_ets_e3b0_nig_disabled()
601 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); bnx2x_ets_e3b0_nig_disabled()
602 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); bnx2x_ets_e3b0_nig_disabled()
605 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, bnx2x_ets_e3b0_nig_disabled()
607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); bnx2x_ets_e3b0_nig_disabled()
618 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); bnx2x_ets_e3b0_nig_disabled()
620 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); bnx2x_ets_e3b0_nig_disabled()
622 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : bnx2x_ets_e3b0_nig_disabled()
631 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : bnx2x_ets_e3b0_nig_disabled()
639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : bnx2x_ets_e3b0_nig_disabled()
644 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); bnx2x_ets_e3b0_nig_disabled()
645 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); bnx2x_ets_e3b0_nig_disabled()
646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); bnx2x_ets_e3b0_nig_disabled()
679 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
705 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); bnx2x_ets_e3b0_pbf_disabled()
708 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); bnx2x_ets_e3b0_pbf_disabled()
713 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); bnx2x_ets_e3b0_pbf_disabled()
716 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : bnx2x_ets_e3b0_pbf_disabled()
722 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : bnx2x_ets_e3b0_pbf_disabled()
725 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : bnx2x_ets_e3b0_pbf_disabled()
739 REG_WR(bp, base_weight + (0x4 * i), 0); bnx2x_ets_e3b0_pbf_disabled()
806 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : bnx2x_ets_e3b0_cli_map()
809 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : bnx2x_ets_e3b0_cli_map()
812 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : bnx2x_ets_e3b0_cli_map()
816 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : bnx2x_ets_e3b0_cli_map()
889 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); bnx2x_ets_e3b0_set_cos_bw()
891 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); bnx2x_ets_e3b0_set_cos_bw()
1113 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1116 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1122 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1127 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1247 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); bnx2x_ets_bw_limit_common()
1254 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); bnx2x_ets_bw_limit_common()
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, bnx2x_ets_bw_limit_common()
1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, bnx2x_ets_bw_limit_common()
1262 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); bnx2x_ets_bw_limit_common()
1265 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); bnx2x_ets_bw_limit_common()
1273 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); bnx2x_ets_bw_limit_common()
1276 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, bnx2x_ets_bw_limit_common()
1278 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, bnx2x_ets_bw_limit_common()
1307 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); bnx2x_ets_bw_limit()
1308 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); bnx2x_ets_bw_limit()
1310 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); bnx2x_ets_bw_limit()
1311 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); bnx2x_ets_bw_limit()
1328 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); bnx2x_ets_strict()
1332 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); bnx2x_ets_strict()
1334 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); bnx2x_ets_strict()
1336 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); bnx2x_ets_strict()
1339 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); bnx2x_ets_strict()
1349 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); bnx2x_ets_strict()
1392 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); bnx2x_update_pfc_xmac()
1393 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); bnx2x_update_pfc_xmac()
1394 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); bnx2x_update_pfc_xmac()
1400 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); bnx2x_update_pfc_xmac()
1401 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); bnx2x_update_pfc_xmac()
1402 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); bnx2x_update_pfc_xmac()
1406 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, bnx2x_update_pfc_xmac()
1411 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, bnx2x_update_pfc_xmac()
1447 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); bnx2x_set_mdio_clk()
1485 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_emac_init()
1488 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, bnx2x_emac_init()
1526 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, bnx2x_set_xumac_nig()
1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, bnx2x_set_xumac_nig()
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : bnx2x_set_xumac_nig()
1550 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); bnx2x_set_umac_rxtx()
1560 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_umac_enable()
1564 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, bnx2x_umac_enable()
1570 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); bnx2x_umac_enable()
1603 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); bnx2x_umac_enable()
1609 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, bnx2x_umac_enable()
1611 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); bnx2x_umac_enable()
1617 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, bnx2x_umac_enable()
1622 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, bnx2x_umac_enable()
1630 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); bnx2x_umac_enable()
1639 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); bnx2x_umac_enable()
1644 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); bnx2x_umac_enable()
1675 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_xmac_init()
1679 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, bnx2x_xmac_init()
1685 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); bnx2x_xmac_init()
1688 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); bnx2x_xmac_init()
1691 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); bnx2x_xmac_init()
1696 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); bnx2x_xmac_init()
1701 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); bnx2x_xmac_init()
1705 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_xmac_init()
1709 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, bnx2x_xmac_init()
1728 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, bnx2x_set_xmac_rxtx()
1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, bnx2x_set_xmac_rxtx()
1738 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); bnx2x_set_xmac_rxtx()
1760 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); bnx2x_xmac_enable()
1766 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, bnx2x_xmac_enable()
1769 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); bnx2x_xmac_enable()
1770 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, bnx2x_xmac_enable()
1775 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); bnx2x_xmac_enable()
1778 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); bnx2x_xmac_enable()
1785 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); bnx2x_xmac_enable()
1786 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); bnx2x_xmac_enable()
1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); bnx2x_xmac_enable()
1803 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); bnx2x_xmac_enable()
1823 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_emac_enable()
1827 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); bnx2x_emac_enable()
1837 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); bnx2x_emac_enable()
1839 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); bnx2x_emac_enable()
1844 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); bnx2x_emac_enable()
1913 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); bnx2x_emac_enable()
1921 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); bnx2x_emac_enable()
1924 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); bnx2x_emac_enable()
1925 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); bnx2x_emac_enable()
1926 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); bnx2x_emac_enable()
1929 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); bnx2x_emac_enable()
1936 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); bnx2x_emac_enable()
1937 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); bnx2x_emac_enable()
1939 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); bnx2x_emac_enable()
2103 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); bnx2x_pfc_nig_rx_priority_mask()
2111 REG_WR(bp, params->shmem_base + bnx2x_update_mng()
2121 REG_WR(bp, params->shmem2_base + bnx2x_update_link_attr()
2175 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : bnx2x_update_pfc_nig()
2177 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : bnx2x_update_pfc_nig()
2179 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : bnx2x_update_pfc_nig()
2181 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : bnx2x_update_pfc_nig()
2184 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : bnx2x_update_pfc_nig()
2187 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : bnx2x_update_pfc_nig()
2190 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : bnx2x_update_pfc_nig()
2194 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : bnx2x_update_pfc_nig()
2198 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : bnx2x_update_pfc_nig()
2209 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : bnx2x_update_pfc_nig()
2213 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : bnx2x_update_pfc_nig()
2217 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : bnx2x_update_pfc_nig()
2271 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); bnx2x_update_pfc()
2415 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_bmac_enable()
2420 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, bnx2x_bmac_enable()
2424 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); bnx2x_bmac_enable()
2431 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); bnx2x_bmac_enable()
2432 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); bnx2x_bmac_enable()
2439 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); bnx2x_bmac_enable()
2440 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); bnx2x_bmac_enable()
2441 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); bnx2x_bmac_enable()
2442 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); bnx2x_bmac_enable()
2443 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); bnx2x_bmac_enable()
2444 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); bnx2x_bmac_enable()
2485 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); bnx2x_pbf_update()
2509 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); bnx2x_pbf_update()
2511 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); bnx2x_pbf_update()
2518 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); bnx2x_pbf_update()
2520 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); bnx2x_pbf_update()
2532 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); bnx2x_pbf_update()
2537 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); bnx2x_pbf_update()
2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); bnx2x_pbf_update()
2542 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); bnx2x_pbf_update()
2605 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, bnx2x_cl22_write()
2612 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); bnx2x_cl22_write()
2627 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); bnx2x_cl22_write()
2641 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, bnx2x_cl22_read()
2648 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); bnx2x_cl22_read()
2666 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); bnx2x_cl22_read()
2693 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); bnx2x_cl45_read()
2714 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); bnx2x_cl45_read()
2769 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); bnx2x_cl45_write()
2789 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); bnx2x_cl45_write()
2916 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), bnx2x_eee_set_timers()
2966 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); bnx2x_eee_disable()
2983 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); bnx2x_eee_advertise()
3007 REG_WR(bp, params->shmem2_base + bnx2x_update_mng_eee()
3111 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); bnx2x_bsc_read()
3115 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); bnx2x_bsc_read()
3122 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); bnx2x_bsc_read()
3146 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); bnx2x_bsc_read()
3321 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); bnx2x_set_serdes_access()
3322 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); bnx2x_set_serdes_access()
3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); bnx2x_set_serdes_access()
3327 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); bnx2x_set_serdes_access()
3339 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); bnx2x_serdes_deassert()
3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); bnx2x_serdes_deassert()
3345 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, bnx2x_serdes_deassert()
3357 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); bnx2x_xgxs_specific_func()
3358 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, bnx2x_xgxs_specific_func()
3375 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); bnx2x_xgxs_deassert()
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); bnx2x_xgxs_deassert()
6103 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, bnx2x_rearm_latch_signal()
6251 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, bnx2x_set_xgxs_loopback()
6272 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, bnx2x_set_xgxs_loopback()
6314 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); bnx2x_set_led()
6315 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, bnx2x_set_led()
6345 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); bnx2x_set_led()
6346 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); bnx2x_set_led()
6366 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); bnx2x_set_led()
6371 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); bnx2x_set_led()
6373 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, bnx2x_set_led()
6378 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); bnx2x_set_led()
6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, bnx2x_set_led()
6396 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); bnx2x_set_led()
6399 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, bnx2x_set_led()
6402 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, bnx2x_set_led()
6404 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + bnx2x_set_led()
6416 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 bnx2x_set_led()
6418 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + bnx2x_set_led()
6420 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + bnx2x_set_led()
6601 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, bnx2x_int_link_reset()
6642 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); bnx2x_update_link_down()
6646 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); bnx2x_update_link_down()
6656 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), bnx2x_update_link_down()
6658 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), bnx2x_update_link_down()
6707 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + bnx2x_update_link_up()
6709 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); bnx2x_update_link_up()
6710 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + bnx2x_update_link_up()
6746 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); bnx2x_update_link_up()
6777 REG_WR(bp, addr, val); bnx2x_chng_link_count()
6839 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); bnx2x_link_update()
6980 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, bnx2x_link_update()
7067 REG_WR(bp, ver_addr, spirom_ver); bnx2x_save_spirom_version()
8229 REG_WR(bp, sync_offset, media_types); bnx2x_get_edc_mode()
8590 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); bnx2x_warpcore_hw_reset()
8593 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); bnx2x_warpcore_hw_reset()
8594 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); bnx2x_warpcore_hw_reset()
8595 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); bnx2x_warpcore_hw_reset()
11193 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); bnx2x_54618se_config_loopback()
11198 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); bnx2x_54618se_config_loopback()
12367 REG_WR(bp, sync_offset, media_types); bnx2x_phy_probe()
12394 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_init_bmac_loopback()
12413 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_init_emac_loopback()
12439 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_init_xmac_loopback()
12454 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_init_umac_loopback()
12504 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_init_xgxs_loopback()
12517 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); bnx2x_set_rx_filter()
12520 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, bnx2x_set_rx_filter()
12524 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : bnx2x_set_rx_filter()
12563 REG_WR(bp, GRCBASE_MISC + bnx2x_avoid_link_flap()
12567 REG_WR(bp, GRCBASE_MISC + bnx2x_avoid_link_flap()
12591 REG_WR(bp, params->lfa_base + bnx2x_avoid_link_flap()
12595 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_avoid_link_flap()
12614 REG_WR(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12618 REG_WR(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12622 REG_WR(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12627 REG_WR(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12638 REG_WR(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12657 REG_WR(bp, params->lfa_base + bnx2x_cannot_avoid_link_flap()
12771 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); bnx2x_link_reset()
12775 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); bnx2x_link_reset()
12776 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); bnx2x_link_reset()
12787 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); bnx2x_link_reset()
12826 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, bnx2x_link_reset()
12828 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); bnx2x_link_reset()
12829 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); bnx2x_link_reset()
12835 REG_WR(bp, xmac_base + XMAC_REG_CTRL, bnx2x_link_reset()
12855 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); bnx2x_lfa_reset()
12890 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_lfa_reset()
13036 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); bnx2x_8726_common_init_phy()
13301 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); bnx2x_common_init_phy()
13404 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); bnx2x_analyze_link_error()
13417 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); bnx2x_analyze_link_error()
13466 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); bnx2x_check_half_open_conn()
13467 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, bnx2x_check_half_open_conn()
13758 REG_WR(bp, sync_offset, vars->aeu_int_mask); bnx2x_init_mod_abs_int()
13771 REG_WR(bp, offset, aeu_mask); bnx2x_init_mod_abs_int()
13776 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); bnx2x_init_mod_abs_int()
H A Dbnx2x_init.h231 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos); bnx2x_map_q_cos()
236 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map)); bnx2x_map_q_cos()
241 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map); bnx2x_map_q_cos()
253 REG_WR(bp, reg_addr, reg_bit_map); bnx2x_map_q_cos()
574 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */
576 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */
578 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */
579 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */
580 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */
687 REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val); bnx2x_set_mcp_parity()
711 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, bnx2x_disable_blocks_parity()
734 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); bnx2x_clear_blocks_parity()
735 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); bnx2x_clear_blocks_parity()
736 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); bnx2x_clear_blocks_parity()
737 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); bnx2x_clear_blocks_parity()
765 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); bnx2x_clear_blocks_parity()
776 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, bnx2x_enable_blocks_parity()
H A Dbnx2x_sriov.c100 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); bnx2x_vf_igu_ack_sb()
106 REG_WR(bp, igu_addr_ctl, ctl); bnx2x_vf_igu_ack_sb()
717 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); bnx2x_vf_enable_internal()
723 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); bnx2x_vf_semi_clear_err()
724 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); bnx2x_vf_semi_clear_err()
725 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); bnx2x_vf_semi_clear_err()
726 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); bnx2x_vf_semi_clear_err()
748 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); bnx2x_vf_pglue_clear_err()
759 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); bnx2x_vf_igu_reset()
760 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); bnx2x_vf_igu_reset()
761 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); bnx2x_vf_igu_reset()
762 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); bnx2x_vf_igu_reset()
763 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); bnx2x_vf_igu_reset()
764 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); bnx2x_vf_igu_reset()
772 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); bnx2x_vf_igu_reset()
785 REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0); bnx2x_vf_igu_reset()
821 REG_WR(bp, PBF_REG_DISABLE_VF, 0); bnx2x_vf_enable_traffic()
1054 REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0); bnx2x_iov_init_dq()
1055 REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); bnx2x_iov_init_dq()
1060 REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); bnx2x_iov_init_dq()
1063 REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); bnx2x_iov_init_dq()
1068 REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3); bnx2x_iov_init_dq()
1074 REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1); bnx2x_iov_init_dq()
1075 REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0); bnx2x_iov_init_dq()
1076 REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); bnx2x_iov_init_dq()
1077 REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); bnx2x_iov_init_dq()
1082 REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64); bnx2x_iov_init_dq()
1088 REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0); bnx2x_iov_init_dmae()
1997 REG_WR(bp, reg, val); bnx2x_vf_qtbl_set_q()
2018 REG_WR(bp, IGU_REG_VF_CONFIGURATION, val); bnx2x_vf_igu_disable()
2161 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);
2531 REG_WR(bp, address, igu_entry); bnx2x_enable_sriov()
2559 REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
H A Dbnx2x_ethtool.c823 REG_WR(bp, write_addr[j], page_addr[i]); bnx2x_read_pages_regs()
1193 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, bnx2x_acquire_nvram_lock()
1225 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, bnx2x_release_nvram_lock()
1254 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, bnx2x_enable_nvram_access()
1266 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, bnx2x_disable_nvram_access()
1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); bnx2x_nvram_read_dword()
1284 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, bnx2x_nvram_read_dword()
1288 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); bnx2x_nvram_read_dword()
1553 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); bnx2x_nvram_write_dword()
1556 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); bnx2x_nvram_write_dword()
1559 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, bnx2x_nvram_write_dword()
1563 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); bnx2x_nvram_write_dword()
2256 REG_WR(bp, offset, wr_val & mask); bnx2x_test_registers()
2261 REG_WR(bp, offset, save_val); bnx2x_test_registers()
2951 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0); bnx2x_self_test()
2988 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val); bnx2x_self_test()
H A Dbnx2x_cmn.h520 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, bnx2x_update_rx_prod()
645 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); bnx2x_igu_ack_sb_gen()
666 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); bnx2x_hc_ack_sb()
1165 REG_WR(bp, addr + (i * 4), data[i]); __storm_memset_struct()
1276 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + bnx2x_link_sync_notify()
H A Dbnx2x.h167 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) macro
199 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
204 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
211 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
220 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
H A Dbnx2x_dcb.c52 /* helpers: read/write len bytes from addr into buff by REG_RD/REG_WR */ bnx2x_read_data()
66 REG_WR(bp, addr + i, *buff); bnx2x_write_data()
H A Dbnx2x_cmn.c1469 REG_WR(bp, BAR_USTRORM_INTMEM + for_each_eth_queue()
1472 REG_WR(bp, BAR_USTRORM_INTMEM + for_each_eth_queue()
2537 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1); bnx2x_load_cnic()
2567 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
H A Dbnx2x_sp.c751 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : bnx2x_set_mac_in_nig()
3109 REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); bnx2x_mcast_setup_e1h()
/linux-4.1.27/drivers/media/radio/wl128x/
H A Dfmdrv_tx.c39 ret = fmc_send_cmd(fmdev, MONO_SET, REG_WR, &payload, fm_tx_set_stereo_mono()
54 ret = fmc_send_cmd(fmdev, RDS_DATA_SET, REG_WR, rds_text, set_rds_text()
61 ret = fmc_send_cmd(fmdev, DISPLAY_MODE, REG_WR, &payload, set_rds_text()
76 ret = fmc_send_cmd(fmdev, PI_SET, REG_WR, &payload, set_rds_data_mode()
83 ret = fmc_send_cmd(fmdev, DI_SET, REG_WR, &payload, set_rds_data_mode()
99 ret = fmc_send_cmd(fmdev, RDS_CONFIG_DATA_SET, REG_WR, &payload, set_rds_len()
134 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, fm_tx_set_rds_mode()
171 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, fm_tx_set_radio_text()
191 ret = fmc_send_cmd(fmdev, TA_SET, REG_WR, &payload, fm_tx_set_af()
211 ret = fmc_send_cmd(fmdev, TX_BAND_SET, REG_WR, &payload, fm_tx_set_region()
227 ret = fmc_send_cmd(fmdev, MUTE, REG_WR, &payload, fm_tx_set_mute_mode()
244 ret = fmc_send_cmd(fmdev, AUDIO_IO_SET, REG_WR, &payload, set_audio_io()
263 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, enable_xmit()
270 ret = fmc_send_cmd(fmdev, POWER_ENB_SET, REG_WR, &payload, enable_xmit()
316 ret = fmc_send_cmd(fmdev, POWER_LEV_SET, REG_WR, &payload, fm_tx_set_pwr_lvl()
352 ret = fmc_send_cmd(fmdev, PREMPH_SET, REG_WR, &payload, fm_tx_set_preemph_filter()
396 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_tx_set_freq()
408 ret = fmc_send_cmd(fmdev, CHANL_SET, REG_WR, &payload, fm_tx_set_freq()
H A Dfmdrv_rx.c62 ret = fmc_send_cmd(fmdev, AUDIO_ENABLE_SET, REG_WR, &payload, fm_rx_set_freq()
69 ret = fmc_send_cmd(fmdev, HILO_SET, REG_WR, &payload, fm_rx_set_freq()
77 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, fm_rx_set_freq()
91 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_rx_set_freq()
98 ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, fm_rx_set_freq()
133 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_rx_set_freq()
159 ret = fmc_send_cmd(fmdev, CHANL_BW_SET, REG_WR, &payload, fm_rx_set_channel_spacing()
214 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, fm_rx_seek()
221 ret = fmc_send_cmd(fmdev, SEARCH_DIR_SET, REG_WR, &payload, fm_rx_seek()
235 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_rx_seek()
242 ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, fm_rx_seek()
262 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_rx_seek()
316 ret = fmc_send_cmd(fmdev, VOLUME_SET, REG_WR, &payload, fm_rx_set_volume()
379 ret = fmc_send_cmd(fmdev, BAND_SET, REG_WR, &payload, fm_rx_set_region()
443 ret = fmc_send_cmd(fmdev, MUTE_STATUS_SET, REG_WR, &payload, fm_config_rx_mute_reg()
554 ret = fmc_send_cmd(fmdev, SEARCH_LVL_SET, REG_WR, &payload, fm_rx_set_rssi_threshold()
593 ret = fmc_send_cmd(fmdev, MOST_MODE_SET, REG_WR, &payload, fm_rx_set_stereo_mono()
600 ret = fmc_send_cmd(fmdev, MOST_BLEND_SET, REG_WR, &payload, fm_rx_set_stereo_mono()
646 ret = fmc_send_cmd(fmdev, DEMPH_MODE_SET, REG_WR, &payload, fm_rx_set_deemphasis_mode()
687 ret = fmc_send_cmd(fmdev, POWER_SET, REG_WR, &payload, fm_rx_set_rds_mode()
694 ret = fmc_send_cmd(fmdev, RDS_CNTRL_SET, REG_WR, &payload, fm_rx_set_rds_mode()
707 ret = fmc_send_cmd(fmdev, RDS_MEM_SET, REG_WR, &payload, fm_rx_set_rds_mode()
715 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_rx_set_rds_mode()
728 ret = fmc_send_cmd(fmdev, POWER_SET, REG_WR, &payload, fm_rx_set_rds_mode()
778 ret = fmc_send_cmd(fmdev, RDS_SYSTEM_SET, REG_WR, &payload, fm_rx_set_rds_system()
809 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_rx_set_af_switch()
H A Dfmdrv_common.c888 if (!fm_send_cmd(fmdev, RDS_PI_SET, REG_WR, &payload, sizeof(payload), NULL)) fm_irq_afjump_set_pi()
907 if (!fm_send_cmd(fmdev, RDS_PI_MASK_SET, REG_WR, &payload, sizeof(payload), NULL)) fm_irq_afjump_set_pimask()
926 if (!fm_send_cmd(fmdev, AF_FREQ_SET, REG_WR, &payload, sizeof(payload), NULL)) fm_irq_afjump_setfreq()
941 if (!fm_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, sizeof(payload), NULL)) fm_irq_afjump_enableint()
955 if (!fm_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, fm_irq_start_afjump()
1036 if (!fm_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, fm_irq_send_intmsk_cmd()
1232 ret = fmc_send_cmd(fmdev, FM_POWER_MODE, REG_WR, &payload, fm_power_down()
1341 if (fmc_send_cmd(fmdev, FM_POWER_MODE, REG_WR, &payload, fm_power_up()
H A Dfmdrv_common.h29 #define REG_WR 0x0 macro
/linux-4.1.27/arch/cris/arch-v32/kernel/
H A Ddebugport.c151 REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); start_port()
152 REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); start_port()
153 REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); start_port()
154 REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); start_port()
155 REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); start_port()
171 REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr); getDebugChar()
H A Dtime.c112 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); reset_watchdog()
127 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); stop_watchdog()
154 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); handle_watchdog_bite()
183 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_clkevt_mode()
194 REG_WR(timer, timer_base, rw_tmr0_div, evt); crisv32_clkevt_next_event()
195 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_clkevt_next_event()
198 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_clkevt_next_event()
217 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_timer_interrupt()
218 REG_WR(timer, timer_base, rw_ack_intr, ack); crisv32_timer_interrupt()
259 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); crisv32_timer_init()
263 REG_WR(timer, timer_base, rw_intr_mask, timer_intr_mask); crisv32_timer_init()
338 REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div); cris_time_freq_notifier()
H A Dfasttimer.c146 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); start_timer_trig()
157 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); start_timer_trig()
160 REG_WR(timer, regi_timer0, rw_trig, trig); start_timer_trig()
162 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); start_timer_trig()
172 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); start_timer_trig()
178 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); start_timer_trig()
179 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); start_timer_trig()
339 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); timer_trig_handler()
344 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); timer_trig_handler()
348 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); timer_trig_handler()
H A Dprocess.c76 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); hard_reset_now()
H A Dkgdb.c1551 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); kgdb_init()
1555 REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask); kgdb_init()
1563 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); kgdb_init()
1567 REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask); kgdb_init()
1575 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); kgdb_init()
1579 REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask); kgdb_init()
1587 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); kgdb_init()
1591 REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask); kgdb_init()
/linux-4.1.27/arch/cris/arch-v32/drivers/
H A Diop_fw_load.c89 REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); iop_fw_load_spu()
93 REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); iop_fw_load_spu()
98 REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); iop_fw_load_spu()
150 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); iop_fw_load_mpu()
156 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); iop_fw_load_mpu()
177 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); iop_start_mpu()
187 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); iop_start_mpu()
191 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); iop_start_mpu()
H A Dsync_serial.c321 REG_WR(sser, port->regi_sser, rw_cfg, cfg); sync_serial_start_port()
322 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); sync_serial_start_port()
323 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); sync_serial_start_port()
367 REG_WR(sser, port->regi_sser, rw_cfg, cfg); initialize_port()
377 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); initialize_port()
391 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); initialize_port()
397 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); initialize_port()
505 REG_WR(dma, port->regi_dmain, rw_cfg, cfg); sync_serial_open()
506 REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); sync_serial_open()
508 REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); sync_serial_open()
509 REG_WR(dma, port->regi_dmaout, rw_intr_mask, intr_mask); sync_serial_open()
1034 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); sync_serial_ioctl_unlocked()
1035 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); sync_serial_ioctl_unlocked()
1036 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); sync_serial_ioctl_unlocked()
1037 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); sync_serial_ioctl_unlocked()
1038 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); sync_serial_ioctl_unlocked()
1045 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); sync_serial_ioctl_unlocked()
1050 REG_WR(sser, port->regi_sser, rw_cfg, gen_cfg); sync_serial_ioctl_unlocked()
1148 REG_WR(sser, port->regi_sser, rw_cfg, cfg); sync_serial_write()
1149 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); sync_serial_write()
1173 REG_WR(sser, port->regi_sser, rw_intr_mask, intr_mask); sync_serial_write()
1212 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1222 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1230 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1238 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1241 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1248 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1251 REG_WR(sser, port->regi_sser, rw_tr_data, tr_data); send_word()
1288 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); start_dma_out()
1356 REG_WR(dma, port->regi_dmaout, rw_ack_intr, ack_intr); tr_interrupt()
1431 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); tr_interrupt()
1483 REG_WR(dma, port->regi_dmain, rw_ack_intr, ack_intr); handle_rx_packet()
1593 REG_WR(sser, port->regi_sser, manual_interrupt()
H A Dcryptocop.c1906 REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); dma_done_interrupt()
1975 REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); init_cryptocop()
1977 REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); init_cryptocop()
1980 REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ init_cryptocop()
1981 REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ init_cryptocop()
1988 REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); init_cryptocop()
1991 REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); init_cryptocop()
2009 REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); release_cryptocop()
2012 REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ release_cryptocop()
2013 REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ release_cryptocop()
2016 REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); release_cryptocop()
2083 REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_out_cfg); cryptocop_job_queue_close()
2087 REG_WR(dma, IN_DMA_INST, rw_cfg, dma_in_cfg); cryptocop_job_queue_close()
2092 REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); cryptocop_job_queue_close()
2221 REG_WR(strcop, regi_strcop, rw_cfg, rw_cfg); cryptocop_start_job()
/linux-4.1.27/drivers/cpufreq/
H A Dcris-artpec3-cpufreq.c43 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); cris_freq_target()
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); cris_sdram_freq_notifier()
H A Dcris-etraxfs-cpufreq.c43 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); cris_freq_target()
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); cris_sdram_freq_notifier()
/linux-4.1.27/arch/cris/boot/compressed/
H A Dmisc.c138 REG_WR(ser, regi_ser, rw_dout, dout); serout()
248 REG_WR(ser, regi_ser, rw_xoff, xoff); serial_setup()
270 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); serial_setup()
271 REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); serial_setup()
272 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); serial_setup()
273 REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); serial_setup()
297 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); decompress_kernel()
323 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); decompress_kernel()
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sap_in_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sap_out_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_spu_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_cfg_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_cpu_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_mpu_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-4.1.27/drivers/tty/serial/
H A Detraxfs-uart.c20 REG_WR(ser, instance, reg, var); \
66 REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en); cris_console_write()
87 REG_WR(ser, up->regi_ser, rw_tr_dma_en, old); cris_console_write()
176 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); crisv32_serial_set_rts()
229 REG_WR(ser, regi_ser, rw_ack_intr, ack_intr); etraxfs_uart_send_xchar()
233 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); etraxfs_uart_send_xchar()
239 REG_WR(ser, regi_ser, rw_dout, dout); etraxfs_uart_send_xchar()
253 REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr); etraxfs_uart_send_xchar()
266 REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en); etraxfs_uart_send_xchar()
270 REG_WR(ser, regi_ser, rw_tr_ctrl, prev_tr_ctrl); etraxfs_uart_send_xchar()
302 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); etraxfs_uart_start_tx_bottom()
305 REG_WR(ser, regi_ser, rw_intr_mask, intr_mask); etraxfs_uart_start_tx_bottom()
335 REG_WR(ser, regi_ser, rw_intr_mask, intr_mask); etraxfs_uart_stop_tx()
339 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); etraxfs_uart_stop_tx()
350 REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr); etraxfs_uart_stop_tx()
358 REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en); etraxfs_uart_stop_tx()
373 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); etraxfs_uart_stop_rx()
476 REG_WR(ser, up->regi_ser, rw_tr_ctrl, tr_ctrl); etraxfs_uart_break_ctl()
477 REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en); etraxfs_uart_break_ctl()
478 REG_WR(ser, up->regi_ser, rw_intr_mask, intr_mask); etraxfs_uart_break_ctl()
500 REG_WR(ser, regi_ser, rw_intr_mask, intr_mask); transmit_chars_no_dma()
511 REG_WR(ser, regi_ser, rw_dout, dout); transmit_chars_no_dma()
512 REG_WR(ser, regi_ser, rw_ack_intr, ack_intr); transmit_chars_no_dma()
543 REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr); receive_chars_no_dma()
625 REG_WR(ser, up->regi_ser, rw_ack_intr, ack_intr); etraxfs_uart_get_poll_char()
657 REG_WR(ser, up->regi_ser, rw_intr_mask, ser_intr_mask); etraxfs_uart_startup()
800 REG_WR(ser, up->regi_ser, rw_tr_dma_en, tx_dma_en); etraxfs_uart_set_termios()
811 REG_WR(ser, up->regi_ser, rw_tr_dma_en, tx_dma_en); etraxfs_uart_set_termios()
829 REG_WR(ser, up->regi_ser, rw_xoff_clr, xoff_clr); etraxfs_uart_set_termios()
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-a3/
H A Dnandflash.c83 REG_WR(pio, regi_pio, rw_dout, dout); crisv32_hwcontrol()
133 REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl); crisv32_nand_flash_probe()
134 REG_WR(pio, regi_pio, rw_dout, dout); crisv32_nand_flash_probe()
135 REG_WR(pio, regi_pio, rw_oe, oe); crisv32_nand_flash_probe()
H A Dgpio.c290 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr); gpio_interrupt()
304 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); gpio_interrupt()
951 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); virtual_gpio_init()
952 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); virtual_gpio_init()
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_version_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_fifo_in_extra_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_fifo_out_extra_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_scrc_in_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_scrc_out_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_trigger_grp_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_crc_par_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_fifo_in_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_mpu_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sap_in_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_timer_grp_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_dmc_in_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_dmc_out_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_fifo_out_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sap_out_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_spu_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_spu_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_cfg_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_cpu_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Diop_sw_mpu_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dstrmux_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dclkgen_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dl2cache_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dmarb_bar_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
304 #ifndef REG_WR
305 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dmarb_foo_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
430 #ifndef REG_WR
431 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dddr2_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dintr_vect_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dpinmux_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dpio_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dtimer_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dgio_defs.h20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-4.1.27/arch/cris/arch-v32/drivers/mach-fs/
H A Dnandflash.c78 REG_WR(gio, regi_gio, rw_pa_dout, dout); crisv32_hwcontrol()
138 REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); crisv32_nand_flash_probe()
142 REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); crisv32_nand_flash_probe()
H A Dgpio.c241 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); gpio_poll()
330 REG_WR(gio, regi_gio, rw_ack_intr, ack_intr); gpio_pa_interrupt()
344 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); gpio_pa_interrupt()
929 REG_WR(gio, regi_gio, rw_intr_cfg, intr_cfg); virtual_gpio_init()
930 REG_WR(gio, regi_gio, rw_intr_mask, intr_mask); virtual_gpio_init()
/linux-4.1.27/arch/cris/arch-v32/mach-a3/
H A Ddma.c173 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); crisv32_request_dma()
174 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); crisv32_request_dma()
H A Dpinmux.c203 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); crisv32_pinmux_alloc_fixed()
204 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); crisv32_pinmux_alloc_fixed()
362 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); crisv32_pinmux_dealloc_fixed()
H A Darbiter.c568 REG_WR(marb_foo_bp, watch->instance, rw_ack, ack); crisv32_foo_arbiter_irq()
569 REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr); crisv32_foo_arbiter_irq()
624 REG_WR(marb_bar_bp, watch->instance, rw_ack, ack); crisv32_bar_arbiter_irq()
625 REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr); crisv32_bar_arbiter_irq()
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dconfig_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dstrmux_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dbif_slave_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dintr_vect_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dmarb_bp_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dmarb_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
282 #ifndef REG_WR
283 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dbif_core_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dgio_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dpinmux_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dtimer_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
H A Dbif_dma_defs.h23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
/linux-4.1.27/arch/cris/arch-v32/mach-fs/
H A Ddma.c218 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); crisv32_request_dma()
219 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); crisv32_request_dma()
H A Darbiter.c307 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); crisv32_arbiter_watch()
341 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); crisv32_arbiter_unwatch()
395 REG_WR(marb_bp, watch->instance, rw_ack, ack); crisv32_arbiter_irq()
396 REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); crisv32_arbiter_irq()
H A Dpinmux.c61 REG_WR(pinmux, regi_pinmux, rw_pa, pa); crisv32_pinmux_init()
166 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); crisv32_pinmux_alloc_fixed()
300 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); crisv32_pinmux_dealloc_fixed()
/linux-4.1.27/drivers/scsi/bnx2i/
H A Dbnx2i.h130 #define REG_WR(__hba, offset, val) \ macro

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