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Searched refs:phy_write (Results 1 – 58 of 58) sorted by relevance

/linux-4.4.14/drivers/net/phy/
Dmarvell.c158 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); in marvell_config_intr()
160 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); in marvell_config_intr()
194 err = phy_write(phydev, MII_M1011_PHY_SCR, val); in marvell_set_polarity()
209 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in marvell_config_aneg()
214 err = phy_write(phydev, 0x1d, 0x1f); in marvell_config_aneg()
218 err = phy_write(phydev, 0x1e, 0x200c); in marvell_config_aneg()
222 err = phy_write(phydev, 0x1d, 0x5); in marvell_config_aneg()
226 err = phy_write(phydev, 0x1e, 0); in marvell_config_aneg()
230 err = phy_write(phydev, 0x1e, 0x100); in marvell_config_aneg()
238 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, in marvell_config_aneg()
[all …]
Dnational.c61 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_read()
67 phy_write(phydev, NS_EXP_MEM_ADD, reg); in ns_exp_write()
68 phy_write(phydev, NS_EXP_MEM_DATA, data); in ns_exp_write()
76 err = phy_write(phydev, DP83865_INT_MASK, in ns_config_intr()
79 err = phy_write(phydev, DP83865_INT_MASK, 0); in ns_config_intr()
92 ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7); in ns_ack_interrupt()
101 phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN)); in ns_giga_speed_fallback()
104 phy_write(phydev, NS_EXP_MEM_CTL, 0); in ns_giga_speed_fallback()
105 phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0); in ns_giga_speed_fallback()
106 phy_write(phydev, NS_EXP_MEM_DATA, 0x0008); in ns_giga_speed_fallback()
[all …]
Drealtek.c49 phy_write(phydev, RTL8211F_PAGE_SELECT, 0xa43); in rtl8211f_ack_interrupt()
52 phy_write(phydev, RTL8211F_PAGE_SELECT, 0x0); in rtl8211f_ack_interrupt()
62 err = phy_write(phydev, RTL821x_INER, in rtl8211b_config_intr()
65 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211b_config_intr()
75 err = phy_write(phydev, RTL821x_INER, in rtl8211e_config_intr()
78 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211e_config_intr()
88 err = phy_write(phydev, RTL821x_INER, in rtl8211f_config_intr()
91 err = phy_write(phydev, RTL821x_INER, 0); in rtl8211f_config_intr()
107 phy_write(phydev, RTL8211F_PAGE_SELECT, 0xd08); in rtl8211f_config_init()
110 phy_write(phydev, 0x11, reg); in rtl8211f_config_init()
[all …]
Dat803x.c80 phy_write(phydev, MII_BMCR, context->bmcr); in at803x_context_restore()
81 phy_write(phydev, MII_ADVERTISE, context->advertise); in at803x_context_restore()
82 phy_write(phydev, MII_CTRL1000, context->control1000); in at803x_context_restore()
83 phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable); in at803x_context_restore()
84 phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed); in at803x_context_restore()
85 phy_write(phydev, AT803X_LED_CONTROL, context->led_control); in at803x_context_restore()
111 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL, in at803x_set_wol()
113 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA, in at803x_set_wol()
115 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL, in at803x_set_wol()
117 phy_write(phydev, AT803X_MMD_ACCESS_CONTROL_DATA, in at803x_set_wol()
[all …]
Dbcm-phy-lib.c28 rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_write_exp()
32 return phy_write(phydev, MII_BCM54XX_EXP_DATA, val); in bcm_phy_write_exp()
40 val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg); in bcm_phy_read_exp()
47 phy_write(phydev, MII_BCM54XX_EXP_SEL, 0); in bcm_phy_read_exp()
59 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_write_misc()
66 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_write_misc()
83 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, in bcm_phy_read_misc()
90 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp); in bcm_phy_read_misc()
127 return phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_phy_config_intr()
133 phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow)); in bcm_phy_read_shadow()
[all …]
Dvitesse.c94 err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon); in vsc824x_add_skew()
103 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc824x_config_init()
133 err = phy_write(phydev, MII_VSC8244_IMASK, in vsc82xx_config_intr()
150 err = phy_write(phydev, MII_VSC8244_IMASK, 0); in vsc82xx_config_intr()
160 err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT, in vsc8221_config_init()
183 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5); in vsc82x4_config_autocross_enable()
185 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012); in vsc82x4_config_autocross_enable()
187 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803); in vsc82x4_config_autocross_enable()
189 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa); in vsc82x4_config_autocross_enable()
192 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); in vsc82x4_config_autocross_enable()
[all …]
Ddavicom.c80 temp = phy_write(phydev, MII_DM9161_INTR, temp); in dm9161_config_intr()
90 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_aneg()
109 err = phy_write(phydev, MII_BMCR, BMCR_ISOLATE); in dm9161_config_init()
126 err = phy_write(phydev, MII_DM9161_SCR, temp); in dm9161_config_init()
131 err = phy_write(phydev, MII_DM9161_10BTCSR, MII_DM9161_10BTCSR_INIT); in dm9161_config_init()
137 return phy_write(phydev, MII_BMCR, BMCR_ANENABLE); in dm9161_config_init()
Dbcm7xxx.c76 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd); in bcm7xxx_28nm_b0_afe_config_init()
127 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_d0_afe_config_init()
155 phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010); in bcm7xxx_28nm_e0_plus_afe_config_init()
238 ret = phy_write(dev, location, v); in phy_set_clr_bits()
250 phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO); in bcm7xxx_config_init()
264 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00); in bcm7xxx_config_init()
268 phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00); in bcm7xxx_config_init()
270 phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555); in bcm7xxx_config_init()
300 ret = phy_write(phydev, in bcm7xxx_suspend()
Dcicada.c72 err = phy_write(phydev, MII_CIS8201_AUX_CONSTAT, in cis820x_config_init()
78 err = phy_write(phydev, MII_CIS8201_EXT_CON1, in cis820x_config_init()
96 err = phy_write(phydev, MII_CIS8201_IMASK, in cis820x_config_intr()
99 err = phy_write(phydev, MII_CIS8201_IMASK, 0); in cis820x_config_intr()
Dsmsc.c29 int rc = phy_write (phydev, MII_LAN83C185_IM, in smsc_phy_config_intr()
60 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in smsc_phy_config_init()
83 phy_write(phydev, MII_LAN83C185_SPECIAL_MODES, rc); in smsc_phy_reset()
84 phy_write(phydev, MII_BMCR, BMCR_RESET); in smsc_phy_reset()
122 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
143 rc = phy_write(phydev, MII_LAN83C185_CTRL_STATUS, in lan87xx_read_status()
Dbroadcom.c35 return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val); in bcm54xx_auxctl_write()
188 err = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm54xx_config_init()
196 err = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm54xx_config_init()
327 phy_write(phydev, 0x18, reg); in bcm5481_config_aneg()
334 phy_write(phydev, 0x18, reg); in bcm5481_config_aneg()
348 return phy_write(phydev, reg, val | set); in brcm_phy_setbits()
356 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in brcm_fet_config_init()
371 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg); in brcm_fet_config_init()
382 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg); in brcm_fet_config_init()
396 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg); in brcm_fet_config_init()
[all …]
Dlxt.c86 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN); in lxt970_config_intr()
88 err = phy_write(phydev, MII_LXT970_IER, 0); in lxt970_config_intr()
97 err = phy_write(phydev, MII_LXT970_CONFIG, 0); in lxt970_config_init()
118 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN); in lxt971_config_intr()
120 err = phy_write(phydev, MII_LXT971_IER, 0); in lxt971_config_intr()
254 phy_write(phydev, MII_BMCR, val); in lxt973_probe()
Dbcm-cygnus.c29 rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, 0x0c30); in bcm_cygnus_afe_config()
59 rc = phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x02); in bcm_cygnus_afe_config()
89 rc = phy_write(phydev, MII_BCM54XX_ECR, reg); in bcm_cygnus_config_init()
97 rc = phy_write(phydev, MII_BCM54XX_IMR, reg); in bcm_cygnus_config_init()
Dmicrel.c125 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); in kszphy_extended_write()
126 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); in kszphy_extended_write()
132 phy_write(phydev, MII_KSZPHY_EXTREG, regnum); in kszphy_extended_read()
162 phy_write(phydev, MII_KSZPHY_CTRL, temp); in kszphy_config_intr()
170 return phy_write(phydev, MII_KSZPHY_INTCS, temp); in kszphy_config_intr()
186 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); in kszphy_rmii_clk_sel()
212 rc = phy_write(phydev, reg, temp); in kszphy_setup_led()
231 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); in kszphy_broadcast_disable()
250 ret = phy_write(phydev, MII_KSZPHY_OMSO, in kszphy_nand_tree_disable()
391 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); in ksz9031_extended_write()
[all …]
Dqsemi.c76 return phy_write(phydev, MII_QS6612_PCR, 0x0dc0); in qs6612_config_init()
105 err = phy_write(phydev, MII_QS6612_IMR, in qs6612_config_intr()
108 err = phy_write(phydev, MII_QS6612_IMR, 0); in qs6612_config_intr()
Dicplus.c112 bmcr = phy_write(phydev, MII_BMCR, bmcr); in ip1xx_reset()
138 c = phy_write(phydev, IP1001_SPEC_CTRL_STATUS_2, c); in ip1001_config_init()
157 c = phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); in ip1001_config_init()
174 c = phy_write(phydev, IP101A_G_IRQ_CONF_STATUS, IP101A_G_IRQ_DEFAULT); in ip101a_g_config_init()
182 return phy_write(phydev, IP10XX_SPEC_CTRL_STATUS, c); in ip101a_g_config_init()
Ddp83848.c51 err = phy_write(phydev, DP83848_MICR, in dp83848_config_intr()
57 return phy_write(phydev, DP83848_MISR, in dp83848_config_intr()
64 return phy_write(phydev, DP83848_MICR, 0x0); in dp83848_config_intr()
Dste10Xp.c45 err = phy_write(phydev, MII_BMCR, value); in ste10Xp_config_init()
62 err = phy_write(phydev, MII_XIE, MII_XIE_DEFAULT_MASK); in ste10Xp_config_intr()
70 err = phy_write(phydev, MII_XIE, 0); in ste10Xp_config_intr()
Ddp83867.c95 return phy_write(phydev, MII_DP83867_MICR, micr_status); in dp83867_config_intr()
99 return phy_write(phydev, MII_DP83867_MICR, micr_status); in dp83867_config_intr()
157 ret = phy_write(phydev, MII_DP83867_PHYCTRL, in dp83867_config_init()
194 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET); in dp83867_phy_reset()
Dmicrochip.c39 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF); in lan88xx_phy_config_intr()
41 rc = phy_write(phydev, LAN88XX_INT_MASK, in lan88xx_phy_config_intr()
45 rc = phy_write(phydev, LAN88XX_INT_MASK, 0); in lan88xx_phy_config_intr()
Damd.c57 err = phy_write(phydev, MII_AM79C_IR, MII_AM79C_IR_IMASK_INIT); in am79c_config_intr()
59 err = phy_write(phydev, MII_AM79C_IR, 0); in am79c_config_intr()
Dbcm63xx.c34 err = phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
43 return phy_write(phydev, MII_BCM63XX_IR, reg); in bcm63xx_config_init()
Det1011c.c61 phy_write(phydev, MII_BMCR, ctl | BMCR_RESET); in et1011c_config_aneg()
80 phy_write(phydev, ET1011C_CONFIG_REG, val\ in et1011c_read_status()
Dbcm87xx.c73 ret = phy_write(phydev, regnum, val); in bcm87xx_of_reg_init()
155 err = phy_write(phydev, BCM87XX_LASI_CONTROL, reg); in bcm87xx_config_intr()
Dphy_device.c836 err = phy_write(phydev, MII_ADVERTISE, adv); in genphy_config_advert()
870 err = phy_write(phydev, MII_CTRL1000, adv); in genphy_config_advert()
900 return phy_write(phydev, MII_BMCR, ctl); in genphy_setup_forced()
920 return phy_write(phydev, MII_BMCR, ctl); in genphy_restart_aneg()
1159 ret = phy_write(phydev, MII_BMCR, BMCR_RESET); in genphy_soft_reset()
1233 phy_write(phydev, MII_BMCR, value | BMCR_PDOWN); in genphy_suspend()
1253 phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN); in genphy_resume()
Ddp83640.c256 phy_write(phydev, regnum, val); in ext_write()
604 phy_write(phydev, PAGESEL, 0); in enable_broadcast()
610 phy_write(phydev, PHYCR2, val); in enable_broadcast()
611 phy_write(phydev, PAGESEL, init_page); in enable_broadcast()
1253 err = phy_write(phydev, MII_DP83640_MISR, misr); in dp83640_config_intr()
1263 return phy_write(phydev, MII_DP83640_MICR, micr); in dp83640_config_intr()
1271 err = phy_write(phydev, MII_DP83640_MICR, micr); in dp83640_config_intr()
1283 return phy_write(phydev, MII_DP83640_MISR, misr); in dp83640_config_intr()
/linux-4.4.14/arch/arm/mach-imx/
Dmach-imx7d.c25 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
26 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
29 phy_write(dev, 0xd, 0x3); in ar8031_phy_fixup()
30 phy_write(dev, 0xe, 0x805d); in ar8031_phy_fixup()
31 phy_write(dev, 0xd, 0x4003); in ar8031_phy_fixup()
34 phy_write(dev, 0xe, val); in ar8031_phy_fixup()
37 phy_write(dev, 0x1d, 0x5); in ar8031_phy_fixup()
40 phy_write(dev, 0x1e, val); in ar8031_phy_fixup()
48 phy_write(dev, 0x1e, 0x21); in bcm54220_phy_fixup()
49 phy_write(dev, 0x1f, 0x7ea8); in bcm54220_phy_fixup()
[all …]
Dmach-imx6q.c47 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
49 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000); in ksz9021rn_phy_fixup()
52 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
54 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0); in ksz9021rn_phy_fixup()
55 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL, in ksz9021rn_phy_fixup()
64 phy_write(dev, 0x0d, device); in mmd_write_reg()
65 phy_write(dev, 0x0e, reg); in mmd_write_reg()
66 phy_write(dev, 0x0d, (1 << 14) | device); in mmd_write_reg()
67 phy_write(dev, 0x0e, val); in mmd_write_reg()
116 phy_write(dev, 0xd, 0x7); in ar8031_phy_fixup()
[all …]
Dmach-imx6ul.c36 phy_write(dev, 0x1f, 0x8110); in ksz8081_phy_fixup()
37 phy_write(dev, 0x16, 0x201); in ksz8081_phy_fixup()
39 phy_write(dev, 0x1f, 0x8190); in ksz8081_phy_fixup()
40 phy_write(dev, 0x16, 0x202); in ksz8081_phy_fixup()
Dmach-imx6sx.c26 phy_write(dev, 0x1d, 0x1f); in ar8031_phy_fixup()
27 phy_write(dev, 0x1e, 0x8); in ar8031_phy_fixup()
30 phy_write(dev, 0x1d, 0x5); in ar8031_phy_fixup()
33 phy_write(dev, 0x1e, val); in ar8031_phy_fixup()
/linux-4.4.14/drivers/gpu/drm/msm/hdmi/
Dhdmi_phy_8x74.c27 static void phy_write(struct hdmi_phy_8x74 *phy, u32 reg, u32 data) in phy_write() function
48 phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG0, 0x1b); in hdmi_phy_8x74_powerup()
49 phy_write(phy_8x74, REG_HDMI_8x74_ANA_CFG1, 0xf2); in hdmi_phy_8x74_powerup()
50 phy_write(phy_8x74, REG_HDMI_8x74_BIST_CFG0, 0x0); in hdmi_phy_8x74_powerup()
51 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN0, 0x0); in hdmi_phy_8x74_powerup()
52 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN1, 0x0); in hdmi_phy_8x74_powerup()
53 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN2, 0x0); in hdmi_phy_8x74_powerup()
54 phy_write(phy_8x74, REG_HDMI_8x74_BIST_PATN3, 0x0); in hdmi_phy_8x74_powerup()
55 phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL1, 0x20); in hdmi_phy_8x74_powerup()
61 phy_write(phy_8x74, REG_HDMI_8x74_PD_CTRL0, 0x7f); in hdmi_phy_8x74_powerdown()
/linux-4.4.14/drivers/net/ethernet/ibm/emac/
Dphy.c32 #define phy_write _phy_write macro
62 phy_write(phy, MII_BMCR, val); in emac_mii_reset_phy()
73 phy_write(phy, MII_BMCR, val & ~BMCR_ISOLATE); in emac_mii_reset_phy()
125 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
145 phy_write(phy, MII_ADVERTISE, adv); in genmii_setup_aneg()
157 phy_write(phy, MII_CTRL1000, adv); in genmii_setup_aneg()
163 phy_write(phy, MII_BMCR, ctl); in genmii_setup_aneg()
183 phy_write(phy, MII_BMCR, ctl | BMCR_RESET); in genmii_setup_forced()
200 phy_write(phy, MII_BMCR, ctl); in genmii_setup_forced()
330 phy_write(phy, MII_CIS8201_EPCR, epcr); in cis8201_init()
[all …]
/linux-4.4.14/arch/powerpc/platforms/85xx/
Dmpc85xx_mds.c79 err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK)); in mpc8568_fixup_125_clock()
84 err = phy_write(phydev, MII_BMCR, BMCR_RESET); in mpc8568_fixup_125_clock()
94 err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008); in mpc8568_fixup_125_clock()
105 err = phy_write(phydev,29, 0x0006); in mpc8568_mds_phy_fixups()
116 err = phy_write(phydev,30, temp); in mpc8568_mds_phy_fixups()
121 err = phy_write(phydev,29, 0x000a); in mpc8568_mds_phy_fixups()
138 err = phy_write(phydev,30,temp); in mpc8568_mds_phy_fixups()
150 err = phy_write(phydev,16,temp); in mpc8568_mds_phy_fixups()
/linux-4.4.14/drivers/net/dsa/
Dmv88e6123_61_65.c110 .phy_write = mv88e6xxx_phy_write,
Dmv88e6171.c96 .phy_write = mv88e6xxx_phy_write_indirect,
Dmv88e6131.c167 .phy_write = mv88e6131_phy_write,
Dmv88e6060.c245 .phy_write = mv88e6060_phy_write,
Dmv88e6352.c309 .phy_write = mv88e6xxx_phy_write_indirect,
Dbcm_sf2.c1374 .phy_write = bcm_sf2_sw_phy_write,
/linux-4.4.14/drivers/net/usb/
Dlan78xx.c1183 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1); in lan78xx_get_mdix_status()
1185 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0); in lan78xx_get_mdix_status()
1197 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, in lan78xx_set_mdix_status()
1201 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, in lan78xx_set_mdix_status()
1203 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, in lan78xx_set_mdix_status()
1206 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, in lan78xx_set_mdix_status()
1210 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, in lan78xx_set_mdix_status()
1212 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, in lan78xx_set_mdix_status()
1215 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, in lan78xx_set_mdix_status()
1219 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, in lan78xx_set_mdix_status()
[all …]
/linux-4.4.14/drivers/net/ethernet/xilinx/
Dxilinx_emaclite.c926 phy_write(lp->phy_dev, MII_CTRL1000, 0); in xemaclite_open()
929 phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL | in xemaclite_open()
935 phy_write(lp->phy_dev, MII_BMCR, bmcr); in xemaclite_open()
/linux-4.4.14/drivers/net/wireless/b43/
Dphy_common.h168 void (*phy_write)(struct b43_wldev *dev, u16 reg, u16 value); member
Dphy_common.c300 if (dev->phy.ops->phy_write) in b43_phy_write()
301 return dev->phy.ops->phy_write(dev, reg, value); in b43_phy_write()
Dphy_a.c582 .phy_write = b43_aphy_op_write,
Dphy_g.c3041 .phy_write = b43_gphy_op_write,
/linux-4.4.14/include/net/
Ddsa.h223 int (*phy_write)(struct dsa_switch *ds, int port, member
/linux-4.4.14/include/linux/
Dphy.h663 static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val) in phy_write() function
/linux-4.4.14/arch/arm/mach-davinci/
Dboard-dm644x-evm.c743 phy_write(phydev, 26, (control | 0x800)); in davinci_phy_fixup()
/linux-4.4.14/drivers/net/ethernet/smsc/
Dsmsc911x.c1369 rc = phy_write(pdata->phy_dev, MII_BMCR, rc & ~BMCR_PDOWN); in smsc911x_phy_general_power_up()
1398 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, in smsc911x_phy_disable_energy_detect()
1429 rc = phy_write(pdata->phy_dev, MII_LAN83C185_CTRL_STATUS, in smsc911x_phy_enable_energy_detect()
/linux-4.4.14/drivers/net/ethernet/
Ddnet.c358 return phy_write(phydev, 0x18, 0x4148); in dnet_phy_marvell_fixup()
/linux-4.4.14/drivers/net/ethernet/freescale/
Ducc_geth.c1386 phy_write(tbiphy, ENET_TBI_MII_CR, value); in adjust_enet_interface()
1713 phy_write(tbiphy, ENET_TBI_MII_ANA, TBIANA_SETTINGS); in uec_configure_serdes()
1715 phy_write(tbiphy, ENET_TBI_MII_TBICON, TBICON_CLK_SELECT); in uec_configure_serdes()
1717 phy_write(tbiphy, ENET_TBI_MII_CR, TBICR_SETTINGS); in uec_configure_serdes()
Dgianfar.c1845 phy_write(tbiphy, MII_TBICON, TBICON_CLK_SELECT); in gfar_configure_serdes()
1847 phy_write(tbiphy, MII_ADVERTISE, in gfar_configure_serdes()
1851 phy_write(tbiphy, MII_BMCR, in gfar_configure_serdes()
/linux-4.4.14/net/dsa/
Dslave.c40 return ds->drv->phy_write(ds, addr, reg, val); in dsa_slave_phy_write()
/linux-4.4.14/drivers/net/ethernet/qlogic/netxen/
Dnetxen_nic.h1664 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); member
Dnetxen_nic_hw.c1804 adapter->phy_write = nx_fw_cmd_set_phy; in netxen_setup_hwops()
/linux-4.4.14/Documentation/networking/
Dphy.txt174 int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
/linux-4.4.14/drivers/net/ethernet/adi/
Dbfin_mac.c1596 phy_write(lp->phydev, MII_BMCR, BMCR_PDOWN); in bfin_mac_close()
/linux-4.4.14/Documentation/networking/dsa/
Ddsa.txt415 - phy_write: Function invoked by the DSA slave MDIO bus when attempting to write