/linux-4.4.14/arch/sh/include/uapi/asm/ |
H A D | cachectl.h | 6 #define CACHEFLUSH_D_INVAL 0x1 /* invalidate (without write back) */ 7 #define CACHEFLUSH_D_WB 0x2 /* write back (without invalidate) */ 8 #define CACHEFLUSH_D_PURGE 0x3 /* writeback and invalidate */
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/linux-4.4.14/arch/avr32/include/uapi/asm/ |
H A D | cachectl.h | 8 /* Clean the data cache, then invalidate the icache */
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/linux-4.4.14/arch/m32r/mm/ |
H A D | cache.c | 16 #define MCCR_IIV (1UL << 6) /* I-cache invalidate */ 17 #define MCCR_DIV (1UL << 5) /* D-cache invalidate */ 27 #define MCCR_IIV (1UL << 0) /* I-cache invalidate */ 31 #define MCCR_IIV (1UL << 8) /* I-cache invalidate */ 32 #define MCCR_DIV (1UL << 9) /* D-cache invalidate */ 46 /* Copy back and invalidate D-cache and invalidate I-cache all */ _flush_cache_all() 55 /* Copyback and invalidate D-cache */ _flush_cache_all() 61 /* Copyback and invalidate D-cache */ _flush_cache_all() 68 /* Copy back D-cache and invalidate I-cache all */ _flush_cache_copyback_all() 77 /* Copyback and invalidate D-cache */ _flush_cache_copyback_all()
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/linux-4.4.14/arch/arm/mm/ |
H A D | copypage-feroceon.c | 33 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 37 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 41 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 45 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 49 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 53 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 57 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 61 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page() 98 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_clear_user_highpage()
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H A D | proc-arm926.S | 40 * using the single invalidate entry instructions. Anything larger 83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 119 * Unconditionally clean and invalidate the entire icache. 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 130 * Clean and invalidate all cache entries in a particular 139 * Clean and invalidate the entire cache. 146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 159 * Clean and invalidate a range of cache entries in the 173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 183 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 184 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 243 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 268 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 299 * Clean and invalidate the specified virtual address range. 308 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 310 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 372 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 375 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 378 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 381 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 417 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 418 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 434 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | cache-fa.S | 44 * Unconditionally clean and invalidate the entire icache. 48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 55 * Clean and invalidate all cache entries in a particular address 63 * Clean and invalidate the entire cache. 69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache 71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line 95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 152 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 175 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry 178 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry 179 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 212 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
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H A D | cache-v4wt.S | 47 * Unconditionally clean and invalidate the entire icache. 51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 66 * Clean and invalidate the entire cache. 73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 80 * Clean and invalidate a range of cache entries in the specified 92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache 160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 169 * Clean and invalidate the specified virtual address range.
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H A D | cache-v6.S | 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache 67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate 69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate 146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate 151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB 180 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 182 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line 223 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line 225 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line 229 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line 231 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line 280 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line 282 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
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H A D | proc-arm925.S | 123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 153 * Unconditionally clean and invalidate the entire icache. 157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 164 * Clean and invalidate all cache entries in a particular 173 * Clean and invalidate the entire cache. 180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 196 * Clean and invalidate a range of cache entries in the 210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 275 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 305 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 336 * Clean and invalidate the specified virtual address range. 345 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 347 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 409 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 413 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 417 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 450 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 453 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-arm946.S | 83 * Unconditionally clean and invalidate the entire icache. 87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 100 * Clean and invalidate the entire cache. 125 * Clean and invalidate a range of cache entries in the 141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 208 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 237 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 268 * Clean and invalidate the specified virtual address range. 279 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 333 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
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H A D | tlb-v6.S | 33 * - the "Invalidate single entry" instruction will invalidate 49 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1) 51 mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1) 53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1) 78 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA 79 mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA 81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
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H A D | proc-arm1022.S | 30 * using the single invalidate entry instructions. Anything larger 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 * Unconditionally clean and invalidate the entire icache. 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 139 * Clean and invalidate the entire cache. 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 305 * Clean and invalidate the specified virtual address range. 314 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 378 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 386 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 390 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 416 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-arm1026.S | 30 * using the single invalidate entry instructions. Anything larger 90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 * Unconditionally clean and invalidate the entire icache. 123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 139 * Clean and invalidate the entire cache. 146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 299 * Clean and invalidate the specified virtual address range. 308 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 371 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate 375 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 379 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-mohawk.S | 75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 101 * Unconditionally clean and invalidate the entire icache. 105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 112 * Clean and invalidate all cache entries in a particular 121 * Clean and invalidate the entire cache. 127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 136 * Clean and invalidate a range of cache entries in the 151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 210 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 238 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 267 * Clean and invalidate the specified virtual address range. 275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 330 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache 331 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 335 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 370 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 373 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches 391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
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H A D | proc-arm920.S | 91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 118 * Unconditionally clean and invalidate the entire icache. 122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 138 * Clean and invalidate the entire cache. 146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 255 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 284 * Clean and invalidate the specified virtual address range. 291 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 351 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 359 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 402 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 403 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 419 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-arm922.S | 93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 120 * Unconditionally clean and invalidate the entire icache. 124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 131 * Clean and invalidate all cache entries in a particular 140 * Clean and invalidate the entire cache. 148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 161 * Clean and invalidate a range of cache entries in the 174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 229 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 257 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 286 * Clean and invalidate the specified virtual address range. 293 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 355 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 363 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 369 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 372 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | copypage-fa.c | 28 mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_copy_user_page() 32 mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_copy_user_page() 69 mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_clear_user_highpage() 72 mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_clear_user_highpage()
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H A D | copypage-v4mc.c | 39 * Note: We rely on all ARMv4 processors implementing the "invalidate D line" 50 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ mc_copy_user_page() 55 mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ mc_copy_user_page() 98 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4_mc_clear_user_highpage() 101 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4_mc_clear_user_highpage()
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H A D | copypage-v4wb.c | 21 * Note: We rely on all ARMv4 processors implementing the "invalidate D line" 32 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_copy_user_page() 37 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_copy_user_page() 77 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_clear_user_highpage() 80 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_clear_user_highpage()
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H A D | proc-fa526.S | 63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache 113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed 118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB 142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM 153 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
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H A D | cache-v4wb.S | 57 * Unconditionally clean and invalidate the entire icache. 61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 68 * Clean and invalidate all cache entries in a particular address 76 * Clean and invalidate the entire cache. 80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 114 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 167 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 194 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 221 * Clean and invalidate the specified virtual address range.
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H A D | proc-arm1020.S | 39 * using the single invalidate entry instructions. Anything larger 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 127 * Unconditionally clean and invalidate the entire icache. 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 * Clean and invalidate the entire cache. 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 198 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 258 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 292 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 326 * Clean and invalidate the specified virtual address range. 336 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 418 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 422 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-arm1020e.S | 39 * using the single invalidate entry instructions. Anything larger 99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 127 * Unconditionally clean and invalidate the entire icache. 132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 148 * Clean and invalidate the entire cache. 158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index 166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 195 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 252 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 281 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 314 * Clean and invalidate the specified virtual address range. 323 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 402 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache 406 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs 429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-feroceon.S | 34 * using the single invalidate entry instructions. Anything larger 104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 132 * Unconditionally clean and invalidate the entire icache. 136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 143 * Clean and invalidate all cache entries in a particular 153 * Clean and invalidate the entire cache. 162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way 170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 177 * Clean and invalidate a range of cache entries in the 190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 191 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry 194 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry 230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry 250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 293 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 352 * Clean and invalidate the specified virtual address range. 360 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry 488 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache 492 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 532 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 533 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 546 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 549 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | cache-v7.S | 24 * the clean + invalidate performed by v7_flush_dcache_all causes a bunch 27 * processor. We fix this by performing an invalidate, rather than a 28 * clean + invalidate, before jumping into the kernel. 77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 190 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 191 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 208 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable 209 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate 290 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line 295 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable 296 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB 334 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line 361 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line 365 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line 367 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line 411 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
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H A D | copypage-xsc3.c | 47 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ xsc3_mc_copy_user_page() 57 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ xsc3_mc_copy_user_page() 98 1: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\ xsc3_mc_clear_user_highpage()
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H A D | proc-xsc3.S | 71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line 116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 148 * Unconditionally clean and invalidate the entire icache. 152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 168 * Clean and invalidate the entire cache. 176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line 200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 205 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB 232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB 275 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line 302 * Clean and invalidate the specified virtual address range. 309 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line 365 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB 370 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs 433 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 436 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 453 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB 456 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
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H A D | proc-sa110.S | 68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
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H A D | proc-arm940.S | 76 * Unconditionally clean and invalidate the entire icache. 80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 93 * Clean and invalidate the entire cache. 123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 178 * There is no efficient way to invalidate a specifid virtual 223 * There is no efficient way to clean and invalidate a specifid 237 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry 279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 280 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
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H A D | proc-sa1100.S | 76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches 79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 150 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 190 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB 204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
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H A D | copypage-xscale.c | 68 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ mc_copy_user_page() 79 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ mc_copy_user_page() 124 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ xscale_mc_clear_user_highpage()
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H A D | proc-xscale.S | 150 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB 158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB 162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 189 * Unconditionally clean and invalidate the entire icache. 193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 209 * Clean and invalidate the entire cache. 308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 334 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 361 * Clean and invalidate the specified virtual address range. 369 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 421 * clear the dirty bits, which means that if we invalidate a dirty line, 425 * doing an invalidate D-cache line, so on the affected processors, 478 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 548 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 549 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 563 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB 565 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
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H A D | proc-v6.S | 156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache 157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 208 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache 209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache 210 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache 212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
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H A D | proc-arm720.S | 80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache 107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache 122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches 150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
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H A D | cache-feroceon-l2.c | 29 * As well as the regular 'clean/invalidate/flush L2 cache line by 31 * 'clean/invalidate L2 range by MVA' operations. 174 * Clean and invalidate partial first cache line. feroceon_l2_inv_range() 182 * Clean and invalidate partial last cache line. feroceon_l2_inv_range()
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H A D | proc-arm740.S | 55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache 66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
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H A D | cache-xsc3l2.c | 110 * Clean and invalidate partial first cache line. xsc3_l2_inv_range() 129 * Clean and invalidate partial last cache line. xsc3_l2_inv_range()
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H A D | pv-fixup-asm.S | 78 mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
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H A D | flush.c | 249 * - VIVT cache: we need to also write back and invalidate all user __flush_dcache_aliases() 397 * Write back and invalidate userspace mapping. __flush_anon_page() 414 * since we actually ask for a write-back and invalidate. __flush_anon_page()
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H A D | cache-tauros2.c | 67 * Clean and invalidate partial first cache line. tauros2_inv_range() 75 * Clean and invalidate partial last cache line. tauros2_inv_range()
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H A D | cache-l2x0.c | 445 * Affects: all clean+invalidate operations 446 * clean and invalidate skips the invalidate step, so we need to issue 453 * Affects: clean+invalidate by way 454 * clean and invalidate by way runs in the background, and a store can 455 * hit the line between the clean operation and invalidate operation, 479 /* Erratum 588369 for both clean+invalidate operations */ l2c310_inv_range_erratum() 1508 * For example, if we need to invalidate addresses starts at 0xBFFF0000 and 1509 * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
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/linux-4.4.14/arch/metag/include/asm/ |
H A D | cache.h | 12 * With an L2 cache, we may invalidate dirty lines, so we need to ensure DMA
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/linux-4.4.14/arch/mn10300/mm/ |
H A D | cache-flush-icache.c | 1 /* Flush dcache and invalidate icache when the dcache is in writeback mode 18 * flush_icache_page - Flush a page from the dcache and invalidate the icache 22 * Write a page back from the dcache and invalidate the icache so that we can 41 * flush_icache_page_range - Flush dcache and invalidate icache for part of a 46 * Flush the dcache and invalidate the icache for part of a single page, as 92 /* flush the dcache and invalidate the icache coverage on that flush_icache_page_range() 100 * flush_icache_range - Globally flush dcache and invalidate icache for region 105 * from the dcache back to RAM and then to globally invalidate the icache over
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H A D | cache-smp-flush.c | 86 * mn10300_dcache_flush_inv - Globally flush and invalidate data cache 88 * Flush and invalidate the data cache on all CPUs. 101 * mn10300_dcache_flush_inv_page - Globally flush and invalidate a page of data 105 * Flush and invalidate a range of addresses in the data cache on all CPUs 121 * mn10300_dcache_flush_inv_range - Globally flush and invalidate range of data 126 * Flush and invalidate a range of addresses in the data cache on all CPUs, 140 * mn10300_dcache_flush_inv_range2 - Globally flush and invalidate range of data 145 * Flush and invalidate a range of addresses in the data cache on all CPUs,
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H A D | cache-smp-inv.c | 16 * mn10300_icache_inv - Globally invalidate instruction cache 31 * mn10300_icache_inv_page - Globally invalidate a page of instruction cache 50 * mn10300_icache_inv_range - Globally invalidate range of instruction cache 68 * mn10300_icache_inv_range2 - Globally invalidate range of instruction cache 86 * mn10300_dcache_inv - Globally invalidate data cache 101 * mn10300_dcache_inv_page - Globally invalidate a page of data cache 120 * mn10300_dcache_inv_range - Globally invalidate range of data cache 138 * mn10300_dcache_inv_range2 - Globally invalidate range of data cache
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H A D | tlb-smp.c | 57 * smp_flush_tlb - Callback to invalidate the TLB. 89 * flush_tlb_others - Tell the specified CPUs to invalidate their TLBs 141 * @mm: The VM context to invalidate. 179 * @vma: The VM context to invalidate the page for. 180 * @va: The virtual address of the page to invalidate. 199 * do_flush_tlb_all - Callback to completely invalidate a TLB 208 * flush_tlb_all - Completely invalidate TLBs on all CPUs
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H A D | cache-flush-by-reg.S | 181 # Flush the entire data cache and invalidate all entries 196 # wait for busy bit of area purge & invalidate 206 # area purge & invalidate 210 # wait for busy bit of area purge & invalidate 227 # Flush and invalidate a range of addresses on a page in the dcache 271 # wait for busy bit of area purge & invalidate 286 # area purge & invalidate 291 # wait for busy bit of area purge & invalidate 297 # check purge & invalidate of end address
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H A D | cache-dbg-flush-by-reg.S | 25 # Flush the entire data cache back to RAM and invalidate the icache 74 # secondly, invalidate the icache if it is enabled 146 # invalidate the cache line at the given address
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H A D | cache-dbg-inv.S | 36 # we only need to invalidate the icache in this cache mode
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H A D | cache-inv-icache.c | 19 * flush_icache_page_range - Flush dcache and invalidate icache for part of a 70 /* invalidate the icache coverage on that region */ flush_icache_page_range() 76 * flush_icache_range - Globally flush dcache and invalidate icache for region 81 * from the dcache back to RAM and then to globally invalidate the icache over
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H A D | cache-dbg-flush-by-tag.S | 26 # Flush the entire data cache back to RAM and invalidate the icache 64 # secondly, invalidate the icache if it is enabled
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H A D | cache-dbg-inv-by-reg.S | 54 # invalidate the cache line at the given address
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H A D | cache-flush-by-tag.S | 155 # Flush the entire data cache and invalidate all entries 188 # Flush and invalidate a range of addresses on a page in the dcache 224 # write a request to flush and invalidate all instances of an address
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H A D | cache-inv-by-reg.S | 136 # writeback mode, in which case we would be in flush and invalidate by 218 # invalidate area 320 /* area invalidate
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H A D | cache-dbg-inv-by-tag.S | 46 # cache line then we invalidate that line
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/linux-4.4.14/arch/arm64/mm/ |
H A D | cache.S | 67 USER(9f, ic ivau, x4 ) // invalidate I line PoU 95 1: dc civac, x0 // clean & invalidate D line / unified line 122 dc civac, x1 // clean & invalidate D / U line 126 dc civac, x0 // clean & invalidate D / U line 128 2: dc ivac, x0 // invalidate D / U line 168 1: dc civac, x0 // clean & invalidate D / U line
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/linux-4.4.14/arch/unicore32/include/asm/ |
H A D | tlbflush.h | 30 * needs to determine if it should invalidate the TLB for each 70 /* TLB invalidate all */ local_flush_tlb_all() 80 /* TLB invalidate all */ local_flush_tlb_mm() 92 /* iTLB invalidate page */ local_flush_tlb_page() 95 /* dTLB invalidate page */ local_flush_tlb_page() 99 /* TLB invalidate all */ local_flush_tlb_page() 109 /* iTLB invalidate page */ local_flush_tlb_kernel_page() 112 /* dTLB invalidate page */ local_flush_tlb_kernel_page() 116 /* TLB invalidate all */ local_flush_tlb_kernel_page()
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H A D | cacheflush.h | 42 * Unconditionally clean and invalidate the entire icache. 48 * Unconditionally clean and invalidate the entire cache. 52 * Clean and invalidate all user space cache entries 57 * Clean and invalidate a range of cache entries in the 90 * Clean and invalidate the specified virtual address range. 172 * have userspace mappings, then we _must_ always clean + invalidate
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H A D | dma-mapping.h | 63 case DMA_BIDIRECTIONAL: /* writeback and invalidate */ dma_cache_sync()
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/linux-4.4.14/arch/blackfin/mach-bf561/ |
H A D | hotplug.c | 24 * As a workaround, we invalidate all the data cache before sleep. platform_cpu_die()
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H A D | atomic.S | 33 * r0 = address of atomic data to flush and invalidate (32bit). 52 /* flush core internal write buffer before invalidate dcache */ 87 * r1 = address of atomic data to flush and invalidate (32bit). 686 * order to invalidate the local cache before testing. 696 /* flush core internal write buffer before invalidate dcache */ 896 * We need this on this architecture in order to invalidate 920 /* flush core internal write buffer before invalidate dcache */
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/linux-4.4.14/arch/mips/include/uapi/asm/ |
H A D | sysmips.h | 20 #define FLUSH_CACHE 3 /* writeback and invalidate caches */
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H A D | mman.h | 56 #define MS_INVALIDATE 0x0002 /* invalidate mappings & caches */
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/linux-4.4.14/arch/powerpc/boot/ |
H A D | virtex405-head.S | 14 * - The 405 core does not invalidate the data cache on power-up
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H A D | gamecube-head.S | 80 /* enable and invalidate the caches if not already enabled */
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H A D | wii-head.S | 104 /* enable and invalidate the caches if not already enabled */
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/linux-4.4.14/arch/sh/mm/ |
H A D | flush-sh4.c | 8 * Write back the dirty D-caches, but not invalidate them. 42 * Write back the dirty D-caches and invalidate them.
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H A D | cache-sh3.c | 26 * Write back the dirty D-caches, but not invalidate them. 69 * Write back the dirty D-caches and invalidate them.
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H A D | cache-sh2a.c | 48 * Write back the dirty D-caches, but not invalidate them. 90 * Write back the dirty D-caches and invalidate them. 168 /* I-Cache invalidate */ sh2a_flush_icache_range()
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H A D | consistent.c | 90 case DMA_FROM_DEVICE: /* invalidate only */ dma_cache_sync() 96 case DMA_BIDIRECTIONAL: /* writeback and invalidate */ dma_cache_sync()
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H A D | cache-sh2.c | 59 * global invalidate. sh2__flush_invalidate_region()
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H A D | cache-sh7705.c | 133 * Write back & invalidate the D-cache of the page. 160 * Write back and invalidate I/D-caches for the page.
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H A D | cache-sh4.c | 57 * Selectively flush d-cache then invalidate the i-cache. sh4_flush_icache_range() 107 * Write back & invalidate the D-cache of the page. 199 * Write back and invalidate I/D-caches for the page. 268 * Write back and invalidate D-caches.
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H A D | cache-sh5.c | 168 /* Switch ASID and run the invalidate loop under cli */ sh64_icache_inv_user_page_range() 216 /* Just invalidate over the range using the natural addresses. TLB sh64_icache_inv_current_user_range() 220 invalidate another processes I-cache entries : no worries, just a sh64_icache_inv_current_user_range() 289 * Don't use OCBI to invalidate the lines. That costs cycles sh64_dcache_purge_sets() 593 * D-cache and invalidate the corresponding region of the I-cache for the
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/linux-4.4.14/arch/m68k/mm/ |
H A D | memory.c | 129 /* invalidate page in both caches */ clear040() 140 /* invalidate page in i-cache */ cleari040() 152 /* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */ push040() 163 /* push and invalidate page in both caches, must disable ints 190 /* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set 192 * this?). So we have to push first and then additionally to invalidate. 247 * and invalidate the range in the instruction cache. It needs not (but may) 248 * invalidate those entries also in the data cache. The range is defined by a
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/linux-4.4.14/arch/cris/arch-v10/mm/ |
H A D | tlb.c | 23 * to invalidate TLB entries. 33 /* invalidate all TLB entries */ 61 /* invalidate the selected mm context only */ 97 /* invalidate a single page */ 113 /* invalidate those TLB entries that match both the mm context flush_tlb_page()
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/linux-4.4.14/arch/microblaze/include/asm/ |
H A D | cacheflush.h | 28 * implemented are to invalidate the instruction cache. These are called 29 * after loading a user application into memory, we must invalidate the 33 /* struct cache, d=dcache, i=icache, fl = flush, iv = invalidate, 41 void (*iin)(void); /* invalidate */ 48 void (*din)(void); /* invalidate */
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H A D | mmu.h | 57 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ 58 extern void _tlbia(void); /* invalidate all TLB entries */
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/linux-4.4.14/arch/arm/include/asm/ |
H A D | outercache.h | 48 * outer_inv_range - invalidate range of outer cache lines 70 * outer_flush_range - clean and invalidate outer cache lines 81 * outer_flush_all - clean and invalidate all cache lines in the outer cache 89 * (Some implementations perform this as a clean followed by an invalidate.) 98 * outer_disable - clean, invalidate and disable the outer cache
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H A D | cacheflush.h | 44 * Unconditionally clean and invalidate the entire icache. 50 * Unconditionally clean and invalidate the entire cache. 55 * inner shareable and invalidate the I-cache. 61 * Clean and invalidate all user space cache entries 66 * Clean and invalidate a range of cache entries in the 99 * Clean and invalidate the specified virtual address range. 287 * have userspace mappings, then we _must_ always clean + invalidate 369 * Any cached read must be preceded by a cache invalidate operation. 370 * Yet, in the read case, a cache flush i.e. atomic clean+invalidate 409 * usage of flush rather than invalidate operations. 423 /* Clean and invalidate stale data for *p from outer ... */ __sync_cache_range_r()
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H A D | mmu_context.h | 124 * so check for possible thread migration and invalidate the I-cache switch_mm()
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H A D | kvm_mmu.h | 194 * we can invalidate just that page, but if we are using a VIPT cache __coherent_cache_guest_page() 195 * we need to invalidate the entire icache - damn shame - as written __coherent_cache_guest_page()
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H A D | tlb.h | 11 * to use the "invalidate whole tlb" rather than "invalidate single
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/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ |
H A D | priv.h | 21 void (*invalidate)(struct nvkm_ltc *); member in struct:nvkm_ltc_func
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H A D | gk104.c | 48 .invalidate = gf100_ltc_invalidate,
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H A D | base.c | 73 if (ltc->func->invalidate) nvkm_ltc_invalidate() 74 ltc->func->invalidate(ltc); nvkm_ltc_invalidate()
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H A D | gf100.c | 134 nvkm_warn(<c->subdev, "LTC invalidate timeout\n"); gf100_ltc_invalidate() 137 nvkm_debug(<c->subdev, "LTC invalidate took %lld ns\n", taken); gf100_ltc_invalidate() 248 .invalidate = gf100_ltc_invalidate,
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H A D | gm107.c | 141 .invalidate = gf100_ltc_invalidate,
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/linux-4.4.14/include/linux/ |
H A D | dcookies.h | 31 * Unregister as a dcookie user. This may invalidate
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/linux-4.4.14/arch/mips/include/asm/octeon/ |
H A D | cvmx-asm.h | 105 /* flush stores, invalidate entire icache */ 109 /* flush stores, invalidate entire icache */ 113 /* complete prefetches, invalidate entire dcache */ 124 /* invalidate the cache block and clear the USED bits for the block */
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/linux-4.4.14/arch/sh/include/cpu-sh2/cpu/ |
H A D | cache.h | 32 #define CCR_CACHE_CF 0x08 /* Cache invalidate */
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/linux-4.4.14/arch/tile/include/uapi/asm/ |
H A D | cachectl.h | 38 #define ICACHE (1<<0) /* invalidate L1 instruction cache */ 39 #define DCACHE (1<<1) /* flush and invalidate data cache */
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/linux-4.4.14/drivers/gpu/drm/i915/ |
H A D | intel_frontbuffer.c | 45 * into the invalidate and the flush functions: At invalidate the caching must 47 * when the frontbuffer changes (e.g. when the hw doesn't initiate an invalidate 52 * (e.g. DRRS). In that case all three (invalidate, flush and flip) indicate 69 * intel_fb_obj_invalidate - invalidate frontbuffer object 70 * @obj: GEM object to invalidate 178 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
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H A D | i915_trace.h | 514 TP_PROTO(struct drm_i915_gem_request *req, u32 invalidate, u32 flush), 515 TP_ARGS(req, invalidate, flush), 520 __field(u32, invalidate) 527 __entry->invalidate = invalidate; 531 TP_printk("dev=%u, ring=%x, invalidate=%04x, flush=%04x", 533 __entry->invalidate, __entry->flush)
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/linux-4.4.14/arch/mn10300/include/asm/ |
H A D | cpu-regs.h | 177 #define CHCTR_ICINV 0x0010 /* instruction cache invalidate */ 178 #define CHCTR_DCINV 0x0020 /* data cache invalidate */ 187 #define ICIVCR __SYSREG(0xc0000c00, u32) /* icache area invalidate control */ 188 #define ICIVCR_ICIVBSY 0x00000008 /* icache area invalidate busy */ 189 #define ICIVCR_ICI 0x00000001 /* icache area invalidate */ 191 #define ICIVMR __SYSREG(0xc0000c04, u32) /* icache area invalidate mask */ 196 #define DCPGCR_DCI 0x00000001 /* data cache area invalidate */ 205 #define MMUCTR_IIV 0x00000080 /* instruction TLB invalidate */ 216 #define MMUCTR_DIV 0x00800000 /* data TLB invalidate */
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H A D | smp.h | 11 * 23-Feb-2007 MEI Add the define related to SMP icahce invalidate.
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/linux-4.4.14/arch/tile/lib/ |
H A D | cacheflush.c | 35 * Flush and invalidate a VA range that is homed remotely on a single 73 * Flush and invalidate the buffer out of the local L1/L2 finv_buffer_remote() 74 * and request the home cache to flush and invalidate as well. finv_buffer_remote() 80 * all the flush-and-invalidate requests. This does not mean finv_buffer_remote() 156 * lines are clean in cache; we will only invalidate those lines. finv_buffer_remote()
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/linux-4.4.14/arch/c6x/platforms/ |
H A D | cache.c | 130 * invalidate or writeback/invalidate 243 * L1P global-invalidate all 254 * L1D global-invalidate all 303 * L2 global-writeback and global-invalidate all
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/linux-4.4.14/arch/powerpc/kvm/ |
H A D | book3s_mmu_hpte.c | 172 /* Check the list for matching entries and invalidate */ kvmppc_mmu_pte_flush_page() 192 /* Check the list for matching entries and invalidate */ kvmppc_mmu_pte_flush_long() 234 /* Check the list for matching entries and invalidate */ kvmppc_mmu_pte_vflush_short() 256 /* Check the list for matching entries and invalidate */ kvmppc_mmu_pte_vflush_64k() 278 /* Check the list for matching entries and invalidate */ kvmppc_mmu_pte_vflush_long()
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H A D | e500.c | 89 * the caller will invalidate everything and start over. local_sid_setup_one() 259 * we invalidate the entire shadow PID. kvmppc_e500_tlbil_one() 270 * search host TLB to invalidate it's shadow TLB entry, kvmppc_e500_tlbil_one()
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/linux-4.4.14/arch/tile/include/asm/ |
H A D | cacheflush.h | 89 /* Flush & invalidate a VA range; pads to L2 cacheline boundaries. */ __finv_buffer() 112 * Flush and invalidate a locally-homecached VA range and wait for the 142 * Flush and invalidate a VA range that is homed remotely, waiting
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H A D | mmu_context.h | 58 * handling a remote TLB invalidate required doing a page table
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/linux-4.4.14/arch/unicore32/boot/compressed/ |
H A D | head.S | 87 movc p0.c5, r0, #28 @ cache invalidate all 89 movc p0.c6, r0, #6 @ tlb invalidate all 145 movc p0.c5, r0, #20 @ icache invalidate all
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/linux-4.4.14/arch/unicore32/mm/ |
H A D | cache-ucv2.S | 38 movc p0.c5, r0, #20 @ Icache invalidate all 77 movc p0.c5, ip, #20 @ Icache invalidate all 127 movc p0.c5, ip, #20 @ Icache invalidate all
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H A D | proc-macros.S | 28 * using the single invalidate entry instructions. Anything larger
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/linux-4.4.14/arch/m32r/boot/compressed/ |
H A D | head.S | 138 ldi r1, 0xd0 ; invalidate i-cache, copy back d-cache 143 ldi r1, 0x0100 ; invalidate 148 ldi r1, 0x0700 ; invalidate i-cache, copy back d-cache
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/linux-4.4.14/arch/blackfin/include/asm/ |
H A D | dma-mapping.h | 53 case DMA_FROM_DEVICE: /* invalidate only */ __dma_sync_inline() 54 case DMA_BIDIRECTIONAL: /* flush and invalidate */ __dma_sync_inline() 55 /* Blackfin has no dedicated invalidate (it includes a flush) */ __dma_sync_inline()
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H A D | cacheflush.h | 52 * are flushed before trying to invalidate the icache. This flush_icache_range()
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/linux-4.4.14/arch/blackfin/mach-common/ |
H A D | cache.S | 103 * write them back. Since the Blackfin ISA does not have an "invalidate" 104 * instruction, we use flush/invalidate. Perhaps as a speed optimization we
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/linux-4.4.14/arch/mips/mm/ |
H A D | sc-ip22.c | 162 writeback + invalidate and just invalidate. */
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H A D | sc-r5k.c | 48 * invalidate less than a page at a time. r5k_dma_cache_inv_sc()
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H A D | cex-sb1.S | 118 * CacheErr-I is valid and we can just invalidate all blocks
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H A D | sc-mips.c | 24 * Writeback and invalidate the secondary cache before DMA.
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H A D | sc-rm7k.c | 39 * Writeback and invalidate the primary cache dcache before DMA.
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/linux-4.4.14/arch/nios2/boot/compressed/ |
H A D | head.S | 24 /* invalidate all instruction cache */ 30 /* invalidate all data cache */
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/linux-4.4.14/arch/cris/mm/ |
H A D | tlb.c | 20 * to invalidate TLB entries. 107 /* invalidate the entire TLB */ tlb_init()
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/linux-4.4.14/arch/avr32/mm/ |
H A D | dma-coherent.c | 25 case DMA_FROM_DEVICE: /* invalidate only */ dma_cache_sync() 31 case DMA_BIDIRECTIONAL: /* writeback and invalidate */ dma_cache_sync()
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/linux-4.4.14/include/trace/events/ |
H A D | thp.h | 24 TP_printk("hugepage invalidate at addr 0x%lx and pte = 0x%lx",
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/linux-4.4.14/arch/powerpc/include/asm/ |
H A D | mmu-book3e.h | 145 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 146 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 147 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 148 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
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H A D | mmu.h | 42 /* Enable use of tlbilx invalidate instructions. 48 * around such invalidate forms.
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H A D | uninorth.h | 65 * In order to invalidate the GART (which is probably necessary to inval 77 * Turning on AGP seem to require a double invalidate operation, one before
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H A D | reg_a2.h | 62 #define MMUCR1_TLBWE_BINV 0x00004000 /* back invalidate on tlbwe */
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/linux-4.4.14/arch/frv/lib/ |
H A D | cache.S | 81 # Write back and invalidate a range of dcache and icache
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/linux-4.4.14/arch/powerpc/kernel/ |
H A D | l2cr_6xx.S | 53 global invalidate. If you are disabling the cache, you must 57 global invalidate bit set. A global invalidate will only be 88 cache, and the invalidate is a control as well as status. 138 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ 152 from getting into the cache. But since we invalidate 315 rlwinm r3,r3,0,22,20 /* Turn off the invalidate bit */
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H A D | misc_32.S | 333 /* 603/604 processor - use invalidate-all bit in HID0 */ 343 * and invalidate the corresponding instruction cache blocks. 371 /* Flash invalidate on 44x because we are passed kmapped addresses and 381 * Does not invalidate the corresponding cache lines (especially for 402 * Write any modified data cache blocks out to memory and invalidate them. 403 * Does not invalidate the corresponding instruction cache blocks. 423 * Like above, but invalidate the D-cache. This is used by the 8xx 424 * to invalidate the cache so the PPC core doesn't get stale data 944 * This would invalidate the entire UTLB including the one we are 978 * Use way '0' so that we could easily invalidate it later.
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H A D | cpu_setup_power.S | 139 * (invalidate by congruence class). P7 has 128 CCs., P8 has 512.
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/linux-4.4.14/arch/arm/boot/compressed/ |
H A D | head.S | 658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 670 /* ?? invalidate for the second time? */ 671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3 1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4 1070 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4 1086 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB 1088 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC 1111 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache 1114 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index 1121 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 1129 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache 1137 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D 1138 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB 1139 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified 1150 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D 1185 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way 1200 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB 1208 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache 1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
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/linux-4.4.14/arch/powerpc/mm/ |
H A D | hash_native_64.c | 299 * We need to invalidate the TLB always because hpte_remove doesn't do native_hpte_updatepp() 300 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less native_hpte_updatepp() 301 * random entry from it. When we do that we don't invalidate the TLB native_hpte_updatepp() 407 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot); native_hpte_invalidate() 414 * We need to invalidate the TLB always because hpte_remove doesn't do native_hpte_invalidate() 415 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less native_hpte_invalidate() 416 * random entry from it. When we do that we don't invalidate the TLB native_hpte_invalidate() 470 /* Even if we miss, we need to invalidate the TLB */ native_hugepage_invalidate() 477 * We need to do tlb invalidate for all the address, tlbie native_hugepage_invalidate()
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H A D | hugepage-hash64.c | 91 * invalidate the old hpte entry if we have that mapped via 64K __hash_page_thp()
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/linux-4.4.14/fs/f2fs/ |
H A D | recovery.c | 408 /* dest is invalid, just invalidate src block */ do_recover_data() 415 * dest is reserved block, invalidate src block do_recover_data() 577 bool invalidate = false; recover_fsync_data() local 580 invalidate = true; recover_fsync_data() 586 /* invalidate temporary meta page */ recover_fsync_data() 587 if (invalidate) recover_fsync_data()
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/linux-4.4.14/fs/xfs/ |
H A D | xfs_attr_inactive.c | 44 * invalidate any buffers that are incore/in transactions. 83 * so there's nothing to invalidate. xfs_attr3_leaf_freextent() 205 * We're doing a depth-first traversal in order to invalidate everything. 309 * Atomically commit the whole invalidate stuff. xfs_attr3_node_inactive() 323 * We're doing a depth-first traversal in order to invalidate everything. 376 * Commit the invalidate and start the next transaction. xfs_attr3_root_inactive()
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/linux-4.4.14/arch/unicore32/kernel/ |
H A D | sleep.S | 171 movc p0.c6, r1, #6 @ invalidate I & D TLBs 172 movc p0.c5, r1, #28 @ invalidate I & D caches, BTB
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H A D | head.S | 133 movc p0.c5, r0, #28 @ cache invalidate all 135 movc p0.c6, r0, #6 @ TLB invalidate all
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/linux-4.4.14/arch/xtensa/include/asm/ |
H A D | cacheflush.h | 19 * invalidate data or instruction cache: 31 * flush and invalidate data cache:
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H A D | initialize_mmu.h | 84 /* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
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/linux-4.4.14/arch/powerpc/platforms/ps3/ |
H A D | htab.c | 142 * instead invalidate it and ask the caller to update it via ps3_hpte_updatepp() 149 /* entry found, just invalidate it */ ps3_hpte_updatepp()
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/linux-4.4.14/arch/s390/include/asm/ |
H A D | tlb.h | 10 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY, 16 * a two step process: i) invalidate the pte, ii) store the new pte.
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/linux-4.4.14/arch/nios2/include/asm/ |
H A D | dma-mapping.h | 28 * instruction will do both writeback and invalidate. __dma_sync_for_device() 30 case DMA_BIDIRECTIONAL: /* flush and invalidate */ __dma_sync_for_device()
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/linux-4.4.14/arch/parisc/include/asm/ |
H A D | cacheflush.h | 49 * the invalidate, because the CPU should refuse to speculate once an 50 * area has been flushed, so invalidate is left empty */ flush_kernel_vmap_range()
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/linux-4.4.14/arch/frv/mm/ |
H A D | dma-alloc.c | 159 case PCI_DMA_FROMDEVICE: /* invalidate only */ consistent_sync() 165 case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */ consistent_sync()
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/linux-4.4.14/arch/arm64/include/asm/ |
H A D | cacheflush.h | 45 * Clean and invalidate all user space cache entries 108 * have userspace mappings, then we _must_ always clean + invalidate
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H A D | tlbflush.h | 32 * to determine if it should invalidate the TLB for each call. Start 158 * Used to invalidate the TLB (walk caches) corresponding to intermediate page
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H A D | tlb.h | 43 * The ASID allocator will either invalidate the ASID or mark tlb_flush()
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/linux-4.4.14/fs/ncpfs/ |
H A D | mmap.c | 27 * XXX: how are we excluding truncate/invalidate here? Maybe need to lock
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/linux-4.4.14/include/net/netfilter/ |
H A D | nf_conntrack_helper.h | 39 invalidate. */
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/linux-4.4.14/include/uapi/asm-generic/ |
H A D | mman-common.h | 34 #define MS_INVALIDATE 2 /* invalidate the caches */
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/linux-4.4.14/include/uapi/linux/ |
H A D | keyctl.h | 58 #define KEYCTL_INVALIDATE 21 /* invalidate a key */
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/linux-4.4.14/arch/sh/kernel/cpu/sh3/ |
H A D | probe.c | 32 /* First, write back & invalidate */ cpu_probe()
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/linux-4.4.14/arch/sparc/include/asm/ |
H A D | cacheflush_64.h | 30 * use block commit stores (which invalidate icache lines) during
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/linux-4.4.14/arch/m68k/include/asm/ |
H A D | cacheflush_no.h | 84 * data and then invalidate the cache lines associated with this address.
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H A D | cacheflush_mm.h | 58 * Use the ColdFire cpushl instruction to push (and invalidate) cache lines. 139 * invalidate the cache for the specified memory range. 152 * push and invalidate pages in the specified user virtual
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/linux-4.4.14/drivers/scsi/isci/ |
H A D | remote_node_context.h | 100 * @SCI_RNC_INVALIDATING: transition state that will post an RNC invalidate to 101 * the hardware. Once the invalidate is complete the remote node context will 148 RNC_DEST_SUSPENDED, /* Set when suspend during post/invalidate */
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/linux-4.4.14/arch/alpha/include/asm/ |
H A D | mmu_context.h | 57 * appropriate PALcode routine to invalidate the translation buffer (TB)". 102 * always considered invalid, so to invalidate another process you only 105 * If we need more ASN's than the processor has, we invalidate the old
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H A D | tlbflush.h | 34 careful about the icache here, there is no way to invalidate a
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/linux-4.4.14/arch/powerpc/platforms/pasemi/ |
H A D | iommu.c | 65 /* Register to invalidate TLB entries */ 107 /* invalidate tlb, can be optimized more */ iobmap_build() 131 /* invalidate tlb, can be optimized more */ iobmap_free()
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/linux-4.4.14/drivers/xen/xen-pciback/ |
H A D | conf_space_header.c | 102 DRV_NAME ": %s: enable memory-write-invalidate\n", command_write() 106 pr_warn("%s: cannot enable memory-write-invalidate (%d)\n", command_write() 114 DRV_NAME ": %s: disable memory-write-invalidate\n", command_write()
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/linux-4.4.14/drivers/misc/sgi-gru/ |
H A D | grutlbpurge.c | 48 * Find a TGH to use for issuing a TLB invalidate. For GRUs that are on the 53 * released when the invalidate is completes. This sucks, but it is the best we 116 * - GRU instructions to invalidate TLB entries are SLOOOOWWW - normally 143 * GRU to do an invalidate. 150 * GRU. TLB invalidate instructions must be issued to the GRU.
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/linux-4.4.14/net/sunrpc/xprtrdma/ |
H A D | frwr_ops.c | 202 /* Add room for frmr register and invalidate WRs. frwr_op_open() 204 * 2. FRMR invalidate WR for head frwr_op_open() 206 * 4. N FRMR invalidate WRs for pagelist frwr_op_open() 208 * 6. FRMR invalidate WR for tail frwr_op_open() 219 depth += 2; /* FRMR reg + invalidate */ frwr_op_open()
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/linux-4.4.14/mm/ |
H A D | truncate.c | 67 * do_invalidatepage - invalidate part or all of a page 69 * @offset: start of the range to invalidate 70 * @length: length of the range to invalidate 177 * Safely invalidate one page from its pagecache mapping. 214 * Note that since ->invalidatepage() accepts range to invalidate 443 * @mapping: the address_space which holds the pages to invalidate 444 * @start: the offset 'from' which to invalidate 445 * @end: the offset 'to' which to invalidate (inclusive) 451 * invalidate pages which are dirty, locked, under writeback or mapped into 555 * @start: the page offset 'from' which to invalidate 556 * @end: the page offset 'to' which to invalidate (inclusive)
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H A D | userfaultfd.c | 85 /* No need to invalidate - it was non-present before */ mcopy_atomic_pte() 116 /* No need to invalidate - it was non-present before */ mfill_zeropage_pte()
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H A D | pgtable-generic.c | 95 * invalidate the entire TLB which is not desitable.
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/linux-4.4.14/net/rds/ |
H A D | iw_rdma.c | 61 struct mutex flush_lock; /* serialize fmr invalidate */ 482 /* Batched invalidate of dirty MRs. rds_iw_flush_mr_pool() 530 void rds_iw_free_mr(void *trans_private, int invalidate) rds_iw_free_mr() argument 547 if (invalidate) { rds_iw_free_mr() 552 * as use_once and invalidate at the same time. */ rds_iw_free_mr() 625 * mappings over time. To avoid stalling on the expensive map and invalidate 810 * of these without requiring an explicit invalidate). rds_iw_unmap_fastreg_list()
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/linux-4.4.14/arch/metag/kernel/ |
H A D | dma.c | 440 * so that we have no dirty lines, and invalidate the cache dma_sync_for_device() 449 * There's no need to invalidate as the device shouldn't write dma_sync_for_device() 481 * This should never cause dirty lines, so a flush or invalidate should dma_sync_for_cpu()
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/linux-4.4.14/drivers/scsi/ |
H A D | mvme147.c | 45 /* invalidate any cache */ dma_setup()
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/linux-4.4.14/drivers/mtd/maps/ |
H A D | pxa2xx-flash.c | 36 /* invalidate D cache line */ pxa2xx_map_inval_cache()
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/linux-4.4.14/arch/um/include/asm/ |
H A D | tlb.h | 117 * later optimise away the tlb invalidate. This helps when userspace is
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/linux-4.4.14/arch/alpha/include/uapi/asm/ |
H A D | mman.h | 36 #define MS_INVALIDATE 4 /* invalidate the caches */
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/linux-4.4.14/security/integrity/ima/ |
H A D | ima_queue.c | 135 if (violation) /* invalidate pcr */ ima_add_template_entry()
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/linux-4.4.14/arch/m68k/lib/ |
H A D | mulsi3.S | 27 This exception does not however invalidate any other reasons why
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H A D | divsi3.S | 27 This exception does not however invalidate any other reasons why
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H A D | modsi3.S | 27 This exception does not however invalidate any other reasons why
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H A D | umodsi3.S | 27 This exception does not however invalidate any other reasons why
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/linux-4.4.14/arch/mn10300/boot/compressed/ |
H A D | head.S | 49 # invalidate and enable both of the caches
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/linux-4.4.14/arch/parisc/include/uapi/asm/ |
H A D | mman.h | 30 #define MS_INVALIDATE 4 /* invalidate the caches */
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/linux-4.4.14/arch/avr32/include/asm/ |
H A D | cacheflush.h | 48 * to memory and then invalidate it.
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/linux-4.4.14/drivers/s390/char/ |
H A D | hmcdrv_cache.c | 149 hmcdrv_cache_file.ofs = -1; /* invalidate content */ hmcdrv_cache_do() 199 /* invalidate the (read) cache in case there was a write operation hmcdrv_cache_cmd()
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/linux-4.4.14/arch/xtensa/mm/ |
H A D | cache.c | 268 /* Flush and invalidate user page if aliased. */ copy_to_user_page() 280 * Flush and invalidate kernel page if aliased and synchronize copy_to_user_page()
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/linux-4.4.14/arch/powerpc/platforms/52xx/ |
H A D | lite5200_sleep.S | 225 /* invalidate caches */ 228 mtspr SPRN_HID0, r5 /* invalidate caches */
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H A D | mpc52xx_pm.c | 150 /* save original, copy our irq handler, flush from dcache and invalidate icache */ mpc52xx_pm_enter()
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/linux-4.4.14/arch/mips/include/asm/ |
H A D | war.h | 117 * Writeback and invalidate the primary cache dcache before DMA. 168 * Hit_Invalidate_I cacheops invalidate an icache line but the refill
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H A D | cacheflush.h | 133 * cache writeback and invalidate operation.
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/linux-4.4.14/arch/score/mm/ |
H A D | cache.c | 253 /* flush dcache to ram, and invalidate dcache lines. */ flush_dcache_range() 272 /* invalidate icache lines. */ flush_icache_range()
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/linux-4.4.14/arch/microblaze/mm/ |
H A D | consistent.c | 242 case PCI_DMA_FROMDEVICE: /* invalidate only */ consistent_sync() 248 case PCI_DMA_BIDIRECTIONAL: /* writeback and invalidate */ consistent_sync()
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/linux-4.4.14/arch/ia64/include/asm/sn/ |
H A D | tioca_provider.h | 30 /* TIO:CA TLB invalidate of written GART entries possibly not occurring in CA*/ 155 * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
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/linux-4.4.14/arch/arm/mach-imx/ |
H A D | mm-imx3.c | 49 /* invalidate I cache */ imx3_idle() 52 /* clear and invalidate D cache */ imx3_idle()
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/linux-4.4.14/drivers/md/bcache/ |
H A D | alloc.c | 18 * When we invalidate a bucket, we have to write its new gen to disk and wait 59 * invalidated, and then invalidate them and stick them on the free_inc list - 345 * we can invalidate. First, invalidate them in memory and add bch_allocator_thread() 364 * waiting on garbage collection before we invalidate bch_allocator_thread()
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/linux-4.4.14/fs/ceph/ |
H A D | snap.c | 673 int invalidate = 0; ceph_update_snap_trace() local 702 invalidate += err; ceph_update_snap_trace() 729 invalidate = 1; ceph_update_snap_trace() 733 invalidate = 1; ceph_update_snap_trace() 740 realm, invalidate, p, e); ceph_update_snap_trace() 742 /* invalidate when we reach the _end_ (root) of the trace */ ceph_update_snap_trace() 743 if (invalidate && p >= e) ceph_update_snap_trace()
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/linux-4.4.14/fs/coda/ |
H A D | dir.c | 105 /* invalidate the directory cnode's attributes so we refetch the coda_dir_update_mtime() 157 /* invalidate the directory cnode's attributes */ coda_create() 190 /* invalidate the directory cnode's attributes */ coda_mkdir()
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/linux-4.4.14/arch/arm/mach-omap2/ |
H A D | sleep44xx.S | 94 * Invalidate L1 data cache. Even though only invalidate is 140 * Clean and invalidate the L2 cache. 287 * L2 cache is already invalidate by ROM code as part
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/linux-4.4.14/drivers/staging/rtl8723au/core/ |
H A D | rtw_sreset.c | 88 /* TH = 1 => means that invalidate usb rx aggregation */ sreset_restore_network_station()
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/linux-4.4.14/drivers/iommu/ |
H A D | io-pgtable.h | 18 * @tlb_flush_all: Synchronously invalidate the entire TLB context.
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/linux-4.4.14/drivers/base/power/ |
H A D | domain_governor.c | 113 * We have to invalidate the cached results for the masters, so default_power_down_ok()
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/linux-4.4.14/arch/xtensa/boot/boot-redboot/ |
H A D | bootstrap.S | 110 /* We have to flush and invalidate the caches here before we jump. */
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/linux-4.4.14/arch/xtensa/include/uapi/asm/ |
H A D | mman.h | 69 #define MS_INVALIDATE 0x0002 /* invalidate mappings & caches */
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/linux-4.4.14/arch/cris/arch-v32/mm/ |
H A D | tlb.c | 34 * invalidate TLB entries.
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/linux-4.4.14/fs/jfs/ |
H A D | jfs_metapage.h | 144 * This routines invalidate all pages for an extent.
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/linux-4.4.14/fs/ocfs2/ |
H A D | mmap.c | 102 * because the "write" would invalidate their data. __ocfs2_page_mkwrite()
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/linux-4.4.14/arch/powerpc/platforms/85xx/ |
H A D | xes_mpc85xx.c | 40 #define MPC85xx_L2CTL_L2I 0x40000000 /* L2 flash invalidate */
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/linux-4.4.14/arch/powerpc/sysdev/ |
H A D | fsl_85xx_cache_ctlr.h | 26 #define L2CR_L2FI 0x40000000 /* L2 flash invalidate */
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/linux-4.4.14/arch/microblaze/kernel/ |
H A D | dma.c | 121 * It's pointless to invalidate the cache if the device isn't dma_direct_sync_single_for_device()
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