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Searched refs:gate (Results 1 – 197 of 197) sorted by relevance

/linux-4.4.14/drivers/clk/tegra/
Dclk-periph-gate.c30 #define read_enb(gate) \ argument
31 readl_relaxed(gate->clk_base + (gate->regs->enb_reg))
32 #define write_enb_set(val, gate) \ argument
33 writel_relaxed(val, gate->clk_base + (gate->regs->enb_set_reg))
34 #define write_enb_clr(val, gate) \ argument
35 writel_relaxed(val, gate->clk_base + (gate->regs->enb_clr_reg))
37 #define read_rst(gate) \ argument
38 readl_relaxed(gate->clk_base + (gate->regs->rst_reg))
39 #define write_rst_clr(val, gate) \ argument
40 writel_relaxed(val, gate->clk_base + (gate->regs->rst_clr_reg))
[all …]
Dclk-periph.c86 struct clk_hw *gate_hw = &periph->gate.hw; in clk_periph_is_enabled()
97 struct clk_hw *gate_hw = &periph->gate.hw; in clk_periph_enable()
108 struct clk_hw *gate_hw = &periph->gate.hw; in clk_periph_disable()
149 bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV); in _tegra_clk_register_periph()
151 if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) { in _tegra_clk_register_periph()
154 } else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE) in _tegra_clk_register_periph()
164 bank = get_reg_bank(periph->gate.clk_num); in _tegra_clk_register_periph()
173 periph->gate.clk_base = clk_base; in _tegra_clk_register_periph()
174 periph->gate.regs = bank; in _tegra_clk_register_periph()
175 periph->gate.enable_refcnt = periph_clk_enb_refcnt; in _tegra_clk_register_periph()
[all …]
DMakefile6 obj-y += clk-periph-gate.o
Dclk-tegra-periph.c598 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
602 data->periph.gate.regs = bank; in periph_clk_init()
628 data->p.parent_name, data->periph.gate.flags, in gate_clk_init()
630 data->periph.gate.clk_num, in gate_clk_init()
Dclk.h447 struct tegra_clk_periph_gate gate; member
487 .gate = { \
/linux-4.4.14/drivers/clk/mmp/
Dclk-gate.c29 struct mmp_clk_gate *gate = to_clk_mmp_gate(hw); in mmp_clk_gate_enable() local
34 if (gate->lock) in mmp_clk_gate_enable()
35 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
37 tmp = readl(gate->reg); in mmp_clk_gate_enable()
38 tmp &= ~gate->mask; in mmp_clk_gate_enable()
39 tmp |= gate->val_enable; in mmp_clk_gate_enable()
40 writel(tmp, gate->reg); in mmp_clk_gate_enable()
42 if (gate->lock) in mmp_clk_gate_enable()
43 spin_unlock_irqrestore(gate->lock, flags); in mmp_clk_gate_enable()
45 if (gate->flags & MMP_CLK_GATE_NEED_DELAY) { in mmp_clk_gate_enable()
[all …]
DMakefile5 obj-y += clk-apbc.o clk-apmu.o clk-frac.o clk-mix.o clk-gate.o clk.o
/linux-4.4.14/drivers/clk/imx/
Dclk-gate2.c43 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_enable() local
47 spin_lock_irqsave(gate->lock, flags); in clk_gate2_enable()
49 if (gate->share_count && (*gate->share_count)++ > 0) in clk_gate2_enable()
52 reg = readl(gate->reg); in clk_gate2_enable()
53 reg |= 3 << gate->bit_idx; in clk_gate2_enable()
54 writel(reg, gate->reg); in clk_gate2_enable()
57 spin_unlock_irqrestore(gate->lock, flags); in clk_gate2_enable()
64 struct clk_gate2 *gate = to_clk_gate2(hw); in clk_gate2_disable() local
68 spin_lock_irqsave(gate->lock, flags); in clk_gate2_disable()
70 if (gate->share_count) { in clk_gate2_disable()
[all …]
Dclk-gate-exclusive.c28 struct clk_gate gate; member
34 struct clk_gate *gate = container_of(hw, struct clk_gate, hw); in clk_gate_exclusive_enable() local
35 struct clk_gate_exclusive *exgate = container_of(gate, in clk_gate_exclusive_enable()
36 struct clk_gate_exclusive, gate); in clk_gate_exclusive_enable()
37 u32 val = readl(gate->reg); in clk_gate_exclusive_enable()
65 struct clk_gate *gate; in imx_clk_gate_exclusive() local
75 gate = &exgate->gate; in imx_clk_gate_exclusive()
83 gate->reg = reg; in imx_clk_gate_exclusive()
84 gate->bit_idx = shift; in imx_clk_gate_exclusive()
85 gate->lock = &imx_ccm_lock; in imx_clk_gate_exclusive()
[all …]
DMakefile8 clk-gate-exclusive.o \
/linux-4.4.14/drivers/staging/sm750fb/
Dddk750_power.c80 void setCurrentGate(unsigned int gate) in setCurrentGate() argument
101 POKE32(gate_reg, gate); in setCurrentGate()
111 u32 gate; in enable2DEngine() local
113 gate = PEEK32(CURRENT_GATE); in enable2DEngine()
115 gate = FIELD_SET(gate, CURRENT_GATE, DE, ON); in enable2DEngine()
116 gate = FIELD_SET(gate, CURRENT_GATE, CSC, ON); in enable2DEngine()
118 gate = FIELD_SET(gate, CURRENT_GATE, DE, OFF); in enable2DEngine()
119 gate = FIELD_SET(gate, CURRENT_GATE, CSC, OFF); in enable2DEngine()
122 setCurrentGate(gate); in enable2DEngine()
127 u32 gate; in enableDMA() local
[all …]
Dddk750_power.h30 void setCurrentGate(unsigned int gate);
/linux-4.4.14/drivers/clk/
Dclk-gate.c46 struct clk_gate *gate = to_clk_gate(hw); in clk_gate_endisable() local
47 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0; in clk_gate_endisable()
53 if (gate->lock) in clk_gate_endisable()
54 spin_lock_irqsave(gate->lock, flags); in clk_gate_endisable()
56 __acquire(gate->lock); in clk_gate_endisable()
58 if (gate->flags & CLK_GATE_HIWORD_MASK) { in clk_gate_endisable()
59 reg = BIT(gate->bit_idx + 16); in clk_gate_endisable()
61 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
63 reg = clk_readl(gate->reg); in clk_gate_endisable()
66 reg |= BIT(gate->bit_idx); in clk_gate_endisable()
[all …]
DMakefile8 obj-$(CONFIG_COMMON_CLK) += clk-gate.o
DKconfig162 a power sleep control module that gate the clock to the IPs and PLLs.
/linux-4.4.14/arch/ia64/kernel/
DMakefile.gate3 targets += gate.so gate-syms.o
5 extra-y += gate.so gate-syms.o gate.lds gate.o
12 GATECFLAGS_gate.so = -shared -s -Wl,-soname=linux-gate.so.1 \
14 $(obj)/gate.so: $(obj)/gate.lds $(obj)/gate.o FORCE
15 $(call if_changed,gate)
17 $(obj)/built-in.o: $(obj)/gate-syms.o
18 $(obj)/built-in.o: ld_flags += -R $(obj)/gate-syms.o
21 $(obj)/gate-syms.o: $(obj)/gate.lds $(obj)/gate.o FORCE
22 $(call if_changed,gate)
27 $(obj)/gate-data.o: $(obj)/gate.so
Dgate-data.S1 .section .data..gate, "aw"
D.gitignore1 gate.lds
DMakefile11 obj-y := entry.o efi.o efi_stub.o gate-data.o fsys.o ia64_ksyms.o irq.o irq_ia64.o \
51 include $(src)/Makefile.gate
Dvmlinux.lds.S162 *(.data..gate)
/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Dgate.txt1 Binding for Texas Instruments gate clock.
6 quite much similar to the basic gate-clock [2], however,
13 [2] Documentation/devicetree/bindings/clock/gate-clock.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
23 "ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
26 "ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
28 "ti,composite-gate-clock" - composite gate clock, to be part of composite
[all …]
Dinterface.txt6 quite much similar to the basic gate-clock [2], however,
8 companion clock finding (match corresponding functional gate
12 [2] Documentation/devicetree/bindings/clock/gate-clock.txt
Ddpll.txt28 "ti,am3-dpll-no-gate-clock",
30 "ti,am3-dpll-no-gate-j-type-clock",
Dautoidle.txt8 clock, it is always a derivative of some basic clock like a gate, divider,
Dcomposite.txt23 [4] Documentation/devicetree/bindings/clock/ti/gate.txt
Dmux.txt8 gate or adjust the parent rate via a divider or multiplier.
Ddivider.txt6 register-mapped adjustable clock rate divider that does not gate and has
/linux-4.4.14/drivers/clk/ingenic/
Djz4780-cgu.c348 .gate = { CGU_REG_CLKGR1, 2 },
390 .gate = { CGU_REG_CLKGR0, 3 },
397 .gate = { CGU_REG_CLKGR0, 11 },
404 .gate = { CGU_REG_CLKGR0, 12 },
413 .gate = { CGU_REG_CLKGR0, 24 },
448 .gate = { CGU_REG_CLKGR1, 3 },
457 .gate = { CGU_REG_CLKGR1, 4 },
466 .gate = { CGU_REG_CLKGR1, 9 },
475 .gate = { CGU_REG_CLKGR0, 1 },
483 .gate = { CGU_REG_CLKGR0, 0 },
[all …]
Djz4740-cgu.c124 .gate = { CGU_REG_CLKGR, 10 },
138 .gate = { CGU_REG_CLKGR, 6 },
146 .gate = { CGU_REG_CLKGR, 4 },
153 .gate = { CGU_REG_CLKGR, 7 },
160 .gate = { CGU_REG_CLKGR, 14 },
168 .gate = { CGU_REG_SCR, 6 },
176 .gate = { CGU_REG_CLKGR, 0 },
182 .gate = { CGU_REG_CLKGR, 15 },
188 .gate = { CGU_REG_CLKGR, 12 },
194 .gate = { CGU_REG_CLKGR, 13 },
[all …]
Dcgu.h157 struct ingenic_cgu_gate_info gate; member
Dcgu.c442 ingenic_cgu_gate_set(cgu, &clk_info->gate, false); in ingenic_clk_enable()
461 ingenic_cgu_gate_set(cgu, &clk_info->gate, true); in ingenic_clk_disable()
478 enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate); in ingenic_clk_is_enabled()
/linux-4.4.14/drivers/clk/ti/
Dgate.c142 struct ti_clk_gate *gate; in ti_clk_register_gate() local
144 gate = setup->data; in ti_clk_register_gate()
146 if (gate->flags & CLKF_INTERFACE) in ti_clk_register_gate()
151 if (gate->flags & CLKF_SET_RATE_PARENT) in ti_clk_register_gate()
154 if (gate->flags & CLKF_SET_BIT_TO_DISABLE) in ti_clk_register_gate()
157 if (gate->flags & CLKF_HSDIV) { in ti_clk_register_gate()
162 if (gate->flags & CLKF_DSS) in ti_clk_register_gate()
165 if (gate->flags & CLKF_WAIT) in ti_clk_register_gate()
168 if (gate->flags & CLKF_CLKDM) in ti_clk_register_gate()
171 if (gate->flags & CLKF_AM35XX) in ti_clk_register_gate()
[all …]
Dinterface.c77 struct ti_clk_gate *gate; in ti_clk_register_interface() local
79 gate = setup->data; in ti_clk_register_interface()
81 reg_setup->index = gate->module; in ti_clk_register_interface()
82 reg_setup->offset = gate->reg; in ti_clk_register_interface()
84 if (gate->flags & CLKF_NO_WAIT) in ti_clk_register_interface()
87 if (gate->flags & CLKF_HSOTGUSB) in ti_clk_register_interface()
90 if (gate->flags & CLKF_DSS) in ti_clk_register_interface()
93 if (gate->flags & CLKF_SSI) in ti_clk_register_interface()
96 if (gate->flags & CLKF_AM35XX) in ti_clk_register_interface()
99 return _register_interface(NULL, setup->name, gate->parent, in ti_clk_register_interface()
[all …]
Dcomposite.c125 struct clk_hw *gate; in ti_clk_register_composite() local
135 gate = ti_clk_build_component_gate(comp->gate); in ti_clk_register_composite()
141 if (gate) in ti_clk_register_composite()
142 parent_names = &comp->gate->parent; in ti_clk_register_composite()
152 &ti_composite_divider_ops, gate, in ti_clk_register_composite()
Dclk-3xxx-legacy.c654 .gate = &mcbsp2_gate_fck_data,
717 .gate = &ssi_ssr_gate_fck_3430es1_data,
826 .gate = &gpt2_gate_fck_data,
965 .gate = &mcbsp3_gate_fck_data,
1010 .gate = &gpt9_gate_fck_data,
1518 .gate = &clkout2_src_gate_ck_data,
1579 .gate = &gpt7_gate_fck_data,
1606 .gate = &usb_l4_gate_ick_data,
1924 .gate = &gpt11_gate_fck_data,
2377 .gate = &gpt1_gate_fck_data,
[all …]
DMakefile2 clk-common = dpll.o composite.o divider.o gate.o \
Dclock.h122 struct ti_clk_gate *gate; member
/linux-4.4.14/drivers/clk/bcm/
Dclk-kona.c357 __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __is_clk_gate_enabled() argument
363 if (!gate_exists(gate)) in __is_clk_gate_enabled()
366 bit_mask = 1 << gate->status_bit; in __is_clk_gate_enabled()
367 reg_val = __ccu_read(ccu, gate->offset); in __is_clk_gate_enabled()
374 is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate) in is_clk_gate_enabled() argument
380 if (!gate_exists(gate)) in is_clk_gate_enabled()
384 ret = __is_clk_gate_enabled(ccu, gate); in is_clk_gate_enabled()
395 __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate) in __gate_commit() argument
401 BUG_ON(!gate_exists(gate)); in __gate_commit()
402 if (!gate_is_sw_controllable(gate)) in __gate_commit()
[all …]
Dclk-bcm281xx.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
42 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
51 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
84 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
103 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
115 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
127 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
139 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
151 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
162 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
[all …]
Dclk-bcm21664.c24 .gate = HW_SW_GATE(0x214, 16, 0, 1),
41 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
66 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
78 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
90 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
102 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
115 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
120 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
125 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
130 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
[all …]
Dclk-iproc-asiu.c33 struct iproc_asiu_gate gate; member
53 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_enable()
56 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
57 val |= (1 << clk->gate.en_shift); in iproc_asiu_clk_enable()
58 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_enable()
70 if (clk->gate.offset == IPROC_CLK_INVALID_OFFSET) in iproc_asiu_clk_disable()
73 val = readl(asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
74 val &= ~(1 << clk->gate.en_shift); in iproc_asiu_clk_disable()
75 writel(val, asiu->gate_base + clk->gate.offset); in iproc_asiu_clk_disable()
187 const struct iproc_asiu_gate *gate, in iproc_asiu_setup() argument
[all …]
Dclk-kona.h54 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS) argument
55 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED) argument
56 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW) argument
57 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW) argument
58 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED) argument
59 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE) argument
61 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED) argument
392 struct bcm_clk_gate gate; member
Dclk-kona-setup.c81 struct bcm_clk_gate *gate; in peri_clk_data_offsets_valid() local
107 gate = &peri->gate; in peri_clk_data_offsets_valid()
109 if (gate_exists(gate)) { in peri_clk_data_offsets_valid()
110 if (gate->offset > limit) { in peri_clk_data_offsets_valid()
112 __func__, name, gate->offset, limit); in peri_clk_data_offsets_valid()
253 static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name, in gate_valid() argument
256 if (!bit_posn_valid(gate->status_bit, "gate status", clock_name)) in gate_valid()
259 if (gate_is_sw_controllable(gate)) { in gate_valid()
260 if (!bit_posn_valid(gate->en_bit, "gate enable", clock_name)) in gate_valid()
263 if (gate_is_hw_controllable(gate)) { in gate_valid()
[all …]
Dclk-iproc.h195 const struct iproc_asiu_gate *gate,
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mtk.c117 const struct mtk_gate *gate = &clks[i]; in mtk_clk_register_gates() local
119 clk = mtk_clk_register_gate(gate->name, gate->parent_name, in mtk_clk_register_gates()
121 gate->regs->set_ofs, in mtk_clk_register_gates()
122 gate->regs->clr_ofs, in mtk_clk_register_gates()
123 gate->regs->sta_ofs, in mtk_clk_register_gates()
124 gate->shift, gate->ops); in mtk_clk_register_gates()
128 gate->name, PTR_ERR(clk)); in mtk_clk_register_gates()
132 clk_data->clks[gate->id] = clk; in mtk_clk_register_gates()
143 struct clk_gate *gate = NULL; in mtk_clk_register_composite() local
174 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in mtk_clk_register_composite()
[all …]
DMakefile1 obj-y += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
/linux-4.4.14/arch/x86/include/asm/
Ddesc.h55 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, in pack_gate() argument
58 gate->offset_low = PTR_LOW(func); in pack_gate()
59 gate->segment = __KERNEL_CS; in pack_gate()
60 gate->ist = ist; in pack_gate()
61 gate->p = 1; in pack_gate()
62 gate->dpl = dpl; in pack_gate()
63 gate->zero0 = 0; in pack_gate()
64 gate->zero1 = 0; in pack_gate()
65 gate->type = type; in pack_gate()
66 gate->offset_middle = PTR_MIDDLE(func); in pack_gate()
[all …]
Dparavirt_types.h143 int entrynum, const gate_desc *gate);
/linux-4.4.14/drivers/clk/sunxi/
Dclk-a10-mod1.c33 struct clk_gate *gate; in sun4i_mod1_clk_setup() local
47 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sun4i_mod1_clk_setup()
48 if (!gate) in sun4i_mod1_clk_setup()
54 gate->reg = reg; in sun4i_mod1_clk_setup()
55 gate->bit_idx = SUN4I_MOD1_ENABLE; in sun4i_mod1_clk_setup()
56 gate->lock = &mod1_lock; in sun4i_mod1_clk_setup()
65 &gate->hw, &clk_gate_ops, 0); in sun4i_mod1_clk_setup()
74 kfree(gate); in sun4i_mod1_clk_setup()
Dclk-a10-hosc.c30 struct clk_gate *gate; in sun4i_osc_clk_setup() local
41 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_osc_clk_setup()
42 if (!gate) in sun4i_osc_clk_setup()
48 gate->reg = of_iomap(node, 0); in sun4i_osc_clk_setup()
49 gate->bit_idx = SUNXI_OSC24M_GATE; in sun4i_osc_clk_setup()
50 gate->lock = &hosc_lock; in sun4i_osc_clk_setup()
57 &gate->hw, &clk_gate_ops, in sun4i_osc_clk_setup()
69 kfree(gate); in sun4i_osc_clk_setup()
Dclk-a20-gmac.c65 struct clk_gate *gate; in sun7i_a20_gmac_clk_setup() local
78 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun7i_a20_gmac_clk_setup()
79 if (!gate) in sun7i_a20_gmac_clk_setup()
91 gate->reg = reg; in sun7i_a20_gmac_clk_setup()
92 gate->bit_idx = SUN7I_A20_GMAC_GPIT; in sun7i_a20_gmac_clk_setup()
93 gate->lock = &gmac_lock; in sun7i_a20_gmac_clk_setup()
103 &gate->hw, &clk_gate_ops, in sun7i_a20_gmac_clk_setup()
117 kfree(gate); in sun7i_a20_gmac_clk_setup()
Dclk-a10-pll2.c53 struct clk_gate *gate; in sun4i_pll2_setup() local
82 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sun4i_pll2_setup()
83 if (!gate) in sun4i_pll2_setup()
86 gate->reg = reg; in sun4i_pll2_setup()
87 gate->bit_idx = SUN4I_PLL2_ENABLE; in sun4i_pll2_setup()
88 gate->lock = &sun4i_a10_pll2_lock; in sun4i_pll2_setup()
107 &gate->hw, &clk_gate_ops, in sun4i_pll2_setup()
178 kfree(gate); in sun4i_pll2_setup()
Dclk-factors.c169 struct clk_gate *gate = NULL; in sunxi_factors_register() local
201 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); in sunxi_factors_register()
202 if (!gate) { in sunxi_factors_register()
208 gate->reg = reg; in sunxi_factors_register()
209 gate->bit_idx = data->enable; in sunxi_factors_register()
210 gate->lock = factors->lock; in sunxi_factors_register()
211 gate_hw = &gate->hw; in sunxi_factors_register()
219 kfree(gate); in sunxi_factors_register()
Dclk-sunxi.c921 u8 gate; /* is it independently gateable? */ member
947 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
983 struct clk_gate *gate = NULL; in sunxi_divs_clk_setup() local
1030 if (data->div[i].gate) { in sunxi_divs_clk_setup()
1031 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in sunxi_divs_clk_setup()
1032 if (!gate) in sunxi_divs_clk_setup()
1035 gate->reg = reg; in sunxi_divs_clk_setup()
1036 gate->bit_idx = data->div[i].gate; in sunxi_divs_clk_setup()
1037 gate->lock = &clk_lock; in sunxi_divs_clk_setup()
1039 gate_hw = &gate->hw; in sunxi_divs_clk_setup()
[all …]
/linux-4.4.14/arch/arm/boot/dts/
Dsocfpga.dtsi298 compatible = "altr,socfpga-gate-clk";
300 clk-gate = <0x60 0>;
312 compatible = "altr,socfpga-gate-clk";
315 clk-gate = <0x60 1>;
320 compatible = "altr,socfpga-gate-clk";
327 compatible = "altr,socfpga-gate-clk";
330 clk-gate = <0x60 2>;
335 compatible = "altr,socfpga-gate-clk";
338 clk-gate = <0x60 3>;
343 compatible = "altr,socfpga-gate-clk";
[all …]
Dam35xx-clocks.dtsi13 compatible = "ti,am35xx-gate-clock";
21 compatible = "ti,gate-clock";
29 compatible = "ti,am35xx-gate-clock";
37 compatible = "ti,gate-clock";
45 compatible = "ti,am35xx-gate-clock";
53 compatible = "ti,gate-clock";
61 compatible = "ti,am35xx-gate-clock";
98 compatible = "ti,wait-gate-clock";
Domap44xx-clocks.dtsi25 compatible = "ti,gate-clock";
51 compatible = "ti,gate-clock";
315 compatible = "ti,composite-no-wait-gate-clock";
557 compatible = "ti,gate-clock";
565 compatible = "ti,gate-clock";
573 compatible = "ti,gate-clock";
581 compatible = "ti,gate-clock";
674 compatible = "ti,gate-clock";
699 compatible = "ti,gate-clock";
742 compatible = "ti,clkdm-gate-clock";
[all …]
Domap3xxx-clocks.dtsi36 compatible = "ti,gate-clock";
222 compatible = "ti,gate-clock";
264 compatible = "ti,gate-clock";
379 compatible = "ti,gate-clock";
438 compatible = "ti,gate-clock";
466 compatible = "ti,gate-clock";
494 compatible = "ti,gate-clock";
511 compatible = "ti,composite-no-wait-gate-clock";
595 compatible = "ti,composite-gate-clock";
617 compatible = "ti,composite-gate-clock";
[all …]
Domap24xx-clocks.dtsi197 compatible = "ti,composite-no-wait-gate-clock";
228 compatible = "ti,gate-clock";
245 compatible = "ti,composite-gate-clock";
275 compatible = "ti,composite-gate-clock";
298 compatible = "ti,composite-gate-clock";
321 compatible = "ti,wait-gate-clock";
347 compatible = "ti,composite-no-wait-gate-clock";
447 compatible = "ti,composite-no-wait-gate-clock";
469 compatible = "ti,wait-gate-clock";
477 compatible = "ti,composite-gate-clock";
[all …]
Domap54xx-clocks.dtsi19 compatible = "ti,gate-clock";
39 compatible = "ti,gate-clock";
414 compatible = "ti,gate-clock";
603 compatible = "ti,gate-clock";
824 compatible = "ti,gate-clock";
832 compatible = "ti,gate-clock";
840 compatible = "ti,gate-clock";
849 compatible = "ti,gate-clock";
857 compatible = "ti,gate-clock";
865 compatible = "ti,gate-clock";
[all …]
Domap36xx-clocks.dtsi20 compatible = "ti,hsdiv-gate-clock";
30 compatible = "ti,hsdiv-gate-clock";
39 compatible = "ti,hsdiv-gate-clock";
48 compatible = "ti,hsdiv-gate-clock";
57 compatible = "ti,hsdiv-gate-clock";
66 compatible = "ti,wait-gate-clock";
Dam33xx-clocks.dtsi101 compatible = "ti,gate-clock";
109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
224 compatible = "ti,am3-dpll-no-gate-clock";
248 compatible = "ti,am3-dpll-no-gate-clock";
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
297 compatible = "ti,gate-clock";
321 compatible = "ti,gate-clock";
344 compatible = "ti,gate-clock";
401 compatible = "ti,gate-clock";
[all …]
Domap36xx-am35xx-omap3430es2plus-clocks.dtsi48 compatible = "ti,composite-gate-clock";
109 compatible = "ti,wait-gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,dss-gate-clock";
182 compatible = "ti,gate-clock";
190 compatible = "ti,dss-gate-clock";
Domap2420-clocks.dtsi14 compatible = "ti,composite-no-wait-gate-clock";
70 compatible = "ti,composite-gate-clock";
101 compatible = "ti,wait-gate-clock";
117 compatible = "ti,wait-gate-clock";
133 compatible = "ti,wait-gate-clock";
149 compatible = "ti,wait-gate-clock";
157 compatible = "ti,wait-gate-clock";
165 compatible = "ti,wait-gate-clock";
181 compatible = "ti,composite-gate-clock";
Domap2430-clocks.dtsi57 compatible = "ti,composite-gate-clock";
119 compatible = "ti,composite-gate-clock";
135 compatible = "ti,composite-gate-clock";
151 compatible = "ti,composite-gate-clock";
167 compatible = "ti,wait-gate-clock";
215 compatible = "ti,wait-gate-clock";
231 compatible = "ti,wait-gate-clock";
247 compatible = "ti,wait-gate-clock";
263 compatible = "ti,wait-gate-clock";
271 compatible = "ti,wait-gate-clock";
Dsocfpga_arria10.dtsi330 compatible = "altr,socfpga-a10-gate-clk";
333 clk-gate = <0x48 1>;
338 compatible = "altr,socfpga-a10-gate-clk";
341 clk-gate = <0x48 2>;
346 compatible = "altr,socfpga-a10-gate-clk";
349 clk-gate = <0x48 3>;
354 compatible = "altr,socfpga-a10-gate-clk";
357 clk-gate = <0x48 0>;
362 compatible = "altr,socfpga-a10-gate-clk";
364 clk-gate = <0xC8 5>;
[all …]
Dam43xx-clocks.dtsi109 compatible = "ti,gate-clock";
117 compatible = "ti,gate-clock";
125 compatible = "ti,gate-clock";
133 compatible = "ti,gate-clock";
141 compatible = "ti,gate-clock";
149 compatible = "ti,gate-clock";
359 compatible = "ti,gate-clock";
521 compatible = "ti,gate-clock";
529 compatible = "ti,gate-clock";
537 compatible = "ti,gate-clock";
[all …]
Domap3430es1-clocks.dtsi13 compatible = "ti,wait-gate-clock";
38 compatible = "ti,wait-gate-clock";
46 compatible = "ti,wait-gate-clock";
54 compatible = "ti,wait-gate-clock";
62 compatible = "ti,wait-gate-clock";
70 compatible = "ti,composite-no-wait-gate-clock";
157 compatible = "ti,gate-clock";
Domap34xx-omap36xx-clocks.dtsi53 compatible = "ti,gate-clock";
70 compatible = "ti,gate-clock";
134 compatible = "ti,wait-gate-clock";
142 compatible = "ti,wait-gate-clock";
187 compatible = "ti,wait-gate-clock";
219 compatible = "ti,wait-gate-clock";
Ddra7xx-clocks.dtsi1162 compatible = "ti,gate-clock";
1227 compatible = "ti,gate-clock";
1235 compatible = "ti,gate-clock";
1253 compatible = "ti,gate-clock";
1261 compatible = "ti,gate-clock";
1269 compatible = "ti,gate-clock";
1277 compatible = "ti,gate-clock";
1498 compatible = "ti,gate-clock";
1506 compatible = "ti,gate-clock";
1514 compatible = "ti,gate-clock";
[all …]
Domap443x-clocks.dtsi13 compatible = "ti,gate-clock";
Domap446x-clocks.dtsi22 compatible = "ti,gate-clock";
Domap36xx-omap3430es2plus-clocks.dtsi13 compatible = "ti,composite-no-wait-gate-clock";
68 compatible = "ti,composite-gate-clock";
Ddm816x-clocks.dtsi108 compatible = "ti,gate-clock";
181 compatible = "ti,gate-clock";
Dvexpress-v2p-ca5s.dts168 /* Test chip gate configuration */
Dimx6qdl-microsom.dtsi44 compatible = "gpio-gate-clock";
Dpicoxcell-pc3x3.dtsi44 compatible = "picochip,pc3x3-clk-gate";
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Drenesas,cpg-mstp-clocks.txt3 The CPG can gate SoC device clocks. The gates are organized in groups of up to
6 This device tree binding describes a single 32 gate clocks group per node.
13 - "renesas,r7s72100-mstp-clocks" for R7S72100 (RZ) MSTP gate clocks
14 - "renesas,r8a73a4-mstp-clocks" for R8A73A4 (R-Mobile APE6) MSTP gate clocks
15 - "renesas,r8a7740-mstp-clocks" for R8A7740 (R-Mobile A1) MSTP gate clocks
16 - "renesas,r8a7778-mstp-clocks" for R8A7778 (R-Car M1) MSTP gate clocks
17 - "renesas,r8a7779-mstp-clocks" for R8A7779 (R-Car H1) MSTP gate clocks
18 - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks
19 - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2-W) MSTP gate clocks
20 - "renesas,r8a7793-mstp-clocks" for R8A7793 (R-Car M2-N) MSTP gate clocks
[all …]
Drockchip.txt12 The gate registers form a continuos block which makes the dt node
14 one gate clock spanning all registers or they can be divided into
19 - compatible : "rockchip,rk2928-gate-clk"
22 - clock-output-names : the corresponding gate names that the clock controls
23 - clocks : should contain the parent clock for each individual gate,
27 Example using multiple gate clocks:
29 clk_gates0: gate-clk@200000d0 {
30 compatible = "rockchip,rk2928-gate-clk";
54 clk_gates1: gate-clk@200000d4 {
55 compatible = "rockchip,rk2928-gate-clk";
Daltr_socfpga.txt12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register
24 - div-reg : For "socfpga-gate-clk" and "socfpga-periph-clock", div-reg contains
Dgpio-gate-clock.txt8 - compatible : shall be "gpio-gate-clock".
17 compatible = "gpio-gate-clock";
Dkeystone-gate.txt3 Binding for Keystone gate control driver which uses PSC controller IP.
Dalphascale,acc.txt19 _AHB_ - AHB gate;
Dst,nomadik.txt35 lines from the HCLK clock tree and the gate for individual
Demev2-clock.txt29 Registers are "xxx clock gate control register" (XXXGCLKCTRL).
Dmvebu-gated-clock.txt190 /* get clk gate bit 8 (sdio0) */
Dsunxi.txt102 offset of the bit controlling this particular gate in the register.
/linux-4.4.14/drivers/clk/shmobile/
Dclk-rcar-gen2.c171 struct clk_gate *gate; in cpg_rcan_clk_register() local
181 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in cpg_rcan_clk_register()
182 if (!gate) { in cpg_rcan_clk_register()
187 gate->reg = cpg->reg + CPG_RCANCKCR; in cpg_rcan_clk_register()
188 gate->bit_idx = 8; in cpg_rcan_clk_register()
189 gate->flags = CLK_GATE_SET_TO_DISABLE; in cpg_rcan_clk_register()
190 gate->lock = &cpg->lock; in cpg_rcan_clk_register()
194 &gate->hw, &clk_gate_ops, 0); in cpg_rcan_clk_register()
196 kfree(gate); in cpg_rcan_clk_register()
214 struct clk_gate *gate; in cpg_adsp_clk_register() local
[all …]
/linux-4.4.14/drivers/clk/rockchip/
Dclk.c51 struct clk_gate *gate = NULL; in rockchip_clk_register_branch() local
71 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in rockchip_clk_register_branch()
72 if (!gate) in rockchip_clk_register_branch()
75 gate->flags = gate_flags; in rockchip_clk_register_branch()
76 gate->reg = base + gate_offset; in rockchip_clk_register_branch()
77 gate->bit_idx = gate_shift; in rockchip_clk_register_branch()
78 gate->lock = lock; in rockchip_clk_register_branch()
101 gate ? &gate->hw : NULL, gate_ops, in rockchip_clk_register_branch()
106 kfree(gate); in rockchip_clk_register_branch()
119 struct clk_gate *gate = NULL; in rockchip_clk_register_frac_branch() local
[all …]
/linux-4.4.14/net/nfc/hci/
Dcommand.c103 int nfc_hci_send_event(struct nfc_hci_dev *hdev, u8 gate, u8 event, in nfc_hci_send_event() argument
108 pr_debug("%d to gate %d\n", event, gate); in nfc_hci_send_event()
110 pipe = hdev->gate2pipe[gate]; in nfc_hci_send_event()
124 int nfc_hci_send_cmd(struct nfc_hci_dev *hdev, u8 gate, u8 cmd, in nfc_hci_send_cmd() argument
131 pipe = hdev->gate2pipe[gate]; in nfc_hci_send_cmd()
139 int nfc_hci_send_cmd_async(struct nfc_hci_dev *hdev, u8 gate, u8 cmd, in nfc_hci_send_cmd_async() argument
147 pipe = hdev->gate2pipe[gate]; in nfc_hci_send_cmd_async()
156 int nfc_hci_set_param(struct nfc_hci_dev *hdev, u8 gate, u8 idx, in nfc_hci_set_param() argument
170 pr_debug("idx=%d to gate %d\n", idx, gate); in nfc_hci_set_param()
179 r = nfc_hci_send_cmd(hdev, gate, NFC_HCI_ANY_SET_PARAMETER, in nfc_hci_set_param()
[all …]
Dcore.c54 hdev->pipes[i].gate = NFC_HCI_INVALID_GATE; in nfc_hci_reset_pipes()
69 hdev->pipes[i].gate = NFC_HCI_INVALID_GATE; in nfc_hci_reset_pipes_per_host()
196 u8 gate = hdev->pipes[pipe].gate; in nfc_hci_cmd_received() local
202 pr_debug("from gate %x pipe %x cmd %x\n", gate, pipe, cmd); in nfc_hci_cmd_received()
218 hdev->pipes[create_info->pipe].gate = create_info->dest_gate; in nfc_hci_cmd_received()
223 if (gate == NFC_HCI_INVALID_GATE) { in nfc_hci_cmd_received()
235 hdev->pipes[delete_info->pipe].gate = NFC_HCI_INVALID_GATE; in nfc_hci_cmd_received()
248 pr_info("Discarded unknown cmd %x to gate %x\n", cmd, gate); in nfc_hci_cmd_received()
279 int nfc_hci_target_discovered(struct nfc_hci_dev *hdev, u8 gate) in nfc_hci_target_discovered() argument
287 pr_debug("from gate %d\n", gate); in nfc_hci_target_discovered()
[all …]
Dhci.h24 u8 gate; member
/linux-4.4.14/drivers/clk/meson/
Dclkc.c56 struct clk_gate *gate = NULL; in meson_clk_register_composite() local
95 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in meson_clk_register_composite()
96 if (!gate) { in meson_clk_register_composite()
101 gate->reg = clk_base + clk_conf->reg_off in meson_clk_register_composite()
103 gate->bit_idx = composite_conf->gate_parm.shift; in meson_clk_register_composite()
104 gate->flags = composite_conf->gate_flags; in meson_clk_register_composite()
105 gate->lock = &clk_lock; in meson_clk_register_composite()
113 gate ? &gate->hw : NULL, &clk_gate_ops, in meson_clk_register_composite()
121 kfree(gate); in meson_clk_register_composite()
/linux-4.4.14/include/net/nfc/
Dhci.h44 int (*target_from_gate) (struct nfc_hci_dev *hdev, u8 gate,
46 int (*complete_target_discovered) (struct nfc_hci_dev *hdev, u8 gate,
76 u8 gate; member
81 u8 gate; member
271 int nfc_hci_disconnect_gate(struct nfc_hci_dev *hdev, u8 gate);
273 int nfc_hci_get_param(struct nfc_hci_dev *hdev, u8 gate, u8 idx,
275 int nfc_hci_set_param(struct nfc_hci_dev *hdev, u8 gate, u8 idx,
277 int nfc_hci_send_cmd(struct nfc_hci_dev *hdev, u8 gate, u8 cmd,
279 int nfc_hci_send_cmd_async(struct nfc_hci_dev *hdev, u8 gate, u8 cmd,
282 int nfc_hci_send_event(struct nfc_hci_dev *hdev, u8 gate, u8 event,
[all …]
Dnci_core.h166 u8 gate; member
172 u8 gate; member
303 int nci_hci_send_event(struct nci_dev *ndev, u8 gate, u8 event,
305 int nci_hci_send_cmd(struct nci_dev *ndev, u8 gate,
311 int nci_hci_set_param(struct nci_dev *ndev, u8 gate, u8 idx,
313 int nci_hci_get_param(struct nci_dev *ndev, u8 gate, u8 idx,
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt48 * "usb_host_hs_utmi_p1_clk" - Port 1 UTMI clock gate.
49 * "usb_host_hs_utmi_p2_clk" - Port 2 UTMI clock gate.
50 * "usb_host_hs_utmi_p3_clk" - Port 3 UTMI clock gate.
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/linux-4.4.14/net/nfc/nci/
Dhci.c127 hdev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes()
139 ndev->hci_dev->pipes[i].gate = NCI_HCI_INVALID_GATE; in nci_hci_reset_pipes_per_host()
220 int nci_hci_send_event(struct nci_dev *ndev, u8 gate, u8 event, in nci_hci_send_event() argument
223 u8 pipe = ndev->hci_dev->gate2pipe[gate]; in nci_hci_send_event()
234 int nci_hci_send_cmd(struct nci_dev *ndev, u8 gate, u8 cmd, in nci_hci_send_cmd() argument
242 u8 pipe = ndev->hci_dev->gate2pipe[gate]; in nci_hci_send_cmd()
297 u8 gate = ndev->hci_dev->pipes[pipe].gate; in nci_hci_cmd_received() local
304 pr_debug("from gate %x pipe %x cmd %x\n", gate, pipe, cmd); in nci_hci_cmd_received()
322 ndev->hci_dev->pipes[new_pipe].gate = dest_gate; in nci_hci_cmd_received()
328 if (gate == NCI_HCI_INVALID_GATE) { in nci_hci_cmd_received()
[all …]
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos-clkout.c29 struct clk_gate gate; member
93 clkout->gate.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG; in exynos_clkout_init()
94 clkout->gate.bit_idx = EXYNOS_CLKOUT_DISABLE_SHIFT; in exynos_clkout_init()
95 clkout->gate.flags = CLK_GATE_SET_TO_DISABLE; in exynos_clkout_init()
96 clkout->gate.lock = &clkout->slock; in exynos_clkout_init()
105 &clk_mux_ops, NULL, NULL, &clkout->gate.hw, in exynos_clkout_init()
/linux-4.4.14/drivers/clk/nxp/
Dclk-lpc18xx-ccu.c44 struct clk_gate gate; member
140 struct clk_gate *gate = to_clk_gate(hw); in lpc18xx_ccu_gate_endisable() local
147 val = clk_readl(gate->reg); in lpc18xx_ccu_gate_endisable()
160 clk_writel(val, gate->reg); in lpc18xx_ccu_gate_endisable()
165 clk_writel(val, gate->reg); in lpc18xx_ccu_gate_endisable()
228 branch->gate.reg = branch->offset + reg_base; in lpc18xx_ccu_register_branch_gate_div()
229 branch->gate.bit_idx = 0; in lpc18xx_ccu_register_branch_gate_div()
234 &branch->gate.hw, &lpc18xx_ccu_gate_ops, 0); in lpc18xx_ccu_register_branch_gate_div()
Dclk-lpc18xx-cgu.c168 struct clk_gate gate; member
184 .gate = { \
202 struct clk_gate gate; member
215 .gate = { \
266 struct clk_gate gate; member
281 .gate = { \
542 clk->gate.reg = reg; in lpc18xx_cgu_register_div()
549 &clk->gate.hw, &lpc18xx_gate_ops, 0); in lpc18xx_cgu_register_div()
564 clk->gate.reg = reg; in lpc18xx_register_base_clk()
577 &clk->gate.hw, &lpc18xx_gate_ops, 0); in lpc18xx_register_base_clk()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/input/touchscreen/
Dcolibri-vf50-ts.txt6 - xp-gpios: FET gate driver for input of X+
7 - xm-gpios: FET gate driver for input of X-
8 - yp-gpios: FET gate driver for input of Y+
9 - ym-gpios: FET gate driver for input of Y-
15 - pinctrl-2: pinctrl node for gpios functioning as FET gate drivers
/linux-4.4.14/drivers/clk/pxa/
Dclk-pxa.c33 struct clk_gate gate; member
91 pxa_clk->gate = clks[i].gate; in clk_pxa_cken_init()
92 pxa_clk->gate.lock = &lock; in clk_pxa_cken_init()
97 &pxa_clk->gate.hw, &clk_gate_ops, in clk_pxa_cken_init()
Dclk-pxa.h78 struct clk_gate gate; member
90 .gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
/linux-4.4.14/drivers/clk/pistachio/
Dclk.c61 struct pistachio_gate *gate, in pistachio_clk_register_gate() argument
68 clk = clk_register_gate(NULL, gate[i].name, gate[i].parent, in pistachio_clk_register_gate()
70 p->base + gate[i].reg, gate[i].shift, in pistachio_clk_register_gate()
72 p->clk_data.clks[gate[i].id] = clk; in pistachio_clk_register_gate()
Dclk.h155 struct pistachio_gate *gate,
/linux-4.4.14/net/mac80211/
Dmesh_pathtbl.c129 struct mpath_node *gate; in mesh_table_free() local
143 hlist_for_each_entry_safe(gate, q, in mesh_table_free()
145 hlist_del(&gate->list); in mesh_table_free()
146 kfree(gate); in mesh_table_free()
447 struct mpath_node *gate, *new_gate; in mesh_path_add_gate() local
453 hlist_for_each_entry_rcu(gate, tbl->known_gates, list) in mesh_path_add_gate()
454 if (gate->mpath == mpath) { in mesh_path_add_gate()
489 struct mpath_node *gate; in mesh_gate_del() local
492 hlist_for_each_entry_safe(gate, q, tbl->known_gates, list) { in mesh_gate_del()
493 if (gate->mpath != mpath) in mesh_gate_del()
[all …]
/linux-4.4.14/drivers/staging/comedi/drivers/
Dni_tio.c994 static unsigned ni_660x_gate_to_generic_gate(unsigned gate) in ni_660x_gate_to_generic_gate() argument
998 switch (gate) { in ni_660x_gate_to_generic_gate()
1011 if (gate == NI_660X_RTSI_GATE_SEL(i)) in ni_660x_gate_to_generic_gate()
1015 if (gate == NI_660X_PIN_GATE_SEL(i)) in ni_660x_gate_to_generic_gate()
1024 static unsigned ni_m_gate_to_generic_gate(unsigned gate) in ni_m_gate_to_generic_gate() argument
1028 switch (gate) { in ni_m_gate_to_generic_gate()
1047 if (gate == NI_M_RTSI_GATE_SEL(i)) in ni_m_gate_to_generic_gate()
1051 if (gate == NI_M_PFI_GATE_SEL(i)) in ni_m_gate_to_generic_gate()
1060 static unsigned ni_660x_gate2_to_generic_gate(unsigned gate) in ni_660x_gate2_to_generic_gate() argument
1064 switch (gate) { in ni_660x_gate2_to_generic_gate()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt13 <&cru SCLK_MAC_RX>: clock gate for RX
14 <&cru SCLK_MAC_TX>: clock gate for TX
15 <&cru SCLK_MACREF>: clock gate for RMII referce clock
16 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
17 <&cru ACLK_GMAC>: AXI clock gate for GMAC
18 <&cru PCLK_GMAC>: APB clock gate for GMAC
Dmarvell-orion-mdio.txt14 - clocks: Phandle to the clock control device and gate bit
/linux-4.4.14/drivers/nfc/microread/
Dmicroread.c346 static int microread_target_from_gate(struct nfc_hci_dev *hdev, u8 gate, in microread_target_from_gate() argument
349 switch (gate) { in microread_target_from_gate()
361 u8 gate, in microread_complete_target_discovered() argument
481 static void microread_target_discovered(struct nfc_hci_dev *hdev, u8 gate, in microread_target_discovered() argument
487 pr_info("target discovered to gate 0x%x\n", gate); in microread_target_discovered()
495 targets->hci_reader_gate = gate; in microread_target_discovered()
497 switch (gate) { in microread_target_discovered()
544 pr_info("discard target discovered to gate 0x%x\n", gate); in microread_target_discovered()
564 u8 gate = hdev->pipes[pipe].gate; in microread_event_received() local
567 pr_info("Microread received event 0x%x to gate 0x%x\n", event, gate); in microread_event_received()
[all …]
/linux-4.4.14/drivers/nfc/st21nfca/
Dcore.c187 (st21nfca_gates[j].gate != info->dst_gate_id) ; j++) in st21nfca_hci_load_session()
191 st21nfca_gates[j].gate == info->dst_gate_id && in st21nfca_hci_load_session()
195 hdev->gate2pipe[st21nfca_gates[j].gate] = in st21nfca_hci_load_session()
197 hdev->pipes[pipe_info[2]].gate = in st21nfca_hci_load_session()
198 st21nfca_gates[j].gate; in st21nfca_hci_load_session()
635 static int st21nfca_hci_target_from_gate(struct nfc_hci_dev *hdev, u8 gate, in st21nfca_hci_target_from_gate() argument
643 switch (gate) { in st21nfca_hci_target_from_gate()
690 u8 gate, in st21nfca_hci_complete_target_discovered() argument
696 if (gate == ST21NFCA_RF_READER_F_GATE) { in st21nfca_hci_complete_target_discovered()
855 u8 gate = hdev->pipes[pipe].gate; in st21nfca_hci_cmd_received() local
[all …]
Dvendor_cmds.c42 u8 gate; member
205 r = nfc_hci_get_param(hdev, param->gate, param->data, &skb); in st21nfca_hci_get_param()
/linux-4.4.14/drivers/clk/st/
Dclkgen-mux.c745 struct clk_gate *gate; in st_of_clkgen_vcc_setup() local
759 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in st_of_clkgen_vcc_setup()
760 if (!gate) in st_of_clkgen_vcc_setup()
765 kfree(gate); in st_of_clkgen_vcc_setup()
771 kfree(gate); in st_of_clkgen_vcc_setup()
776 gate->reg = reg + VCC_GATE_OFFSET; in st_of_clkgen_vcc_setup()
777 gate->bit_idx = i; in st_of_clkgen_vcc_setup()
778 gate->flags = CLK_GATE_SET_TO_DISABLE; in st_of_clkgen_vcc_setup()
779 gate->lock = data->lock; in st_of_clkgen_vcc_setup()
795 &gate->hw, &clk_gate_ops, in st_of_clkgen_vcc_setup()
[all …]
Dclkgen-pll.c1004 struct clk_gate *gate; in clkgen_odf_register() local
1009 gate = kzalloc(sizeof(*gate), GFP_KERNEL); in clkgen_odf_register()
1010 if (!gate) in clkgen_odf_register()
1013 gate->flags = CLK_GATE_SET_TO_DISABLE; in clkgen_odf_register()
1014 gate->reg = reg + pll_data->odf_gate[odf].offset; in clkgen_odf_register()
1015 gate->bit_idx = pll_data->odf_gate[odf].shift; in clkgen_odf_register()
1016 gate->lock = odf_lock; in clkgen_odf_register()
1020 kfree(gate); in clkgen_odf_register()
1033 &gate->hw, &clk_gate_ops, in clkgen_odf_register()
/linux-4.4.14/drivers/clk/socfpga/
DMakefile2 obj-y += clk-gate.o
5 obj-y += clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
/linux-4.4.14/drivers/nfc/st-nci/
Dse.c233 (st_nci_gates[j].gate != dm_pipe_info->dst_gate_id); j++) in st_nci_hci_load_session()
237 st_nci_gates[j].gate == dm_pipe_info->dst_gate_id && in st_nci_hci_load_session()
241 ndev->hci_dev->gate2pipe[st_nci_gates[j].gate] = in st_nci_hci_load_session()
243 ndev->hci_dev->pipes[pipe_info[2]].gate = in st_nci_hci_load_session()
244 st_nci_gates[j].gate; in st_nci_hci_load_session()
375 u8 gate = ndev->hci_dev->pipes[pipe].gate; in st_nci_hci_event_received() local
378 switch (gate) { in st_nci_hci_event_received()
400 u8 gate = ndev->hci_dev->pipes[pipe].gate; in st_nci_hci_cmd_received() local
406 if (gate != ST_NCI_APDU_READER_GATE && in st_nci_hci_cmd_received()
Dvendor_cmds.c46 u8 gate; member
228 r = nci_hci_get_param(ndev, param->gate, param->data, &skb); in st_nci_hci_get_param()
/linux-4.4.14/drivers/nfc/pn544/
Dpn544.c492 static int pn544_hci_target_from_gate(struct nfc_hci_dev *hdev, u8 gate, in pn544_hci_target_from_gate() argument
495 switch (gate) { in pn544_hci_target_from_gate()
514 u8 gate, in pn544_hci_complete_target_discovered() argument
520 if (gate == PN544_RF_READER_NFCIP1_INITIATOR_GATE) in pn544_hci_complete_target_discovered()
731 u8 gate = hdev->pipes[pipe].gate; in pn544_hci_event_received() local
737 if (gate == PN544_RF_READER_NFCIP1_INITIATOR_GATE) { in pn544_hci_event_received()
738 r = nfc_hci_target_discovered(hdev, gate); in pn544_hci_event_received()
739 } else if (gate == PN544_RF_READER_NFCIP1_TARGET_GATE) { in pn544_hci_event_received()
740 r = nfc_hci_get_param(hdev, gate, PN544_DEP_ATR_REQ, in pn544_hci_event_received()
755 r = nfc_hci_send_event(hdev, gate, NFC_HCI_EVT_END_OPERATION, in pn544_hci_event_received()
/linux-4.4.14/arch/mips/include/asm/octeon/
Dcvmx-rst-defs.h255 uint64_t gate:48; member
257 uint64_t gate:48;
264 uint64_t gate:4; member
266 uint64_t gate:4;
/linux-4.4.14/drivers/mfd/
Dsm501.c320 unsigned long gate; in sm501_unit_power() local
326 gate = smc501_readl(sm->regs + SM501_CURRENT_GATE); in sm501_unit_power()
348 if (gate & (1 << unit)) in sm501_unit_power()
350 gate |= (1 << unit); in sm501_unit_power()
352 if (!(gate & (1 << unit))) in sm501_unit_power()
354 gate &= ~(1 << unit); in sm501_unit_power()
359 smc501_writel(gate, sm->regs + SM501_POWER_MODE_0_GATE); in sm501_unit_power()
365 smc501_writel(gate, sm->regs + SM501_POWER_MODE_1_GATE); in sm501_unit_power()
371 gate = -1; in sm501_unit_power()
379 gate, clock, mode); in sm501_unit_power()
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/iommu/
Dsamsung,sysmmu.txt42 - clock-names: Should be "sysmmu" if the System MMU is needed to gate its clock.
44 another gate clock other than "sysmmu".
47 - clocks: Required if the System MMU is needed to gate its clock.
48 - power-domains: Required if the System MMU is needed to gate its power.
/linux-4.4.14/drivers/gpu/drm/radeon/
Dkv_dpm.c56 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
57 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
58 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
59 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
1423 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate) in kv_update_uvd_dpm() argument
1431 if (!gate) { in kv_update_uvd_dpm()
1456 return kv_enable_uvd_dpm(rdev, !gate); in kv_update_uvd_dpm()
1516 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate) in kv_update_samu_dpm() argument
1523 if (!gate) { in kv_update_samu_dpm()
1544 return kv_enable_samu_dpm(rdev, !gate); in kv_update_samu_dpm()
[all …]
Dci_dpm.c185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
761 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate) in ci_dpm_powergate_uvd() argument
765 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
768 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
770 ci_update_uvd_dpm(rdev, gate); in ci_dpm_powergate_uvd()
4044 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate) in ci_update_uvd_dpm() argument
4049 if (!gate) { in ci_update_uvd_dpm()
4063 return ci_enable_uvd_dpm(rdev, !gate); in ci_update_uvd_dpm()
4112 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4114 return ci_enable_samu_dpm(rdev, gate);
[all …]
Dradeon_asic.h892 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
921 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
Dradeon.h1988 void (*powergate_uvd)(struct radeon_device *rdev, bool gate);
/linux-4.4.14/drivers/media/tuners/
Dtda18271-common.c26 enum tda18271_i2c_gate gate; in tda18271_i2c_gate_ctrl() local
29 switch (priv->gate) { in tda18271_i2c_gate_ctrl()
32 gate = priv->gate; in tda18271_i2c_gate_ctrl()
38 gate = TDA18271_GATE_DIGITAL; in tda18271_i2c_gate_ctrl()
42 gate = TDA18271_GATE_ANALOG; in tda18271_i2c_gate_ctrl()
47 switch (gate) { in tda18271_i2c_gate_ctrl()
Dtda18271.h97 enum tda18271_i2c_gate gate; member
Dtda18271-fe.c1205 priv->gate = (cfg) ? cfg->gate : TDA18271_GATE_AUTO; in tda18271_setup_configuration()
1316 if (cfg->gate != TDA18271_GATE_ANALOG) in tda18271_attach()
1317 priv->gate = cfg->gate; in tda18271_attach()
Dtda18271-priv.h109 enum tda18271_i2c_gate gate; member
Dtda8290.c575 .gate = TDA18271_GATE_ANALOG,
/linux-4.4.14/drivers/media/platform/s5p-g2d/
Dg2d.c509 clk_enable(dev->gate); in device_run()
544 clk_disable(dev->gate); in g2d_isr()
655 dev->gate = clk_get(&pdev->dev, "fimg2d"); in g2d_probe()
656 if (IS_ERR(dev->gate)) { in g2d_probe()
662 ret = clk_prepare(dev->gate); in g2d_probe()
744 clk_unprepare(dev->gate); in g2d_probe()
746 clk_put(dev->gate); in g2d_probe()
764 clk_unprepare(dev->gate); in g2d_remove()
765 clk_put(dev->gate); in g2d_remove()
Dg2d.h31 struct clk *gate; member
/linux-4.4.14/Documentation/
Dclk.txt97 drivers/clk/clk-gate.c:
126 [resolves struct clk gate with to_clk_gate(hw)]
127 clk_gate_set_bit(gate);
131 static void clk_gate_set_bit(struct clk_gate *gate)
135 reg = __raw_readl(gate->reg);
136 reg |= BIT(gate->bit_idx);
137 writel(reg, gate->reg);
197 | gate | change rate | single parent | multiplexer | root |
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dkv_dpm.c67 static void kv_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
68 static void kv_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
69 static void kv_dpm_powergate_samu(struct amdgpu_device *adev, bool gate);
70 static void kv_dpm_powergate_acp(struct amdgpu_device *adev, bool gate);
1493 static int kv_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in kv_update_uvd_dpm() argument
1501 if (!gate) { in kv_update_uvd_dpm()
1526 return kv_enable_uvd_dpm(adev, !gate); in kv_update_uvd_dpm()
1592 static int kv_update_samu_dpm(struct amdgpu_device *adev, bool gate) in kv_update_samu_dpm() argument
1599 if (!gate) { in kv_update_samu_dpm()
1620 return kv_enable_samu_dpm(adev, !gate); in kv_update_samu_dpm()
[all …]
Dcz_dpm.c45 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate);
46 static void cz_dpm_powergate_vce(struct amdgpu_device *adev, bool gate);
1825 static int cz_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in cz_update_uvd_dpm() argument
1827 return cz_enable_uvd_dpm(adev, !gate); in cz_update_uvd_dpm()
1831 static void cz_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) in cz_dpm_powergate_uvd() argument
1836 if (pi->uvd_power_gated == gate) in cz_dpm_powergate_uvd()
1839 pi->uvd_power_gated = gate; in cz_dpm_powergate_uvd()
1841 if (gate) { in cz_dpm_powergate_uvd()
1851 cz_update_uvd_dpm(adev, gate); in cz_dpm_powergate_uvd()
1870 cz_update_uvd_dpm(adev, gate); in cz_dpm_powergate_uvd()
[all …]
Dgmc_v7_0.c1349 bool gate = false; in gmc_v7_0_set_clockgating_state() local
1353 gate = true; in gmc_v7_0_set_clockgating_state()
1356 gmc_v7_0_enable_mc_mgcg(adev, gate); in gmc_v7_0_set_clockgating_state()
1357 gmc_v7_0_enable_mc_ls(adev, gate); in gmc_v7_0_set_clockgating_state()
1359 gmc_v7_0_enable_bif_mgls(adev, gate); in gmc_v7_0_set_clockgating_state()
1360 gmc_v7_0_enable_hdp_mgcg(adev, gate); in gmc_v7_0_set_clockgating_state()
1361 gmc_v7_0_enable_hdp_ls(adev, gate); in gmc_v7_0_set_clockgating_state()
Dvce_v2_0.c588 bool gate = false; in vce_v2_0_set_clockgating_state() local
592 gate = true; in vce_v2_0_set_clockgating_state()
594 vce_v2_0_enable_mgcg(adev, gate); in vce_v2_0_set_clockgating_state()
Duvd_v4_2.c830 bool gate = false; in uvd_v4_2_set_clockgating_state() local
834 gate = true; in uvd_v4_2_set_clockgating_state()
836 uvd_v4_2_enable_mgcg(adev, gate); in uvd_v4_2_set_clockgating_state()
Dcik_sdma.c1258 bool gate = false; in cik_sdma_set_clockgating_state() local
1262 gate = true; in cik_sdma_set_clockgating_state()
1264 cik_enable_sdma_mgcg(adev, gate); in cik_sdma_set_clockgating_state()
1265 cik_enable_sdma_mgls(adev, gate); in cik_sdma_set_clockgating_state()
Dci_dpm.c302 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate);
879 static void ci_dpm_powergate_uvd(struct amdgpu_device *adev, bool gate) in ci_dpm_powergate_uvd() argument
883 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
886 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
888 ci_update_uvd_dpm(adev, gate); in ci_dpm_powergate_uvd()
4182 static int ci_update_uvd_dpm(struct amdgpu_device *adev, bool gate) in ci_update_uvd_dpm() argument
4187 if (!gate) { in ci_update_uvd_dpm()
4201 return ci_enable_uvd_dpm(adev, !gate); in ci_update_uvd_dpm()
4256 static int ci_update_samu_dpm(struct amdgpu_device *adev, bool gate)
4258 return ci_enable_samu_dpm(adev, gate);
[all …]
Dgfx_v7_0.c5496 bool gate = false; in gfx_v7_0_set_clockgating_state() local
5500 gate = true; in gfx_v7_0_set_clockgating_state()
5504 if (gate) { in gfx_v7_0_set_clockgating_state()
5519 bool gate = false; in gfx_v7_0_set_powergating_state() local
5523 gate = true; in gfx_v7_0_set_powergating_state()
5531 gfx_v7_0_update_gfx_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5533 gfx_v7_0_enable_cp_pg(adev, gate); in gfx_v7_0_set_powergating_state()
5534 gfx_v7_0_enable_gds_pg(adev, gate); in gfx_v7_0_set_powergating_state()
Damdgpu.h1584 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
1585 void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
/linux-4.4.14/arch/um/os-Linux/drivers/
Dethertap_user.c91 static int etap_tramp(char *dev, char *gate, int control_me, in etap_tramp() argument
107 if (gate != NULL) { in etap_tramp()
108 strncpy(gate_buf, gate, 15); in etap_tramp()
Dtuntap_user.c62 static int tuntap_open_tramp(char *gate, int *fd_out, int me, int remote, in tuntap_open_tramp() argument
67 char *argv[] = { "uml_net", version_buf, "tuntap", "up", gate, in tuntap_open_tramp()
/linux-4.4.14/Documentation/arm/sunxi/
Dclocks.txt12 steps, one can gate it and keep the system running. Consider this
36 Finally you can gate the main oscillator
/linux-4.4.14/drivers/clk/keystone/
DMakefile1 obj-y += pll.o gate.o
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi-mt65xx.txt26 The third is <&pericfg CLK_PERI_SPI0>. It's clock gate.
29 muxes clock, and "spi-clk" for the clock gate.
Dbrcm,bcm2835-aux-spi.txt13 as this clock will enable the output gate for the specific
/linux-4.4.14/include/media/
Dvideobuf2-dvb.h46 int gate; /* Frontend with gate control 0=!MFE,1=fe0,2=fe1 etc */ member
Dvideobuf-dvb.h40 int gate; /* Frontend with gate control 0=!MFE,1=fe0,2=fe1 etc */ member
/linux-4.4.14/Documentation/nfc/
Dnfc-hci.txt44 A gate defines the 'port' where some service can be found. In order to access
45 a service, one must create a pipe to that gate and open it. In this
73 int (*target_from_gate) (struct nfc_hci_dev *hdev, u8 gate,
75 int (*complete_target_discovered) (struct nfc_hci_dev *hdev, u8 gate,
83 int (*event_received)(struct nfc_hci_dev *hdev, u8 gate, u8 event,
100 corresponding to a proprietary gate.
209 int nfc_hci_send_cmd (struct nfc_hci_dev *hdev, u8 gate, u8 cmd,
254 ANY_GET_PARAMETER to the reader A gate to get information on the target
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dexynos-jpeg-codec.txt12 - "jpeg" for the core gate clock,
Dexynos-fimc-lite.txt12 - clocks : FIMC LITE gate clock should be specified in this property.
Dexynos4-fimc-is.txt40 - clocks : must contain gate clock specifier for this controller;
/linux-4.4.14/Documentation/ia64/
Dfsys.txt209 such that execution resumes in the gate page at
220 PSR.is Unchanged (guaranteed to be 0 on entry to the gate page).
228 state such that execution resumes in the gate page at
255 mov r2 = 0xa000000000020660;; // gate address
274 In reality, getting the gate address is accomplished by two extra
278 o AT_SYSINFO_EHDR : is the address of the kernel gate ELF DSO
281 the gate page. It is a proper ELF shared object so, with a dynamic
/linux-4.4.14/arch/x86/kvm/
Di8254.h20 u8 gate; /* timer start */ member
Di8254.c92 if (c->gate < val) in pit_set_gate()
97 c->gate = val; in pit_set_gate()
104 return kvm->arch.vpit->pit_state.channels[channel].gate; in pit_get_gate()
652 c->gate = (i != 2); in kvm_pit_reset()
/linux-4.4.14/Documentation/devicetree/bindings/serio/
Dallwinner,sun4i-ps2.txt13 - clocks : The gate clk connected to the PS2.
/linux-4.4.14/Documentation/devicetree/bindings/phy/
Dkeystone-usb-phy.txt10 gate on the Keystone SOC for both the USB2 and USB3 PHY. Otherwise it is just
Dsamsung-phy.txt43 - the "phy" clock is required by the phy module, used as a gate
147 gate clocks available:
/linux-4.4.14/drivers/clk/mvebu/
Dcommon.c215 struct clk_gate *gate = in clk_gating_get_src() local
217 if (clkspec->args[0] == gate->bit_idx) in clk_gating_get_src()
/linux-4.4.14/Documentation/devicetree/bindings/arm/ux500/
Dpower_domain.txt3 UX500 supports multiple PM domains which are used to gate power to one or
/linux-4.4.14/arch/sh/kernel/vsyscall/
DMakefile17 vsyscall-flags = -shared -s -Wl,-soname=linux-gate.so.1 \
/linux-4.4.14/Documentation/devicetree/bindings/usb/
Dallwinner,sun4i-a10-musb.txt8 - clocks : clock specifier for the musb controller ahb gate clock
/linux-4.4.14/Documentation/devicetree/bindings/i2c/
Di2c-sunxi-p2wi.txt10 - clocks : The gate clk connected to the P2WI peripheral.
/linux-4.4.14/Documentation/devicetree/bindings/display/imx/
Dldb.txt25 "di0" - LDB LVDS channel 0 gate
26 "di1" - LDB LVDS channel 1 gate
/linux-4.4.14/drivers/media/usb/dvb-usb-v2/
Dlmedm04.c540 u8 gate = st->i2c_gate; in lme2510_i2c_xfer() local
544 if (gate == 0) in lme2510_i2c_xfer()
545 gate = 5; in lme2510_i2c_xfer()
551 gate = (msg[i].addr == st->i2c_tuner_addr) in lme2510_i2c_xfer()
555 obuf[0] = gate | (read << 7); in lme2510_i2c_xfer()
557 if (gate == 5) in lme2510_i2c_xfer()
Daf9015.c884 .gate = TDA18271_GATE_DIGITAL,
/linux-4.4.14/Documentation/devicetree/bindings/bus/
Dsunxi-rsb.txt12 - clocks : The gate clk associated to the RSB controller.
/linux-4.4.14/Documentation/virtual/kvm/
Dtimekeeping.txt52 has a connected gate input, required for modes 1 and 5. The gate line is
81 when the gate is high (always true for timers 0 and 1). When the count
84 Mode 1: Triggered One-shot. The output is initially set high. When the gate
85 line is set high, a countdown is initiated (which does not stop if the gate is
91 is reloaded and the countdown automatically resumes. If the gate line goes
92 low, the count is halted. If the output is low when the gate is lowered, the
97 when zero is reached. The count only proceeds when gate is high and is
109 Counting only occurs when gate is high.
112 output remains high. When the gate is raised, a countdown is initiated
113 (which does not stop if the gate is lowered). When the counter reaches zero,
/linux-4.4.14/drivers/media/usb/pvrusb2/
Dpvrusb2-devattr.c336 .gate = TDA18271_GATE_ANALOG,
434 .gate = TDA18271_GATE_ANALOG,
/linux-4.4.14/Documentation/devicetree/bindings/clock/st/
Dst,flexgen.txt6 - a pre and final dividers (represented by a divider and gate elements)
/linux-4.4.14/Documentation/devicetree/bindings/power/
Dpd-samsung.txt4 to gate power to one or more peripherals on the processor.
/linux-4.4.14/arch/parisc/kernel/
Dsyscall.S80 gate lws_start, %r0 /* increase privilege */
91 gate .+8, %r0 /* increase privilege */
105 gate .+8, %r0 /* become privileged */
/linux-4.4.14/drivers/media/pci/cx23885/
Dcx23885-dvb.c149 if (f->gate <= 1) /* undefined or fe0 */ in cx23885_dvb_gate_ctrl()
152 fe = vb2_dvb_get_frontend(f, f->gate); in cx23885_dvb_gate_ctrl()
330 .gate = TDA18271_GATE_ANALOG,
336 .gate = TDA18271_GATE_ANALOG,
341 .gate = TDA18271_GATE_DIGITAL,
346 .gate = TDA18271_GATE_DIGITAL,
1207 port->frontends.gate = 0; in dvb_register()
1706 port->frontends.gate = 0;/* not clear for me yet */ in dvb_register()
/linux-4.4.14/Documentation/gpio/
Ddrivers-on-gpio.txt48 - gpio-gate-clock: drivers/clk/clk-gpio-gate.c is used to control a gated clock
/linux-4.4.14/drivers/media/usb/cx231xx/
Dcx231xx-dvb.c96 .gate = TDA18271_GATE_ANALOG,
138 .gate = TDA18271_GATE_DIGITAL,
148 .gate = TDA18271_GATE_DIGITAL,
/linux-4.4.14/drivers/media/pci/saa7134/
Dsaa7134-dvb.c231 .gate = TDA18271_GATE_DIGITAL,
1108 .gate = TDA18271_GATE_ANALOG,
1130 .gate = TDA18271_GATE_ANALOG,
1156 .gate = TDA18271_GATE_ANALOG,
1175 .gate = TDA18271_GATE_ANALOG,
1188 .gate = TDA18271_GATE_ANALOG,
/linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm7120-l2-intc.txt74 have a mux gate, typically UARTs. Setting these bits will make their
/linux-4.4.14/drivers/media/pci/cx88/
Dcx88-dvb.c215 if (f->gate <= 1) /* undefined or fe0 */ in cx88_dvb_gate_ctrl()
218 fe = vb2_dvb_get_frontend(f, f->gate); in cx88_dvb_gate_ctrl()
1023 dev->frontends.gate = 0; in dvb_register()
1083 dev->frontends.gate = 2; in dvb_register()
1452 dev->frontends.gate = 2; in dvb_register()
/linux-4.4.14/arch/x86/include/uapi/asm/
Dkvm.h243 __u8 gate; member
/linux-4.4.14/arch/x86/entry/vdso/
DMakefile124 VDSO_LDFLAGS_vdso32.lds = -m32 -Wl,-m,elf_i386 -Wl,-soname=linux-gate.so.1
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Dsamsung-i2s.txt44 CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock,
/linux-4.4.14/arch/arm/common/
Dmcpm_head.S193 @ Observability order of CPU_UP and opening of the gate does not matter.
/linux-4.4.14/drivers/media/pci/saa7164/
Dsaa7164-dvb.c66 .gate = TDA18271_GATE_ANALOG,
72 .gate = TDA18271_GATE_ANALOG,
/linux-4.4.14/drivers/media/usb/em28xx/
Dem28xx-dvb.c370 .gate = TDA18271_GATE_DIGITAL,
808 .gate = TDA18271_GATE_DIGITAL,
834 .gate = TDA18271_GATE_DIGITAL,
858 .gate = TDA18271_GATE_DIGITAL,
/linux-4.4.14/Documentation/x86/
Dentry_64.txt81 If we are at an interrupt or user-trap/gate-alike boundary then we can
Dkernel-stacks43 interrupt-gate descriptor. When an interrupt occurs and the hardware
/linux-4.4.14/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt14 When the WFI instruction is executed the ARM core would gate its internal
/linux-4.4.14/drivers/media/pci/cx18/
Dcx18-dvb.c105 .gate = TDA18271_GATE_DIGITAL,
/linux-4.4.14/drivers/media/usb/au0828/
Dau0828-dvb.c107 .gate = TDA18271_GATE_DIGITAL,
/linux-4.4.14/arch/arm/mach-tegra/
Dsleep-tegra30.S175 * Clear this CPU's "event" and "interrupt" flags and power gate
/linux-4.4.14/Documentation/devicetree/bindings/
Dmarvell.txt117 - clocks : Phandle to the clock control device and gate bit
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
Dich8lan.c154 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
2743 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate) in e1000_gate_hw_phy_config_ich8lan() argument
2752 if (gate) in e1000_gate_hw_phy_config_ich8lan()
/linux-4.4.14/drivers/media/usb/dvb-usb/
Ddw2102.c1141 .gate = TDA18271_GATE_DIGITAL,
/linux-4.4.14/drivers/net/ethernet/nvidia/
Dforcedeth.c1050 static void nv_txrx_gate(struct net_device *dev, bool gate) in nv_txrx_gate() argument
1059 if (gate) in nv_txrx_gate()
/linux-4.4.14/Documentation/power/
Ddevices.txt377 On many platforms they will gate off one or more clock sources; sometimes they