1Samsung S5P/EXYNOS SoC series MIPI CSIS/DSIM DPHY
2-------------------------------------------------
3
4Required properties:
5- compatible : should be "samsung,s5pv210-mipi-video-phy";
6- #phy-cells : from the generic phy bindings, must be 1;
7- syscon - phandle to the PMU system controller;
8
9For "samsung,s5pv210-mipi-video-phy" compatible PHYs the second cell in
10the PHY specifier identifies the PHY and its meaning is as follows:
11  0 - MIPI CSIS 0,
12  1 - MIPI DSIM 0,
13  2 - MIPI CSIS 1,
14  3 - MIPI DSIM 1.
15
16Samsung EXYNOS SoC series Display Port PHY
17-------------------------------------------------
18
19Required properties:
20- compatible : should be one of the following supported values:
21	 - "samsung,exynos5250-dp-video-phy"
22	 - "samsung,exynos5420-dp-video-phy"
23- samsung,pmu-syscon: phandle for PMU system controller interface, used to
24		      control pmu registers for power isolation.
25- #phy-cells : from the generic PHY bindings, must be 0;
26
27Samsung S5P/EXYNOS SoC series USB PHY
28-------------------------------------------------
29
30Required properties:
31- compatible : should be one of the listed compatibles:
32	- "samsung,exynos3250-usb2-phy"
33	- "samsung,exynos4210-usb2-phy"
34	- "samsung,exynos4x12-usb2-phy"
35	- "samsung,exynos5250-usb2-phy"
36	- "samsung,s5pv210-usb2-phy"
37- reg : a list of registers used by phy driver
38	- first and obligatory is the location of phy modules registers
39- samsung,sysreg-phandle - handle to syscon used to control the system registers
40- samsung,pmureg-phandle - handle to syscon used to control PMU registers
41- #phy-cells : from the generic phy bindings, must be 1;
42- clocks and clock-names:
43	- the "phy" clock is required by the phy module, used as a gate
44	- the "ref" clock is used to get the rate of the clock provided to the
45	  PHY module
46
47Optional properties:
48- vbus-supply: power-supply phandle for vbus power source
49
50The first phandle argument in the PHY specifier identifies the PHY, its
51meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
52and Exynos 4212) it is as follows:
53  0 - USB device ("device"),
54  1 - USB host ("host"),
55  2 - HSIC0 ("hsic0"),
56  3 - HSIC1 ("hsic1"),
57Exynos3250 has only USB device phy available as phy 0.
58
59Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
60register is supplied.
61
62Example:
63
64For Exynos 4412 (compatible with Exynos 4212):
65
66usbphy: phy@125b0000 {
67	compatible = "samsung,exynos4x12-usb2-phy";
68	reg = <0x125b0000 0x100>;
69	clocks = <&clock 305>, <&clock 2>;
70	clock-names = "phy", "ref";
71	status = "okay";
72	#phy-cells = <1>;
73	samsung,sysreg-phandle = <&sys_reg>;
74	samsung,pmureg-phandle = <&pmu_reg>;
75};
76
77Then the PHY can be used in other nodes such as:
78
79phy-consumer@12340000 {
80	phys = <&usbphy 2>;
81	phy-names = "phy";
82};
83
84Refer to DT bindings documentation of particular PHY consumer devices for more
85information about required PHYs and the way of specification.
86
87Samsung SATA PHY Controller
88---------------------------
89
90SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
91Each SATA PHY controller should have its own node.
92
93Required properties:
94- compatible        : compatible list, contains "samsung,exynos5250-sata-phy"
95- reg : offset and length of the SATA PHY register set;
96- #phy-cells : must be zero
97- clocks : must be exactly one entry
98- clock-names : must be "sata_phyctrl"
99- samsung,exynos-sataphy-i2c-phandle : a phandle to the I2C device, no arguments
100- samsung,syscon-phandle : a phandle to the PMU system controller, no arguments
101
102Example:
103	sata_phy: sata-phy@12170000 {
104		compatible = "samsung,exynos5250-sata-phy";
105		reg = <0x12170000 0x1ff>;
106		clocks = <&clock 287>;
107		clock-names = "sata_phyctrl";
108		#phy-cells = <0>;
109		samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>;
110		samsung,syscon-phandle = <&pmu_syscon>;
111	};
112
113Device-Tree bindings for sataphy i2c client driver
114--------------------------------------------------
115
116Required properties:
117compatible: Should be "samsung,exynos-sataphy-i2c"
118- reg: I2C address of the sataphy i2c device.
119
120Example:
121
122	sata_phy_i2c:sata-phy@38 {
123		compatible = "samsung,exynos-sataphy-i2c";
124		reg = <0x38>;
125	};
126
127Samsung Exynos5 SoC series USB DRD PHY controller
128--------------------------------------------------
129
130Required properties:
131- compatible : Should be set to one of the following supported values:
132	- "samsung,exynos5250-usbdrd-phy" - for exynos5250 SoC,
133	- "samsung,exynos5420-usbdrd-phy" - for exynos5420 SoC.
134	- "samsung,exynos5433-usbdrd-phy" - for exynos5433 SoC.
135	- "samsung,exynos7-usbdrd-phy" - for exynos7 SoC.
136- reg : Register offset and length of USB DRD PHY register set;
137- clocks: Clock IDs array as required by the controller
138- clock-names: names of clocks correseponding to IDs in the clock property;
139	       Required clocks:
140	- phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),
141	       used for register access.
142	- ref: PHY's reference clock (usually crystal clock), used for
143	       PHY operations, associated by phy name. It is used to
144	       determine bit values for clock settings register.
145	       For Exynos5420 this is given as 'sclk_usbphy30' in CMU.
146	- optional clocks: Exynos5433 & Exynos7 SoC has now following additional
147			   gate clocks available:
148			   - phy_pipe: for PIPE3 phy
149			   - phy_utmi: for UTMI+ phy
150			   - itp: for ITP generation
151- samsung,pmu-syscon: phandle for PMU system controller interface, used to
152		      control pmu registers for power isolation.
153- #phy-cells : from the generic PHY bindings, must be 1;
154
155For "samsung,exynos5250-usbdrd-phy" and "samsung,exynos5420-usbdrd-phy"
156compatible PHYs, the second cell in the PHY specifier identifies the
157PHY id, which is interpreted as follows:
158  0 - UTMI+ type phy,
159  1 - PIPE3 type phy,
160
161Example:
162	usbdrd_phy: usbphy@12100000 {
163		compatible = "samsung,exynos5250-usbdrd-phy";
164		reg = <0x12100000 0x100>;
165		clocks = <&clock 286>, <&clock 1>;
166		clock-names = "phy", "ref";
167		samsung,pmu-syscon = <&pmu_system_controller>;
168		#phy-cells = <1>;
169	};
170
171- aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
172	   'usbdrd_phy' nodes should have numbered alias in the aliases node,
173	   in the form of usbdrdphyN, N = 0, 1... (depending on number of
174	   controllers).
175Example:
176	aliases {
177		usbdrdphy0 = &usb3_phy0;
178		usbdrdphy1 = &usb3_phy1;
179	};
180