Searched refs:d0 (Results 1 - 200 of 271) sorted by relevance

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/linux-4.4.14/arch/m68k/kernel/
H A D	relocate_kernel.S	33 pmove %tc,%d0 /* Disable MMU */ 34 bclr #7,%d0 35 pmove %d0,%tc 55 movel %a4,%d0 56 andl #0xff000000,%d0 57 orw #0xe020,%d0 /* Map 16 MiB, enable, cacheable */ 59 movec %d0,%itt0 60 movec %d0,%dtt0 65 moveq #0,%d0 67 movec %d0,%tc /* Disable MMU */ 68 movec %d0,%itt0 69 movec %d0,%itt1 70 movec %d0,%dtt0 71 movec %d0,%dtt1 80 movel %a0@+,%d0 /* d0 = entry = *ptr */ 83 btst #2,%d0 /* entry & IND_DONE? */ 86 btst #1,%d0 /* entry & IND_INDIRECTION? */ 88 andw %d2,%d0 89 movel %d0,%a0 /* ptr = entry & PAGE_MASK */ 93 btst #0,%d0 /* entry & IND_DESTINATION? */ 95 andw %d2,%d0 96 movel %d0,%a2 /* a2 = dst = entry & PAGE_MASK */ 100 btst #3,%d0 /* entry & IND_SOURCE? */ 103 andw %d2,%d0 104 movel %d0,%a3 /* a3 = src = entry & PAGE_MASK */ 105 movew #PAGE_SIZE/32 - 1,%d0 /* d0 = PAGE_SIZE/32 - 1 */ 115 dbf %d0, 3b 126 movec %cacr,%d0 127 orw #0x808,%d0 128 movec %d0,%cacr
H A D	sun3-head.S	39 moveq #FC_CONTROL, %d0 40 movec %d0, %sfc 41 movec %d0, %dfc 44 moveq #0, %d0 45 movsb %d0, AC_CONTEXT 63 moveq #ICACHE_ONLY,%d0 | Cache disabled until we're ready to enable it 64 movc %d0, %cacr | is this the right value? (yes --m) 72 movl #(PAGESIZE),%d0 73 movc %d0,%msp 74 moveq #-1,%d0 75 movsb %d0,(AC_SEGMAP+0x0)
H A D	entry.S	86 GET_CURRENT(%d0) 94 GET_CURRENT(%d0) 125 GET_CURRENT(%d0) 141 moveq #__NR_sigreturn,%d0 145 movel #__NR_rt_sigreturn,%d0 157 movel %sp@(PT_OFF_ORIG_D0),%d0 158 cmpl #NR_syscalls,%d0 181 bfextu %sp@(PT_OFF_FORMATVEC){#0,#4},%d0 182 subql #7,%d0 | bus error frame ? 203 cmpl #NR_syscalls,%d0 206 jbsr @(sys_call_table,%d0:l:4)@(0) 207 movel %d0,%sp@(PT_OFF_D0) | save the return value 211 movew %a1@(TINFO_FLAGS+2),%d0 218 lslw #1,%d0 221 lslw #8,%d0 238 moveb %a1@(TINFO_FLAGS+3),%d0 245 lslb #1,%d0 277 GET_CURRENT(%d0) 278 | put exception # in d0 279 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 280 subw #VEC_SPUR,%d0 283 movel %d0,%sp@- | put vector # on stack 293 GET_CURRENT(%d0) 294 | put exception # in d0 295 bfextu %sp@(PT_OFF_FORMATVEC){#4,#10},%d0 297 subw #VEC_USER,%d0 300 movel %d0,%sp@- | put vector # on stack 309 GET_CURRENT(%d0) 327 movec %sfc,%d0 328 movew %d0,%a0@(TASK_THREAD+THREAD_FS) 332 movec %usp,%d0 333 movel %d0,%a0@(TASK_THREAD+THREAD_USP)
H A D	head.S	657 movel %pc@(m68k_cputype),%d0 666 btst #CPUB_68060,%d0 675 btst #CPUB_68040,%d0 684 btst #CPUB_68020,%d0 710 clrl %d0 730 movel #_PAGE_CACHE040W,%d0 734 movew #_PAGE_CACHE040,%d0 742 movel %d0,%a0@ 776 tstl %d0 784 moveq #0,%d0 787 movel #0xff000000,%d0 /* Hades I/O base addr: 0xff000000 */ 789 movel %d0,%a0@ 806 tstl %d0 820 tstl %d0 850 tstl %d0 856 tstl %d0 915 movel %a0@(4),%d0 917 cmpl %d0,%d1 920 cmpl %d0,%d1 990 moveq #0,%d0 996 2: movel #0xff000000,%d0 /* Medusa/Hades base addr: 0xff000000 */ 997 1: movel %d0,%d3 1177 movel #VIDEOMEMMASK,%d0 1178 andl %pc@(L(mac_videobase)),%d0 1180 mmu_map #VIDEOMEMBASE,%d0,#VIDEOMEMSIZE,%d3 1202 movel #0xfee00000, %d0 1204 lsrl %d1,%d0 1205 mmu_get_root_table_entry %d0 1207 movel #0xfee00000, %d0 1209 lsrl %d1,%d0 1210 andl #PTR_TABLE_SIZE-1, %d0 1211 mmu_get_ptr_table_entry %a0,%d0 1213 movel #0xfee00000, %d0 1215 lsrl %d1,%d0 1216 andl #PAGE_TABLE_SIZE-1, %d0 1217 mmu_get_page_table_entry %a0,%d0 1279 movel %pc@(L(phys_kernel_start)),%d0 1280 subl #PAGE_OFFSET,%d0 1282 subl %d0,%a0 1286 subl %d0,%a0 1288 subl %d0,%a1 1393 movel #~VIDEOMEMMASK,%d0 1394 andl L(mac_videobase),%d0 1395 addl #VIDEOMEMBASE,%d0 1396 movel %d0,L(mac_videobase) 1398 movel %pc@(L(phys_kernel_start)),%d0 1399 subl #PAGE_OFFSET,%d0 1400 subl %d0,L(console_font) 1401 subl %d0,L(console_font_data) 1464 movel #CC6_ENABLE_D+CC6_ENABLE_I,%d0 1466 movec %d0,%cacr 1470 movel #CC6_ENABLE_D+CC6_ENABLE_I+CC6_ENABLE_SB+CC6_PUSH_DPI+CC6_ENABLE_B+CC6_CLRA_B,%d0 1472 movec %d0,%cacr 1474 moveq #1,%d0 1476 movec %d0,%pcr 1482 movel #CC3_ENABLE_DB+CC3_CLR_D+CC3_ENABLE_D+CC3_ENABLE_IB+CC3_CLR_I+CC3_ENABLE_I,%d0 1483 movec %d0,%cacr 1516 * Returns: d0: size (-1 if not found) 1521 movel ARG1,%d0 1525 cmpw %a0@(BIR_TAG),%d0 1529 2: moveq #0,%d0 1530 movew %a0@(BIR_SIZE),%d0 1533 3: moveq #-1,%d0 1624 func_start mmu_print,%a0-%a6/%d0-%d7 1705 moveql #0,%d0 1740 moveml %d0-%d1,%sp@- 1741 movel %a4,%d0 1746 moveml %sp@+,%d0-%d1 1759 addq #1,%d0 1760 cmpib #128,%d0 1764 movec %dtt1,%d0 1765 movel %d0,%d1 1769 movel %d0,%d1 1775 movel %d0,%d6 1778 movec %dtt0,%d0 1779 movel %d0,%d1 1783 movel %d0,%d1 1789 movel %d0,%d6 1825 movel %a5,%d0 1826 andil #0xfffffff0,%d0 1827 movel %d0,%a0 1829 movel #0,%d0 1886 addq #1,%d0 1887 cmpib #128,%d0 1897 moveml %d0-%d1,%sp@- 1898 movel %a4,%d0 1902 moveml %sp@+,%d0-%d1 1924 moveml %d0-%d7/%a0,%sp@- 1935 putn %d0 1953 moveml %sp@+,%d0-%d7/%a0 1997 func_start mmu_map_tt,%d0/%d1/%a0,4 2016 moveq #-1,%d0 2017 lsrl %d1,%d0 2018 lsrl #1,%d0 2022 movel %d0,%d1 2028 lsrl #8,%d0 2029 orl %d0,%d1 2038 movel ARG4,%d0 2039 btst #6,%d0 2099 func_start mmu_map,%d0-%d4/%a0-%a4 2110 movel ARG1,%d0 2111 andl #-(PAGESIZE*PAGE_TABLE_SIZE),%d0 2112 movel %d0,%a3 2122 movel ARG2,%d0 2123 andl #-(PAGESIZE*PAGE_TABLE_SIZE),%d0 2124 movel %d0,%a2 2128 movel ARG4,%d0 2129 orw #_PAGE_PRESENT+_PAGE_ACCESSED+_PAGE_DIRTY,%d0 2130 addw %d0,%a2 2158 movel %a3,%d0 2160 lsrl %d1,%d0 2161 mmu_get_root_table_entry %d0 2165 movel %a3,%d0 2167 lsrl %d1,%d0 2168 andl #PTR_TABLE_SIZE-1,%d0 2169 mmu_get_ptr_table_entry %a0,%d0 2173 movel %a3,%d0 2175 lsrl %d1,%d0 2176 andl #PAGE_TABLE_SIZE-1,%d0 2177 mmu_get_page_table_entry %a0,%d0 2201 movel %a3,%d0 2203 lsrl %d1,%d0 2204 mmu_get_root_table_entry %d0 2209 movel %a3,%d0 2210 andl #(PTR_TABLE_SIZE*PAGE_TABLE_SIZE*PAGESIZE-1)&(-ROOT_TABLE_SIZE),%d0 2241 movel %a3,%d0 2243 lsrl %d1,%d0 2244 andl #PTR_TABLE_SIZE-1,%d0 2245 mmu_get_ptr_table_entry %a0,%d0 2289 func_start mmu_fixup_page_mmu_cache,%d0/%a0 2296 movel ARG1,%d0 2298 lsrl %d1,%d0 2299 mmu_get_root_table_entry %d0 2303 movel ARG1,%d0 2305 lsrl %d1,%d0 2306 andl #PTR_TABLE_SIZE-1,%d0 2307 mmu_get_ptr_table_entry %a0,%d0 2311 movel ARG1,%d0 2313 lsrl %d1,%d0 2314 andl #PAGE_TABLE_SIZE-1,%d0 2315 mmu_get_page_table_entry %a0,%d0 2317 movel %a0@,%d0 2318 andil #_CACHEMASK040,%d0 2319 orl %pc@(m68k_pgtable_cachemode),%d0 2320 movel %d0,%a0@ 2333 func_start mmu_temp_map,%d0/%d1/%a0/%a1 2344 movel ARG2,%d0 2346 lsrl %d1,%d0 2347 mmu_get_root_table_entry %d0 2351 movel %a0@,%d0 2352 cmpl %pc@(L(memory_start)),%d0 2357 movel %a1@,%d0 2359 orw #_PAGE_TABLE+_PAGE_ACCESSED,%d0 2360 movel %d0,%a0@ 2363 dputn %d0 2366 andw #-ROOT_TABLE_SIZE,%d0 2367 movel %d0,%a0 2371 movel ARG2,%d0 2373 lsrl %d1,%d0 2374 andl #PTR_TABLE_SIZE-1,%d0 2375 lea %a0@(%d0*4),%a0 2380 movel %a0@,%d0 2385 movel %a1@,%d0 2389 orw #_PAGE_TABLE+_PAGE_ACCESSED,%d0 2390 movel %d0,%a0@ 2393 dputn %d0 2396 andw #-PTR_TABLE_SIZE,%d0 2397 movel %d0,%a0 2401 movel ARG2,%d0 2403 lsrl %d1,%d0 2404 andl #PAGE_TABLE_SIZE-1,%d0 2405 lea %a0@(%d0*4),%a0 2410 movel ARG1,%d0 2411 andw #-PAGESIZE,%d0 2412 orw #_PAGE_PRESENT+_PAGE_ACCESSED+_PAGE_DIRTY,%d0 2413 movel %d0,%a0@ 2414 dputn %d0 2420 func_start mmu_engage,%d0-%d2/%a0-%a3 2422 moveq #ROOT_TABLE_SIZE-1,%d0 2431 dbra %d0,1b 2436 movew #PAGESIZE-1,%d0 2439 dbra %d0,1b 2468 movel #TC_ENABLE+TC_PAGE4K,%d0 2469 movec %d0,%tc /* enable the MMU */ 2487 movel #0x0808,%d0 2488 movec %d0,%cacr 2499 movel #0x0808,%d0 2500 movec %d0,%cacr 2515 func_start mmu_get_root_table_entry,%d0/%a1 2535 movel %a0,%d0 2536 andw #-PAGESIZE,%d0 2538 dputn %d0 2541 movel %d0,%a0@ 2543 movel %d0,%a0@ 2560 movew #PAGESIZE/4-1,%d0 2563 dbra %d0,1b 2571 movel ARG1,%d0 2572 lea %a0@(%d0*4),%a0 2583 func_start mmu_get_ptr_table_entry,%d0/%a1 2593 movel %a0@,%d0 2600 movel %a0@,%d0 2606 andw #7,%d0 2616 movel %a1@,%d0 2619 dputn %d0 2625 orw #_PAGE_TABLE+_PAGE_ACCESSED,%d0 2626 movel %d0,%a0@ 2630 andw #-PTR_TABLE_SIZE,%d0 2631 movel %d0,%a0 2632 movel ARG2,%d0 2633 lea %a0@(%d0*4),%a0 2643 func_start mmu_get_page_table_entry,%d0/%a1 2653 movel %a0@,%d0 2665 movel ARG1,%d0 2666 andw #-(PAGESIZE/PAGE_TABLE_SIZE),%d0 2667 movel %d0,%a1 2671 moveq #PAGESIZE/PAGE_TABLE_SIZE/4-1,%d0 2675 dbra %d0,1b 2680 movel %a0@,%d0 2684 andw #-PAGE_TABLE_SIZE,%d0 2685 movel %d0,%a0 2686 movel ARG2,%d0 2687 lea %a0@(%d0*4),%a0 2701 func_start get_new_page,%d0/%a1 2714 movew #PAGESIZE/4-1,%d0 2717 dbra %d0,1b 2817 func_start serial_init,%d0/%d1/%a0/%a1 2822 * d0 = boot info offset 2826 * d0 = init data for serial port 2830 * d0 = init data for serial port 2858 moveb %a1@(LPSG_READ),%d0 2859 bset #5,%d0 2860 moveb %d0,%a1@(LPSG_WRITE) 2864 moveb %a0@,%d0 2870 movel #32,%d0 2872 subq #1,%d0 2876 2: moveb %a1@+,%d0 2878 moveb %d0,%a0@ 2903 moveb %a0@(mac_scc_cha_a_ctrl_offset),%d0 2909 movel #35,%d0 2911 subq #1,%d0 2917 5: moveb %a1@+,%d0 2919 moveb %d0,%a0@(mac_scc_cha_a_ctrl_offset) 2927 7: moveb %a1@+,%d0 2929 moveb %d0,%a0@(mac_scc_cha_b_ctrl_offset) 2986 func_start serial_putc,%d0/%d1/%a0/%a1 2988 movel ARG1,%d0 2989 cmpib #'\n',%d0 2998 andw #0x00ff,%d0 2999 oriw #0x0100,%d0 3001 movew %d0,%a0@(CUSTOMBASE+C_SERDAT) 3002 1: movew %a0@(CUSTOMBASE+C_SERDATR),%d0 3003 andw #0x2000,%d0 3017 moveb %d0,%a1@(mac_scc_cha_a_data_offset) 3022 moveb %d0,%a1@(mac_scc_cha_b_data_offset) 3035 moveb %d0,%a1@(LPSG_WRITE) 3037 moveb %a1@(LPSG_READ),%d0 3038 bclr #5,%d0 3039 moveb %d0,%a1@(LPSG_WRITE) 3042 bset #5,%d0 3043 moveb %d0,%a1@(LPSG_WRITE) 3047 moveb %d0,%a1@(LSCC_DATA) 3051 moveb %d0,%a1@(LMFP_UDR) 3061 moveb %d0,M147_SCC_DATA_A 3075 moveml %d0-%d7/%a2-%a6,%sp@- 3092 moveb %d0,M162_SCC_CTRL_A 3108 moveb %d0,M167_CYTDR 3113 moveb %d0,%sp@- 3117 moveml %sp@+,%d0-%d7/%a2-%a6 3129 moveb %d0,BVME_SCC_DATA_A 3136 movel %d0,-(%sp) 3150 move.b %d0,%a0@ 3160 moveb %d0,%a1@(LTHRB0) 3161 1: moveb %a1@(LSRB0),%d0 3162 andb #0x4,%d0 3179 moveb %d0,%a1@(DCADATA) 3184 moveb %d0,%a1@(APCIDATA) 3195 func_start puts,%d0/%a0 3201 console_putc %d0 3204 serial_putc %d0 3206 2: moveb %a0@+,%d0 3215 func_start putn,%d0-%d2 3219 movel ARG1,%d0 3221 1: roll #4,%d0 3222 move %d0,%d2 3252 moveml %d0/%d1/%a0,%sp@- 3260 console_putc %d0 3263 serial_putc %d0 3267 moveb %a0@+,%d0 3271 moveml %sp@+,%d0/%d1/%a0 3276 func_start set_leds,%d0/%a0 3277 movel ARG1,%d0 3281 moveb %d0,%a0@(0x1ffff) 3287 lsll #8,%d0 3288 eorw #0xff00,%d0 3289 moveb %d0,%a0@(LCPUCTRL) 3306 func_start console_init,%a0-%a4/%d0-%d7 3334 moveq #-1,%d0 /* Mac_black */ 3338 movel %d0,%a1@+ 3339 movel %d0,%a1@+ 3365 movel %a0@(FONT_DESC_DATA),%d0 3367 addl %a1,%d0 3368 movel %d0,%a4@ 3377 movel %d3,%d0 /* screen width in pixels */ 3378 divul %a0@(FONT_DESC_WIDTH),%d0 /* d0 = max num chars per row */ 3383 movel %d0,%a2@(Lconsole_struct_num_columns) 3400 func_start console_put_penguin,%a0-%a1/%d0-%d7 3406 movel %a0@,%d0 3407 andil #0xffff,%d0 3408 subil #64,%d0 /* snug up against the right edge */ 3417 console_plot_pixel %d0,%d1,%d2 3418 addq #1,%d0 3420 console_plot_pixel %d0,%d1,%d2 3421 addq #1,%d0 3424 subil #64,%d0 3441 func_start console_scroll,%a0-%a4/%d0-%d7 3492 moveq #-1,%d0 3494 movel %d0,%a1@+ 3495 movel %d0,%a1@+ 3496 movel %d0,%a1@+ 3497 movel %d0,%a1@+ 3498 movel %d0,%a1@+ 3499 movel %d0,%a1@+ 3500 movel %d0,%a1@+ 3501 movel %d0,%a1@+ 3508 func_start console_putc,%a0/%a1/%d0-%d7 3527 movel %a0@(Lconsole_struct_cur_row),%d0 3528 addil #1,%d0 3529 movel %d0,%a0@(Lconsole_struct_cur_row) 3531 cmpl %d1,%d0 3533 subil #1,%d0 3534 movel %d0,%a0@(Lconsole_struct_cur_row) 3557 * d0 = cursor column 3562 movel %a0@(Lconsole_struct_cur_column),%d0 3565 cmpl %d1,%d0 3584 * d0 = pixel coordinate, x 3592 mulul %a0@(FONT_DESC_WIDTH),%d0 3606 console_plot_pixel %d0,%d1,%d2 3607 addq #1,%d0 3611 subl %a0@(FONT_DESC_WIDTH),%d0 3620 * d0 = x coordinate 3625 func_start console_plot_pixel,%a0-%a1/%d0-%d4 3629 movel ARG1,%d0 3636 * d0 = x coord becomes byte offset into frame buffer 3640 * d4 = temp of x (d0) for many bit depths 3645 movel %d0,%d4 /* we need the low order 3 bits! */ 3646 divul #8,%d0 3647 addal %d0,%a1 3662 movel %d0,%d4 /* we need the low order 2 bits! */ 3663 divul #4,%d0 3664 addal %d0,%a1 3684 movel %d0,%d4 /* we need the low order bit! */ 3685 divul #2,%d0 3686 addal %d0,%a1 3714 addal %d0,%a1 3727 addal %d0,%a1 3728 addal %d0,%a1
H A D	signal.c	117 switch (regs->d0) { ptrace_signal_deliver() 121 regs->d0 = regs->orig_d0; ptrace_signal_deliver() 665 regs->d0 = context.sc_d0; restore_sigcontext() 702 err |= __get_user(regs->d0, &gregs[0]); rt_restore_ucontext() 760 return regs->d0; do_sigreturn() 784 return regs->d0; do_rt_sigreturn() 796 sc->sc_d0 = regs->d0; setup_sigcontext() 814 err |= __put_user(regs->d0, &gregs[0]); rt_setup_ucontext() 881 /* moveq #,d0; trap #0 */ setup_frame() 962 /* movel #__NR_rt_sigreturn,d0; trap #0 */ setup_rt_frame() 967 /* moveq #,d0; notb d0; trap #0 */ setup_rt_frame() 1017 switch (regs->d0) { handle_restart() 1021 regs->d0 = -EINTR; handle_restart() 1026 regs->d0 = __NR_restart_syscall; handle_restart() 1030 regs->d0 = -EINTR; handle_restart() 1035 regs->d0 = -EINTR; handle_restart() 1041 regs->d0 = regs->orig_d0; handle_restart()
H A D	asm-offsets.c	45 DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0)); main()
H A D	process.c	94 regs->orig_d0, regs->d0, regs->a2, regs->a1); show_regs() 163 frame->regs.d0 = 0; copy_thread()
/linux-4.4.14/arch/mn10300/kernel/
H A D	head.S	68 mov d0,a3 71 mov swapper_pg_dir,d0 72 mov d0,(PTBR) 73 clr d0 74 movbu d0,(PIDR) 77 mov MMUCTR_IIV|MMUCTR_DIV,d0 78 mov d0,(MMUCTR) 80 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0 82 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 84 mov d0,(MMUCTR) 87 movhu (CPUP),d0 88 or CPUP_EXM_AM33V2,d0 89 movhu d0,(CPUP) 90 mov CONFIG_INTERRUPT_VECTOR_BASE,d0 91 mov d0,(TBR) 96 clr d0 97 mov d0,(a0) 100 clr d0 101 movhu d0,(a0) # turn off first 102 mov CHCTR_ICINV|CHCTR_DCINV,d0 103 movhu d0,(a0) 105 mov (a0),d0 106 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy 112 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 114 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 117 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 119 movhu d0,(a0) # enable 130 clr d0 134 mov d0,(a0) 149 movbu (a3),d0 151 movbu d0,(a0) 161 movbu (a3),d0 163 movbu d0,(a0) 173 mov 0xea01eaea,d0 174 mov d0,(4,sp) # EPSW save area 175 mov 0xea02eaea,d0 176 mov d0,(8,sp) # PC save area 178 mov 0xeb0060ed,d0 179 mov d0,mdr 180 mov 0xeb0061ed,d0 181 mov d0,mdrq 182 mov 0xeb0062ed,d0 183 mov d0,mcrh 184 mov 0xeb0063ed,d0 185 mov d0,mcrl 186 mov 0xeb0064ed,d0 187 mov d0,mcvf 200 mov 0xed00d0ed,d0 211 mov 0xffffffff,d0 212 mov d0,(REG_ORIG_D0,fp) 215 mov 0xfb0060ed,d0 216 mov d0,mdr 217 mov 0xfb0061ed,d0 218 mov d0,mdrq 219 mov 0xfb0062ed,d0 220 mov d0,mcrh 221 mov 0xfb0063ed,d0 222 mov d0,mcrl 223 mov 0xfb0064ed,d0 224 mov d0,mcvf 237 mov 0xfd00d0ed,d0 257 mov 0x1,d0 258 mov d0,(a0) 268 movhu (a0),d0 269 or GxICR_REQUEST|GxICR_DETECT,d0 270 movhu d0,(a0) 271 movhu (a0),d0 # flush 276 mov DELAY_TIME_BOOT_IPI,d0 280 mov (a0),d0 281 lsr d2,d0 282 btst 0x1,d0 313 mov swapper_pg_dir,d0 314 mov d0,(PTBR) 315 clr d0 316 movbu d0,(PIDR) 319 mov MMUCTR_IIV|MMUCTR_DIV,d0 320 mov d0,(MMUCTR) 322 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE|MMUCTR_WTE,d0 324 mov MMUCTR_ITE|MMUCTR_DTE|MMUCTR_CE,d0 326 mov d0,(MMUCTR) 329 movhu (CPUP),d0 330 or CPUP_EXM_AM33V2,d0 331 movhu d0,(CPUP) 334 mov CONFIG_INTERRUPT_VECTOR_BASE,d0 335 mov d0,(TBR) 339 clr d0 340 mov d0,(a0) 342 clr d0 343 movhu d0,(a0) # turn off first 344 mov CHCTR_ICINV|CHCTR_DCINV,d0 345 movhu d0,(a0) 347 mov (a0),d0 348 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer) 354 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 356 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK|CHCTR_DCALMD,d0 359 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 361 movhu d0,(a0) # enable 365 movhu (GxICR(SMP_BOOT_IRQ)),d0 366 and ~GxICR_REQUEST,d0 367 movhu d0,(GxICR(SMP_BOOT_IRQ)) 368 movhu (GxICR(SMP_BOOT_IRQ)),d0 # flush 372 mov (CPUID),d0 373 and CPUID_MASK,d0 374 mulu CONFIG_BOOT_STACK_SIZE,d0 375 sub d0,a0 382 mov (CPUID),d0 384 asl d0,d1 395 mov (CHCTR),d0 396 btst CHCTR_DCBUSY,d0 # wait till not busy (use CPU loop buffer) 402 mov CPUM_SLEEP,d0 403 movhu d0,(CPUM)
H A D	smp-low.S	33 mov d0,(sp) 34 movhu (IAGR),d0 35 and IAGR_GN,d0 36 lsr 0x2,d0 38 cmp FLUSH_CACHE_IPI,d0 41 cmp SMP_BOOT_IRQ,d0 44 mov (sp),d0 59 mov (sp),d0 80 movhu (GxICR(SMP_BOOT_IRQ)),d0 81 and ~GxICR_REQUEST,d0 82 movhu d0,(GxICR(SMP_BOOT_IRQ)) 83 mov (sp),d0
H A D	gdb-low.S	35 mov d0,a0 37 clr d0 47 mov d0,a0 49 clr d0 59 mov d0,a0 61 clr d0 78 mov d0,a0 80 clr d0 89 mov d0,a0 91 clr d0 100 mov d0,a0 102 clr d0
H A D	entry.S	54 clr d0 55 mov d0,(REG_D0,fp) 60 mov (REG_D0,fp),d0 64 clr d0 65 mov d0,(REG_D0,fp) 76 mov d0,(REG_ORIG_D0,fp) 78 cmp nr_syscalls,d0 83 add d0,d0,a1 85 mov (REG_A0,fp),d0 88 mov d0,(REG_D0,fp) 107 mov (REG_EPSW,fp),d0 108 and EPSW_nSL,d0 115 mov fp,d0 143 mov fp,d0 150 mov -ENOSYS,d0 151 mov d0,(REG_D0,fp) 152 mov fp,d0 155 cmp nr_syscalls,d0 160 mov -ENOSYS,d0 161 mov d0,(REG_D0,fp) 171 mov (REG_EPSW,fp),d0 # need to deliver signals before 173 and EPSW_nSL,d0 179 mov (TI_preempt_count,a2),d0 # non-zero preempt_count ? 180 cmp 0,d0 186 mov (REG_EPSW,fp),d0 187 and EPSW_IM,d0 188 cmp EPSW_IM_7,d0 # interrupts off (exception path) ? 208 mov 0xffffffff,d0 209 mov d0,(REG_ORIG_D0,fp) 211 mov fp,d0 230 mov d0,(__df_stack-8) # EPSW as was 232 mov 0xaa55aa55,d0 233 mov d0,(__df_stack-12) # no ORIG_D0 239 mov fp,d0 252 mov d0,(sp) 254 mov (MMUCTR),d0 255 mov d0,(MMUCTR) 257 mov (BCBERR),d0 # what 258 btst BCBERR_BEMR_DMA,d0 # see if it was an external bus error 285 mov d0,(sp) 286 mov (TBR),d0 290 mov d0,(sp) # save d0(TBR) 291 movhu (NMIAGR),d0 292 and NMIAGR_GN,d0 293 lsr 0x2,d0 294 cmp CALL_FUNCTION_NMI_IPI,d0 299 mov GxICR_DETECT,d0 # clear NMI request 300 movbu d0,(GxICR(CALL_FUNCTION_NMI_IPI)) 301 movhu (GxICR(CALL_FUNCTION_NMI_IPI)),d0 304 mov (sp),d0 # restore d0 311 cmp DEBUGGER_NMI_IPI,d0 316 mov GxICR_DETECT,d0 # clear NMI 317 movbu d0,(GxICR(DEBUGGER_NMI_IPI)) 318 movhu (GxICR(DEBUGGER_NMI_IPI)),d0 321 mov (sp),d0 323 mov fp,d0 # arg 0: stacked register file 330 mov (sp),d0 # restore TBR to d0 343 mov d0,(sp) 345 mov (MMUCTR),d0 346 mov d0,(MMUCTR) 350 mov (TBR),d0 355 and 0x0000FFFF,d0 # turn the exception code into a vector 358 btst 0x00000007,d0 360 cmp 0x00000400,d0 366 mov (REG_ORIG_D0,fp),d0 367 mov d0,(REG_D0,fp) 368 mov -1,d0 369 mov d0,(REG_ORIG_D0,fp) 374 and d0,d0 # check return value 381 mov fp,d0 388 mov fp,d0 # arg 0: stacked register file 417 lsr 1,d0 418 add exception_table,d0 419 mov d1,(d0)
H A D	switch_to.S	37 mov d0,a0 41 mov __switch_back,d0 51 mov d0,(THREAD_PC,a0) 69 mov d2,d0 # for ret_from_fork 70 mov d0,a0 # for __switch_to 99 movbu (kgdb_sstep_bp),d0 100 movbu d0,(a2) 102 mov a2,d0 113 movbu (kgdb_sstep_bp+1),d0 114 movbu d0,(a2) 116 mov a2,d0 124 mov __switch_back__reinstall_sstep_bp,d0 145 movbu (a2),d0 146 movbu d0,(kgdb_sstep_bp) 149 mov a2,d0 160 movbu (a2),d0 161 movbu d0,(kgdb_sstep_bp+1) 164 mov a2,d0 175 mov a0,d0
H A D	mn10300-watchdog-low.S	35 mov 0xffffffff,d0 36 mov d0,(REG_ORIG_D0,fp) 38 mov fp,d0 56 clr d0 60 mov d0, (a0+)
H A D	fpu-nofpu-low.S	30 mov -1,d0 31 mov d0,(REG_ORIG_D0,fp) 35 mov fp,d0
H A D	signal.c	84 err |= __get_user(*_d0, &sc->d0); restore_sigcontext() 98 long d0; sys_sigreturn() local 113 if (restore_sigcontext(current_frame(), &frame->sc, &d0)) sys_sigreturn() 116 return d0; sys_sigreturn() 130 long d0; sys_rt_sigreturn() local 140 if (restore_sigcontext(current_frame(), &frame->uc.uc_mcontext, &d0)) sys_rt_sigreturn() 146 return d0; sys_rt_sigreturn() 164 COPY(d0); COPY(d1); COPY(d2); COPY(d3); setup_sigcontext() 234 /* this is mov $,d0; syscall 0 */ setup_frame() 248 regs->d0 = sig; setup_frame() 298 /* This is mov $,d0; syscall 0 */ setup_rt_frame() 314 regs->d0 = sig; setup_rt_frame() 343 switch (regs->d0) { handle_signal() 346 regs->d0 = -EINTR; handle_signal() 351 regs->d0 = -EINTR; handle_signal() 357 regs->d0 = regs->orig_d0; handle_signal() 387 switch (regs->d0) { do_signal() 391 regs->d0 = regs->orig_d0; do_signal() 396 regs->d0 = __NR_restart_syscall; do_signal()
H A D	fpu-low.S	137 mov epsw,d0 151 mov d0,epsw 173 mov d0,a0 174 FPU_SAVE_ALL a0,d0 220 FPU_SAVE_ALL a0,d0 222 mov (REG_EPSW,a1),d0 223 and ~EPSW_FE,d0 224 mov d0,(REG_EPSW,a1) 233 FPU_RESTORE_ALL a2,d0 249 mov -1,d0 250 mov d0,(REG_ORIG_D0,fp) 254 mov fp,d0
H A D	gdb-io-serial-low.S	77 mov 0xffffffff,d0 78 mov d0,(REG_ORIG_D0,fp) 81 mov fp,d0
H A D	gdb-io-ttysm-low.S	79 mov 0xffffffff,d0 80 mov d0,(REG_ORIG_D0,fp) 83 mov fp,d0
H A D	asm-offsets.c	20 OFFSET(SIGCONTEXT_d0, sigcontext, d0); foo() 32 OFFSET(REG_D0, pt_regs, d0); foo()
H A D	process.c	169 c_regs->d0 = ustk_size; /* argument */ copy_thread()
/linux-4.4.14/arch/powerpc/math-emu/
H A D	udivmodti4.c	11 _FP_W_TYPE d1, _FP_W_TYPE d0) _fp_udivmodti4() 19 if (d0 > n1) _fp_udivmodti4() 23 udiv_qrnnd (q0, n0, n1, n0, d0); _fp_udivmodti4() 32 if (d0 == 0) _fp_udivmodti4() 33 d0 = 1 / d0; /* Divide intentionally by zero. */ _fp_udivmodti4() 35 udiv_qrnnd (q1, n1, 0, n1, d0); _fp_udivmodti4() 36 udiv_qrnnd (q0, n0, n1, n0, d0); _fp_udivmodti4() 46 if (d0 > n1) _fp_udivmodti4() 50 count_leading_zeros (bm, d0); _fp_udivmodti4() 57 d0 = d0 << bm; _fp_udivmodti4() 62 udiv_qrnnd (q0, n0, n1, n0, d0); _fp_udivmodti4() 71 if (d0 == 0) _fp_udivmodti4() 72 d0 = 1 / d0; /* Divide intentionally by zero. */ _fp_udivmodti4() 74 count_leading_zeros (bm, d0); _fp_udivmodti4() 78 /* From (n1 >= d0) /\ (the most significant bit of d0 is set), _fp_udivmodti4() 85 n1 -= d0; _fp_udivmodti4() 96 d0 = d0 << bm; _fp_udivmodti4() 101 udiv_qrnnd (q1, n1, n2, n1, d0); _fp_udivmodti4() 104 /* n1 != d0... */ _fp_udivmodti4() 106 udiv_qrnnd (q0, n0, n1, n0, d0); _fp_udivmodti4() 143 if (n1 > d1 || n0 >= d0) _fp_udivmodti4() 146 sub_ddmmss (n1, n0, n1, n0, d1, d0); _fp_udivmodti4() 164 d1 = (d1 << bm) | (d0 >> b); _fp_udivmodti4() 165 d0 = d0 << bm; _fp_udivmodti4() 171 umul_ppmm (m1, m0, q0, d0); _fp_udivmodti4() 176 sub_ddmmss (m1, m0, m1, m0, d1, d0); _fp_udivmodti4() 9 _fp_udivmodti4(_FP_W_TYPE q[2], _FP_W_TYPE r[2], _FP_W_TYPE n1, _FP_W_TYPE n0, _FP_W_TYPE d1, _FP_W_TYPE d0) _fp_udivmodti4() argument
/linux-4.4.14/arch/mn10300/lib/
H A D	do_csum.S	26 mov d0,a0 # buff 39 movbu (a0),d0 41 asl +8,d0 42 add d0,d1 50 movhu (a0+),d0 51 add d0,d1 65 mov (a0+),d0 69 add d0,d1 73 mov (a0+),d0 77 addc d0,d1 93 mov (a0+),d0 97 add d0,d1 113 mov (a0+),d0 114 add d0,d1 117 mov (a0+),d0 118 add d0,d1 121 mov (a0+),d0 122 add d0,d1 128 xor_cmp d0,d0,+2,d2 130 movhu (a0+),d0 135 add d3,d0 137 add d0,d1 142 mov +0xffff0000,d0 143 and d1,d0 145 add d1,d0 146 addc +0xffff,d0 147 lsr +16,d0 152 swaph d0,d0 # exchange bits 15:8 with 7:0
H A D	memmove.S	26 cmp d1,d0 31 mov d0,(12,sp) 34 add d0,d2,a0 # dst end 36 mov d0,e3 # the return value 42 or d0,d1,d3 56 mov (a1),d0 58 mov d0,(a0) 63 mov (a1),d0 65 mov d0,(a0) 70 mov (a1),d0 72 mov d0,(a0) 77 mov (a1),d0 79 mov d0,(a0) 94 mov (a1),d0 96 mov d0,(a0) 114 mov (a1),d0 116 mov d0,(a0) 118 mov (a1),d0 120 mov d0,(a0) 122 mov (a1),d0 124 mov d0,(a0) 148 movbu (a1),d0 150 movbu d0,(a0)
H A D	__ucmpdi2.S	30 sub a0,d0 33 mov +1,d0 38 subc d0,d0 # -1 if LE, 0 if GE 39 add +1,d0 # 0 if LE, 1 if GE 40 add d0,d0 # 0 if LE, 2 if GE
H A D	memcpy.S	25 mov d0,(12,sp) 28 mov d0,a0 # dst 30 mov d0,e3 # the return value 36 or d0,d1,d3 50 mov (a1+),d0 58 mov d0,(a0+) 78 mov (a1+),d0 82 mov d0,(a0+) 94 mov (a1+),d0 95 mov d0,(a0+) 97 mov (a1+),d0 98 mov d0,(a0+) 100 mov (a1+),d0 101 mov d0,(a0+) 126 movbu (a1),d0 127 movbu d0,(a0)
H A D	__ashldi3.S	37 lsr a1,d0,a1 # get overflow from LSW -> MSW 39 or_asl a1,d1,a0,d0 # insert overflow into MSW and 46 asl a0,d0,d1 47 clr d0
H A D	__lshrdi3.S	34 lsr a0,d0 40 or_lsr a1,d0,a0,d1 # insert underflow into LSW and 47 lsr a0,d1,d0
H A D	__ashrdi3.S	33 lsr a0,d0 39 or_asr a1,d0,a0,d1 # insert underflow into LSW and 46 asr a0,d1,d0 47 ext d0 # sign-extend result through MDR
H A D	delay.c	21 int d0; __delay() local 30 : "=&d" (d0) __delay()
H A D	memset.S	25 mov d0,(12,sp) 28 mov d0,a0 # dst 29 mov d0,e3 # the return value 35 or d0,d2,d3
/linux-4.4.14/arch/mn10300/mm/
H A D	cache-dbg-inv-by-tag.S	38 movhu (a2),d0 39 btst CHCTR_ICEN,d0 42 mov d0,a1 48 mov a1,d0 49 and L1_CACHE_TAG_ENTRY,d0 50 add d0,a0 # starting icache tag RAM 60 movhu (a2),d0 61 and ~CHCTR_ICEN,d0 62 movhu d0,(a2) 66 movhu (a2),d0 67 btst CHCTR_ICBUSY,d0 71 mov (a0),d0 # read the tag in the way 0 slot 72 xor a1,d0 73 and d1,d0 77 mov (a0),d0 # read the tag in the way 1 slot 78 xor a1,d0 79 and d1,d0 83 mov (a0),d0 # read the tag in the way 2 slot 84 xor a1,d0 85 and d1,d0 89 mov (a0),d0 # read the tag in the way 3 slot 90 xor a1,d0 91 and d1,d0 95 mov d0,(a0) # kill the tag (D0 is 0 at this point) 100 movhu (a2),d0 101 btst CHCTR_ICBUSY,d0 105 or CHCTR_ICEN,d0 106 movhu d0,(a2) 107 movhu (a2),d0
H A D	cache-dbg-flush-by-reg.S	35 movhu (CHCTR),d0 36 btst CHCTR_DCEN|CHCTR_ICEN,d0 46 btst CHCTR_DCEN,d0 51 mov (a0),d0 52 btst DCPGCR_DCPGBSY,d0 56 clr d0 57 mov d0,(DCPGMR) 63 mov DCPGCR_DCP,d0 64 mov d0,(a0) 68 mov (a0),d0 69 btst DCPGCR_DCPGBSY,d0 77 movhu (a0),d0 78 btst CHCTR_ICEN,d0 108 and L1_CACHE_TAG_MASK,d0 109 mov d0,a1 110 mov d0,d1 114 and L1_CACHE_TAG_ENTRY,d0 115 add d0,a0 128 movhu (a0),d0 129 btst CHCTR_ICEN,d0 138 mov (a0),d0 139 btst ICIVCR_ICIVBSY,d0 143 mov L1_CACHE_TAG_MASK,d0 144 mov d0,(ICIVMR) 152 mov (a0),d0 153 btst ICIVCR_ICIVBSY,d0
H A D	cache-dbg-flush-by-tag.S	36 movhu (CHCTR),d0 37 btst CHCTR_DCEN|CHCTR_ICEN,d0 40 btst CHCTR_DCEN,d0 51 mov (a0),d0 52 and L1_CACHE_TAG_MASK,d0 53 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the 55 mov d0,(a1) # conditional purge 67 movhu (a0),d0 68 btst CHCTR_ICEN,d0 95 and L1_CACHE_TAG_MASK,d0 96 mov d0,a1 100 and L1_CACHE_TAG_ENTRY,d0 101 add d0,a0
H A D	cache-inv-by-tag.S	70 movhu (a0),d0 71 btst CHCTR_ICEN,d0 92 movhu (a0),d0 93 btst CHCTR_DCEN,d0 118 and ~(PAGE_SIZE-1),d0 121 add d0,d1 127 btst ~L1_CACHE_TAG_MASK,d0 144 and L1_CACHE_TAG_MASK,d0 # round start addr down 149 mov d0,a1 157 mov a1,d0 158 and L1_CACHE_TAG_ENTRY,d0 159 add d0,a0 # starting dcache tag RAM 172 movhu (a2),d0 173 and ~CHCTR_DCEN,d0 174 movhu d0,(a2) 178 movhu (a2),d0 179 btst CHCTR_DCBUSY,d0 185 mov (L1_CACHE_WAYDISP*0,a0),d0 # read the tag in the way 0 slot 186 btst L1_CACHE_TAG_VALID,d0 190 xor a1,d0 191 lsr 12,d0 199 mov (L1_CACHE_WAYDISP*1,a0),d0 # read the tag in the way 1 slot 200 btst L1_CACHE_TAG_VALID,d0 204 xor a1,d0 205 lsr 12,d0 213 mov (L1_CACHE_WAYDISP*2,a0),d0 # read the tag in the way 2 slot 214 btst L1_CACHE_TAG_VALID,d0 218 xor a1,d0 219 lsr 12,d0 227 mov (L1_CACHE_WAYDISP*3,a0),d0 # read the tag in the way 3 slot 228 btst L1_CACHE_TAG_VALID,d0 232 xor a1,d0 233 lsr 12,d0 253 movhu (a2),d0 254 btst CHCTR_DCBUSY,d0 258 or CHCTR_DCEN,d0 259 movhu d0,(a2) 260 movhu (a2),d0
H A D	cache-dbg-inv-by-reg.S	33 mov d0,a1 36 movhu (a0),d0 37 btst CHCTR_ICEN,d0 46 mov (a0),d0 47 btst ICIVCR_ICIVBSY,d0 51 mov ~L1_CACHE_TAG_MASK,d0 52 mov d0,(ICIVMR) 61 mov (a0),d0 62 btst ICIVCR_ICIVBSY,d0
H A D	cache-flush-by-reg.S	52 movhu (CHCTR),d0 53 btst CHCTR_DCEN,d0 62 mov (a0),d0 63 btst DCPGCR_DCPGBSY,d0 67 clr d0 68 mov d0,(DCPGMR) 74 mov DCPGCR_DCP,d0 75 mov d0,(a0) 79 mov (a0),d0 80 btst DCPGCR_DCPGBSY,d0 105 and ~(PAGE_SIZE-1),d0 108 add d0,d1 124 sub d0,d1,d3 150 and d1,d0,a2 # a2 = mask & start 154 mov a2,d0 155 or DCPGCR_DCP,d0 156 mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCP 188 movhu (CHCTR),d0 189 btst CHCTR_DCEN,d0 198 mov (a0),d0 199 btst DCPGCR_DCPGBSY,d0 203 clr d0 204 mov d0,(DCPGMR) 207 mov DCPGCR_DCP|DCPGCR_DCI,d0 208 mov d0,(a0) 212 mov (a0),d0 213 btst DCPGCR_DCPGBSY,d0 238 and ~(PAGE_SIZE-1),d0 241 add d0,d1 257 sub d0,d1,d3 283 and d1,d0,a2 # a2 = mask & start 287 mov a2,d0 288 or DCPGCR_DCP|DCPGCR_DCI,d0 289 mov d0,(a0) # DCPGCR = (mask & start)|DCPGCR_DCP|DCPGCR_DCI
H A D	cache-inv-by-reg.S	62 movhu (a0),d0 63 btst CHCTR_ICEN,d0 84 movhu (a0),d0 85 btst CHCTR_DCEN,d0 110 and ~(PAGE_SIZE-1),d0 113 add d0,d1 119 btst ~L1_CACHE_TAG_MASK,d0 139 and L1_CACHE_TAG_MASK,d0 # round start addr down 146 sub d0,d1,d2 # calculate the total size 147 mov d0,a2 # A2 = start address 154 mov (a0),d0 155 btst DCPGCR_DCPGBSY,d0 176 mov d1,d0 177 and a2,d0 199 mov 0x80000000,d0 # start from 31bit=1 201 lsr 1,d0 202 mov d0,e0 205 mov d0,d1 213 mov d1,d0 214 add -1,d0 215 not d0 216 mov d0,(DCPGMR) 219 mov a2,d0 220 or DCPGCR_DCI,d0 221 mov d0,(a0) # DCPGCR = (mask & start) | DCPGCR_DCI 224 mov (a0),d0 225 btst DCPGCR_DCPGBSY,d0 264 and ~(PAGE_SIZE-1),d0 267 add d0,d1 285 sub d0,d1,d3 317 and d1,d0,a2 324 mov a2,d0 325 or ICIVCR_ICI,d0 326 mov d0,(a0)
H A D	cache-flush-by-tag.S	52 movhu (CHCTR),d0 53 btst CHCTR_DCEN,d0 64 mov (a0),d0 65 and L1_CACHE_TAG_MASK,d0 66 or L1_CACHE_TAG_VALID,d0 # retain valid entries in the 68 mov d0,(a1) # conditional purge 95 and ~(PAGE_SIZE-1),d0 98 add d0,d1 106 sub d0,d1,a0 115 and L1_CACHE_TAG_MASK,d0 116 mov d0,a1 123 mov a1,d0 124 and L1_CACHE_TAG_ENTRY,d0 125 add d0,a0 # starting dcache purge control 162 movhu (CHCTR),d0 163 btst CHCTR_DCEN,d0 170 mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge 171 mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge 172 mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge 173 mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge 199 and ~(PAGE_SIZE-1),d0 202 add d0,d1 210 sub d0,d1,a0 218 and L1_CACHE_TAG_MASK,d0 # round start addr down 219 mov d0,a1 227 mov a1,d0 228 and L1_CACHE_TAG_ENTRY,d0 229 add d0,a0 # starting dcache purge control
H A D	tlb-mn10300.S	171 mov (IPTEU),d0 172 and PAGE_MASK,d0 173 mov d0,(12,sp) 175 clr d0 176 mov d0,(IPTEL2) 179 mov fp,d0 208 mov a2,d0 209 and PAGE_MASK,d0 210 mov d0,(12,sp) 212 clr d0 213 mov d0,(DPTEL2) 216 mov fp,d0
H A D	cache-dbg-inv.S	39 movhu (a0),d0 40 btst CHCTR_ICEN,d0
/linux-4.4.14/drivers/video/fbdev/core/
H A D	cfbcopyarea.c	107 unsigned long d0, d1; bitcpy() local 117 d0 = FB_READL(src); bitcpy() 118 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy() 121 d0 <<= left; bitcpy() 124 d0 >>= right; bitcpy() 129 d0 = d0 >> right | d1 << left; bitcpy() 131 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy() 132 FB_WRITEL(comp(d0, FB_READL(dst), first), dst); bitcpy() 139 'd0'. */ bitcpy() 140 d0 = FB_READL(src++); bitcpy() 141 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy() 145 d1 = d0; bitcpy() 146 d0 <<= left; bitcpy() 153 d0 = d0 >> right | d1 << left; bitcpy() 156 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy() 157 FB_WRITEL(comp(d0, FB_READL(dst), first), dst); bitcpy() 158 d0 = d1; bitcpy() 166 FB_WRITEL(d0 >> right | d1 << left, dst++); bitcpy() 167 d0 = d1; bitcpy() 169 FB_WRITEL(d0 >> right | d1 << left, dst++); bitcpy() 170 d0 = d1; bitcpy() 172 FB_WRITEL(d0 >> right | d1 << left, dst++); bitcpy() 173 d0 = d1; bitcpy() 175 FB_WRITEL(d0 >> right | d1 << left, dst++); bitcpy() 176 d0 = d1; bitcpy() 182 d0 = d0 >> right | d1 << left; bitcpy() 183 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy() 184 FB_WRITEL(d0, dst++); bitcpy() 185 d0 = d1; bitcpy() 192 d0 >>= right; bitcpy() 198 d0 = d0 >> right | d1 << left; bitcpy() 200 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy() 201 FB_WRITEL(comp(d0, FB_READL(dst), last), dst); bitcpy() 280 unsigned long d0, d1; bitcpy_rev() local 290 d0 = FB_READL(src); bitcpy_rev() 293 d0 >>= right; bitcpy_rev() 296 d0 <<= left; bitcpy_rev() 301 d0 = d0 << left | d1 >> right; bitcpy_rev() 303 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy_rev() 304 FB_WRITEL(comp(d0, FB_READL(dst), last), dst); bitcpy_rev() 311 'd0'. */ bitcpy_rev() 313 d0 = FB_READL(src--); bitcpy_rev() 314 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy_rev() 318 d1 = d0; bitcpy_rev() 319 d0 >>= right; bitcpy_rev() 324 d0 = d0 << left | d1 >> right; bitcpy_rev() 326 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy_rev() 328 FB_WRITEL(d0, dst); bitcpy_rev() 330 FB_WRITEL(comp(d0, FB_READL(dst), first), dst); bitcpy_rev() 331 d0 = d1; bitcpy_rev() 340 FB_WRITEL(d0 << left | d1 >> right, dst--); bitcpy_rev() 341 d0 = d1; bitcpy_rev() 343 FB_WRITEL(d0 << left | d1 >> right, dst--); bitcpy_rev() 344 d0 = d1; bitcpy_rev() 346 FB_WRITEL(d0 << left | d1 >> right, dst--); bitcpy_rev() 347 d0 = d1; bitcpy_rev() 349 FB_WRITEL(d0 << left | d1 >> right, dst--); bitcpy_rev() 350 d0 = d1; bitcpy_rev() 356 d0 = d0 << left | d1 >> right; bitcpy_rev() 357 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy_rev() 358 FB_WRITEL(d0, dst--); bitcpy_rev() 359 d0 = d1; bitcpy_rev() 366 d0 <<= left; bitcpy_rev() 372 d0 = d0 << left | d1 >> right; bitcpy_rev() 374 d0 = fb_rev_pixels_in_long(d0, bswapmask); bitcpy_rev() 375 FB_WRITEL(comp(d0, FB_READL(dst), last), dst); bitcpy_rev()
H A D	syscopyarea.c	76 unsigned long d0, d1; bitcpy() local 95 d0 = *src++; bitcpy() 97 *dst = comp(d0 >> right | d1 << left, *dst, bitcpy() 107 this value in 'd0'. */ bitcpy() 108 d0 = *src++; bitcpy() 112 *dst = comp(d0 << left, *dst, first); bitcpy() 118 *dst = comp(d0 >> right | d1 << left, *dst, bitcpy() 120 d0 = d1; bitcpy() 130 *dst++ = d0 >> right | d1 << left; bitcpy() 131 d0 = d1; bitcpy() 133 *dst++ = d0 >> right | d1 << left; bitcpy() 134 d0 = d1; bitcpy() 136 *dst++ = d0 >> right | d1 << left; bitcpy() 137 d0 = d1; bitcpy() 139 *dst++ = d0 >> right | d1 << left; bitcpy() 140 d0 = d1; bitcpy() 145 *dst++ = d0 >> right | d1 << left; bitcpy() 146 d0 = d1; bitcpy() 153 d0 >>= right; bitcpy() 157 d0 = d0 >> right | d1 << left; bitcpy() 159 *dst = comp(d0, *dst, last); bitcpy() 252 this value in 'd0'. */ bitcpy_rev() 253 unsigned long d0, d1; bitcpy_rev() local 256 d0 = *src--; bitcpy_rev() 260 d1 = d0; bitcpy_rev() 261 d0 >>= right; bitcpy_rev() 265 d0 = d0 << left | d1 >> right; bitcpy_rev() 268 *dst = d0; bitcpy_rev() 270 *dst = comp(d0, *dst, first); bitcpy_rev() 271 d0 = d1; bitcpy_rev() 280 *dst-- = d0 << left | d1 >> right; bitcpy_rev() 281 d0 = d1; bitcpy_rev() 283 *dst-- = d0 << left | d1 >> right; bitcpy_rev() 284 d0 = d1; bitcpy_rev() 286 *dst-- = d0 << left | d1 >> right; bitcpy_rev() 287 d0 = d1; bitcpy_rev() 289 *dst-- = d0 << left | d1 >> right; bitcpy_rev() 290 d0 = d1; bitcpy_rev() 295 *dst-- = d0 << left | d1 >> right; bitcpy_rev() 296 d0 = d1; bitcpy_rev() 303 d0 <<= left; bitcpy_rev() 307 d0 = d0 << left | d1 >> right; bitcpy_rev() 309 *dst = comp(d0, *dst, last); bitcpy_rev()
/linux-4.4.14/arch/m68k/fpsp040/
H A D	sto_res.S	34 bfextu CMDREG1B(%a6){#13:#3},%d0 |extract cos destination 35 cmpib #3,%d0 |check for fp0/fp1 cases 39 subl %d0,%d1 |d1 = 7- (dest. reg. no.) 40 clrl %d0 41 bsetl %d1,%d0 |d0 is dynamic register mask 42 fmovemx (%a7)+,%d0 45 cmpib #0,%d0 47 cmpib #1,%d0 49 cmpib #2,%d0 67 bfextu CMDREG1B(%a6){#6:#3},%d0 |extract destination register 68 cmpib #3,%d0 |check for fp0/fp1 cases 72 subl %d0,%d1 |d1 = 7- (dest. reg. no.) 73 clrl %d0 74 bsetl %d1,%d0 |d0 is dynamic register mask 75 fmovemx (%a7)+,%d0 78 cmpib #0,%d0 80 cmpib #1,%d0 82 cmpib #2,%d0
H A D	x_store.S	41 movel CMDREG3B(%a6),%d0 42 bfextu %d0{#6:#3},%d0 |isolate dest. reg from cmdreg3b 45 moveb (%a1,%d0.w),%d0 |convert reg# to dynamic register mask 50 fmovemx (%a0),%d0 |move to correct register 56 cmpb #0x80,%d0 61 cmpb #0x40,%d0 66 cmpb #0x20,%d0 71 cmpb #0x10,%d0 79 bsrl g_opcls |returns opclass in d0 80 cmpib #3,%d0 82 movel CMDREG1B(%a6),%d0 83 bfextu %d0{#6:#3},%d0 |extract destination register 87 bsrl g_dfmtou |returns dest format in d0 91 cmpil #0,%d0 |if dest format is extended 93 cmpil #1,%d0 |if dest format is single 108 | d0 -> 0 131 clrl %d0 |clear d0 132 movew LOCAL_EX(%a1),%d0 |get exponent 133 subw #0x3fff,%d0 |subtract extended precision bias 134 cmpw #0x4000,%d0 |check if inf 136 addw #0x3ff,%d0 |add double precision bias 137 swap %d0 |d0 now in upper word 138 lsll #4,%d0 |d0 now in proper place for dbl prec exp 141 bsetl #31,%d0 |if negative, put in sign information 145 movel #0x7ff00000,%d0 |load dbl inf exponent 149 bsetl #31,%d0 |if negative put in sign information 151 movel %d0,LOCAL_EX(%a1) |put the new exp back on the stack 156 orl %d1,%d0 |put these bits in ms word of double 157 movel %d0,LOCAL_EX(%a1) |put the new exp back on the stack 159 movel #21,%d0 |load shift count 160 lsll %d0,%d1 |put lower 11 bits in upper bits 163 bfextu %d1{#0:#21},%d0 |get ls 21 bits of double 164 orl %d0,LOCAL_HI(%a1) |put them in double result 166 movel #0x8,%d0 |byte count for double precision number 180 | d0 -> 0 202 clrl %d0 203 movew LOCAL_EX(%a1),%d0 |get exponent 204 subw #0x3fff,%d0 |subtract extended precision bias 205 cmpw #0x4000,%d0 |check if inf 207 addw #0x7f,%d0 |add single precision bias 208 swap %d0 |put exp in upper word of d0 209 lsll #7,%d0 |shift it into single exp bits 212 bsetl #31,%d0 |if negative, put in sign first 215 movel #0x7f800000,%d0 |load single inf exp to d0 218 bsetl #31,%d0 |if negative, put in sign info 224 orl %d1,%d0 |put these bits in ms word of single 227 movel %d0,L_SCR1(%a6) |put the new exp back on the stack 228 movel #0x4,%d0 |byte count for single precision number 236 bsrl get_fline |returns fline word in d0 237 andw #0x7,%d0 |isolate register number 238 movel %d0,%d1 |d1 has size:reg formatted for reg_dest 250 movel #0x0c,%d0 |byte count for extended number
H A D	stanh.S	87 movel (%a0),%d0 88 movew 4(%a0),%d0 89 movel %d0,X(%a6) 90 andl #0x7FFFFFFF,%d0 91 cmp2l BOUNDS1(%pc),%d0 | ...2**(-40) < |X| < (5/2)LOG2 ? 97 movel X(%a6),%d0 98 movel %d0,SGN(%a6) 99 andl #0x7FFF0000,%d0 100 addl #0x00010000,%d0 | ...EXPONENT OF 2|X| 101 movel %d0,X(%a6) 113 movel SGN(%a6),%d0 115 eorl %d0,V(%a6) 122 cmpl #0x3FFF8000,%d0 125 cmpl #0x40048AA1,%d0 132 movel X(%a6),%d0 133 movel %d0,SGN(%a6) 134 andl #0x7FFF0000,%d0 135 addl #0x00010000,%d0 | ...EXPO OF 2|X| 136 movel %d0,X(%a6) | ...Y = 2|X| 138 movel SGN(%a6),%d0 146 movel SGN(%a6),%d0 149 eorl #0xC0000000,%d0 | ...-SIGN(X)*2 150 fmoves %d0,%fp1 | ...-SIGN(X)*2 IN SGL FMT 153 movel SGN(%a6),%d0 154 orl #0x3F800000,%d0 | ...SGN 155 fmoves %d0,%fp0 | ...SGN IN SGL FMT 172 movel X(%a6),%d0 173 andl #0x80000000,%d0 174 orl #0x3F800000,%d0 175 fmoves %d0,%fp0 176 andl #0x80000000,%d0 177 eorl #0x80800000,%d0 | ...-SIGN(X)*EPS 180 fadds %d0,%fp0
H A D	sgetem.S	49 movew LOCAL_EX(%a0),%d0 |get the exponent 50 bclrl #15,%d0 |clear the sign bit 51 subw #0x3fff,%d0 |subtract off the bias 52 fmovew %d0,%fp0 |move the exp to fp0 59 movew LOCAL_EX(%a0),%d0 |load resulting exponent into d0 60 subw #0x3fff,%d0 |subtract off the bias 61 fmovew %d0,%fp0 |move the exp to fp0 78 movel USER_FPCR(%a6),%d0 79 andil #0xffffff00,%d0 |clear rounding precision and mode 80 fmovel %d0,%fpcr |this fpcr setting is used by the 882 81 movew LOCAL_EX(%a0),%d0 |get the exp (really just want sign bit) 82 orw #0x7fff,%d0 |clear old exp 83 bclrl #14,%d0 |make it the new exp +-3fff 84 movew %d0,LOCAL_EX(%a0) |move the sign & exp back to fsave stack 94 movel LOCAL_HI(%a0),%d0 |load ms mant in d0 97 movel %d0,LOCAL_HI(%a0) |put ms mant back on stack 106 | ms mantissa part in d0 109 | shifted bits in d0 and d1 111 tstl %d0 |if any bits set in ms mant 119 exg %d0,%d1 |shift ls mant to ms mant 120 bfffo %d0{#0:#32},%d3 |find first 1 in ls mant to d0 121 lsll %d3,%d0 |shift first 1 to integer bit in ms mant 127 bfffo %d0{#0:#32},%d3 |find first 1 in ls mant to d0 128 lsll %d3,%d0 |shift ms mant until j-bit is set 135 orl %d6,%d0 |shift the ls mant bits into the ms mant
H A D	x_operr.S	67 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 82 movel CMDREG1B(%a6),%d0 83 bfextu %d0{#3:#3},%d0 |0=long, 4=word, 6=byte 84 cmpib #0,%d0 |determine size; check long 86 cmpib #4,%d0 |check word 88 cmpib #6,%d0 |check byte 101 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 110 moveb STAG(%a6),%d0 |test stag for nan 111 andib #0xe0,%d0 |clr all but tag 112 cmpib #0x60,%d0 |check for nan 117 tstl %d0 118 bnes chklerr |if d0 is true, check for incorrect operr 119 movel #0x80000000,%d0 |store special case result 126 movew FPTEMP_EX(%a6),%d0 127 andw #0x7FFF,%d0 |ignore sign bit 128 cmpw #0x3FFE,%d0 |this is the only possible exponent value 131 movel FPTEMP_LO(%a6),%d0 135 movew FPTEMP_EX(%a6),%d0 136 andw #0x7FFF,%d0 |ignore sign bit 137 cmpw #0x4000,%d0 140 movel FPTEMP_LO(%a6),%d0 141 andl #0x7FFF0000,%d0 |look for all 1's on bits 30-16 142 cmpl #0x7FFF0000,%d0 157 moveb STAG(%a6),%d0 |test stag for nan 158 andib #0xe0,%d0 |clr all but tag 159 cmpib #0x60,%d0 |check for nan 164 tstl %d0 165 bnes chkwerr |if d0 is true, check for incorrect operr 166 movel #0x80000000,%d0 |store special case result 173 movew FPTEMP_EX(%a6),%d0 174 andw #0x7FFF,%d0 |ignore sign bit 175 cmpw #0x3FFE,%d0 |this is the only possible exponent value 177 movel FPTEMP_LO(%a6),%d0 178 swap %d0 184 moveb STAG(%a6),%d0 |test stag for nan 185 andib #0xe0,%d0 |clr all but tag 186 cmpib #0x60,%d0 |check for nan 191 tstl %d0 192 bnes chkberr |if d0 is true, check for incorrect operr 193 movel #0x80000000,%d0 |store special case result 200 movew FPTEMP_EX(%a6),%d0 201 andw #0x7FFF,%d0 |ignore sign bit 202 cmpw #0x3FFE,%d0 |this is the only possible exponent value 204 movel FPTEMP_LO(%a6),%d0 205 asll #8,%d0 206 swap %d0 218 movel ETEMP_HI(%a6),%d0 |output will be from upper 32 bits 234 movel #0x7fffffff,%d0 238 movel #0x80000000,%d0 243 | This routine stores the data in d0, for the given size in d1, 248 movel %d0,L_SCR1(%a6) |move write data to L_SCR1 250 bsrl get_fline |fline returned in d0 252 bftst %d0{#26:#3} |if mode is zero, dest is Dn 255 | Destination is Dn. Get register number from d0. Data is on 258 andil #7,%d0 |isolate register number 263 orl #8,%d0 266 orl #0x10,%d0 268 movel %d0,%d1 |format size:reg for reg_dest 278 movel %d1,%d0 |put size in d0 283 | mantissa for $ffffffff. If both are true, return d0 clr 285 | to d0 for write out. If not, it is a real operr, and set d0. 295 movel #1,%d0 |signal real operr 298 clrl %d0 |signal no real operr 312 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 327 moveb FPCR_ENABLE(%a6),%d0 328 andb FPSR_EXCEPT(%a6),%d0 329 andib #0x3,%d0 338 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 349 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
H A D	round.S	33 | d0{31:29} contains the g,r,s bits (extended) 36 | a0 is preserved and the g-r-s bits in d0 are cleared. 52 tstl %d0 |if grs are zero, go force 84 movel #0xffffffff,%d0 |force g,r,s to be all f's 97 movel #0xffffffff,%d0 |force g,r,s to be all f's 117 asll #1,%d0 |shift g-bit to c-bit 127 | Output: d0{31:29}= guard, round, sticky 131 | only. All registers except d0 are kept intact. d0 becomes an 132 | updated guard,round,sticky in d0{31:29} 156 tstl %d0 |test original g,r,s 166 tstl %d0 |test word original g,r,s 172 movel %d3,%d0 |return grs to d0 200 tstl %d0 |test for rs = 0 222 tstl %d0 |test rs = 0 241 tstl %d0 |test for rs = 0 281 | exponent (d0) is set to 0 and the mantissa (d1 & d2) is not 305 movew LOCAL_EX(%a0),%d0 306 cmpw #64,%d0 |see if exp > 64 318 cmpw %d3,%d0 |of X>Y 326 lsll %d0,%d2 |shift ls mant by count 327 lsll %d0,%d1 |shift ms mant by count 329 subl %d0,%d5 |make op a denorm by shifting bits 333 movel #0,%d0 |same as if decremented exp to 0 335 movew %d0,LOCAL_EX(%a0) 344 cmpw %d3,%d0 |if X>Y 365 movel LOCAL_HI(%a0),%d0 |d0 has ms mant 368 lsll %d7,%d0 |shift first 1 to j bit position 376 orl %d1,%d0 |shift the ls mant bits into the ms mant 377 movel %d0,LOCAL_HI(%a0) |store ms mant into memory 386 movew LOCAL_EX(%a0),%d0 |d0 has exponent 388 subw #32,%d0 |account for ms mant being all zeros 390 subw %d7,%d0 |subtract shift count from exp 392 movew %d0,LOCAL_EX(%a0) |store ms mant 406 | d0: rounding precision 411 | d0 is guard,round,sticky 413 | d0 comes into this routine with the rounding precision. It 425 cmpib #0,%d0 |if 0 then extended precision 429 clrl %d0 |clear the sticky flag 436 cmpil #1,%d0 |if 1 then single precision 441 movel %d1,%d0 |copy d1 into d0 442 subw LOCAL_EX(%a0),%d0 |diff = threshold - exp 443 cmpw #67,%d0 |if diff > 67 (mant + grs bits) 446 clrl %d0 |else clear the sticky flag 454 movel %d1,%d0 |copy d1 into d0 455 subw LOCAL_EX(%a0),%d0 |diff = threshold - exp 456 cmpw #67,%d0 |if diff > 67 (mant + grs bits) 459 clrl %d0 |else clear the sticky flag 473 movel #0x20000000,%d0 |set sticky bit in return value 489 | d0{31:29} initial guard,round,sticky 493 | d0{31:29} final guard,round,sticky 507 movel #29,%d0 508 lsll %d0,%d2 |shift g,r,s to their positions 509 movel %d2,%d0 513 movel %d0,FP_SCR2+LOCAL_GRS(%a6) 514 movel %d1,%d0 |copy the denorm threshold 527 movel FP_SCR2+LOCAL_GRS(%a6),%d0 |restore original g,r,s 534 movew %d0,LOCAL_EX(%a0) |exponent = denorm threshold 535 movel #32,%d0 536 subw %d1,%d0 |d0 = 32 - d1 537 bfextu LOCAL_EX(%a0){%d0:#32},%d2 538 bfextu %d2{%d1:%d0},%d2 |d2 = new LOCAL_HI 539 bfextu LOCAL_HI(%a0){%d0:#32},%d1 |d1 = new LOCAL_LO 540 bfextu FP_SCR2+LOCAL_LO(%a6){%d0:#32},%d0 |d0 = new G,R,S 544 bftst %d0{#2:#30} 546 bsetl #rnd_stky_bit,%d0 553 orl #0x20000000,%d0 |set sticky bit in d0 555 andil #0xe0000000,%d0 |clear all but G,R,S 563 movew %d0,LOCAL_EX(%a0) |unsigned exponent = threshold 565 movel #32,%d0 566 subw %d1,%d0 |d0 = 32 - d1 567 bfextu LOCAL_EX(%a0){%d0:#32},%d2 568 bfextu %d2{%d1:%d0},%d2 |d2 = new LOCAL_LO 569 bfextu LOCAL_HI(%a0){%d0:#32},%d1 |d1 = new G,R,S 572 bftst FP_SCR2+LOCAL_LO(%a6){%d0:#32} 574 movel %d1,%d0 578 movel %d1,%d0 579 bsetl #rnd_stky_bit,%d0 588 orl #0x20000000,%d0 |set sticky bit in d0 590 andil #0xe0000000,%d0 |get rid of all but G,R,S 598 movew %d0,LOCAL_EX(%a0) 614 movel #0x20000000,%d0 619 movel LOCAL_HI(%a0),%d0 620 bfextu %d0{#2:#30},%d1 621 andil #0xc0000000,%d0 625 movel LOCAL_HI(%a0),%d0 626 bfextu %d0{#1:#31},%d1 627 andil #0x80000000,%d0 628 lsrl #1,%d0 |shift high bit into R bit 641 bsetl #rnd_stky_bit,%d0
H A D	x_snan.S	45 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 63 moveb FPCR_ENABLE(%a6),%d0 64 andb FPSR_EXCEPT(%a6),%d0 65 andib #0x3,%d0 72 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 92 moveql #13,%d0 |need to zero 14 lwords 95 moveql #11,%d0 |need to zero 12 lwords 100 dbra %d0,loop1 105 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 120 moveql #13,%d0 |need to zero 14 lwords 123 moveql #11,%d0 |need to zero 12 lwords 128 dbra %d0,loop2 133 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 146 bfextu CMDREG1B(%a6){#3:#3},%d0 |move rx field to d0{2:0} 147 cmpil #0,%d0 |check for long 150 cmpil #4,%d0 |check for word 153 cmpil #6,%d0 |check for byte 165 movel #4,%d0 |load byte count 187 movel #2,%d0 |load byte count 209 movel #1,%d0 |load byte count 234 movel %d0,-(%a7) |size 235 bsrl get_fline |returns fline word in d0 236 movel %d0,%d1 238 movel (%sp)+,%d0 |get original size 239 cmpil #4,%d0 241 cmpil #2,%d0 255 movel DTAG(%a6),%d0 256 bfextu %d0{#0:#3},%d0 |isolate dtag in lsbs 258 cmpib #3,%d0 |check for nan in destination 263 movew FPTEMP_EX(%a6),%d0 266 movew ETEMP_EX(%a6),%d0 268 btstl #15,%d0 |test for sign of snan
H A D	util.S	106 movew CMDREG3B(%a6),%d0 |get the command word 107 andiw #0x00000060,%d0 |clear all bits except 6 and 5 108 cmpil #0x00000040,%d0 110 cmpil #0x00000060,%d0 112 movew CMDREG3B(%a6),%d0 |get the command word again 113 andil #0x7f,%d0 |clear all except operation 114 cmpil #0x33,%d0 116 cmpil #0x30,%d0 121 movew CMDREG1B(%a6),%d0 |get command word 122 andil #0x00000044,%d0 |clear all bits except 6 and 2 123 cmpil #0x00000040,%d0 125 cmpil #0x00000044,%d0 127 movew CMDREG1B(%a6),%d0 |again get the command word 128 andil #0x0000007f,%d0 |clear all except the op code 129 cmpil #0x00000027,%d0 131 cmpil #0x00000024,%d0 139 clrl %d0 143 movel #0x00000001,%d0 |set single 146 movel #0x00000002,%d0 |set double 152 bfextu FPCR_MODE(%a6){#0:#2},%d0 |set round precision 168 bsr g_dfmtou |get dest fmt in d0{1:0} 182 lsll #2,%d0 |move round precision to d0{3:2} 184 orl %d1,%d0 |index is fmt:mode in d0{3:0} 186 movel %a1@(%d0:l:4),%a1 |use d0 as index to the table 303 | Returns opcode in the low word of d0. 309 movel #2,%d0 |count 311 movel (%a7)+,%d0 314 | g_rndpr --- put rounding precision in d0{1:0} 344 bsr g_opcls |get opclass in d0{2:0} 345 cmpw #0x0003,%d0 |check for opclass 011 358 movel CMDREG3B(%a6),%d0 |rounding precision in d0{10:9} 359 bfextu %d0{#9:#2},%d0 |move the rounding prec bits to d0{1:0} 360 cmpil #0x2,%d0 362 cmpil #0x3,%d0 |force precision is double 364 movew CMDREG3B(%a6),%d0 |get the command word again 365 andil #0x7f,%d0 |clear all except operation 366 cmpil #0x33,%d0 368 cmpil #0x30,%d0 372 movel CMDREG1B(%a6),%d0 |get 32 bits off the stack, 1st 16 bits 374 andil #0x00440000,%d0 |clear all bits except bits 6 and 2 375 cmpil #0x00400000,%d0 377 cmpil #0x00440000,%d0 |force double 379 movel CMDREG1B(%a6),%d0 |get the command word again 380 andil #0x007f0000,%d0 |clear all bits except the operation 381 cmpil #0x00270000,%d0 383 cmpil #0x00240000,%d0 398 movel #1,%d0 |return 1 404 movel #2,%d0 |return 2 410 movel #0,%d0 416 movel USER_FPCR(%a6),%d0 |rounding precision bits in d0{7:6} 417 bfextu %d0{#24:#2},%d0 |move the rounding prec bits to d0{1:0} 420 | g_opcls --- put opclass in d0{2:0} 426 clrl %d0 |if E3, only opclass 0x0 is possible 429 movel CMDREG1B(%a6),%d0 430 bfextu %d0{#0:#3},%d0 |shift opclass bits d0{31:29} to d0{2:0} 433 | g_dfmtou --- put destination format in d0{1:0} 446 clrl %d0 |if E1, size is always ext 449 movel CMDREG1B(%a6),%d0 450 bfextu %d0{#3:#3},%d0 |dest fmt from cmdreg1b{12:10} 451 cmpb #1,%d0 |check for single 453 movel #1,%d0 456 cmpb #5,%d0 |check for double 458 movel #2,%d0 461 clrl %d0 |must be extended 485 | d0 contains round precision 512 lsll #2,%d0 |move round precision to d0{3:2} 514 orl %d1,%d0 |index is fmt:mode in d0{3:0} 516 movel %a1@(%d0:l:4),%a1 |use d0 as index to the table
H A D	ssinh.S	78 movel (%a0),%d0 79 movew 4(%a0),%d0 80 movel %d0,%a1 | save a copy of original (compacted) operand 81 andl #0x7FFFFFFF,%d0 82 cmpl #0x400CB167,%d0 101 movel %a1,%d0 102 andl #0x80000000,%d0 103 orl #0x3F000000,%d0 105 movel %d0,-(%sp) 113 cmpl #0x400CB2B3,%d0 119 movel %a1,%d0 120 andl #0x80000000,%d0 121 orl #0x7FFB0000,%d0 122 movel %d0,-(%sp) | ...EXTENDED FMT
H A D	res_func.S	99 movew CMDREG1B(%a6),%d0 |get command register 100 andil #0x7f,%d0 |strip to only command word 107 btstl #0,%d0 116 movew CMDREG1B(%a6),%d0 117 andib #0x3b,%d0 |isolate bits to select inst 118 tstb %d0 120 cmpib #0x18,%d0 122 cmpib #0x1a,%d0 129 movew LOCAL_EX(%a0),%d0 130 bclrl #15,%d0 135 cmpiw #0x7fff,%d0 |test for inf/nan 162 moveb STAG(%a6),%d0 163 btstl #5,%d0 |test for NaN or zero 172 moveb STAG(%a6),%d0 173 btstl #5,%d0 |test for NaN or zero 184 moveb STAG(%a6),%d0 185 andib #0xe0,%d0 |isolate stag bits 197 bfextu FPCR_MODE(%a6){#0:#2},%d0 198 tstb %d0 |check for extended 200 cmpib #1,%d0 |check for single 206 movel #2,%d0 |set up the size for denorm 213 clrl %d0 |clear g,r,s for round 230 movel #1,%d0 237 clrl %d0 303 movel USER_FPCR(%a6),%d0 304 andil #0x30,%d0 |isolate rmode 305 cmpil #0x20,%d0 327 moveb STAG(%a6),%d0 328 andib #0xe0,%d0 329 cmpib #0x40,%d0 |check if input was tagged zero 373 movew CMDREG1B(%a6),%d0 |get command register 374 andil #0x7f,%d0 |strip to only command word 381 btstl #0,%d0 419 movew CMDREG1B(%a6),%d0 420 andib #0x3b,%d0 |isolate bits to select inst 421 tstb %d0 423 cmpib #0x18,%d0 425 cmpib #0x1a,%d0 432 movew LOCAL_EX(%a0),%d0 433 bclrl #15,%d0 438 cmpiw #0x7fff,%d0 |test for inf/nan 490 bfextu FPCR_MODE(%a6){#0:#2},%d0 491 tstb %d0 |check for extended 493 cmpib #1,%d0 |check for single 680 movew CMDREG1B(%a6),%d0 681 andiw #0x3b,%d0 |strip to command bits 682 cmpiw #addcode,%d0 684 cmpiw #subcode,%d0 686 cmpiw #mulcode,%d0 688 cmpiw #cmpcode,%d0 705 bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) 707 subl %d1,%d0 |subtract dest from src 708 cmpl #0x7fff,%d0 711 movew ETEMP_EX(%a6),%d0 |find the sign of the result 713 eorw %d1,%d0 714 andiw #0x8000,%d0 720 moveb STAG(%a6),%d0 |check source tag for inf or nan 723 moveb DTAG(%a6),%d0 |check destination tag for inf or nan 725 andib #0x60,%d0 |isolate tag bits 726 cmpb #0x40,%d0 |is it inf? 728 cmpb #0x60,%d0 |is it nan? 730 cmpb #0x20,%d0 |is it a zero? 732 clrl %d0 736 moveql #-1,%d0 744 bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) 746 subl %d1,%d0 |subtract src from dest 747 cmpl #0x8000,%d0 750 movew ETEMP_EX(%a6),%d0 |find the sign of the result 752 eorw %d1,%d0 753 andiw #0x8000,%d0 765 movew CMDREG1B(%a6),%d0 766 btstl #6,%d0 |test for forced precision 768 btstl #2,%d0 |check for double 770 movel #0x1,%d0 |inst is forced single 773 movel #0x2,%d0 |inst is forced double 776 bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec 781 | tst.b %d0 809 bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) 811 subl %d1,%d0 |subtract dest from src 812 cmpl #0x8000,%d0 818 bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) 820 subl %d1,%d0 |subtract src from dest 821 cmpl #0x8000,%d0 834 movew ETEMP_EX(%a6),%d0 836 eorw %d1,%d0 837 andiw #0x8000,%d0 844 movew FPTEMP_EX(%a6),%d0 845 andiw #0x8000,%d0 846 orw #0x3fff,%d0 |force the exponent to +/- 1 847 movew %d0,FPTEMP_EX(%a6) |in the denorm 848 movel USER_FPCR(%a6),%d0 849 andil #0x30,%d0 850 fmovel %d0,%fpcr |set up users rmode and X 857 lsrl #4,%d0 |put rmode in lower 2 bits 862 orl %d0,%d1 |set up for round call 863 clrl %d0 |force sticky to zero 872 movew ETEMP_EX(%a6),%d0 873 andiw #0x8000,%d0 874 orw #0x3fff,%d0 |force the exponent to +/- 1 875 movew %d0,ETEMP_EX(%a6) |in the denorm 876 movel USER_FPCR(%a6),%d0 877 andil #0x30,%d0 878 fmovel %d0,%fpcr |set up users rmode and X 885 lsrl #4,%d0 |put rmode in lower 2 bits 890 orl %d0,%d1 |set up for round call 891 clrl %d0 |force sticky to zero 907 movel USER_FPCR(%a6),%d0 908 andil #0x30,%d0 909 lsrl #4,%d0 |put rmode in lower 2 bits 914 orl %d0,%d1 |set up for round call 915 movel #0x20000000,%d0 |set sticky for round 933 movel USER_FPCR(%a6),%d0 934 andil #0x30,%d0 935 lsrl #4,%d0 |put rmode in lower 2 bits 940 orl %d0,%d1 |set up for round call 941 movel #0x20000000,%d0 |set sticky for round 957 movew WBTEMP_EX(%a6),%d0 958 andiw #0x7fff,%d0 959 cmpiw #0x7fff,%d0 984 bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) 986 subl %d1,%d0 |subtract src from dest 987 cmpl #0x8000,%d0 993 bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) 995 subl %d1,%d0 |subtract dest from src 996 cmpl #0x8000,%d0 1009 movew ETEMP_EX(%a6),%d0 1011 eorw %d1,%d0 1012 andiw #0x8000,%d0 1019 movew FPTEMP_EX(%a6),%d0 1020 andiw #0x8000,%d0 1021 orw #0x3fff,%d0 |force the exponent to +/- 1 1022 movew %d0,FPTEMP_EX(%a6) |in the denorm 1023 movel USER_FPCR(%a6),%d0 1024 andil #0x30,%d0 1025 fmovel %d0,%fpcr |set up users rmode and X 1032 lsrl #4,%d0 |put rmode in lower 2 bits 1037 orl %d0,%d1 |set up for round call 1038 clrl %d0 |force sticky to zero 1047 movew ETEMP_EX(%a6),%d0 1048 andiw #0x8000,%d0 1049 orw #0x3fff,%d0 |force the exponent to +/- 1 1050 movew %d0,ETEMP_EX(%a6) |in the denorm 1051 movel USER_FPCR(%a6),%d0 1052 andil #0x30,%d0 1053 fmovel %d0,%fpcr |set up users rmode and X 1060 lsrl #4,%d0 |put rmode in lower 2 bits 1065 orl %d0,%d1 |set up for round call 1066 clrl %d0 |force sticky to zero 1082 movel USER_FPCR(%a6),%d0 1083 andil #0x30,%d0 1084 lsrl #4,%d0 |put rmode in lower 2 bits 1089 orl %d0,%d1 |set up for round call 1090 movel #0x20000000,%d0 |set sticky for round 1114 movel USER_FPCR(%a6),%d0 1115 andil #0x30,%d0 1116 lsrl #4,%d0 |put rmode in lower 2 bits 1121 orl %d0,%d1 |set up for round call 1122 movel #0x20000000,%d0 |set sticky for round 1138 movew WBTEMP_EX(%a6),%d0 1139 andiw #0x7fff,%d0 1140 cmpiw #0x7fff,%d0 1165 bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) 1167 subl %d1,%d0 |subtract dest from src 1168 cmpl #0x8000,%d0 1176 bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) 1178 subl %d1,%d0 |subtract src from dest 1179 cmpl #0x8000,%d0 1203 bfextu ETEMP_EX(%a6){#1:#15},%d0 |get src exp (always pos) 1205 addl %d1,%d0 |subtract dest from src 1211 bfextu FPTEMP_EX(%a6){#1:#15},%d0 |get dest exp (always pos) 1213 addl %d1,%d0 |subtract src from dest 1225 movew ETEMP_EX(%a6),%d0 |find the sign of the result 1227 eorw %d1,%d0 1228 andiw #0x8000,%d0 1233 movew CMDREG1B(%a6),%d0 1234 btstl #6,%d0 |test for forced precision 1236 btstl #2,%d0 |check for double 1238 movel #0x1,%d0 |inst is forced single 1241 movel #0x2,%d0 |inst is forced double 1244 bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec 1261 movew CMDREG1B(%a6),%d0 1262 btstl #6,%d0 |test for forced precision 1264 btstl #2,%d0 |check for double 1266 movel #0x1,%d0 |inst is forced single 1269 movel #0x2,%d0 |inst is forced double 1272 bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec 1273 tstb %d0 1290 bfextu CMDREG1B(%a6){#6:#3},%d0 |extract fp destination register 1291 cmpib #3,%d0 1294 subl %d0,%d1 1295 clrl %d0 1296 bsetl %d1,%d0 1297 fmovemx WBTEMP(%a6),%d0 1300 cmpib #0,%d0 1302 cmpib #1,%d0 1304 cmpib #2,%d0 1350 moveb STAG(%a6),%d0 |check if stag is inf 1351 andib #0xe0,%d0 1352 cmpib #0x40,%d0 1360 cmpib #0x60,%d0 |check if stag is NaN 1370 cmpib #0x20,%d0 |check if zero 1377 bfextu CMDREG1B(%a6){#6:#3},%d0 |extract fp destination register 1378 cmpib #3,%d0 1381 subl %d0,%d1 1382 clrl %d0 1383 bsetl %d1,%d0 1384 fmovemx ETEMP(%a6),%d0 1388 cmpib #0,%d0 1390 cmpib #1,%d0 1392 cmpib #2,%d0 1417 movew CMDREG1B(%a6),%d0 |check if packed moveout 1418 andiw #0x0c00,%d0 |isolate last 2 bits of size field 1419 cmpiw #0x0c00,%d0 |if size is 011 or 111, it is packed 1490 moveql #4,%d0 |set byte count 1535 moveql #2,%d0 |set byte count 1580 moveql #1,%d0 |set byte count 1625 | byte-width (store in d0) of result must be honored. In the second case, 1643 addal %d0,%a1 | offset by destination width -1 1667 movel %d0,-(%sp) |d0 currently contains the size to write 1668 bsrl get_fline |get_fline returns Dn in d0 1669 andiw #0x7,%d0 |isolate register 1675 orl #8,%d0 |add 'word' size to register# 1678 orl #0x10,%d0 |add 'long' size to register# 1680 movel %d0,%d1 |reg_dest expects size:reg in d1 1689 clrl %d0 1697 movew LOCAL_EX(%a0),%d0 1699 cmpw (%a1),%d0 1701 cmpw 2(%a1),%d0 1703 movel #1,%d0 |set destination format to single 1713 movew LOCAL_EX(%a0),%d0 1716 cmpw (%a1),%d0 1718 cmpw 2(%a1),%d0 1721 movel #2,%d0 |set destination format to double 1726 swap %d0 |rnd prec in upper word 1727 addl %d0,%d1 |d1 has PREC/MODE info 1729 clrl %d0 |clear g,r,s 1770 cmpw 4(%a1),%d0 1773 movel #1,%d0 |load in round precision 1784 cmpw 4(%a1),%d0 1788 movel #2,%d0 1791 | ;expects d0 to have round precision 1803 movel #1,%d0 |set round precision to sgl 1809 movel #1,%d0 1810 subw %d0,LOCAL_EX(%a0) |account for difference between 1824 movel #2,%d0 |set round precision to dbl 1829 movel #1,%d0 1830 subw %d0,LOCAL_EX(%a0) |account for difference between 1847 movel #1,%d0 1866 movel #2,%d0 1890 | d0 is the round precision (=1 for sgl; =2 for dbl) 1901 movel %d0,-(%a7) |save round precision 1902 clrl %d0 |clear initial g,r,s 1903 bsrl dnrm_lp |careful with d0, it's needed by round 1912 movew #1,%d0 1913 subw %d0,LOCAL_EX(%a0) |account for difference in denorm 1955 movew STAG(%a6),%d0 |get source tag 1956 bfextu %d0{#16:#3},%d0 |isolate source bits 1957 movel (%a0,%d0.w*4),%a0 |load a0 with routine label for tag 1961 movel #0x0c,%d0 |get byte count 1980 movew CMDREG1B(%a6),%d0 1981 btstl #kfact_bit,%d0 |test for dynamic k-factor 1984 bfextu %d0{#25:#3},%d0 |isolate register for dynamic k-factor 1986 movel %a0@(%d0:l:4),%a0 1989 andiw #0x007f,%d0 |get k-factor 1990 bfexts %d0{#25:#7},%d0 |sign extend d0 for bindec 2015 movel USER_D0(%a6),%d0 2018 movel USER_D1(%a6),%d0 2021 movel %d2,%d0 2024 movel %d3,%d0 2027 movel %d4,%d0 2030 movel %d5,%d0 2033 movel %d6,%d0 2036 movel %d7,%d0
H A D	ssin.S	184 movel (%a0),%d0 185 movew 4(%a0),%d0 187 andil #0x7FFFFFFF,%d0 | ...COMPACTIFY X 189 cmpil #0x3FD78000,%d0 | ...|X| >= 2**(-40)? 194 cmpil #0x4004BC7E,%d0 | ...|X| < 15 PI? 211 movel N(%a6),%d0 212 asll #4,%d0 213 addal %d0,%a1 | ...A1 IS THE ADDRESS OF N*PIBY2 224 movel N(%a6),%d0 225 addl ADJN(%a6),%d0 | ...SEE IF D0 IS ODD OR EVEN 226 rorl #1,%d0 | ...D0 WAS ODD IFF D0 IS NEGATIVE 227 cmpil #0,%d0 249 rorl #1,%d0 250 andil #0x80000000,%d0 252 eorl %d0,X(%a6) | ...X IS NOW R'= SGN*R 305 rorl #1,%d0 306 andil #0x80000000,%d0 311 eorl %d0,X(%a6) | ...X IS NOW S'= SGN*S 312 andil #0x80000000,%d0 316 oril #0x3F800000,%d0 | ...D0 IS SGN IN SINGLE 317 movel %d0,POSNEG1(%a6) 352 cmpil #0x3FFF8000,%d0 357 movel ADJN(%a6),%d0 358 cmpil #0,%d0 384 |--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that 388 cmpil #0x7ffeffff,%d0 |is argument dangerously large? 415 movew INARG(%a6),%d0 416 movel %d0,%a1 | ...save a copy of D0 417 andil #0x00007FFF,%d0 418 subil #0x00003FFF,%d0 | ...D0 IS K 419 cmpil #28,%d0 422 subil #27,%d0 | ...D0 IS L := K-27 426 clrl %d0 | ...D0 IS L := 0 437 subl %d0,%d2 | ...BIASED EXPO OF 2**(-L)*(2/PI) 458 movel %d0,%d2 473 addil #0x00003FDD,%d0 474 movew %d0,FP_SCR3(%a6) 479 movel ENDFLAG(%a6),%d0 503 cmpil #0,%d0 517 movel ADJN(%a6),%d0 518 cmpil #4,%d0 538 movel (%a0),%d0 539 movew 4(%a0),%d0 541 andil #0x7FFFFFFF,%d0 | ...COMPACTIFY X 543 cmpil #0x3FD78000,%d0 | ...|X| >= 2**(-40)? 548 cmpil #0x4004BC7E,%d0 | ...|X| < 15 PI? 566 movel N(%a6),%d0 567 asll #4,%d0 568 addal %d0,%a1 | ...ADDRESS OF N*PIBY2, IN Y1, Y2 577 movel N(%a6),%d0 578 rorl #1,%d0 580 cmpil #0,%d0 | ...D0 < 0 IFF N IS ODD 592 movel %d0,%d2 598 eorl %d0,%d2 606 rorl #1,%d0 607 andil #0x80000000,%d0 611 eorl %d0,POSNEG1(%a6) 619 eorl %d0,SPRIME(%a6) 670 rorl #1,%d0 671 andil #0x80000000,%d0 674 eorl %d0,RPRIME(%a6) 675 eorl %d0,SPRIME(%a6) 677 oril #0x3F800000,%d0 678 movel %d0,POSNEG1(%a6) 728 cmpil #0x3FFF8000,%d0
H A D	sasin.S	65 movel (%a0),%d0 66 movew 4(%a0),%d0 67 andil #0x7FFFFFFF,%d0 68 cmpil #0x3FFF8000,%d0 95 movel (%a0),%d0 96 andil #0x80000000,%d0 | ...SIGN BIT OF X 97 oril #0x3F800000,%d0 | ...+-1 IN SGL FORMAT 98 movel %d0,-(%sp) | ...push SIGN(X) IN SGL-FMT
H A D	satanh.S	69 movel (%a0),%d0 70 movew 4(%a0),%d0 71 andil #0x7FFFFFFF,%d0 72 cmpil #0x3FFF8000,%d0 84 movel (%a0),%d0 85 andil #0x80000000,%d0 86 oril #0x3F000000,%d0 | ...SIGN(X)*HALF 87 movel %d0,-(%sp)
H A D	x_unfl.S	48 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 67 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no 68 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 73 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 86 moveb FPCR_ENABLE(%a6),%d0 87 andb FPSR_EXCEPT(%a6),%d0 88 andib #0x3,%d0 101 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no 102 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 108 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 122 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no 123 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 127 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 134 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 143 bsrl g_rndpr |returns RND_PREC in d0 0=ext, 148 movew %d0,-(%a7) |copy RND_PREC to stack 170 clrl %d0 183 | ;d0 has guard,round sticky bit 196 | WARNING: a0 and d0 are assumed to be intact between the denorm and 198 | must not corrupt a0 and d0. 203 | d0{31:29} has guard, round, sticky 214 bsrl g_opcls |returns opclass in d0{2:0} 215 cmpib #0x3,%d0 222 tstb %d0
H A D	smovecr.S	45 bfextu CMDREG1B(%a6){#9:#7},%d0 |get offset 50 tstb %d0 |if zero, offset is to pi 52 cmpib #0x0a,%d0 |check range $01 - $0a 54 cmpib #0x0e,%d0 |check range $0b - $0e 56 cmpib #0x2f,%d0 |check range $10 - $2f 58 cmpib #0x3f,%d0 |check range $30 - $3f 78 subil #0xb,%d0 |make offset in 0 - 4 range 85 cmpib #0x2,%d0 |check if result is inex 90 cmpib #0x2,%d0 |check if result is inex 95 cmpib #0x2,%d0 |check if result is inex 99 subil #0x30,%d0 |make offset in 0 - f range 106 cmpib #0x1,%d0 |check if result is inex 108 cmpib #0x7,%d0 |second check 113 cmpib #0x1,%d0 |check if result is inex 115 cmpib #0x7,%d0 |second check 120 cmpib #0x1,%d0 |check if result is inex 122 cmpib #0x7,%d0 |second check 128 mulul #12,%d0 |use offset to point into tables 136 fmovemx (%a0,%d0),%fp0-%fp0 |return result in fp0 144 movel (%a0,%d0),FP_SCR1(%a6) |load first word to temp storage 145 movel 4(%a0,%d0),FP_SCR1+4(%a6) |load second word 146 movel 8(%a0,%d0),FP_SCR1+8(%a6) |load third word 147 clrl %d0 |clear g,r,s
H A D	srem_mod.S	156 movew -12(%a0),%d0 157 movew %d0,SignX(%a6) 159 eorl %d0,%d1 162 andil #0x00007FFF,%d0 165 tstl %d0 167 movel #0x00003FFE,%d0 174 subil #32,%d0 178 subl %d6,%d0 | ...(D0,D1,D2) is normalized 185 subl %d6,%d0 197 addil #0x00003FFE,%d0 | ...(D0,D1,D2) normalized 203 movel %d0,L_SCR2(%a6) |save d0 204 subl %d3,%d0 | ...L := expo(X)-expo(Y) 211 tstl %d0 216 movel L_SCR2(%a6),%d0 |restore d0 249 tstl %d0 | ...see if j = 0. 257 subql #1,%d0 | ...j := j - 1 266 movel L_SCR1(%a6),%d0 | ...new biased expo of R 273 subil #32,%d0 277 subl %d6,%d0 | ...(D0,D1,D2) is normalized 285 subl %d6,%d0 296 cmpil #0x000041FE,%d0 299 movew %d0,R(%a6) 314 subil #0x3FFE,%d0 315 movew %d0,R(%a6) 335 cmpl %d6,%d0 380 movel Sc_Flag(%a6),%d0 393 cmpil #8,%d0 | ...D0 is j 396 lsll %d0,%d3
H A D	stwotox.S	201 movel (%a0),%d0 202 orl #0x00800001,%d0 203 fadds %d0,%fp0 211 movel (%a0),%d0 212 movew 4(%a0),%d0 214 andil #0x7FFFFFFF,%d0 216 cmpil #0x3FB98000,%d0 | ...|X| >= 2**(-70)? 221 cmpil #0x400D80C0,%d0 | ...|X| > 16480? 236 movel N(%a6),%d0 237 movel %d0,%d2 238 andil #0x3F,%d0 | ...D0 IS J 239 asll #4,%d0 | ...DISPLACEMENT FOR 2^(J/64) 240 addal %d0,%a1 | ...ADDRESS FOR 2^(J/64) 242 movel %d2,%d0 243 asrl #1,%d0 | ...D0 IS M 244 subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J 265 addw %d0,FACT1(%a6) 268 addw %d0,FACT2(%a6) 274 cmpil #0x3FFF8000,%d0 288 movel X(%a6),%d0 289 cmpil #0,%d0 305 movel (%a0),%d0 306 orl #0x00800001,%d0 307 fadds %d0,%fp0 315 movel (%a0),%d0 316 movew 4(%a0),%d0 318 andil #0x7FFFFFFF,%d0 320 cmpil #0x3FB98000,%d0 | ...|X| >= 2**(-70)? 325 cmpil #0x400B9B07,%d0 | ...|X| <= 16480*log2/log10 ? 339 movel N(%a6),%d0 340 movel %d0,%d2 341 andil #0x3F,%d0 | ...D0 IS J 342 asll #4,%d0 | ...DISPLACEMENT FOR 2^(J/64) 343 addal %d0,%a1 | ...ADDRESS FOR 2^(J/64) 345 movel %d2,%d0 346 asrl #1,%d0 | ...D0 IS M 347 subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J 378 addw %d0,FACT1(%a6) 379 addw %d0,FACT2(%a6)
H A D	x_unimp.S	46 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 49 moveb (%a7),%d0 |test for valid version num 50 andib #0xf0,%d0 |test for $4x 51 cmpib #VER_4,%d0 |must be $4x or exit 58 movel USER_FPSR(%a6),%d0 59 andl #0xFF00FF,%d0 |clear all but accrued exceptions 60 movel %d0,USER_FPSR(%a6)
H A D	x_fline.S	49 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 52 movel #4,%d0 58 movel L_SCR1(%a6),%d0 |d0 contains the fline and command word 59 bfextu %d0{#4:#3},%d1 |extract coprocessor id 62 bfextu %d0{#16:#6},%d1 90 movew %d0,CMDREG1B(%a6) |move the lower word into CMDREG1B 93 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers 97 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 |restore data registers
H A D	slog2.S	118 movel (%a0),%d0 131 movel (%a0),%d0 145 movel (%a0),%d0 157 movel (%a0),%d0 160 movel 8(%a0),%d0 163 movel 4(%a0),%d0 164 andl #0x7FFFFFFF,%d0 165 tstl %d0 169 movew (%a0),%d0 170 andl #0x00007FFF,%d0 171 subl #0x3FFF,%d0 173 fmovel %d0,%fp0
H A D	decbin.S	133 | (*) d0: temp digit storage 154 bfextu %d4{%d3:#4},%d0 |get the digit and zero extend into d0 155 addl %d0,%d1 |d1 = d1 + d0 179 | (*) d0: temp digit storage 199 bfextu (%a0){#28:#4},%d0 |integer part is ls digit in long word 200 faddb %d0,%fp0 |add digit to sum in fp0 211 bfextu %d4{%d3:#4},%d0 |get the digit and zero extend 212 faddb %d0,%fp0 |fp0 = fp0 + digit 269 | (*) d0: temp digit storage 293 bfextu %d4{#28:#4},%d0 |get M16 in d0 306 bfextu %d4{%d3:#4},%d0 |get digit 312 movel %d1,%d0 |copy counter to d2 314 subl %d0,%d1 |subtract count from exp 330 asrl #1,%d0 |shift lsb into carry 335 tstl %d0 |check if d0 is zero 354 bfextu %d4{%d3:#4},%d0 |get digit 360 movel %d1,%d0 |copy counter to d0 362 subl %d0,%d1 |subtract count from exp 378 asrl #1,%d0 |shift lsb into carry 383 tstl %d0 |check if d0 is zero 393 | (*) d0: temp 400 | (*) d0: temp 435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE} 436 addl %d0,%d2 |in d2 as index into RTABLE 438 moveb (%a1,%d2),%d0 |load new rounding bits from table 440 bfins %d0,%d3{#26:#2} |stuff new rounding bits in FPCR 442 asrl #1,%d0 |write correct PTENxx table 447 asrl #1,%d0 |keep checking 454 movel %d1,%d0 |copy exp to d0;use d0 456 negl %d0 |invert it 462 asrl #1,%d0 |shift next bit into carry 467 tstl %d0 |check if d0 is zero 497 fmovel %FPSR,%d0 |get status register 498 bclrl #inex2_bit+8,%d0 |test for inex2 and clear it 499 fmovel %d0,%FPSR |return status reg w/o inex2
H A D	bugfix.S	180 moveb CU_SAVEPC(%a6),%d0 181 andib #0xFE,%d0 193 movew CMDREG1B(%a6),%d0 194 andiw #0xE000,%d0 |strip all but opclass 200 bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src 202 cmpb %d0,%d1 208 bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest 209 cmpb %d0,%d1 |cmp 1st dest with 3rd dest 215 cmpb %d0,%d1 |cmp 1st dest with 2nd dest 217 bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src 218 cmpb %d0,%d1 |cmp 1st src with 2nd dest 225 bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no 227 subl %d0,%d1 228 clrl %d0 229 bsetl %d1,%d0 230 fmovemx %d0,ETEMP(%a6) |load source to ETEMP 232 moveb #0x12,%d0 233 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended 285 bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no 286 cmpil #3,%d0 289 cmpil #1,%d0 308 movel #22,%d0 |clear 23 lwords 312 dbf %d0,op0_loop 319 bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no 321 subl %d0,%d1 322 clrl %d0 323 bsetl %d1,%d0 324 fmovemx %d0,ETEMP(%a6) |load source to ETEMP 326 moveb #0x12,%d0 327 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended 351 movew CMDREG1B(%a6),%d0 352 andiw #0xFC00,%d0 |strip all but opclass and size 353 cmpiw #0x4400,%d0 |test for opclass 2 and size=sgl 360 bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest 362 cmpb %d0,%d1 |cmp 1st dest with 3rd dest 365 cmpb %d0,%d1 |cmp 1st dest with 2nd dest 411 bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no 412 cmpil #3,%d0 415 cmpil #1,%d0 434 movel #22,%d0 |clear 23 lwords 438 dbf %d0,op2_loop 454 moveb #0x15,%d0 455 bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, double
H A D	setox.S	451 movel (%a0),%d0 452 andil #0x80000000,%d0 453 oril #0x00800000,%d0 | ...sign(X)*2^(-126) 454 movel %d0,-(%sp) 465 movel (%a0),%d0 | ...load part of input X 466 andil #0x7FFF0000,%d0 | ...biased expo. of X 467 cmpil #0x3FBE0000,%d0 | ...2^(-65) 473 movew 4(%a0),%d0 | ...expo. and partial sig. of |X| 474 cmpil #0x400CB167,%d0 | ...16380 log2 trunc. 16 bits 487 fmovel %fp0,%d0 | ...N = int( X * 64/log2 ) 489 fmovel %d0,%fp0 | ...convert to floating-format 491 movel %d0,L_SCR1(%a6) | ...save N temporarily 492 andil #0x3F,%d0 | ...D0 is J = N mod 64 493 lsll #4,%d0 494 addal %d0,%a1 | ...address of 2^(J/64) 495 movel L_SCR1(%a6),%d0 496 asrl #6,%d0 | ...D0 is M 497 addiw #0x3FFF,%d0 | ...biased expo. of 2^(M) 531 movew %d0,SCALE(%a6) | ...SCALE is 2^(M) in extended 558 movel ADJFLAG(%a6),%d0 561 tstl %d0 579 cmpil #0x400CB27C,%d0 | ...16480 log2 588 fmovel %fp0,%d0 | ...N = int( X * 64/log2 ) 590 fmovel %d0,%fp0 | ...convert to floating-format 591 movel %d0,L_SCR1(%a6) | ...save N temporarily 592 andil #0x3F,%d0 | ...D0 is J = N mod 64 593 lsll #4,%d0 594 addal %d0,%a1 | ...address of 2^(J/64) 595 movel L_SCR1(%a6),%d0 596 asrl #6,%d0 | ...D0 is K 597 movel %d0,L_SCR1(%a6) | ...save K temporarily 598 asrl #1,%d0 | ...D0 is M1 599 subl %d0,L_SCR1(%a6) | ...a1 is M 600 addiw #0x3FFF,%d0 | ...biased expo. of 2^(M1) 601 movew %d0,ADJSCALE(%a6) | ...ADJSCALE := 2^(M1) 605 movel L_SCR1(%a6),%d0 | ...D0 is M 606 addiw #0x3FFF,%d0 | ...biased expo. of 2^(M) 612 movel (%a0),%d0 614 cmpil #0,%d0 631 movel (%a0),%d0 | ...load part of input X 632 andil #0x7FFF0000,%d0 | ...biased expo. of X 633 cmpil #0x3FFD0000,%d0 | ...1/4 640 movew 4(%a0),%d0 | ...expo. and partial sig. of |X| 641 cmpil #0x4004C215,%d0 | ...70log2 rounded up to 16 bits 654 fmovel %fp0,%d0 | ...N = int( X * 64/log2 ) 656 fmovel %d0,%fp0 | ...convert to floating-format 658 movel %d0,L_SCR1(%a6) | ...save N temporarily 659 andil #0x3F,%d0 | ...D0 is J = N mod 64 660 lsll #4,%d0 661 addal %d0,%a1 | ...address of 2^(J/64) 662 movel L_SCR1(%a6),%d0 663 asrl #6,%d0 | ...D0 is M 664 movel %d0,L_SCR1(%a6) | ...save a copy of M 676 addiw #0x3FFF,%d0 | ...D0 is biased expo. of 2^M 696 movew %d0,SC(%a6) | ...SC is 2^(M) in extended 702 movel L_SCR1(%a6),%d0 | ...D0 is M 703 negw %d0 | ...D0 is -M 705 addiw #0x3FFF,%d0 | ...biased expo. of 2^(-M) 710 oriw #0x8000,%d0 | ...signed/expo. of -2^(-M) 711 movew %d0,ONEBYSC(%a6) | ...OnebySc is -2^(-M) 733 movel L_SCR1(%a6),%d0 | ...retrieve M 734 cmpil #63,%d0 744 cmpil #-3,%d0 768 cmpil #0x3FBE0000,%d0 | ...2^(-65) 773 cmpil #0x00330000,%d0 | ...2^(-16312) 854 movel (%a0),%d0 855 cmpil #0,%d0
H A D	stan.S	173 movel (%a0),%d0 174 movew 4(%a0),%d0 175 andil #0x7FFFFFFF,%d0 177 cmpil #0x3FD78000,%d0 | ...|X| >= 2**(-40)? 181 cmpil #0x4004BC7E,%d0 | ...|X| < 15 PI? 196 fmovel %fp1,%d0 | ...CONVERT TO INTEGER 198 asll #4,%d0 199 addal %d0,%a1 | ...ADDRESS N*PIBY2 IN Y1, Y2 206 rorl #5,%d0 207 andil #0x80000000,%d0 | ...D0 WAS ODD IFF D0 < 0 211 cmpil #0,%d0 294 cmpil #0x3FFF8000,%d0 315 |--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that 319 cmpil #0x7ffeffff,%d0 |is argument dangerously large? 346 movew INARG(%a6),%d0 347 movel %d0,%a1 | ...save a copy of D0 348 andil #0x00007FFF,%d0 349 subil #0x00003FFF,%d0 | ...D0 IS K 350 cmpil #28,%d0 353 subil #27,%d0 | ...D0 IS L := K-27 357 clrl %d0 | ...D0 IS L := 0 368 subl %d0,%d2 | ...BIASED EXPO OF 2**(-L)*(2/PI) 389 movel %d0,%d2 404 addil #0x00003FDD,%d0 405 movew %d0,FP_SCR3(%a6) 410 movel ENDFLAG(%a6),%d0 434 cmpil #0,%d0 448 movel N(%a6),%d0 449 rorl #1,%d0
H A D	scale.S	55 movew ETEMP(%a6),%d0 |check src bounds 56 andiw #0x7fff,%d0 |clr sign bit 57 cmp2w SRC_BNDS,%d0 59 cmpiw #0x400c,%d0 |test for too large 66 moveb DTAG(%a6),%d0 67 andib #0xe0,%d0 68 tstb %d0 83 | move it to d0. 88 fmovel %fp0,%d0 |int src to d0 100 addl %d0,%d1 |add src to dest exp 147 addl %d0,%d1 |add src to dest 169 movew %d1,%d0 |use d0 for exp 175 addw #1,%d0 |drive d0 to 0 181 tstw %d0 |it is finished when 182 blts fix_loop |d0 is zero or the mantissa 308 tstl %d0 |otherwise, test shift count 310 subil #1,%d0 |dec src 319 addw %d0,%d1 |dst is normalized; add src
H A D	x_ovfl.S	60 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 79 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no 80 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 85 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 98 | move.b FPCR_ENABLE(%a6),%d0 99 | and.b FPSR_EXCEPT(%a6),%d0 100 | andi.b #$3,%d0 109 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no 110 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 116 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 130 bfextu CMDREG3B(%a6){#6:#3},%d0 |get dest reg no 131 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 136 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 143 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 168 bsrl g_opcls |returns opclass in d0 169 cmpiw #3,%d0 |check for opclass3
H A D	bindec.S	12 | value in memory; d0 contains the k-factor sign-extended 112 | d0: scratch; LEN input to binstr 177 movel %d0,%d7 |move k-factor to d7 179 movew STAG(%a6),%d0 |get stag 180 andiw #0xe000,%d0 |isolate stag bits 186 movew (%a0),%d0 187 andiw #0x7fff,%d0 |strip sign of normalized exp 191 subw #1,%d0 199 tstw %d0 203 andiw #0x7fff,%d0 |strip sign of normalized exp 204 movew %d0,(%a0) 224 | d0: k-factor/exponent 247 movew FP_SCR2(%a6),%d0 |move exp to d0 250 subw #0x3fff,%d0 |strip off bias 251 faddw %d0,%fp0 |add in exp 287 | d0: exponent/Unchanged 359 | d0: exponent/scratch - final is 0 384 movel %d6,%d0 |calc ILOG + 1 - LEN in d0 385 addql #1,%d0 |add the 1 386 subl %d4,%d0 |sub off LEN 390 tstl %d0 |test sign of ISCALE 393 cmpl #0xffffecd4,%d0 |test iscale <= -4908 395 addil #24,%d0 |add in 24 to iscale 398 negl %d0 |and take abs of ISCALE 428 lsrl #1,%d0 |shift next bit into carry 433 tstl %d0 |test if ISCALE is zero 464 | d0: FPCR with RZ mode/Unchanged 525 | d0: FPCR with RZ mode/FPSR with INEX2 isolated 540 fmovel %FPSR,%d0 |get FPSR 543 btstl #9,%d0 |check if INEX2 set 566 | d0: FPSR with AINEX cleared/FPCR with size set to ext 586 moveml %d0-%d1/%a0-%a1,-(%a7) |save regs used by sintd0 601 moveml (%a7)+,%d0-%d1/%a0-%a1 |restore regs used by sint 619 | d0: FPCR with size set to ext/scratch final = 0 645 movel %d4,%d0 |put LEN in d0 646 subql #1,%d0 |d0 = LEN -1 649 lsrl #1,%d0 |shift next bit into carry 654 tstl %d0 |test if LEN is zero 697 movel %d4,%d0 |put LEN in d0 700 lsrl #1,%d0 |shift next bit into carry 705 tstl %d0 |test if LEN is zero 727 | d0: x/LEN call to binstr - final is 0 756 movel (%a0),%d0 |move exponent to d0 757 swap %d0 |put exponent in lower word 759 subil #0x3ffd,%d0 |sub bias less 2 to make fract 760 tstl %d0 |check if > 1 762 negl %d0 |make exp positive 766 dbf %d0,m_loop |given in d0 778 movel %d4,%d0 |put LEN in d0 for binstr call 800 | d0: x/LEN call to binstr - final is 0 849 movew (%a2),%d0 |move exp to d0 851 subiw #0x3ffd,%d0 |subtract off bias 852 negw %d0 |make exp positive 856 dbf %d0,x_loop |given in d0 862 movel #4,%d0 |put 4 in d0 for binstr call 865 movel L_SCR1(%a6),%d0 |load L_SCR1 lword to d0 867 lsrl %d1,%d0 |shift d0 right by 12 868 bfins %d0,FP_SCR1(%a6){#4:#12} |put e3:e2:e1 in FP_SCR1 869 lsrl %d1,%d0 |shift d0 right by 12 870 bfins %d0,FP_SCR1(%a6){#16:#4} |put e4 in FP_SCR1 871 tstb %d0 |check if e4 is zero 881 | d0: x/scratch - final is x 900 clrl %d0 |clr d0 for collection of signs 904 moveql #2,%d0 |move 2 in to d0 for SM 908 addql #1,%d0 |set bit 0 in d0 for SE 910 bfins %d0,FP_SCR1(%a6){#0:#2} |insert SM and SE into FP_SCR1
H A D	sacos.S	66 movel (%a0),%d0 | ...pack exponent with upper 16 fraction 67 movew 4(%a0),%d0 68 andil #0x7FFFFFFF,%d0 69 cmpil #0x3FFF8000,%d0 95 movel (%a0),%d0 | ...pack exponent with upper 16 fraction 96 movew 4(%a0),%d0 97 cmpl #0,%d0 |D0 has original exponent+fraction
H A D	skeleton.S	73 GET_CURRENT(%d0) 151 moveml %d0/%d1,USER_DA(%a6) 152 bfextu CMDREG1B(%a6){#6:#3},%d0 |get dest reg no 153 bclrb %d0,FPR_DIRTY_BITS(%a6) |clr dest dirty bit 155 moveml USER_DA(%a6),%d0/%d1 164 GET_CURRENT(%d0) 190 GET_CURRENT(%d0) 216 GET_CURRENT(%d0) 238 GET_CURRENT(%d0) 260 GET_CURRENT(%d0) 288 GET_CURRENT(%d0) 309 GET_CURRENT(%d0) 331 GET_CURRENT(%d0) 382 GET_CURRENT(%d0) 395 | d0 - number of bytes to write (maximum count is 12) 414 subql #1,%d0 419 movel %d0,-(%sp) 440 | d0 - number of bytes to read (maximum count is 12) 453 subql #1,%d0 458 movel %d0,-(%sp) 474 movel 12(%sp),%d0 | count 475 subl #1,%d0 | dec count by 1 for dbra 484 dbf %d0,moreout 490 movel 12(%sp),%d0 | count 491 subl #1,%d0 | dec count by 1 for dbra 499 dbf %d0,morein
H A D	gen_except.S	74 movel CMDREG1B(%a6),%d0 |fix cmd1b to make it 75 andl #0x03c30000,%d0 |work for cmd3b 79 orl %d1,%d0 |put it in the right place 83 orl %d1,%d0 |put them in the right place 84 movel %d0,CMDREG3B(%a1) |in the busy frame 88 fmovel %FPSR,%d0 89 orl %d0,USER_FPSR(%a6) 119 fmovel %FPSR,%d0 120 orl %d0,USER_FPSR(%a6) 135 fmovel %FPSR,%d0 136 orl %d0,USER_FPSR(%a6) 153 moveb FPCR_ENABLE(%a6),%d0 |get fpcr enable byte 154 andb FPSR_EXCEPT(%a6),%d0 |and in the fpsr exc byte 155 bfffo %d0{#24:#8},%d1 |test for first set bit 193 movel CMDREG1B(%a6),%d0 194 andl #0x03c30000,%d0 |work for cmd3b 198 orl %d1,%d0 |put it in the right place 202 orl %d1,%d0 |put them in the right place 203 movel %d0,CMDREG3B(%a6) |in the busy frame 231 moveml USER_DA(%a6),%d0-%d1/%a0-%a1 282 moveql #13,%d0 |need to zero 14 lwords 287 moveql #11,%d0 |need to zero 12 lwords 293 dbra %d0,loop1 305 movel CMDREG1B(%a6),%d0 |fix cmd1b to make it 306 andl #0x03c30000,%d0 |work for cmd3b 310 orl %d1,%d0 |put it in the right place 314 orl %d1,%d0 |put them in the right place 315 movel %d0,CMDREG3B(%a6) |in the busy frame 331 moveql #13,%d0 |in orig, need to zero 14 lwords 336 moveql #11,%d0 |in rev, need to zero 12 lwords 343 dbra %d0,loop2 360 bfextu USER_FPSR(%a6){#17:#4},%d0 |get snan/operr/ovfl/unfl bits 361 bfins %d0,NMCEXC(%a1){#4:#4} |and insert them in nmcexc 366 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
H A D	slogn.S	327 movel (%a0),%d0 328 movew 4(%a0),%d0 334 cmpil #0,%d0 | ...CHECK IF X IS NEGATIVE 336 cmp2l BOUNDS1,%d0 | ...X IS POSITIVE, CHECK IF X IS NEAR 1 352 asrl #8,%d0 353 asrl #8,%d0 | ...SHIFTED 16 BITS, BIASED EXPO. OF X 354 subil #0x3FFF,%d0 | ...THIS IS K 355 addl ADJK(%a6),%d0 | ...ADJUST K, ORIGINAL INPUT MAY BE DENORM. 357 fmovel %d0,%fp1 | ...CONVERT K TO FLOATING-POINT FORMAT 364 movel FFRAC(%a6),%d0 | ...READY TO GET ADDRESS OF 1/F 365 andil #0x7E000000,%d0 366 asrl #8,%d0 367 asrl #8,%d0 368 asrl #4,%d0 | ...SHIFTED 20, D0 IS THE DISPLACEMENT 369 addal %d0,%a0 | ...A0 IS THE ADDRESS FOR 1/F 502 movel X(%a6),%d0 503 cmpil #0,%d0 505 cmp2l BOUNDS2,%d0 513 cmp2l BOUNDS1,%d0 537 cmpil #0x3FFF8000,%d0 | ...SEE IF 1+Z > 1 545 movel FFRAC(%a6),%d0 546 andil #0x7E000000,%d0 547 asrl #8,%d0 548 asrl #8,%d0 549 asrl #4,%d0 | ...D0 CONTAINS DISPLACEMENT FOR 1/F 554 addal %d0,%a0 563 movel FFRAC(%a6),%d0 564 andil #0x7E000000,%d0 565 asrl #8,%d0 566 asrl #8,%d0 567 asrl #4,%d0 571 addal %d0,%a0 | ...A0 IS ADDRESS OF 1/F 577 cmpil #0,%d0
H A D	get_op.S	181 bfextu CMDREG1B(%a6){#3:#3},%d0 182 cmpb #3,%d0 195 bfextu CMDREG1B(%a6){#0:#6},%d0 |get opclass and src fields 196 cmpil #0x17,%d0 |if op class and size fields are $17, 210 moveb STAG(%a6),%d0 211 orb DTAG(%a6),%d0 |check if either of STAG/DTAG msb set 225 movew FPTEMP_EX(%a6),%d0 |get destination exponent 226 andiw #0x7fff,%d0 |mask sign, check if exp = 0000 255 movew ETEMP_EX(%a6),%d0 |get source exponent 256 andiw #0x7fff,%d0 |mask sign, check if exp = 0000 301 moveb L_SCR1(%a6),STAG(%a6) |put tag into source tag reg - d0 317 bfextu CMDREG1B(%a6){#6:#3},%d0 |extract dest fp reg 319 subl %d0,%d1 320 clrl %d0 321 bsetl %d1,%d0 |set up d0 as a dynamic register mask 322 fmovemx %d0,FPTEMP(%a6) |write to FPTEMP 330 moveb DTAG(%a6),%d0 331 andib #0xf0,%d0 |strip to only dtag:fpte15 332 tstb %d0 |check for normalized value 334 movew FPTEMP_EX(%a6),%d0 335 andiw #0x7fff,%d0 336 cmpiw #0x3fff,%d0 |check if fpte15 needs setting 346 bfextu CMDREG1B(%a6){#4:#2},%d0 347 cmpib #3,%d0 359 movew CMDREG1B(%a6),%d0 360 btstl #5,%d0 |testing extension command word 362 btstl #4,%d0 |know that bit 5 = 1 364 andiw #0x007f,%d0 |get rid of all but extension bits {6:0} 365 cmpiw #0x0038,%d0 |if extension = $38 then fcmp (dyadic) 491 movew CMDREG1B(%a6),%d0 |examine command word, looking for fmove's 492 andw #0x3b,%d0 495 movew ETEMP(%a6),%d0 |get word with inf information 496 bfextu %d0{#20:#12},%d1 |get exponent into d1 499 bfextu %d0{#17:#3},%d1 |get SE and y bits into d1 514 movew ETEMP_EX+2(%a6),%d0 |get word 4 515 andiw #0x000f,%d0 |clear all but last ni(y)bble 516 tstw %d0 |check for zero. 547 movew ETEMP(%a6),%d0 |get word with inf information 548 bfextu %d0{#20:#12},%d1 |get exponent into d1 551 bfextu %d0{#17:#3},%d1 |get SE and y bits into d1 581 movew ETEMP_EX+2(%a6),%d0 |get word 4 582 andiw #0x000f,%d0 |clear all but last ni(y)bble 583 tstw %d0 |check for zero. 611 movew CMDREG1B(%a6),%d0 |get the command word 612 andw #0xfbff,%d0 |change the source specifier field to 614 movew %d0,CMDREG1B(%a6) |write command word back to fsave stack 646 movel #0x40,%d0 650 movel #0x60,%d0 658 movel #0x20,%d0 669 movel #0,%d0
H A D	x_bsun.S	32 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 39 moveml USER_DA(%a6),%d0-%d1/%a0-%a1
H A D	x_unsupp.S	45 moveml %d0-%d1/%a0-%a1,USER_DA(%a6) 51 moveb (%a7),%d0 |test for valid version num 52 andib #0xf0,%d0 |test for $4x 53 cmpib #VER_4,%d0 |must be $4x or exit
H A D	do_func.S	69 bfextu CMDREG1B(%a6){#0:#6},%d0 |get opclass and src fields 70 cmpil #0x17,%d0 |if op class and size fields are $17, 76 movew CMDREG1B(%a6),%d0 77 andl #0x7F,%d0 78 cmpil #0x38,%d0 |if the extension is >= $38, 81 lsll #3,%d0 |make room for STAG 82 addl %d1,%d0 |combine for final index into table 84 movel (%a1,%d0.w*4),%a1 |real target address 275 bfextu STAG(%a6){#0:#3},%d0 |stag = d0 281 bclrl #2,%d0 285 orb %d0,%d1 |d1{3:2} = dtag, d1{1:0} = stag 303 moveb FPTEMP(%a6),%d0 |get sign of dst op 304 eorb %d0,%d1 |get exor of sign bits 309 btstl #7,%d0 |test if + or - 315 moveb FPTEMP(%a6),%d0 |get sign of dst op 316 eorb %d0,%d1 |get exor of sign bits 356 bfextu STAG(%a6){#0:#3},%d0 |stag = d0 361 bclr #2,%d0 365 orb %d0,%d1 |d1{3:2} = dtag, d1{1:0} = stag 383 moveb FPTEMP(%a6),%d0 |get sign of dst op 384 eorb %d0,%d1 |get exor of sign bits 389 btstl #7,%d0 |test if + or - 395 moveb FPTEMP(%a6),%d0 |get sign of dst op 396 eorb %d0,%d1 |get exor of sign bits 434 bfextu STAG(%a6){#0:#3},%d0 |stag in d0 436 bclrl #2,%d0 |alias denorm into norm 439 orb %d0,%d1 |d1{4:2} = dtag, d1{1:0} = stag
H A D	scosh.S	82 movel (%a0),%d0 83 movew 4(%a0),%d0 84 andil #0x7FFFFFFF,%d0 85 cmpil #0x400CB167,%d0 109 cmpil #0x400CB2B3,%d0
H A D	binstr.S	8 | d0, and a pointer to start in memory for bcd characters 9 | in d0. (This pointer must point to byte 4 of the first 40 | upper word of d0. If it is the ls digit, write the word 41 | from d0 to memory. 49 | d0: LEN counter 74 moveml %d0-%d7,-(%a7) 79 subql #1,%d0 |for dbf d0 would have LEN+1 passes 122 dbf %d0,loop |do loop some more! 129 dbf %d0,loop |do loop some more! 137 moveml (%a7)+,%d0-%d7
H A D	satan.S	242 movel (%a0),%d0 243 movew 4(%a0),%d0 245 andil #0x7FFFFFFF,%d0 247 cmpil #0x3FFB8000,%d0 | ...|X| >= 1/16? 252 cmpil #0x4002FFFF,%d0 | ...|X| < 16 ? 296 movel %d0,%d2 | ...THE EXPO AND 16 BITS OF X 297 andil #0x00007800,%d0 | ...4 VARYING BITS OF F'S FRACTION 301 addl %d2,%d0 | ...THE 7 BITS IDENTIFYING F 302 asrl #7,%d0 | ...INDEX INTO TBL OF ATAN(|F|) 304 addal %d0,%a1 | ...ADDRESS OF ATAN(|F|) 308 movel X(%a6),%d0 | ...LOAD SIGN AND EXPO. AGAIN 309 andil #0x80000000,%d0 | ...SIGN(F) 310 orl %d0,ATANF(%a6) | ...ATANF IS NOW SIGN(F)*ATAN(|F|) 341 |--|X| IS IN d0 IN COMPACT FORM. FP1, d0 SAVED. 343 cmpil #0x3FFF8000,%d0 353 cmpil #0x3FD78000,%d0 404 cmpil #0x40638000,%d0
H A D	kernel_ex.S	160 bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision 195 moveb FPCR_MODE(%a6),%d0 196 andib #0xc0,%d0 198 cmpib #0x40,%d0 |test for single 203 movel ETEMP_HI(%a6),%d0 204 andil #0xff,%d0 |look at only lower 8 bits 208 movel ETEMP_LO(%a6),%d0 209 andil #0x7ff,%d0 |look at only lower 11 bits 298 moveb STAG(%a6),%d0 299 andib #0xe0,%d0 300 cmpib #0x60,%d0 411 bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision
H A D	sint.S	209 clrl %d0 |clear d0 - initial g,r,s for 216 | ;output d0 supplies g,r,s 223 | ; d0 g,r,s bits
H A D	fpsp.h	20 | movem.l d0-d1/a0-a1,USER_DA(a6) 50 | movem.l USER_DA(a6),d0-d1/a0-a1 69 | The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
/linux-4.4.14/arch/m68k/coldfire/
H A D	head.S	30 movel #CONFIG_RAMSIZE,%d0 /* hard coded memory size */ 44 movel MCFSIM_DMR0,%d0 /* get mask for 1st bank */ 45 btst #0,%d0 /* check if region enabled */ 47 andl #0xfffc0000,%d0 49 addl #0x00040000,%d0 /* convert mask to size */ 57 addl %d1,%d0 /* total mem size in d0 */ 63 movel MCFSIM_CSOR7,%d0 /* get SDRAM address mask */ 64 andil #0xfffff000,%d0 /* mask out chip select options */ 65 negl %d0 /* negate bits */ 70 clrl %d0 75 moveql #1, %d0 76 lsll %d2, %d0 /* 2 ^ exponent */ 84 addl %d1, %d0 /* Total size of SDRAM in d0 */ 155 movel #CACHE_INIT,%d0 /* disable cache */ 156 movec %d0,%CACR 162 movel #CONFIG_MBAR+1,%d0 /* configured MBAR address */ 163 movec %d0,%MBAR /* set it */ 185 addl %a7,%d0 186 movel %d0,_ramend /* set end ram addr */ 195 movel #ACR0_MODE,%d0 /* set RAM region for caching */ 196 movec %d0,%ACR0 197 movel #ACR1_MODE,%d0 /* anything else to cache? */ 198 movec %d0,%ACR1 200 movel #ACR2_MODE,%d0 201 movec %d0,%ACR2 202 movel #ACR3_MODE,%d0 203 movec %d0,%ACR3 205 movel #CACHE_MODE,%d0 /* enable cache */ 206 movec %d0,%CACR 213 movel #(MMUBASE+1),%d0 /* enable MMUBAR registers */ 214 movec %d0,%MMUBAR 215 movel #MMUOR_CA,%d0 /* clear TLB entries */ 216 movel %d0,MMUOR 217 movel #0,%d0 /* set ASID to 0 */ 218 movec %d0,%asid 220 movel #MMUCR_EN,%d0 /* Enable the identity map */ 221 movel %d0,MMUCR 237 movel 8(%a0),%d0 /* get size of ROMFS */ 238 addql #8,%d0 /* allow for rounding */ 239 andl #0xfffffffc, %d0 /* whole words */ 241 addl %d0,%a0 /* copy from end */ 242 addl %d0,%a1 /* copy from end */ 246 movel -(%a0),%d0 /* copy dword */ 247 movel %d0,-(%a1) 262 clrl %d0 /* set value */ 264 movel %d0,(%a0)+ /* clear each word */ 279 movel #CPU_COLDFIRE,%d0 280 movel %d0,m68k_cputype /* Mark us as a ColdFire */ 281 movel #MMU_COLDFIRE,%d0 282 movel %d0,m68k_mmutype 283 movel #FPU_COLDFIRE,%d0 284 movel %d0,m68k_fputype 285 movel #MACH_M54XX,%d0 286 movel %d0,m68k_machtype /* Mark us as a 54xx machine */
H A D	cache.c	28 "clrl %%d0\n\t" mcf_cache_push() 30 "movel %%d0,%%a0\n\t" mcf_cache_push() 36 "addql #1,%%d0\n\t" mcf_cache_push() 37 "cmpil %2,%%d0\n\t" mcf_cache_push() 43 : "d0", "a0" ); mcf_cache_push()
H A D	entry.S	67 cmpl #NR_syscalls,%d0 70 lsll #2,%d0 /* movel %a0@(%d0:l:4),%d3 */ 71 movel %a0@(%d0),%d3 85 movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 97 movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 130 movel %sp@+,%d0 131 addql #4,%sp /* orig d0 */ 169 movew %sp@(PT_OFF_FORMATVEC),%d0 /* put exception # in d0 */ 170 andl #0x03fc,%d0 /* mask out vector only */ 173 lsrl #2,%d0 /* calculate real vector # */ 174 movel %d0,%sp@- /* push vector number */
/linux-4.4.14/arch/mn10300/boot/compressed/
H A D	head.S	41 mov d0,(a0) 51 clr d0 52 movhu d0,(a0) # turn off first 53 mov CHCTR_ICINV|CHCTR_DCINV,d0 54 movhu d0,(a0) 56 mov (a0),d0 57 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy 62 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRBACK,d0 64 mov CHCTR_ICEN|CHCTR_DCEN|CHCTR_DCWTMD_WRTHROUGH,d0 66 movhu d0,(a0) # enable 72 clr d0 76 movbu d0,(a0) 89 clr d0 90 movhu d0,(a0) 92 mov (a0),d0 93 btst CHCTR_ICBUSY|CHCTR_DCBUSY,d0 # wait till not busy 97 mov (a0),d0 114 movhu (CHCTR),d0 115 btst CHCTR_DCEN,d0 122 mov (DCACHE_PURGE_WAY0(0),a1),d0 # unconditional purge 123 mov (DCACHE_PURGE_WAY1(0),a1),d0 # unconditional purge 124 mov (DCACHE_PURGE_WAY2(0),a1),d0 # unconditional purge 125 mov (DCACHE_PURGE_WAY3(0),a1),d0 # unconditional purge
/linux-4.4.14/arch/m68k/math-emu/
H A D	fp_cond.S	62 move.l %d2,%d0 63 swap %d0 64 fp_get_instr_word %d0,fp_err_ua1 65 lea (-2,%a0,%d0.l),%a0 67 move.l %d2,%d0 68 swap %d0 70 tst.l %d0 79 fp_get_instr_word %d0,fp_err_ua1 80 add.w %d0,%a1 82 printf PDECODE,"d%d,%x\n",2,%d0,%a1 86 move.l %d0,%d1 88 subq.w #1,%d0 100 move.l %d2,%d0 102 move.w %d0,%d1 116 move.w %d0,%d1 | save register nr 119 move.b %d1,%d0 146 bfextu %d2{#13,#3},%d0 147 jmp ([0f:w,%pc,%d0*4]) 177 btst #4,%d0 184 1: and.w #0xf,%d0 185 jmp ([0f:w,%pc,%d0.w*4]) 195 moveq #0,%d0 199 moveq #0,%d0 202 moveq #-1,%d0 206 moveq #0,%d0 213 moveq #-1,%d0 217 moveq #-1,%d0 224 1: moveq #0,%d0 228 moveq #0,%d0 235 moveq #-1,%d0 239 moveq #-1,%d0 246 1: moveq #0,%d0 250 moveq #0,%d0 255 moveq #-1,%d0 259 moveq #0,%d0 262 moveq #-1,%d0 266 moveq #0,%d0 269 moveq #-1,%d0 273 moveq #-1,%d0 278 moveq #0,%d0 282 moveq #-1,%d0 289 1: moveq #0,%d0 293 moveq #-1,%d0 300 moveq #0,%d0 304 moveq #-1,%d0 311 1: moveq #0,%d0 315 moveq #-1,%d0 322 moveq #0,%d0 326 moveq #0,%d0 329 moveq #-1,%d0 333 moveq #-1,%d0
H A D	fp_util.S	49 * something here. %d0 and %d1 is always usable, sometimes %d2 (or 70 2: clr.l %d0 94 | args: %d0 = source (32-bit long) 98 printf PCONV,"l2e: %p -> %p(",2,%d0,%a0 100 tst.l %d0 104 neg.l %d0 108 move.l %d0,(%a0)+ | set mantissa 125 | args: %d0 = source (single-precision fp value) 129 printf PCONV,"s2e: %p -> %p(",2,%d0,%a0 130 move.l %d0,%d1 131 lsl.l #8,%d0 | shift mantissa 138 bset #31,%d0 | set explizit bit 141 move.l %d0,(%a0)+ | high lword of fp_ext.mant 150 tst.l %d0 156 bclr #31,%d0 | clear explizit bit 162 getuser.l %a1@(0),%d0,fp_err_ua2,%a1 164 printf PCONV,"d2e: %p%p -> %p(",3,%d0,%d1,%a0 166 getuser.l (%a1)+,%d0,fp_err_ua2,%a1 167 move.l %d0,%d1 168 lsl.l #8,%d0 | shift high mantissa 169 lsl.l #3,%d0 176 bset #31,%d0 | set explizit bit 179 move.l %d0,(%a0)+ 180 getuser.l (%a1)+,%d0,fp_err_ua2,%a1 181 move.l %d0,%d1 182 lsl.l #8,%d0 183 lsl.l #3,%d0 184 move.l %d0,(%a0) 185 moveq #21,%d0 186 lsr.l %d0,%d1 195 tst.l %d0 201 bclr #31,%d0 | clear explizit bit 210 | returns 0 in %d0 for a NaN, otherwise 1 216 move.l (%a0)+,%d0 217 cmp.w #0x7fff,%d0 | Inf / NaN? 219 move.l (%a0),%d0 225 move.b (%a0),%d0 231 moveq #1,%d0 239 tst.b %d0 | test guard bit 243 lsl.b #1,%d0 | check low bits 271 move.l (4,%a0),%d0 274 clr.l %d0 275 move.b (-4,%a0),%d0 284 moveq #1,%d0 288 bfffo %d0{#0,#32},%d1 299 lsl.l %d2,%d0 300 move.l %d0,(%a0)+ 301 move.l (%a0),%d0 302 move.l %d0,%d1 303 lsl.l %d2,%d0 304 move.l %d0,(%a0) 311 clr.l %d0 312 move.b (-4,%a0),%d0 317 lsl.l %d2,%d0 318 or.l %d0,(4,%a0) 321 lsl.l %d2,%d0 322 move.b %d0,(-4,%a0) 323 lsr.l #8,%d0 324 or.l %d0,(4,%a0) 329 bfffo %d0{#0,#32},%d1 343 lsl.l %d1,%d0 | lower lword needs only to be shifted 344 move.l %d0,(%a0) | into the higher lword 346 clr.l %d0 347 move.b (-4,%a0),%d0 351 bfins %d0,(%a0){%d1,#8} 355 bfins %d0,(%a0){%d1,#32} | higher and lower lword 364 bfffo %d0{#24,#8},%d1 381 lsl.l %d1,%d0 382 move.l %d0,(%a0) 385 bfins %d0,(%a0){%d1,#8} 387 2: lsl.l %d1,%d0 388 move.b %d0,(-4,%a0) 389 lsr.l #8,%d0 390 move.b %d0,(7,%a0) 393 1: move.l %d0,%d1 | lower lword is splitted between 394 lsl.l %d2,%d0 | higher and lower lword 395 move.l %d0,(%a0) 396 move.l %d1,%d0 399 lsr.l %d2,%d0 400 move.l %d0,-(%a0) 404 move.l (%a0)+,%d0 408 moveq #1,%d0 415 3: lsl.l #1,%d0 418 4: clrl %d0 441 move.l (%a0)+,%d0 442 cmp.w #0x7fff,%d0 | Inf / NaN? 444 move.l (%a0),%d0 450 move.b (%a0),%d0 463 tst.b %d0 | test guard bit 467 lsl.b #1,%d0 | check low bits 496 move.l (4,%a0),%d0 499 clr.l %d0 500 move.b (-4,%a0),%d0 512 bfffo %d0{#0,#32},%d1 524 lsl.l %d2,%d0 525 move.l %d0,(%a0)+ 526 move.l (%a0),%d0 527 move.l %d0,%d1 528 lsl.l %d2,%d0 529 move.l %d0,(%a0) 536 clr.l %d0 537 move.b (-4,%a0),%d0 542 lsl.l %d2,%d0 543 or.l %d0,(4,%a0) 546 lsl.l %d2,%d0 547 move.b %d0,(-4,%a0) 548 lsr.l #8,%d0 549 or.l %d0,(4,%a0) 554 bfffo %d0{#0,#32},%d1 569 lsl.l %d1,%d0 | lower lword needs only to be shifted 570 move.l %d0,(%a0) | into the higher lword 572 clr.l %d0 573 move.b (-4,%a0),%d0 577 bfins %d0,(%a0){%d1,#8} 581 bfins %d0,(%a0){%d1,#32} | higher and lower lword 590 bfffo %d0{#24,#8},%d1 607 lsl.l %d1,%d0 608 move.l %d0,(%a0) 611 bfins %d0,(%a0){%d1,#8} 613 2: lsl.l %d1,%d0 614 move.b %d0,(-4,%a0) 615 lsr.l #8,%d0 616 move.b %d0,(7,%a0) 621 move.l (%a0)+,%d0 631 3: move.l %d0,%d1 637 4: bset #30,%d0 640 move.l %d0,(-4,%a0) 673 move.l (%a0),%d0 | low lword of mantissa 677 lsl.l %d1,%d0 | keep 11 low bits. 692 tst.l %d0 | test guard bit 704 lsl.l #1,%d0 | check low bits 746 move.l (%a0),%d0 747 move.l %d0,%d1 748 lsr.l %d2,%d0 749 move.l %d0,(%a0)+ 750 move.l (%a0),%d0 751 lsr.l %d2,%d0 755 or.l %d1,%d0 757 move.l %d0,(%a0) 761 bset #0,%d0 | Yes, so set the "sticky bit". 767 move.l (%a0),%d0 769 move.l %d0,%d1 770 lsr.l %d2,%d0 776 bset #0,%d0 | Sticky bit. 777 1: move.l %d0,(%a0) 780 bset #0,%d0 785 moveq #1,%d0 | Smallest possible fraction, 808 moveq #1,%d0 812 move.w #0x7ff,%d0 813 and.w (6,%a0),%d0 836 moveq #-1,%d0 837 move.l %d0,(%a0)+ 838 move.w #0xf800,%d0 839 move.l %d0,(%a0) 866 move.l (%a0)+,%d0 | get high lword of mantissa 873 bset #0,%d0 876 tst.b %d0 | 8 low bits. 890 tst.b %d0 | test guard bit 892 btst #8,%d0 | test lsb bit 895 lsl.b #1,%d0 | check low bits 932 move.l (%a0),%d0 933 move.l %d0,%d1 934 lsr.l %d2,%d0 935 move.l %d0,(%a0)+ 941 bset #0,%d0 | Sticky bit. 946 bset #0,%d0 | Sticky bit. 951 moveq #1,%d0 | Smallest possible fraction, 1002 moveq #1,%d0 1026 move.l (%a0)+,%d0 | get high lword of mantissa 1033 bset #0,%d0 1036 tst.b %d0 | 8 low bits. 1050 tst.b %d0 | test guard bit 1052 btst #8,%d0 | test lsb bit 1055 lsl.b #1,%d0 | check low bits 1131 | Returns the integer in %d0 (like it should) 1147 move.l (%a0),%d0 1148 move.l %d0,%d1 1155 lsr.l %d2,%d0 1158 tst.\s %d0 1160 printf PCONV,"-> %p\n",1,%d0 1162 1: neg.\s %d0 1165 1: printf PCONV,"-> %p\n",1,%d0 1174 lsr.l %d2,%d0 1179 btst %d2,%d0 | test lsb bit (%d2 still 0) 1186 addq.l #1,%d0 1211 clr.l %d0 1220 clr.l %d0 1227 subq.\s #1,%d0 1231 addq.\s #1,%d0 1232 3: printf PCONV,"-> %p\n",1,%d0 1236 move.\s #inf,%d0 1239 addq.\s #1,%d0 1240 1: printf PCONV,"-> %p\n",1,%d0 1243 move.\s (%a0),%d0 1253 1: printf PCONV,"-> %p\n",1,%d0 1275 move.l (%a0)+,%d0 1278 move.l (%a0)+,%d0 1284 move.l %d0,%d1 1285 lsl.l #1,%d0 1286 lsr.l #4,%d0 1287 lsr.l #8,%d0 1288 or.l %d2,%d0 1289 putuser.l %d0,(%a1)+,fp_err_ua2,%a1 1290 moveq #21,%d0 1291 lsl.l %d0,%d1 1292 move.l (%a0),%d0 1293 lsr.l #4,%d0 1294 lsr.l #7,%d0 1295 or.l %d1,%d0 1296 putuser.l %d0,(%a1),fp_err_ua2,%a1 1298 getuser.l %a1@(-4),%d0,fp_err_ua2,%a1 1300 printf PCONV,"%p(%08x%08x)\n",3,%a1,%d0,%d1 1313 move.l (%a0)+,%d0 1316 move.l (%a0)+,%d0 1322 bclr #31,%d0 1323 lsr.l #8,%d0 1324 or.l %d1,%d0 1325 printf PCONV,"%08x\n",1,%d0 1358 move.w (FPD_PREC,FPDATA),%d0 1359 subq.w #1,%d0 1371 clr.l %d0 1375 bset #FPSR_CC_NEG-24,%d0 | N bit 1393 8: bset %d1,%d0 1394 9: move.b %d0,(FPD_FPSR+0,FPDATA) | set condition test result 1401 move.l (FPD_FPSR,FPDATA),%d0 1403 btst #FPSR_EXC_SNAN,%d0 | EXC_SNAN 1405 btst #FPSR_EXC_OPERR,%d0 | EXC_OPERR 1407 1: bset #FPSR_AEXC_IOP,%d0 | set IOP bit 1408 2: btst #FPSR_EXC_OVFL,%d0 | EXC_OVFL 1410 bset #FPSR_AEXC_OVFL,%d0 | set OVFL bit 1411 1: btst #FPSR_EXC_UNFL,%d0 | EXC_UNFL 1413 btst #FPSR_EXC_INEX2,%d0 | EXC_INEX2 1415 bset #FPSR_AEXC_UNFL,%d0 | set UNFL bit 1416 1: btst #FPSR_EXC_DZ,%d0 | EXC_INEX1 1418 bset #FPSR_AEXC_DZ,%d0 | set DZ bit 1419 1: btst #FPSR_EXC_OVFL,%d0 | EXC_OVFL 1421 btst #FPSR_EXC_INEX2,%d0 | EXC_INEX2 1423 btst #FPSR_EXC_INEX1,%d0 | EXC_INEX1 1425 1: bset #FPSR_AEXC_INEX,%d0 | set INEX bit 1426 2: move.l %d0,(FPD_FPSR,FPDATA) 1429 move.l %d0,%d2 1430 lsr.l #5,%d0 1431 move.l %d0,%d1 1433 or.l %d0,%d1 1435 move.l %d2,%d0 1436 lsr.l #6,%d0 1437 or.l %d1,%d0 1441 and.b %d1,%d0 1445 or.b %d1,%d0 1446 and.b #0xf8,%d0 1447 or.b %d0,%d2 1450 move.b (FPD_FPSR+2,FPDATA),%d0 1451 and.b (FPD_FPCR+2,FPDATA),%d0
H A D	fp_entry.S	50 GET_CURRENT(%d0) 73 tst.l %d0 115 jmp ([0f:w,%pc,%d0.w*4]) 125 move.l (PT_OFF_D0+8,%sp),%d0 126 printf PREGISTER,"{d0->%08x}",1,%d0 130 move.l (PT_OFF_D1+8,%sp),%d0 131 printf PREGISTER,"{d1->%08x}",1,%d0 135 move.l (PT_OFF_D2+8,%sp),%d0 136 printf PREGISTER,"{d2->%08x}",1,%d0 140 move.l %d3,%d0 141 printf PREGISTER,"{d3->%08x}",1,%d0 145 move.l %d4,%d0 146 printf PREGISTER,"{d4->%08x}",1,%d0 150 move.l %d5,%d0 151 printf PREGISTER,"{d5->%08x}",1,%d0 155 move.l %d6,%d0 156 printf PREGISTER,"{d6->%08x}",1,%d0 160 move.l %d7,%d0 161 printf PREGISTER,"{d7->%08x}",1,%d0 175 printf PREGISTER,"{d0<-%08x}",1,%d0 176 move.l %d0,(PT_OFF_D0+8,%sp) 180 printf PREGISTER,"{d1<-%08x}",1,%d0 181 move.l %d0,(PT_OFF_D1+8,%sp) 185 printf PREGISTER,"{d2<-%08x}",1,%d0 186 move.l %d0,(PT_OFF_D2+8,%sp) 190 printf PREGISTER,"{d3<-%08x}",1,%d0 191 | move.l %d0,%d3 192 move.l %d0,(PT_OFF_D3+8,%sp) 196 printf PREGISTER,"{d4<-%08x}",1,%d0 197 | move.l %d0,%d4 198 move.l %d0,(PT_OFF_D4+8,%sp) 202 printf PREGISTER,"{d5<-%08x}",1,%d0 203 | move.l %d0,%d5 204 move.l %d0,(PT_OFF_D5+8,%sp) 208 printf PREGISTER,"{d6<-%08x}",1,%d0 209 move.l %d0,%d6 213 printf PREGISTER,"{d7<-%08x}",1,%d0 214 move.l %d0,%d7 218 jmp ([0f:w,%pc,%d0.w*4]) 268 jmp ([0f:w,%pc,%d0.w*4])
H A D	fp_movem.S	54 bfextu %d2{#24,#8},%d0 | static register list 56 1: bfextu %d2{#25,#3},%d0 | dynamic register list 58 2: move.l %d0,%d1 62 2: lsr.b #1,%d0 | register list and keep it in %d1 114 jmp ([0f:w,%pc,%d0*4]) 134 moveq #12,%d0 137 lea (-12,%a1,%d0*8),%a1 138 neg.l %d0 155 add.l %d0,%a0 156 2: add.l %d0,%a1 174 add.l %d0,%a0 175 2: add.l %d0,%a1 206 bfextu %d2{#19,#3},%d0 207 move.l %d0,%d1 211 2: lsr.l #1,%d0 234 move.w %d0,%d1 235 bfffo %d2{#19,#3},%d0 236 sub.w #19,%d0 237 lea (FPD_FPCR,FPDATA,%d0.w*4),%a1 240 move.w %d1,%d0 242 move.l %d0,(%a1) 244 1: move.l (%a1),%d0 250 printf PDECODE,"a%d",1,%d0 282 jmp ([0f:w,%pc,%d0*4]) 310 1: move.l %d0,(%a0) 328 getuser.l (%a0)+,%d0,fp_err_ua1,%a0 329 move.l %d0,(%a1) 338 move.l (%a1),%d0 339 putuser.l %d0,(%a0)+,fp_err_ua1,%a0 348 move.l (FPD_FPCR,FPDATA),%d0 349 lsr.l #4,%d0 351 and.l %d0,%d1 353 lsr.l #2,%d0 355 and.l %d0,%d1 362 clr.l %d0 363 move.w (FPD_PREC,FPDATA),%d0 364 printf PMOVEM,"prec : %04x\n",1,%d0 365 move.w (FPD_RND,FPDATA),%d0 366 printf PMOVEM,"rnd : %04x\n",1,%d0
H A D	fp_scan.S	67 getuser.b (%a0),%d0,fp_err_ua1,%a0 69 cmp.b #0xf2,%d0 | cpid = 1 71 cmp.b #0xfc,%d0 | cpid = 6 95 printf PDECODE,"f<op>.x fp%d",1,%d0 108 cmp.w #7,%d0 110 move.w %d0,%d1 | store data size twice in %d1 112 move.w %d0,%d1 115 clr.l %d0 116 move.b (%a0,%d1.w),%d0 117 printf PDECODE,"f<op>.%c ",1,%d0 157 extb.l %d0 161 ext.l %d0 202 jmp ([0f:w,%pc,%d0*4]) 225 move.w (fp_datasize,%d1.w*2),%d0 226 addq.w #1,%d0 227 and.w #-2,%d0 229 movem.l %d0/%d1,-(%sp) 235 2: dbra %d0,1b 236 movem.l (%sp)+,%d0/%d1 238 lea (%a0,%d0.w),%a1 255 getuser.l (%a1),%d0,fp_err_ua1,%a1 260 getuser.l (%a1),%d0,fp_err_ua1,%a1 265 getuser.l (%a1)+,%d0,fp_err_ua1,%a1 266 lsr.l #8,%d0 267 lsr.l #7,%d0 268 lsr.w #1,%d0 269 move.l %d0,(%a0)+ 270 getuser.l (%a1)+,%d0,fp_err_ua1,%a1 271 move.l %d0,(%a0)+ 272 getuser.l (%a1),%d0,fp_err_ua1,%a1 273 move.l %d0,(%a0) 282 getuser.w (%a1),%d0,fp_err_ua1,%a1 283 ext.l %d0 292 getuser.b (%a1),%d0,fp_err_ua1,%a1 293 extb.l %d0 299 bfextu %d2{#22,#3},%d0 300 printf PDECODE,",fp%d\n",1,%d0 304 bfextu %d2{#25,#7},%d0 305 jmp ([0f:w,%pc,%d0*4]) 346 bfextu %d2{#27,#5},%d0 347 printf PINSTR,"fp_fmovecr #%d",1,%d0 348 move.l %d0,%d1 349 add.l %d0,%d0 350 add.l %d1,%d0 351 lea (fp_constants,%d0*4),%a0 352 move.l #0x801cc0ff,%d0 354 lsl.l %d1,%d0 357 1: moveq #-128,%d0 | continue with fmove 358 and.l %d0,%d2 468 getuser.l (%a0),%d0,fp_err_ua1,%a0 469 printf ,"nonstd ((%08x)=%08x)\n",2,%a0,%d0 470 moveq #-1,%d0
H A D	fp_decode.h	46 * d0 - will contain source operand for data direct mode, 73 bfextu %d2{#8,#2},%d0 74 jmp ([0f:w,%pc,%d0*4]) 85 bfextu %d2{#16,#3},%d0 86 jmp ([0f:w,%pc,%d0*4]) 99 bfextu %d2{#19,#3},%d0 104 bfextu %d2{#19,#3},%d0 109 bfextu %d2{#22,#3},%d0 115 bfextu %d2{#10,#3},%d0 116 jmp ([0f:w,%pc,%d0*4]) 130 bfextu %d2{#13,#3},%d0 135 move.b %d2,%d0 136 ext.w %d0 141 bfextu %d2{#17,#3},%d0 | get the register nr 144 printf PDECODE,"d%d",1,%d0 147 1\@: printf PDECODE,"a%d",1,%d0 149 move.l %a0,%d0 155 ext.l %d0 164 lsl.l %d1,%d0 169 bfextu %d2{#26,#2},%d0 170 jmp ([0f:w,%pc,%d0*4]) 179 bfextu %d2{#30,#2},%d0 180 jmp ([0f:w,%pc,%d0*4]) 217 printf PDECODE,"d%d",1,%d0 223 printf PDECODE,"(a%d)",1,%d0 233 cmp.w #7,%d0 247 printf PDECODE,"(a%d)+",1,%d0 266 printf PDECODE,"-(a%d)",1,%d0 299 printf PDECODE,"a%d",1,%d0 308 moveq #3,%d0 309 and.w %d2,%d0 340 printf PDECODE,"a%d",1,%d0 348 debug ext.l "%d0" 349 printf PDECODE,"@(%x,",1,%d0 350 add.w %d0,%a1 352 add.l %d0,%a1 381 add.l %d0,%a1
H A D	fp_move.S	48 move.w %d0,%d1 | store data size twice in %d1 50 move.w %d0,%d1 53 clr.l %d0 54 move.b (%a0,%d1.w),%d0 55 printf PDECODE,"fmove.%c ",1,%d0 57 printf PDECODE,"fp%d,",1,%d0 75 move.w %d0,%d1 98 move.l %d0,%d1 100 move.w %d2,%d0 102 move.b %d1,%d0 110 move.l %d0,%d1 112 move.w %d2,%d0 114 move.w %d1,%d0 161 jmp ([0f:w,%pc,%d0*4]) 203 putuser.l %d0,(%a1),fp_err_ua1,%a1 208 putuser.l %d0,(%a1),fp_err_ua1,%a1 212 move.l (%a0)+,%d0 213 lsl.w #1,%d0 214 lsl.l #7,%d0 215 lsl.l #8,%d0 216 putuser.l %d0,(%a1)+,fp_err_ua1,%a1 217 move.l (%a0)+,%d0 218 putuser.l %d0,(%a1)+,fp_err_ua1,%a1 219 move.l (%a0),%d0 220 putuser.l %d0,(%a1),fp_err_ua1,%a1 230 putuser.w %d0,(%a1),fp_err_ua1,%a1 239 putuser.b %d0,(%a1),fp_err_ua1,%a1
H A D	fp_trig.h	29 they return a status code, which should end up in %d0, if all goes
H A D	fp_emu.h	66 register int res asm ("d0"); \ 110 register int __res asm ("d0"); \ 120 register int __src asm ("d0") = src; \
/linux-4.4.14/arch/m68k/include/asm/
H A D	irqflags.h	20 "move %/sr,%%d0 \n\t" arch_local_irq_disable() 21 "ori.l #0x0700,%%d0 \n\t" arch_local_irq_disable() 22 "move %%d0,%/sr \n" arch_local_irq_disable() 25 : "cc", "%d0", "memory"); arch_local_irq_disable() 35 "move %/sr,%%d0 \n\t" arch_local_irq_enable() 36 "andi.l #0xf8ff,%%d0 \n\t" arch_local_irq_enable() 37 "move %%d0,%/sr \n" arch_local_irq_enable() 40 : "cc", "%d0", "memory"); arch_local_irq_enable()
H A D	raw_io.h	299 "1:\tmovew %/a0@,%/d0\n\t" raw_insw_swapw() 300 "rolw #8,%/d0\n\t" raw_insw_swapw() 301 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 305 : "d0", "a0", "a1", "d6"); raw_insw_swapw() 313 "1:\tmovew %/a0@,%/d0\n\t" raw_insw_swapw() 314 "rolw #8,%/d0\n\t" raw_insw_swapw() 315 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 316 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 317 "rolw #8,%/d0\n\t" raw_insw_swapw() 318 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 319 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 320 "rolw #8,%/d0\n\t" raw_insw_swapw() 321 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 322 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 323 "rolw #8,%/d0\n\t" raw_insw_swapw() 324 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 325 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 326 "rolw #8,%/d0\n\t" raw_insw_swapw() 327 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 328 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 329 "rolw #8,%/d0\n\t" raw_insw_swapw() 330 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 331 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 332 "rolw #8,%/d0\n\t" raw_insw_swapw() 333 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 334 "movew %/a0@,%/d0\n\t" raw_insw_swapw() 335 "rolw #8,%/d0\n\t" raw_insw_swapw() 336 "movew %/d0,%/a1@+\n\t" raw_insw_swapw() 340 : "d0", "a0", "a1", "d6"); raw_insw_swapw() 352 "1:\tmovew %/a1@+,%/d0\n\t" raw_outsw_swapw() 353 "rolw #8,%/d0\n\t" raw_outsw_swapw() 354 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 358 : "d0", "a0", "a1", "d6"); raw_outsw_swapw() 366 "1:\tmovew %/a1@+,%/d0\n\t" raw_outsw_swapw() 367 "rolw #8,%/d0\n\t" raw_outsw_swapw() 368 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 369 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 370 "rolw #8,%/d0\n\t" raw_outsw_swapw() 371 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 372 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 373 "rolw #8,%/d0\n\t" raw_outsw_swapw() 374 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 375 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 376 "rolw #8,%/d0\n\t" raw_outsw_swapw() 377 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 378 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 379 "rolw #8,%/d0\n\t" raw_outsw_swapw() 380 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 381 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 382 "rolw #8,%/d0\n\t" raw_outsw_swapw() 383 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 384 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 385 "rolw #8,%/d0\n\t" raw_outsw_swapw() 386 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 387 "movew %/a1@+,%/d0\n\t" raw_outsw_swapw() 388 "rolw #8,%/d0\n\t" raw_outsw_swapw() 389 "movew %/d0,%/a0@\n\t" raw_outsw_swapw() 393 : "d0", "a0", "a1", "d6"); raw_outsw_swapw()
H A D	entry.h	23 * 20(sp) - d0 72 movel %d0,%sp@- /* orig d0 */ 73 movel %d0,%sp@- /* d0 */ 82 movel %d0,%sp@- /* orig d0 */ 83 movel %d0,%sp@- /* d0 */ 91 moveq #-1,%d0 /* not system call entry */ 92 movel %d0,%sp@(PT_OFF_ORIG_D0) variable 102 movel %sp@+,%d0 103 addql #4,%sp /* orig d0 */ 128 movel %d0,%sp@- /* orig d0 */ 129 movel %d0,%sp@- /* d0 */ 137 pea -1:w /* orig d0 */ 138 movel %d0,%sp@- /* d0 */ 146 movel %sp@+,%d0 147 addql #4,%sp /* orig d0 */ 187 pea -1:w /* orig d0 */ 188 movel %d0,%sp@- /* d0 */ 194 movel %d0,%sp@- /* orig d0 */ 195 movel %d0,%sp@- /* d0 */ 201 movel %sp@+,%d0 202 addql #4,%sp /* orig d0 */ 228 .macro get_current reg=%d0 248 "pea -1:w;" /* orig d0 = -1 */ \ 249 "movel %%d0,%%sp@-;" /* d0 */ \
H A D	m525xsim.h	241 moveb #MCFINTC2_VECBASE,%d0 242 moveb %d0,0x16b(%a1) /* interrupt base register */ variable 247 movel #0x001F0021,%d0 /* disable C/I bit */ 248 movel %d0,0x84(%a0) /* set CSMR0 */ variable 254 movel 0x180(%a1),%d0 /* get current PLL value */ 255 andl #0xfffffffe,%d0 /* PLL bypass first */ 256 movel %d0,0x180(%a1) /* set PLL register */ variable 265 movel #0x125a40f0,%d0 /* set for 140MHz */ 266 movel %d0,0x180(%a1) /* set PLL register */ variable 267 orl #0x1,%d0 268 movel %d0,0x180(%a1) /* set PLL register */ variable 275 movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ 276 movel %d0,0x8c(%a0) variable 277 movel #0x001f0021,%d0 /* CS1 size of 1Mb */ 278 movel %d0,0x90(%a0) variable 279 movew #0x0080,%d0 /* CS1 = 16bit port, AA */ 280 movew %d0,0x96(%a0) variable 285 movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ 286 movel %d0,0x98(%a0) variable 287 movel #0x001f0001,%d0 /* CS2 size of 1MB */ 288 movel %d0,0x9c(%a0) variable 289 movew #0x0080,%d0 /* CS2 = 16bit, TA */ 290 movew %d0,0xa2(%a0) variable 292 movel #0x00107000,%d0 /* IDEconfig1 */ 293 movel %d0,0x18c(%a1) variable 294 movel #0x000c0400,%d0 /* IDEconfig2 */ 295 movel %d0,0x190(%a1) variable 297 movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ 298 orl %d0,0xc(%a1) /* function GPIO19 */ variable 299 orl %d0,0x8(%a1) /* enable GPIO19 as output */ variable 300 orl %d0,0x4(%a1) /* de-assert IDE reset */ variable
H A D	math-emu.h	160 lea (FPD_FPREG,FPDATA,%d0.w*4),%a0 161 lea (%a0,%d0.w*8),%a0 259 movem.l %d0/%d1/%a0/%a1,-(%sp) 262 moveq #\bit,%d0 263 andw #7,%d0 264 btst %d0,fp_debugprint+((31-\bit)/8) 275 movem.l (%sp)+,%d0/%d1/%a0/%a1 281 movem.l %d0/%a0,-(%sp) 284 moveq #'+',%d0 287 moveq #'-',%d0 288 .Lx1\@: printf \bit," %c",1,%d0 289 move.l (4,%a0),%d0 290 bclr #31,%d0 295 .Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8) 296 move.w (2,%a0),%d0 297 ext.l %d0 298 printf \bit,"E%04x",1,%d0 302 movem.l (%sp)+,%d0/%a0
H A D	bootstd.h	40 /* let errno be a function, preserve res in %d0 */ \ 51 register long __res __asm__ ("%d0") = __BN_##name; \ 62 register long __res __asm__ ("%d0") = __BN_##name; \ 74 register long __res __asm__ ("%d0") = __BN_##name; \ 87 register long __res __asm__ ("%d0") = __BN_##name; \ 102 register long __res __asm__ ("%d0") = __BN_##name; \ 118 register long __res __asm__ ("%d0") = __BN_##name; \
H A D	switch_to.h	12 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and 37 : "d0", "d2", "d3", "d4", "d5"); \
H A D	a.out-core.h	56 dump->regs.d0 = regs->d0; aout_dump_thread()
H A D	elf.h	89 pr_reg[14] = regs->d0; \
H A D	user.h	42 long d0; member in struct:user_regs_struct
/linux-4.4.14/arch/x86/boot/compressed/
H A D	string.c	6 int d0, d1, d2; memcpy() local 11 : "=&c" (d0), "=&D" (d1), "=&S" (d2) memcpy() 20 long d0, d1, d2; memcpy() local 25 : "=&c" (d0), "=&D" (d1), "=&S" (d2) memcpy()
/linux-4.4.14/arch/arm/include/asm/
H A D	swab.h	6 * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 8 * d0...d31 11 * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 13 * d0...d31
H A D	vfpmacros.h	22 LDC p11, cr0, [\base],#33*4 @ FLDMIAX \base!, {d0-d15} 24 LDC p11, cr0, [\base],#32*4 @ FLDMIAD \base!, {d0-d15} 46 STC p11, cr0, [\base],#33*4 @ FSTMIAX \base!, {d0-d15} 48 STC p11, cr0, [\base],#32*4 @ FSTMIAD \base!, {d0-d15}
/linux-4.4.14/arch/arm/include/uapi/asm/
H A D	byteorder.h	6 * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 8 * d0...d31 11 * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 13 * d0...d31
H A D	swab.h	6 * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 8 * d0...d31 11 * 0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7 13 * d0...d31
/linux-4.4.14/arch/m68k/ifpsp060/
H A D	os.S	81 | d0 - number of bytes to write 88 subq.l #1,%d0 93 dbra %d0,super_write | quit if --ctr < 0 100 dbra %d0,user_write | quit if --ctr < 0 112 | d0 - number of bytes to read 121 subq.l #1,%d0 126 dbra %d0,super_read | quit if --ctr < 0 133 dbra %d0,user_read | quit if --ctr < 0 146 | d0 - data byte in d0 151 clr.l %d0 | clear whole longword 155 dmrbuae:movs.b (%a0),%d0 | fetch user byte 157 dmrbs: move.b (%a0),%d0 | fetch super byte 169 | d0 - data word in d0 180 | d0 - instruction word in d0 188 clr.l %d0 | clear whole longword 191 dmrwuae:movs.w (%a0), %d0 | fetch user word 193 dmrws: move.w (%a0), %d0 | fetch super word 205 | d0 - data longword in d0 216 | d0 - instruction longword in d0 226 dmrluae:movs.l (%a0),%d0 | fetch user longword 228 dmrls: move.l (%a0),%d0 | fetch super longword 238 | d0 - data byte in d0 248 dmwbuae:movs.b %d0,(%a0) | store user byte 250 dmwbs: move.b %d0,(%a0) | store super byte 260 | d0 - data word in d0 271 dmwwuae:movs.w %d0,(%a0) | store user word 273 dmwws: move.w %d0,(%a0) | store super word 284 | d0 - data longword in d0 294 dmwluae:movs.l %d0,(%a0) | store user longword 296 dmwls: move.l %d0,(%a0) | store super longword 320 move.l 12(%sp),%d0 | count 321 subq.l #1,%d0 326 dbra %d0,moreout | are we through yet? 327 moveq #0,%d0 | return success 337 move.l 12(%sp),%d0 | count 338 subq.l #1,%d0 343 dbra %d0,morein | are we through yet? 344 moveq #0,%d0 | return success
H A D	iskeleton.S	77 GET_CURRENT(%d0) 192 | d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user 195 | d0 = 0 -> success; non-zero -> failure 205 tst.b %d0 207 moveq #1,%d0 209 1: moveq #5,%d0 211 movec.l %d0,%dfc 212 movec.l %d0,%sfc 214 clr.l %d0 239 11: move.l #0x020003c0,%d0 240 or.l %d2,%d0 241 swap %d0 243 21: move.l #0x02000bc0,%d0 244 or.l %d2,%d0 245 swap %d0 258 | d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user 265 clr.l %d0
H A D	fskeleton.S	233 move.l %d0,-(%sp) | enabled the fpu 234 .long 0x4E7A0808 |movec pcr,%d0 235 bclr #0x1,%d0 236 .long 0x4E7B0808 |movec %d0,pcr 237 move.l (%sp)+,%d0
/linux-4.4.14/arch/x86/lib/
H A D	string_32.c	19 int d0, d1, d2; strcpy() local 24 : "=&S" (d0), "=&D" (d1), "=&a" (d2) strcpy() 34 int d0, d1, d2, d3; strncpy() local 44 : "=&S" (d0), "=&D" (d1), "=&c" (d2), "=&a" (d3) strncpy() 54 int d0, d1, d2, d3; strcat() local 62 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) strcat() 72 int d0, d1, d2, d3; strncat() local 85 : "=&S" (d0), "=&D" (d1), "=&a" (d2), "=&c" (d3) strncat() 96 int d0, d1; strcmp() local 108 : "=a" (res), "=&S" (d0), "=&D" (d1) strcmp() 120 int d0, d1, d2; strncmp() local 133 : "=a" (res), "=&S" (d0), "=&D" (d1), "=&c" (d2) strncmp() 144 int d0; strchr() local 155 : "=a" (res), "=&S" (d0) strchr() 166 int d0; strlen() local 170 : "=c" (res), "=&D" (d0) strlen() 181 int d0; memchr() local 190 : "=D" (res), "=&c" (d0) memchr() 218 int d0; strnlen() local 229 : "=a" (res), "=&d" (d0) strnlen()
H A D	strstr_32.c	5 int d0, d1; strstr() local 26 : "=a" (__res), "=&c" (d0), "=&S" (d1) strstr()
H A D	memcpy_32.c	25 int d0,d1,d2,d3,d4,d5; memmove() local 198 : "=&c" (d0), "=&S" (d1), "=&D" (d2), memmove()
H A D	delay.c	159 int d0; __const_udelay() local 163 :"=d" (xloops), "=&a" (d0) __const_udelay()
H A D	usercopy_32.c	103 int d0, d1; __copy_user_intel() local 198 : "=&c"(size), "=&D" (d0), "=&S" (d1) __copy_user_intel() 207 int d0, d1; __copy_user_zeroing_intel() local 290 : "=&c"(size), "=&D" (d0), "=&S" (d1) __copy_user_zeroing_intel() 304 int d0, d1; __copy_user_zeroing_intel_nocache() local 389 : "=&c"(size), "=&D" (d0), "=&S" (d1) __copy_user_zeroing_intel_nocache() 398 int d0, d1; __copy_user_intel_nocache() local 477 : "=&c"(size), "=&D" (d0), "=&S" (d1) __copy_user_intel_nocache()
H A D	mmx_32.c	338 int d0, d1; slow_zero_page() local 344 : "=&c" (d0), "=&D" (d1) slow_zero_page() 360 int d0, d1, d2; slow_copy_page() local 365 : "=&c" (d0), "=&D" (d1), "=&S" (d2) slow_copy_page()
/linux-4.4.14/lib/
H A D	rational.c	35 unsigned long n, d, n0, d0, n1, d1; rational_best_approximation() local 39 n1 = d0 = 1; rational_best_approximation() 44 d1 = d0; rational_best_approximation() 56 t = d0 + a * d1; rational_best_approximation() 57 d0 = d1; rational_best_approximation()
H A D	checksum.c	23 * specify d0 and d1 as scratch registers. Letting gcc
/linux-4.4.14/arch/m68k/ifpsp060/src/
H A D	isp.S	98 mov.l %d0,-(%sp) 99 mov.l (_060ISP_TABLE-0x80+_off_chk,%pc),%d0 100 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 101 mov.l 0x4(%sp),%d0 106 mov.l %d0,-(%sp) 107 mov.l (_060ISP_TABLE-0x80+_off_divbyzero,%pc),%d0 108 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 109 mov.l 0x4(%sp),%d0 114 mov.l %d0,-(%sp) 115 mov.l (_060ISP_TABLE-0x80+_off_trace,%pc),%d0 116 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 117 mov.l 0x4(%sp),%d0 122 mov.l %d0,-(%sp) 123 mov.l (_060ISP_TABLE-0x80+_off_access,%pc),%d0 124 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 125 mov.l 0x4(%sp),%d0 130 mov.l %d0,-(%sp) 131 mov.l (_060ISP_TABLE-0x80+_off_done,%pc),%d0 132 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 133 mov.l 0x4(%sp),%d0 140 mov.l %d0,-(%sp) 141 mov.l (_060ISP_TABLE-0x80+_off_cas,%pc),%d0 142 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 143 mov.l 0x4(%sp),%d0 148 mov.l %d0,-(%sp) 149 mov.l (_060ISP_TABLE-0x80+_off_cas2,%pc),%d0 150 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 151 mov.l 0x4(%sp),%d0 156 mov.l %d0,-(%sp) 157 mov.l (_060ISP_TABLE-0x80+_off_lock,%pc),%d0 158 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 159 mov.l 0x4(%sp),%d0 164 mov.l %d0,-(%sp) 165 mov.l (_060ISP_TABLE-0x80+_off_unlock,%pc),%d0 166 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 167 mov.l 0x4(%sp),%d0 174 mov.l %d0,-(%sp) 175 mov.l (_060ISP_TABLE-0x80+_off_imr,%pc),%d0 176 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 177 mov.l 0x4(%sp),%d0 182 mov.l %d0,-(%sp) 183 mov.l (_060ISP_TABLE-0x80+_off_dmr,%pc),%d0 184 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 185 mov.l 0x4(%sp),%d0 190 mov.l %d0,-(%sp) 191 mov.l (_060ISP_TABLE-0x80+_off_dmw,%pc),%d0 192 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 193 mov.l 0x4(%sp),%d0 198 mov.l %d0,-(%sp) 199 mov.l (_060ISP_TABLE-0x80+_off_irw,%pc),%d0 200 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 201 mov.l 0x4(%sp),%d0 206 mov.l %d0,-(%sp) 207 mov.l (_060ISP_TABLE-0x80+_off_irl,%pc),%d0 208 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 209 mov.l 0x4(%sp),%d0 214 mov.l %d0,-(%sp) 215 mov.l (_060ISP_TABLE-0x80+_off_drb,%pc),%d0 216 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 217 mov.l 0x4(%sp),%d0 222 mov.l %d0,-(%sp) 223 mov.l (_060ISP_TABLE-0x80+_off_drw,%pc),%d0 224 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 225 mov.l 0x4(%sp),%d0 230 mov.l %d0,-(%sp) 231 mov.l (_060ISP_TABLE-0x80+_off_drl,%pc),%d0 232 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 233 mov.l 0x4(%sp),%d0 238 mov.l %d0,-(%sp) 239 mov.l (_060ISP_TABLE-0x80+_off_dwb,%pc),%d0 240 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 241 mov.l 0x4(%sp),%d0 246 mov.l %d0,-(%sp) 247 mov.l (_060ISP_TABLE-0x80+_off_dww,%pc),%d0 248 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 249 mov.l 0x4(%sp),%d0 254 mov.l %d0,-(%sp) 255 mov.l (_060ISP_TABLE-0x80+_off_dwl,%pc),%d0 256 pea.l (_060ISP_TABLE-0x80,%pc,%d0) 257 mov.l 0x4(%sp),%d0 290 set EXC_D0, EXC_DREGS+(0*4) # offset of d0 401 movm.l &0x3fff,EXC_DREGS(%a6) # store d0-d7/a0-a5 429 mov.l %d0,EXC_OPWORD(%a6) # store extword on stack 466 btst &0x1e,%d0 # group1 or group2 474 btst &0x16,%d0 # test for div64 523 btst &0x18,%d0 # test for not movep 531 btst &0x1b,%d0 # test for chk2,cmp2 534 swap %d0 # put opword in lo word 535 cmpi.b %d0,&0xfc # test for cas2 588 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 654 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 688 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 725 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 763 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 790 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 804 # d0 = fslw 807 mov.l %d0,-0x4(%a6) # save partial fslw 810 movm.l (%sp)+,&0x7fff # restore d0-d7/a0-a6 829 movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5 850 clr.l %d0 851 mov.b EXC_SAVREG(%a6),%d0 # regno to restore 852 mov.l EXC_SAVVAL(%a6),(EXC_AREGS,%a6,%d0.l*4) # restore value 868 # d0 = number of bytes related to effective address (w,l) # 873 # d0 = FSLW # 914 mov.l %d0,%a0 # move # bytes to a0 917 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word 918 mov.w %d0,%d1 # make a copy 920 andi.w &0x3f,%d0 # extract mode field 924 mov.w (tbl_ea_mode.b,%pc,%d0.w*2), %d0 # fetch jmp distance 925 jmp (tbl_ea_mode.b,%pc,%d0.w*1) # jmp to correct ea mode 1040 mov.l %a0,%d0 # copy no. bytes 1042 add.l %a0,%d0 # increment 1043 mov.l %d0,EXC_A0(%a6) # save incremented value 1051 mov.l %a0,%d0 # copy no. bytes 1053 add.l %a0,%d0 # increment 1054 mov.l %d0,EXC_A1(%a6) # save incremented value 1062 mov.l %a0,%d0 # copy no. bytes 1064 add.l %a0,%d0 # increment 1065 mov.l %d0,EXC_A2(%a6) # save incremented value 1073 mov.l %a0,%d0 # copy no. bytes 1075 add.l %a0,%d0 # increment 1076 mov.l %d0,EXC_A3(%a6) # save incremented value 1084 mov.l %a0,%d0 # copy no. bytes 1086 add.l %a0,%d0 # increment 1087 mov.l %d0,EXC_A4(%a6) # save incremented value 1095 mov.l %a0,%d0 # copy no. bytes 1097 add.l %a0,%d0 # increment 1098 mov.l %d0,EXC_A5(%a6) # save incremented value 1106 mov.l %a0,%d0 # copy no. bytes 1108 add.l %a0,%d0 # increment 1109 mov.l %d0,EXC_A6(%a6) # save incremented value 1119 mov.l %a0,%d0 # copy no. bytes 1121 add.l %a0,%d0 # increment 1122 mov.l %d0,EXC_A7(%a6) # save incremented value 1129 mov.l EXC_A0(%a6),%d0 # Get current a0 1130 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1131 sub.l %a0,%d0 # Decrement 1132 mov.l %d0,EXC_A0(%a6) # Save decr value 1133 mov.l %d0,%a0 1140 mov.l EXC_A1(%a6),%d0 # Get current a1 1141 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1142 sub.l %a0,%d0 # Decrement 1143 mov.l %d0,EXC_A1(%a6) # Save decr value 1144 mov.l %d0,%a0 1151 mov.l EXC_A2(%a6),%d0 # Get current a2 1152 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1153 sub.l %a0,%d0 # Decrement 1154 mov.l %d0,EXC_A2(%a6) # Save decr value 1155 mov.l %d0,%a0 1162 mov.l EXC_A3(%a6),%d0 # Get current a3 1163 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1164 sub.l %a0,%d0 # Decrement 1165 mov.l %d0,EXC_A3(%a6) # Save decr value 1166 mov.l %d0,%a0 1173 mov.l EXC_A4(%a6),%d0 # Get current a4 1174 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1175 sub.l %a0,%d0 # Decrement 1176 mov.l %d0,EXC_A4(%a6) # Save decr value 1177 mov.l %d0,%a0 1184 mov.l EXC_A5(%a6),%d0 # Get current a5 1185 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1186 sub.l %a0,%d0 # Decrement 1187 mov.l %d0,EXC_A5(%a6) # Save decr value 1188 mov.l %d0,%a0 1195 mov.l EXC_A6(%a6),%d0 # Get current a6 1196 mov.l %d0,EXC_SAVVAL(%a6) # save in case of access error 1197 sub.l %a0,%d0 # Decrement 1198 mov.l %d0,EXC_A6(%a6) # Save decr value 1199 mov.l %d0,%a0 1208 mov.l EXC_A7(%a6),%d0 # Get current a7 1209 sub.l %a0,%d0 # Decrement 1210 mov.l %d0,EXC_A7(%a6) # Save decr value 1211 mov.l %d0,%a0 1225 mov.w %d0,%a0 # sign extend displacement 1237 mov.w %d0,%a0 # sign extend displacement 1249 mov.w %d0,%a0 # sign extend displacement 1261 mov.w %d0,%a0 # sign extend displacement 1273 mov.w %d0,%a0 # sign extend displacement 1285 mov.w %d0,%a0 # sign extend displacement 1297 mov.w %d0,%a0 # sign extend displacement 1309 mov.w %d0,%a0 # sign extend displacement 1324 bsr.l _imem_read_word # fetch extword in d0 1333 btst &0x8,%d0 1338 mov.l %d0,%d5 # put extword in d5 1346 mov.l %d0,%d1 1352 btst &0xb,%d0 # is it word or long? 1356 mov.l %d0,%d2 1362 extb.l %d0 # sign extend displacement 1363 add.l %d1,%d0 # index + disp 1364 add.l %d0,%a0 # An + (index + disp) 1393 mov.w %d0,%a0 # return <ea> in a0 1407 mov.l %d0,%a0 # return <ea> in a0 1421 mov.w %d0,%a0 # sign extend displacement 1447 btst &0x8,%d0 # is disp only 8 bits? 1454 mov.l %d0,%d5 # put extword in d5 1462 mov.l %d0,%d1 # make extword copy 1468 btst &0xb,%d0 # is index word or long? 1472 mov.l %d0,%d2 # make extword copy 1478 extb.l %d0 # sign extend displacement 1479 add.l %d1,%d0 # index + disp 1480 add.l %d0,%a0 # An + (index + disp) 1506 bfextu %d5{&21:&2},%d0 1507 lsl.l %d0,%d2 1513 bfextu %d5{&26:&2},%d0 # get bd size 1515 cmpi.b %d0,&2 1535 ext.l %d0 # sign extend bd 1538 add.l %d0,%d3 # base += bd 1540 bfextu %d5{&30:&2},%d0 # is od suppressed? 1542 cmpi.b %d0,&0x2 1563 ext.l %d0 # sign extend od 1567 clr.l %d0 1569 mov.l %d0,%d4 1579 add.l %d2,%d0 # <ea> += index 1580 add.l %d4,%d0 # <ea> += od 1591 add.l %d4,%d0 # ea += od 1596 mov.l %d3,%d0 1598 mov.l %d0,%a0 1613 mov.l &0x01010001,%d0 # pass fslw 1631 # d0 = FSLW # 1654 mov.b %d1,%d0 1655 and.w &0x7,%d0 # extract Ay from opcode word 1657 mov.l (EXC_AREGS,%a6,%d0.w*4),%a0 # fetch ay 1666 mov.w %d1,%d0 1667 rol.w &0x7,%d0 1668 and.w &0x7,%d0 # extract Dx from opcode word 1670 mov.l (EXC_DREGS,%a6,%d0.w*4), %d0 # fetch dx 1676 # d0 = Dx 1678 mov.l %d0,%d2 # store data 1681 mov.l %d2,%d0 1691 mov.l %d2,%d0 1701 mov.l %d2,%d0 1711 mov.l %d2,%d0 1721 # d0 = Dx 1723 mov.l %d0,%d2 # store data 1725 lsr.w &0x8,%d0 1734 mov.l %d2,%d0 1758 mov.l %d0,%d2 1769 mov.b %d0,%d2 # append bytes 1780 mov.b %d0,%d2 # append bytes 1791 mov.b %d0,%d2 # append bytes 1810 mov.l %d0,%d2 1821 mov.b %d0,%d2 # append bytes 1841 mov.l &0x00a10001,%d0 # pass fslw 1851 mov.l &0x01210001,%d0 # pass fslw 1870 # d0 = FSLW # 1897 mov.b EXC_EXTWORD(%a6), %d0 # fetch hi extension word 1898 rol.b &0x4, %d0 # rotate reg bits into lo 1899 and.w &0xf, %d0 # extract reg bits 1901 mov.l (EXC_DREGS,%a6,%d0.w*4), %d2 # get regval 1908 # bound into d0 and the higher bound into d1. 1916 mov.l %d0,%d3 # save long lower bound 1924 mov.l %d0,%d1 # long upper bound in d1 1925 mov.l %d3,%d0 # long lower bound in d0 1938 mov.w %d0, %d1 # place hi in %d1 1939 swap %d0 # place lo in %d0 1941 ext.l %d0 # sign extend lo bnd 1962 mov.b %d0, %d1 # place hi in %d1 1963 lsr.w &0x8, %d0 # place lo in %d0 1965 extb.l %d0 # sign extend lo bnd 1983 sub.l %d0, %d2 # (Rn - lo) 1986 sub.l %d0, %d1 # (hi - lo) 2024 mov.l &0x01010001,%d0 # pass fslw 2034 mov.l &0x01410001,%d0 # pass fslw 2054 # d0 = FSLW # 2087 mov.b EXC_OPWORD+1(%a6), %d0 2088 andi.b &0x38, %d0 # extract src mode 2092 mov.b EXC_OPWORD+1(%a6), %d0 # extract Dn from opcode 2093 andi.w &0x7, %d0 2094 mov.l (EXC_DREGS,%a6,%d0.w*4), %d7 # fetch divisor from register 2099 mov.b EXC_EXTWORD+1(%a6), %d0 # extract Dr from extword 2101 and.w &0x7, %d0 2104 mov.w %d0, NDRSAVE(%a6) # save Dr for later 2108 mov.l (EXC_DREGS,%a6,%d0.w*4), %d5 # get dividend hi 2173 mov.b NDIVISOR(%a6), %d0 2174 eor.b %d0, NDIVIDEND(%a6) # chk if quotient is negative 2196 mov.w NDRSAVE(%a6), %d0 # get Dr off stack 2201 mov.l %d5, (EXC_DREGS,%a6,%d0.w*4) # save remainder 2324 mov.w %d4,%d0 2327 tst.w %d0 # is upper word set? 2430 movq.l &LONG,%d0 2442 mov.l %d0, %d7 2455 mov.l %d0,%d7 2473 mov.l &0x01010001,%d0 # pass fslw 2492 # d0 = FSLW # 2515 mov.b EXC_OPWORD+1(%a6), %d0 # extract src {mode,reg} 2516 cmpi.b %d0, &0x7 # is src mode Dn or other? 2522 andi.w &0x7, %d0 # extract Dn 2523 mov.l (EXC_DREGS,%a6,%d0.w*4), %d3 # fetch multiplier 2664 movq.l &LONG, %d0 # pass # of bytes 2676 mov.l %d0, %d3 # store multiplier in %d3 2690 mov.l %d0,%d3 2708 mov.l &0x01010001,%d0 # pass fslw 2727 # d0 = instruction extension word # 2765 mov.l %d0,EXC_TEMP+0x4(%a6) # store for possible restart 2766 mov.l %d0,%d1 # extension word in d0 2768 rol.w &0x4,%d0 2769 andi.w &0xf,%d0 # extract Rn2 2770 mov.l (EXC_DREGS,%a6,%d0.w*4),%a1 # fetch ADDR2 2773 mov.l %d1,%d0 2779 andi.w &0x7,%d0 # extract Dc2 2780 mov.l (EXC_DREGS,%a6,%d0.w*4),%d3 # fetch Compare2 Op 2781 mov.w %d0,DC2(%a6) 2783 mov.w EXC_EXTWORD(%a6),%d0 2784 mov.l %d0,%d1 2786 rol.w &0x4,%d0 2787 andi.w &0xf,%d0 # extract Rn1 2788 mov.l (EXC_DREGS,%a6,%d0.w*4),%a0 # fetch ADDR1 2791 mov.l %d1,%d0 2797 andi.w &0x7,%d0 # extract Dc1 2798 mov.l (EXC_DREGS,%a6,%d0.w*4),%d2 # fetch Compare1 Op 2799 mov.w %d0,DC1(%a6) 2811 mov.l %d6,%d0 # pass mode 2814 tst.l %d0 # error? 2818 mov.l %d6,%d0 # pass mode 2822 tst.l %d0 # error? 2833 mov.l %d0,-(%sp) # save FSLW 2835 mov.l %d6,%d0 # pass mode 2838 mov.l (%sp)+,%d0 # restore FSLW 2850 cmp.w %d0,%d2 2863 mov.w %d0,(2+EXC_DREGS,%a6,%d2.w*4) # store new Compare1 Op 2868 mov.l %d2,%d0 # pass mode 2873 mov.l %d2,%d0 # pass mode 2881 cmp.l %d0,%d2 2894 mov.l %d0,(EXC_DREGS,%a6,%d2.w*4) # store new Compare1 Op 2899 mov.l %d2,%d0 # pass mode 2904 mov.l %d2,%d0 # pass mode 2913 mov.l EXC_TEMP+0x4(%a6),%d0 2941 # d0 = FSLW # 2957 # d0 = 0 => in range; -1 => out of range # 3009 movq.l &0x2,%d0 # size = 2 bytes 3016 movq.l &0x4,%d0 # size = 4 bytes 3022 mov.w EXC_EXTWORD(%a6),%d0 # fetch cas extension word 3023 mov.l %d0,%d1 # make a copy 3025 lsr.w &0x6,%d0 3026 andi.w &0x7,%d0 # extract Du 3027 mov.l (EXC_DREGS,%a6,%d0.w*4),%d2 # get update operand 3038 mov.l %d6,%d0 # pass mode 3040 tst.l %d0 # did error occur? 3056 cmp.w %d0,%d4 # do word compare 3063 mov.w %d0,(EXC_DREGS+2,%a6,%d3.w*4) # Dc = destination 3069 sne %d0 # pass mode 3077 cmp.l %d0,%d4 # do longword compare 3084 mov.l %d0,(EXC_DREGS,%a6,%d3.w*4) # Dc = destination 3090 sne %d0 # pass mode 3111 # At this stage, it would be nice if d0 held the FSLW. 3121 mov.l %d0,-(%sp) 3123 mov.l (%sp)+,%d0 3137 mov.l %d0,EXC_IVOFF+0x6(%a6) # put FSLW on stack 3146 clr.l %d0 # clear return result 3153 rts # yes; return d0 = 0 3155 mov.l &-0x1,%d0 # out of range; return d0 = -1 3260 movq.l &0x1,%d0 # load user data fc 3263 movq.l &0x5,%d0 # load supervisor data fc 3285 movc %d0,%sfc # store new SFC 3286 movc %d0,%dfc # store new DFC 3319 mov.l %a0,%d0 # is ADDR1 misaligned? 3320 andi.b &0x3,%d0 3322 cmpi.b %d0,&0x2 3346 movs.l (%a0),%d0 # fetch Dest1[31:0] 3352 cmp.l %d0,%d2 # Dest1 - Compare1 3369 movs.l %d0,(%a0) # Dest1[31:0] -> DEST1 3437 movs.l (%a0),%d0 # fetch Dest1[31:0] 3443 cmp.l %d0,%d2 # Dest1 - Compare1 3467 swap %d0 # get Dest1[31:16] 3468 movs.w %d0,(%a0)+ # Dest1[31:16] -> DEST1 3470 swap %d0 # get Dest1[15:0] 3475 movs.w %d0,(%a0) # Dest1[15:0] -> DEST1+0x2 3497 movs.l (%a0),%d0 # fetch Dest1[31:0] 3503 cmp.l %d0,%d2 # Dest1 - Compare1 3536 rol.l &0x8,%d0 # get Dest1[31:24] 3537 movs.b %d0,(%a0)+ # Dest1[31:24] -> DEST1 3538 swap %d0 # get Dest1[23:8] 3539 movs.w %d0,(%a0)+ # Dest1[23:8] -> DEST1+0x1 3544 rol.l &0x8,%d0 # get Dest1[7:0] 3546 movs.b %d0,(%a0) # Update1[7:0] -> DEST1+0x3 3587 movc %d0,%sfc # store new SFC 3588 movc %d0,%dfc # store new DFC 3621 mov.l %a0,%d0 # is ADDR1 misaligned? 3622 btst &0x0,%d0 3646 movs.w (%a0),%d0 # fetch Dest1[15:0] 3652 cmp.w %d0,%d2 # Dest1 - Compare1 3669 movs.w %d0,(%a0) # Dest1[15:0] -> DEST1 3737 movs.w (%a0),%d0 # fetch Dest1[15:0] 3743 cmp.w %d0,%d2 # Dest1 - Compare1 3767 ror.l &0x8,%d0 # get Dest1[15:8] 3768 movs.b %d0,(%a0)+ # Dest1[15:8] -> DEST1 3770 rol.l &0x8,%d0 # get Dest1[7:0] 3775 movs.b %d0,(%a0) # Dest1[7:0] -> DEST1+0x1 3872 movq.l &0x1,%d0 # load user data fc 3875 movq.l &0x5,%d0 # load supervisor data fc 3896 movc %d0,%sfc # load new sfc 3897 movc %d0,%dfc # load new dfc 3936 movs.w (%a0),%d0 # fetch Dest[15:0] 3937 cmp.w %d0,%d4 # Dest - Compare 3960 ror.l &0x8,%d0 # get Dest[15:8] 3961 movs.b %d0,(%a0)+ # Dest[15:8] -> DEST 3963 rol.l &0x8,%d0 # get Dest[7:0] 3968 movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x1 4054 movc %d0,%sfc # load new sfc 4055 movc %d0,%dfc # load new dfc 4092 movs.l (%a0),%d0 # fetch Dest[31:0] 4093 cmp.l %d0,%d4 # Dest - Compare 4116 swap %d0 # get Dest[31:16] 4117 movs.w %d0,(%a0)+ # Dest[31:16] -> DEST 4118 swap %d0 # get Dest[15:0] 4124 movs.w %d0,(%a0) # Dest[15:0] -> DEST+0x2 4200 movc %d0,%sfc # load new sfc 4201 movc %d0,%dfc # load new dfc 4240 movs.l (%a0),%d0 # fetch Dest[31:0] 4241 cmp.l %d0,%d4 # Dest - Compare 4262 rol.l &0x8,%d0 # get Dest[31:24] 4263 movs.b %d0,(%a0)+ # Dest[31:24] -> DEST 4264 swap %d0 # get Dest[23:8] 4265 movs.w %d0,(%a0)+ # Dest[23:8] -> DEST+0x1 4270 rol.l &0x8,%d0 # get Dest[7:0] 4272 movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x3
H A D	ftest.S	69 tst.l %d0 269 tst.b %d0 273 tst.b %d0 309 tst.b %d0 313 tst.b %d0 346 tst.b %d0 350 tst.b %d0 382 tst.b %d0 386 tst.b %d0 419 tst.b %d0 423 tst.b %d0 454 tst.b %d0 458 tst.b %d0 461 clr.l %d0 501 tst.b %d0 505 tst.b %d0 537 tst.b %d0 541 tst.b %d0 567 tst.b %d0 571 tst.b %d0 597 tst.b %d0 601 tst.b %d0 627 tst.b %d0 631 tst.b %d0 658 tst.b %d0 662 tst.b %d0 683 mov.l &0xffffffaa,%d0 693 fmovm.x %d0,-(%sp) 713 tst.b %d0 717 tst.b %d0 750 mov.l &0xffffffaa,%d0 759 fmovm.x (%sp)+,%d0 769 tst.b %d0 773 tst.b %d0 793 mov.l &0xffffff00,%d0 803 fmovm.x %d0,-(%sp) 813 tst.b %d0 817 tst.b %d0 820 clr.l %d0 864 tst.b %d0 868 tst.b %d0 871 clr.l %d0 916 tst.b %d0 920 tst.b %d0 923 clr.l %d0 968 tst.b %d0 972 tst.b %d0 975 clr.l %d0 1019 tst.b %d0 1023 tst.b %d0 1026 clr.l %d0 1070 tst.b %d0 1074 tst.b %d0 1077 clr.l %d0 1121 tst.b %d0 1125 tst.b %d0 1128 clr.l %d0 1172 tst.b %d0 1176 tst.b %d0 1179 clr.l %d0 1223 tst.b %d0 1227 tst.b %d0 1230 clr.l %d0 1273 tst.b %d0 1277 tst.b %d0 1315 tst.b %d0 1319 tst.b %d0 1356 tst.b %d0 1360 tst.b %d0 1363 clr.l %d0 1372 mov.l &14,%d0 1376 dbra.w %d0,chkregs_loop 1378 mov.w ICCR(%a6),%d0 1380 cmp.w %d0,%d1 1383 clr.l %d0 1387 movq.l &0x1,%d0 1392 movq.l &0x1,%d0 1398 mov.l &23,%d0 1402 dbra.w %d0,chkfpregs_loop 1413 clr.l %d0 1417 movq.l &0x1,%d0 1443 mov.l %d0,-(%sp) 1444 mov.l (TESTTOP-0x80+0x0,%pc),%d0 1445 pea (TESTTOP-0x80,%pc,%d0) 1446 mov.l 0x4(%sp),%d0 1450 mov.l %d0,-(%sp) 1451 mov.l (TESTTOP-0x80+0x4,%pc),%d0 1452 pea (TESTTOP-0x80,%pc,%d0) 1453 mov.l 0x4(%sp),%d0
H A D	pfpsp.S	97 mov.l %d0,-(%sp) 98 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0 99 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 100 mov.l 0x4(%sp),%d0 105 mov.l %d0,-(%sp) 106 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0 107 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 108 mov.l 0x4(%sp),%d0 113 mov.l %d0,-(%sp) 114 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0 115 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 116 mov.l 0x4(%sp),%d0 121 mov.l %d0,-(%sp) 122 mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0 123 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 124 mov.l 0x4(%sp),%d0 129 mov.l %d0,-(%sp) 130 mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0 131 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 132 mov.l 0x4(%sp),%d0 137 mov.l %d0,-(%sp) 138 mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0 139 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 140 mov.l 0x4(%sp),%d0 145 mov.l %d0,-(%sp) 146 mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0 147 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 148 mov.l 0x4(%sp),%d0 153 mov.l %d0,-(%sp) 154 mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0 155 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 156 mov.l 0x4(%sp),%d0 161 mov.l %d0,-(%sp) 162 mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0 163 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 164 mov.l 0x4(%sp),%d0 169 mov.l %d0,-(%sp) 170 mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0 171 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 172 mov.l 0x4(%sp),%d0 177 mov.l %d0,-(%sp) 178 mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0 179 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 180 mov.l 0x4(%sp),%d0 185 mov.l %d0,-(%sp) 186 mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0 187 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 188 mov.l 0x4(%sp),%d0 193 mov.l %d0,-(%sp) 194 mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0 195 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 196 mov.l 0x4(%sp),%d0 203 mov.l %d0,-(%sp) 204 mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0 205 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 206 mov.l 0x4(%sp),%d0 211 mov.l %d0,-(%sp) 212 mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0 213 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 214 mov.l 0x4(%sp),%d0 219 mov.l %d0,-(%sp) 220 mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0 221 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 222 mov.l 0x4(%sp),%d0 227 mov.l %d0,-(%sp) 228 mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0 229 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 230 mov.l 0x4(%sp),%d0 235 mov.l %d0,-(%sp) 236 mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0 237 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 238 mov.l 0x4(%sp),%d0 243 mov.l %d0,-(%sp) 244 mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0 245 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 246 mov.l 0x4(%sp),%d0 251 mov.l %d0,-(%sp) 252 mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0 253 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 254 mov.l 0x4(%sp),%d0 259 mov.l %d0,-(%sp) 260 mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0 261 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 262 mov.l 0x4(%sp),%d0 267 mov.l %d0,-(%sp) 268 mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0 269 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 270 mov.l 0x4(%sp),%d0 275 mov.l %d0,-(%sp) 276 mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0 277 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 278 mov.l 0x4(%sp),%d0 283 mov.l %d0,-(%sp) 284 mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0 285 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 286 mov.l 0x4(%sp),%d0 644 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 653 mov.l %d0,EXC_OPWORD(%a6) 668 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 676 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 681 cmpi.b %d0,&UNNORM # is operand an UNNORM? 685 mov.b %d0,DTAG(%a6) # save dst optype tag 696 clr.l %d0 697 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 718 bfextu EXC_CMDREG(%a6){&6:&3},%d0 732 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 747 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 766 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 785 clr.l %d0 786 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 805 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 884 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 893 mov.l %d0,EXC_OPWORD(%a6) 906 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 919 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 924 cmpi.b %d0,&UNNORM # is operand an UNNORM? 928 mov.b %d0,DTAG(%a6) # save dst optype tag 939 clr.l %d0 940 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 957 bfextu EXC_CMDREG(%a6){&6:&3},%d0 982 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1009 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1040 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1059 clr.l %d0 1060 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 1079 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1209 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1235 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 1247 bfextu EXC_CMDREG(%a6){&0:&6},%d0 1248 cmpi.b %d0,&0x13 1270 cmpi.b %d0,&UNNORM # is operand an UNNORM? 1275 mov.b %d0,STAG(%a6) # save src optype tag 1277 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1290 cmpi.b %d0,&UNNORM # is operand an UNNORM? 1294 mov.b %d0,DTAG(%a6) # save dst optype tag 1297 clr.l %d0 1298 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1322 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set 1327 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1328 andi.b &0x38,%d0 # extract bits 3-5 1329 cmpi.b %d0,&0x38 # is instr fcmp or ftst? 1332 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1339 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1346 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled 1347 bfffo %d0{&24:&8},%d0 # find highest priority exception 1371 # shift enabled exception field into lo byte of d0; 1384 subi.l &24,%d0 # fix offset to be 0-8 1385 cmpi.b %d0,&0x6 # is exception INEX? (6) 1398 mov.l %d0,-(%sp) # save d0 1400 mov.l (%sp)+,%d0 # restore d0 1402 mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status 1406 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1419 mov.w &0x4,%d0 1422 mov.w &0x03,%d0 1431 bfextu EXC_CMDREG(%a6){&0:&6},%d0 # extract opclass,src fmt 1432 cmpi.b %d0,&0x11 # is class = 2 & fmt = sgl? 1434 cmpi.b %d0,&0x15 # is class = 2 & fmt = dbl? 1439 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1440 andi.w &0x7fff,%d0 # strip sign 1441 cmpi.w %d0,&0x3f80 # is |exp| == $3f80? 1443 cmpi.w %d0,&0x407f # no; is |exp| == $407f? 1453 neg.w %d0 # -shft amt 1454 addi.w &0x3f81,%d0 # adjust new exponent 1456 or.w %d0,LOCAL_EX(%a0) # insert new exponent 1469 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1470 andi.w &0x7fff,%d0 # strip sign 1471 cmpi.w %d0,&0x3c00 # is |exp| == $3c00? 1473 cmpi.w %d0,&0x43ff # no; is |exp| == $43ff? 1485 neg.w %d0 # -shft amt 1486 addi.w &0x3c01,%d0 # adjust new exponent 1488 or.w %d0,LOCAL_EX(%a0) # insert new exponent 1499 bfextu EXC_CMDREG(%a6){&3:&3},%d0 1500 cmpi.b %d0,&0x3 1502 cmpi.b %d0,&0x7 1516 mov.w FP_SRC_EX(%a6),%d0 # get exponent 1517 andi.w &0x7fff,%d0 # strip sign 1523 mov.b %d0,STAG(%a6) 1530 clr.l %d0 1531 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1550 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1571 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1595 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1615 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled 1616 bfffo %d0{&24:&8},%d0 # find highest priority exception 1655 subi.l &24,%d0 # fix offset to be 0-8 1659 mov.w (tbl_fu_out.b,%pc,%d0.w*2),%d0 1660 jmp (tbl_fu_out.b,%pc,%d0.w*1) 1678 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1710 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1739 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1763 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1791 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1820 mov.b %d0,STAG(%a6) # save src optype tag 1822 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1835 cmpi.b %d0,&UNNORM # is operand an UNNORM? 1839 mov.b %d0,DTAG(%a6) # save dst optype tag 1842 clr.l %d0 1843 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1867 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1872 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1873 andi.b &0x38,%d0 # extract bits 3-5 1874 cmpi.b %d0,&0x38 # is instr fcmp or ftst? 1877 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1891 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1909 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1924 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set 1925 bfffo %d0{&24:&8},%d0 # find highest priority exception 1949 # shift enabled exception field into lo byte of d0; 1962 subi.l &24,%d0 # fix offset to be 0-8 1963 cmpi.b %d0,&0x6 # is exception INEX? (6 or 7) 1986 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 1990 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2006 mov.w &0x3,%d0 2010 mov.w &0x4,%d0 2017 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2021 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2073 bfextu EXC_CMDREG(%a6){&6:&3},%d0 2080 cmpi.b %d0,&UNNORM # is operand an UNNORM? 2085 mov.b %d0,STAG(%a6) # save src optype tag 2087 clr.l %d0 2088 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 2107 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2122 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2140 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2160 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled 2161 bfffo %d0{&24:&8},%d0 # find highest priority exception 2169 cmpi.b %d0,&0x1a 2190 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2230 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2270 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2302 bfextu EXC_EXTWORD(%a6){&3:&3},%d0 # extract src specifier 2303 cmpi.b %d0,&0x1 # was src sgl? 2305 cmpi.b %d0,&0x5 # was src dbl? 2310 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2311 andi.w &0x7fff,%d0 # strip sign 2313 cmpi.w %d0,&0x3f80 2315 neg.w %d0 # make exponent negative 2316 addi.w &0x3f81,%d0 # find amt to shift 2318 lsr.l %d0,%d1 # shift it 2327 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2328 andi.w &0x7fff,%d0 # strip sign 2330 cmpi.w %d0,&0x3c00 2335 mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign 2336 clr.l %d0 # clear g,r,s 2340 mov.w &0x3c00,%d0 # new exponent 2343 bset &15,%d0 # set sign 2346 mov.w %d0,FP_SRC_EX(%a6) # insert new exponent 2457 mov.l %d0,-(%sp) # save d0 2458 movc %pcr,%d0 # load proc cr 2459 btst &0x1,%d0 # is FPU disabled? 2461 mov.l (%sp)+,%d0 # restore d0 2465 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2475 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2479 tst.w %d0 # is operation fmovem? 2504 btst &0xa,%d0 # is src fmt x or p? 2510 mov.l &0xc,%d0 # pass: 12 bytes 2522 mov.l &0xc,%d0 # pass: 12 bytes 2529 bfextu FP_SRC(%a6){&1:&15},%d0 # get exp 2530 cmpi.w %d0,&0x7fff # INF or NAN? 2535 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 2536 andi.b &0x0f,%d0 # clear all but last nybble 2553 mov.b %d0,STAG(%a6) # could be ANYTHING!!! 2554 cmpi.b %d0,&UNNORM # is operand an UNNORM? 2557 mov.b %d0,STAG(%a6) # set new optype tag 2567 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno 2572 mov.b %d0,DTAG(%a6) # could be ANYTHING!!! 2573 cmpi.b %d0,&UNNORM # is operand an UNNORM? 2576 mov.b %d0,DTAG(%a6) # set new optype tag 2590 clr.l %d0 2591 mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec 2619 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2629 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno 2638 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2648 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set 2649 bfffo %d0{&24:&8},%d0 # find highest priority exception 2665 subi.l &24,%d0 # fix offset to be 0-8 2666 cmpi.b %d0,&0x6 # is exception INEX? 2678 mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2698 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2736 btst &14,%d0 # ctrl or data reg 2763 # right now, d0 = the size. 2771 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2772 mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0) 2773 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2775 lea (EXC_SR,%a6,%d0),%a0 2780 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2787 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2788 mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0) 2789 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2790 mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0) 2792 lea (EXC_SR-0x4,%a6,%d0),%a0 2797 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2803 # right now, d1 = size and d0 = the strg. 2806 mov.b %d0,0x1+EXC_VOFF(%a6) # store size 2810 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2813 mov.l %d0,-(%sp) # save d0 2817 clr.l %d0 2818 mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size 2819 neg.l %d0 # get negative of size 2824 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2825 mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0) 2826 mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0) 2827 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2829 pea (%a6,%d0) # create final sp 2833 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2834 mov.l (%sp)+,(EXC_PC,%a6,%d0) 2835 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2837 pea (0x4,%a6,%d0) # create final sp 2845 fmovm.x &0x80,(0x4+0x8,%a6,%d0) 2846 addi.l &0xc,%d0 2850 fmovm.x &0x40,(0x4+0x8,%a6,%d0) 2851 addi.l &0xc,%d0 2855 fmovm.x &0x20,(0x4+0x8,%a6,%d0) 2856 addi.l &0xc,%d0 2860 fmovm.x &0x10,(0x4+0x8,%a6,%d0) 2861 addi.l &0xc,%d0 2865 fmovm.x &0x08,(0x4+0x8,%a6,%d0) 2866 addi.l &0xc,%d0 2870 fmovm.x &0x04,(0x4+0x8,%a6,%d0) 2871 addi.l &0xc,%d0 2875 fmovm.x &0x02,(0x4+0x8,%a6,%d0) 2876 addi.l &0xc,%d0 2880 fmovm.x &0x01,(0x4+0x8,%a6,%d0) 2883 mov.l 0x8(%sp),%d0 2899 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2950 mov.l (%sp)+,%d0 # restore d0 2954 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2961 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2963 tst.w %d0 # is instr fmovm? 2968 mov.l &0x10,%d0 # 16 bytes of instruction 2971 btst &0xe,%d0 # is instr fmovm ctrl 2974 bfextu %d0{&19:&3},%d1 2975 mov.l &0xc,%d0 2978 addq.l &0x4,%d0 2985 clr.l %d0 2987 mov.l EXC_EXTWPTR(%a6),%d0 2988 sub.l EXC_PC(%a6),%d0 2990 mov.w %d0,EXC_VOFF(%a6) # store stack shift value 2992 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3000 mov.l %d0,-(%sp) # save d0 3003 clr.l %d0 3004 mov.w 0x12(%sp),%d0 3006 add.l %d0,0x6(%sp) # make Next PC 3008 mov.l (%sp)+,%d0 # restore d0 3015 movc %pcr,%d0 3016 btst &0x1,%d0 3021 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3055 mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp) 3058 movm.l LOCAL_SIZE+EXC_DREGS(%sp),&0x0303 # restore d0-d1/a0-a1 3112 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3122 mov.l %d0,EXC_OPWORD(%a6) 3126 btst &13,%d0 # is instr an fmove out? 3140 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3189 bfextu %d0{&19:&3},%d0 # extract dst format field 3191 mov.w (tbl_operr.b,%pc,%d0.w*2),%a0 3205 mov.b L_SCR1(%a6),%d0 # load positive default result 3221 mov.w L_SCR1(%a6),%d0 # load positive default result 3237 mov.l L_SCR1(%a6),%d0 # load positive default result 3308 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3318 mov.l %d0,EXC_OPWORD(%a6) 3322 btst &13,%d0 # is instr an fmove out? 3336 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3359 bfextu %d0{&19:&3},%d0 # extract dst format field 3361 mov.w (tbl_snan.b,%pc,%d0.w*2),%a0 3375 mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN 3376 bset &6,%d0 # set SNAN bit 3392 mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN 3393 bset &14,%d0 # set SNAN bit 3409 mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN 3410 bset &30,%d0 # set SNAN bit 3428 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3429 andi.l &0x80000000,%d0 # keep sign 3430 ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit 3433 or.l %d1,%d0 # create sgl SNAN 3442 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3443 andi.l &0x80000000,%d0 # keep sign 3444 ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit 3448 or.l %d1,%d0 # create sgl SNAN 3455 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3456 andi.l &0x80000000,%d0 # keep sign 3457 ori.l &0x7ff80000,%d0 # insert new exponent,SNAN bit 3459 mov.l %d0,FP_SCR0_EX(%a6) # store to temp space 3460 mov.l &11,%d0 # load shift amt 3461 lsr.l %d0,%d1 3465 ror.l %d0,%d1 3468 lsr.l %d0,%d1 3472 movq.l &0x8,%d0 # pass: size of 8 bytes 3488 mov.l FP_SRC_HI(%a6),%d0 3489 bset &30,%d0 3490 mov.l %d0,FP_SCR0_HI(%a6) 3510 movq.l &0xc,%d0 # pass: size of extended 3533 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3600 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3610 mov.l %d0,EXC_OPWORD(%a6) 3614 btst &13,%d0 # is instr an fmove out? 3621 bfextu %d0{&19:&3},%d0 # fetch instr size 3650 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 3661 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 3666 cmpi.b %d0,&UNNORM # is operand an UNNORM? 3670 mov.b %d0,DTAG(%a6) # save dst optype tag 3673 clr.l %d0 3674 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 3687 bfextu EXC_CMDREG(%a6){&6:&3},%d0 3693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3701 clr.l %d0 3702 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3726 clr.l %d0 3727 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3774 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3784 mov.l %d0,EXC_OPWORD(%a6) 3798 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3855 # d0 = number of bytes to adjust <ea> by # 3877 mov.l %d0, %a0 # move # bytes to %a0 3879 mov.b 1+EXC_OPWORD(%a6), %d0 # fetch opcode word 3880 mov.l %d0, %d1 # make a copy 3882 andi.w &0x38, %d0 # extract mode field 3885 cmpi.b %d0,&0x18 # is mode (An)+ ? 3888 cmpi.b %d0,&0x20 # is mode -(An) ? 3891 or.w %d1,%d0 # concat mode,reg 3892 cmpi.b %d0,&0x3c # is mode #<data>? 3909 mov.l %a0,%d0 # pass amt to inc by 3920 mov.l %a0,%d0 # pass amt to dec by 3925 cmpi.b %d0,&0xc # is opsize ext or packed? 3962 mov.b 1+EXC_OPWORD(%a6),%d0 # fetch opcode word 3963 mov.l %d0,%d1 # make a copy 3965 andi.w &0x38,%d0 # extract mode field 3968 cmpi.b %d0,&0x18 # is mode (An)+ ? 3971 cmpi.b %d0,&0x20 # is mode -(An) ? 4214 # d0 = size of dump # 4217 # d0 = FSLW # 4219 # d0 = FSLW # 4272 # fetch the bit string into d0... 4275 andi.l &0x000000ff,%d0 # keep only lo byte 4277 mov.l %d0,-(%sp) # save strg 4278 mov.b (tbl_fmovm_size.w,%pc,%d0),%d0 4279 mov.l %d0,-(%sp) # save size 4281 mov.l (%sp)+,%d0 # restore size 4322 sub.l %d0,%sp # subtract size of dump 4386 mov.l %d0,-(%sp) # save size 4389 mov.l (%sp)+,%d0 4390 add.l %d0,%sp # clear fpreg data from stack 4403 sub.l %d0,%sp # make room for fpregs 4407 mov.l %d0,-(%sp) # save # of bytes 4411 mov.l (%sp)+,%d0 # retrieve # of bytes 4472 add.l %d0,%sp # remove fpregs from stack 4573 mov.l %d0,%a0 # move # bytes to a0 4577 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word 4578 mov.w %d0,%d1 # make a copy 4580 andi.w &0x3f,%d0 # extract mode field 4584 mov.w (tbl_fea_mode.b,%pc,%d0.w*2),%d0 # fetch jmp distance 4585 jmp (tbl_fea_mode.b,%pc,%d0.w*1) # jmp to correct ea mode 4700 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 4701 mov.l %d0,%d1 4704 mov.l %d0,%a0 4708 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 4709 mov.l %d0,%d1 4712 mov.l %d0,%a0 4716 mov.l %a2,%d0 # Get current a2 4717 mov.l %d0,%d1 4720 mov.l %d0,%a0 4724 mov.l %a3,%d0 # Get current a3 4725 mov.l %d0,%d1 4728 mov.l %d0,%a0 4732 mov.l %a4,%d0 # Get current a4 4733 mov.l %d0,%d1 4736 mov.l %d0,%a0 4740 mov.l %a5,%d0 # Get current a5 4741 mov.l %d0,%d1 4744 mov.l %d0,%a0 4748 mov.l (%a6),%d0 # Get current a6 4749 mov.l %d0,%d1 4752 mov.l %d0,%a0 4758 mov.l EXC_A7(%a6),%d0 # Get current a7 4759 mov.l %d0,%d1 4762 mov.l %d0,%a0 4769 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 4770 sub.l %a0,%d0 # Decrement 4771 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value 4772 mov.l %d0,%a0 4776 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 4777 sub.l %a0,%d0 # Decrement 4778 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value 4779 mov.l %d0,%a0 4783 mov.l %a2,%d0 # Get current a2 4784 sub.l %a0,%d0 # Decrement 4785 mov.l %d0,%a2 # Save decr value 4786 mov.l %d0,%a0 4790 mov.l %a3,%d0 # Get current a3 4791 sub.l %a0,%d0 # Decrement 4792 mov.l %d0,%a3 # Save decr value 4793 mov.l %d0,%a0 4797 mov.l %a4,%d0 # Get current a4 4798 sub.l %a0,%d0 # Decrement 4799 mov.l %d0,%a4 # Save decr value 4800 mov.l %d0,%a0 4804 mov.l %a5,%d0 # Get current a5 4805 sub.l %a0,%d0 # Decrement 4806 mov.l %d0,%a5 # Save decr value 4807 mov.l %d0,%a0 4811 mov.l (%a6),%d0 # Get current a6 4812 sub.l %a0,%d0 # Decrement 4813 mov.l %d0,(%a6) # Save decr value 4814 mov.l %d0,%a0 4820 mov.l EXC_A7(%a6),%d0 # Get current a7 4821 sub.l %a0,%d0 # Decrement 4822 mov.l %d0,EXC_A7(%a6) # Save decr value 4823 mov.l %d0,%a0 4837 mov.w %d0,%a0 # sign extend displacement 4850 mov.w %d0,%a0 # sign extend displacement 4863 mov.w %d0,%a0 # sign extend displacement 4876 mov.w %d0,%a0 # sign extend displacement 4889 mov.w %d0,%a0 # sign extend displacement 4902 mov.w %d0,%a0 # sign extend displacement 4915 mov.w %d0,%a0 # sign extend displacement 4928 mov.w %d0,%a0 # sign extend displacement 4942 mov.l %d0,-(%sp) 4946 bsr.l _imem_read_word # fetch extword in d0 4953 btst &0x8,%d0 4956 mov.l %d0,L_SCR1(%a6) # hold opword 4958 mov.l %d0,%d1 4970 ext.l %d0 # sign extend word index 4976 lsl.l %d1,%d0 # shift index by scale 4979 add.l %d2,%d0 # index + disp 4980 add.l %d0,%a0 # An + (index + disp) 4996 mov.w %d0,%a0 # return <ea> in a0 5010 mov.l %d0,%a0 # return <ea> in a0 5024 mov.w %d0,%a0 # sign extend displacement 5049 btst &0x8,%d0 # is disp only 8 bits? 5052 mov.l %d0,L_SCR1(%a6) # store opword 5054 mov.l %d0,%d1 # make extword copy 5066 ext.l %d0 # sign extend word index 5072 lsl.l %d1,%d0 # shift index by scale 5075 add.l %d2,%d0 # disp + index 5076 add.l %d0,%a0 # An + (index + disp) 5086 btst &0x6,%d0 # is the index suppressed? 5091 mov.l %d0,%d5 # put extword in d5 5099 mov.l %d0,L_SCR1(%a6) # save d0 (opword) 5100 bfextu %d0{&16:&4},%d1 # fetch dreg index 5104 mov.l %d0,%d2 # put index in d2 5113 bfextu %d5{&21:&2},%d0 5114 lsl.l %d0,%d2 5125 bfextu %d5{&26:&2},%d0 # get bd size 5128 cmpi.b %d0,&0x2 5149 ext.l %d0 # sign extend bd 5152 add.l %d0,%d3 # base += bd 5156 bfextu %d5{&30:&2},%d0 # is od suppressed? 5159 cmpi.b %d0,&0x2 5180 ext.l %d0 # sign extend od 5184 clr.l %d0 5187 mov.l %d0,%d4 5198 add.l %d2,%d0 # <ea> += index 5199 add.l %d4,%d0 # <ea> += od 5210 add.l %d4,%d0 # ea += od 5215 mov.l %d3,%d0 5217 mov.l %d0,%a0 5227 mov.w &0x0101,%d0 5236 mov.w &0x00e1,%d0 5241 mov.w &0x0161,%d0 5286 mov.b EXC_EXTWORD(%a6),%d0 # fetch reg select bits 5287 cmpi.b %d0,&0x9c # fpcr & fpsr & fpiar ? 5289 cmpi.b %d0,&0x98 # fpcr & fpsr ? 5291 cmpi.b %d0,&0x94 # fpcr & fpiar ? 5303 mov.l %d0,USER_FPSR(%a6) # store new FPSR to stack 5311 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 5323 mov.l %d0,USER_FPCR(%a6) # store new FPCR to stack 5331 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 5343 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 5351 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 5363 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 5371 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 5379 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to mem 5399 # d0 = scale amount # 5405 # do the opposite. Return this scale factor in d0. # 5418 mov.w SRC_EX(%a0),%d0 5420 mov.w %d0,FP_SCR0_EX(%a6) 5423 andi.w &0x7fff,%d0 5425 mov.w %d0,L_SCR1(%a6) # store src exponent 5428 cmp.w %d0, %d1 # is src exp >= dst exp? 5434 mov.l %d0,-(%sp) # save scale factor 5441 neg.w %d0 # new exp = -(shft val) 5442 mov.w %d0,L_SCR1(%a6) # inset new exp 5445 mov.w 2+L_SCR1(%a6),%d0 5446 subi.w &mantissalen+2,%d0 # subtract mantissalen+2 from larger exp 5448 cmp.w %d0,L_SCR1(%a6) # is difference >= len(mantissa)+2? 5451 mov.w L_SCR1(%a6),%d0 5452 add.w 0x2(%sp),%d0 # scale src exponent by scale factor 5455 or.w %d1,%d0 # concat {sgn,new exp} 5456 mov.w %d0,FP_SCR0_EX(%a6) # insert new dst exponent 5458 mov.l (%sp)+,%d0 # return SCALE factor 5465 mov.l (%sp)+,%d0 # return SCALE factor 5471 mov.l %d0,-(%sp) # save scale factor 5477 neg.w %d0 # new exp = -(shft val) 5478 mov.w %d0,2+L_SCR1(%a6) # inset new exp 5481 mov.w L_SCR1(%a6),%d0 5482 subi.w &mantissalen+2,%d0 # subtract mantissalen+2 from larger exp 5484 cmp.w %d0,2+L_SCR1(%a6) # is difference >= len(mantissa)+2? 5487 mov.w 2+L_SCR1(%a6),%d0 5488 add.w 0x2(%sp),%d0 # scale dst exponent by scale factor 5491 or.w %d1,%d0 # concat {sgn,new exp} 5492 mov.w %d0,FP_SCR1_EX(%a6) # insert new dst exponent 5494 mov.l (%sp)+,%d0 # return SCALE factor 5501 mov.l (%sp)+,%d0 # return SCALE factor 5519 # d0 = scale value # 5532 mov.w %d1,%d0 # make a copy 5536 andi.w &0x8000,%d0 # extract operand's sgn 5537 or.w &0x3fff,%d0 # insert new operand's exponent(=0) 5539 mov.w %d0,FP_SCR0_EX(%a6) # insert biased exponent 5545 mov.l &0x3fff,%d0 5546 sub.l %d1,%d0 # scale = BIAS + (-exp) 5553 neg.l %d0 # new exponent = -(shft val) 5554 mov.l %d0,%d1 # prepare for op_norm call 5572 # d0 = scale value # 5598 mov.l &0x3fff,%d0 5599 sub.l %d1,%d0 # scale = BIAS + (-exp) 5600 asr.l &0x1,%d0 # divide scale factor by 2 5606 mov.l &0x3ffe,%d0 5607 sub.l %d1,%d0 # scale = BIAS + (-exp) 5608 asr.l &0x1,%d0 # divide scale factor by 2 5615 btst &0x0,%d0 # is exp even or odd? 5620 add.l &0x3fff,%d0 5621 asr.l &0x1,%d0 # divide scale factor by 2 5627 add.l &0x3ffe,%d0 5628 asr.l &0x1,%d0 # divide scale factor by 2 5646 # d0 = scale value # 5659 mov.w %d1,%d0 # make a copy 5663 andi.w &0x8000,%d0 # extract operand's sgn 5664 or.w &0x3fff,%d0 # insert new operand's exponent(=0) 5666 mov.w %d0,FP_SCR1_EX(%a6) # insert biased exponent 5672 mov.l &0x3fff,%d0 5673 sub.l %d1,%d0 # scale = BIAS + (-exp) 5679 neg.l %d0 # new exponent = -(shft val) 5680 mov.l %d0,%d1 # prepare for op_norm call 5804 # d0 = rounding precision # 5810 # d0 = guard,round,sticky # 5840 lsr.b &0x2, %d0 # shift prec to lo bits 5841 mov.w (tbl_thresh.b,%pc,%d0.w*2), %d1 # load prec threshold 5842 mov.w %d1, %d0 # copy d1 into d0 5843 sub.w FTEMP_EX(%a0), %d0 # diff = threshold - exp 5844 cmpi.w %d0, &66 # is diff > 65? (mant + g,r bits) 5847 clr.l %d0 # clear g,r,s 5850 bset &29, %d0 # yes; set sticky bit 5861 mov.l &0x20000000, %d0 # set sticky bit in return value 5872 # %d0{31:29} : initial guard,round,sticky # 5876 # %d0{31:29} : final guard,round,sticky # 5891 mov.l %d0, GRS(%a6) # place g,r,s after it 5897 mov.l %d1, %d0 # copy the denorm threshold 5910 mov.l GRS(%a6), %d0 # restore original g,r,s 5916 # %d0 = denorm threshold 5939 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 5940 mov.l &32, %d0 5941 sub.w %d1, %d0 # %d0 = 32 - %d1 5949 bfextu FTEMP_HI(%a0){&0:%d0}, %d2 # %d2 = new FTEMP_HI 5950 bfextu FTEMP_HI(%a0){%d0:&32}, %d1 # %d1 = new FTEMP_LO 5951 bfextu FTEMP_LO2(%a6){%d0:&32}, %d0 # %d0 = new G,R,S 5956 bftst %d0{&2:&30} # were bits shifted off? 5958 bset &rnd_stky_bit, %d0 # yes; set sticky bit 5961 and.l &0xe0000000, %d0 # clear all but G,R,S 5968 # %d0 = denorm threshold 5991 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 5993 mov.l &0x20, %d0 5994 sub.w %d1, %d0 # %d0 = 32 - %d1 6002 bfextu FTEMP_HI(%a0){&0:%d0}, %d2 # %d2 = new FTEMP_LO 6003 bfextu FTEMP_HI(%a0){%d0:&32}, %d1 # %d1 = new G,R,S 6007 bftst FTEMP_LO2(%a6){%d0:&31} # were any bits shifted off? 6010 mov.l %d1, %d0 # move new G,R,S to %d0 6014 mov.l %d1, %d0 # move new G,R,S to %d0 6015 bset &rnd_stky_bit, %d0 # set sticky bit 6020 and.l &0xe0000000, %d0 # clear all but G,R,S 6028 # %d0 = denorm threshold 6032 mov.w %d0, FTEMP_EX(%a0) # insert denorm threshold 6046 mov.l &0x20000000, %d0 # set sticky bit 6070 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 6071 mov.l %d0, %d1 # make a copy 6072 and.l &0xc0000000, %d0 # extract G,R 6098 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 6099 and.l &0x80000000, %d0 # extract R bit 6100 lsr.l &0x1, %d0 # shift high bit into R bit 6126 bset &rnd_stky_bit,%d0 # set new sticky bit 6149 # d0{31:29} = contains the g,r,s bits (extended) # 6156 # a0 is preserved and the g-r-s bits in d0 are cleared. # 6175 tst.l %d0 # are G,R,S zero? 6202 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 6219 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 6234 asl.l &0x1, %d0 # shift g-bit to c-bit 6258 tst.l %d0 # test for rs = 0 6280 tst.l %d0 # test rs = 0 6301 tst.l %d0 # test for rs = 0 6326 # d0 = extended precision g,r,s (in d0{31:29}) 6329 # d0{31:29} = guard, round, sticky 6333 # only. All registers except d0 are kept intact. d0 becomes an 6334 # updated guard,round,sticky in d0{31:29} 6348 # %d0 actually already hold g,r,s since _round() had it before calling 6382 tst.l %d0 # test original g,r,s 6405 tst.l %d0 # test word original g,r,s 6412 mov.l %d3, %d0 # return grs to d0 6433 # d0 = number of bit positions the mantissa was shifted # 6443 mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) 6446 bfffo %d0{&0:&32}, %d2 # how many places to shift? 6450 lsl.l %d2, %d0 # left shift hi(man) 6453 or.l %d3, %d0 # create hi(man) 6456 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 6459 mov.l %d2, %d0 # return shift amount 6474 mov.l %d2, %d0 # return shift amount 6495 # d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO # 6503 bfffo FTEMP_HI(%a0){&0:&32}, %d0 # how many shifts are needed? 6510 bfffo FTEMP_LO(%a0){&0:&32}, %d0 # is operand really a zero? 6513 add.w &32, %d0 # no; fix shift distance 6516 # d0 = # shifts needed for complete normalization 6523 cmp.w %d0, %d1 # will denorm push exp < 0? 6529 sub.w %d0, %d1 # shift exponent value 6530 mov.w FTEMP_EX(%a0), %d0 # load old exponent 6531 and.w &0x8000, %d0 # save old sign 6532 or.w %d0, %d1 # {sgn,new exp} 6537 mov.b &NORM, %d0 # return new optype tag 6547 bfextu FTEMP_HI(%a0){%d1:&32}, %d0 # extract new hi(man) 6548 mov.l %d0, FTEMP_HI(%a0) # save new hi(man) 6550 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 6551 lsl.l %d1, %d0 # extract new lo(man) 6552 mov.l %d0, FTEMP_LO(%a0) # save new lo(man) 6556 mov.b &DENORM, %d0 # return new optype tag 6565 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 6566 lsl.l %d1, %d0 # left shift lo(man) 6568 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 6573 mov.b &DENORM, %d0 # return new optype tag 6582 mov.b &ZERO, %d0 # fix optype tag 6596 # d0 = value of type tag # 6609 mov.w FTEMP_EX(%a0), %d0 # extract exponent 6610 andi.w &0x7fff, %d0 # strip off sign 6611 cmpi.w %d0, &0x7fff # is (EXP == MAX)? 6617 mov.b &NORM, %d0 6620 tst.w %d0 # is exponent = 0? 6628 mov.b &ZERO, %d0 6631 mov.b &DENORM, %d0 6642 mov.b &ZERO, %d0 6645 mov.b &UNNORM, %d0 6650 mov.l FTEMP_HI(%a0), %d0 6651 and.l &0x7fffffff, %d0 # msb is a don't care! 6654 mov.b &INF, %d0 6659 mov.b &QNAN, %d0 6662 mov.b &SNAN, %d0 6676 # d0 = value of type tag # 6687 mov.l FTEMP(%a0), %d0 6688 mov.l %d0, %d1 6690 andi.l &0x7ff00000, %d0 6693 cmpi.l %d0, &0x7ff00000 6697 mov.b &NORM, %d0 6705 mov.b &ZERO, %d0 6708 mov.b &DENORM, %d0 6716 mov.b &INF, %d0 6722 mov.b &SNAN, %d0 6725 mov.b &QNAN, %d0 6739 # d0 = value of type tag # 6750 mov.l FTEMP(%a0), %d0 6751 mov.l %d0, %d1 6753 andi.l &0x7f800000, %d0 6756 cmpi.l %d0, &0x7f800000 6760 mov.b &NORM, %d0 6766 mov.b &ZERO, %d0 6769 mov.b &DENORM, %d0 6775 mov.b &INF, %d0 6781 mov.b &SNAN, %d0 6784 mov.b &QNAN, %d0 6801 # d0 = scale factor # 6806 # d0.b = result FPSR_cc which caller may or may not want to save # 6812 # according to the scale factor passed in d0. Then, round the # 6815 # d0 in case the caller doesn't want to save them (as is the case for # 6830 sub.w %d0, %d1 6835 mov.l 0x4(%sp),%d0 # pass rnd prec. 6836 andi.w &0x00c0,%d0 6837 lsr.w &0x4,%d0 6861 clr.l %d0 6867 bset &z_bit, %d0 # yes; set zero ccode bit 6894 sub.w %d0,%d1 6899 clr.l %d0 # force rnd prec = ext 6921 clr.l %d0 6927 bset &z_bit,%d0 # yes; set zero ccode bit 6957 # d0 = rnd mode/prec # 6959 # hi(d0) = rnd prec # 6960 # lo(d0) = rnd mode # 6964 # d0.b = condition code bits # 6971 # resulting condition codes are returned in d0 in case the caller # 6979 lsr.b &0x4,%d0 # shift prec/mode 6980 or.b %d0,%d1 # concat the two 6981 mov.w %d1,%d0 # make a copy 6988 or.b %d0, %d1 # insert rnd mode 6989 swap %d0 6990 or.b %d0, %d1 # insert rnd prec 6991 mov.w %d1, %d0 # make a copy 6999 mov.b (tbl_ovfl_cc.b,%pc,%d0.w*1), %d0 # fetch result ccodes 7070 # d0 = round prec,mode # 7130 fmov.l %d0,%fpcr # insert rnd prec,mode 7132 fmov.b %fp0,%d0 # exec move out w/ correct rnd mode 7176 fmov.l %d0,%fpcr # insert rnd prec:mode 7178 fmov.w %fp0,%d0 # exec move out w/ correct rnd mode 7222 fmov.l %d0,%fpcr # insert rnd prec:mode 7224 fmov.l %fp0,%d0 # exec move out w/ correct rnd mode 7279 mov.l &0xc,%d0 # pass: opsize is 12 bytes 7300 mov.b FPCR_ENABLE(%a6),%d0 7301 andi.b &0x0a,%d0 # is UNFL or INEX enabled? 7320 neg.w %d0 # new exp = -(shft amt) 7321 andi.w &0x7fff,%d0 7323 or.w %d0,FP_SCR0_EX(%a6) # insert new exponent 7335 andi.b &0x30,%d0 # clear rnd prec 7336 ori.b &s_mode*0x10,%d0 # insert sgl prec 7337 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 7345 mov.w SRC_EX(%a0),%d0 # extract exponent 7346 andi.w &0x7fff,%d0 # strip sign 7348 cmpi.w %d0,&SGL_HI # will operand overflow? 7351 cmpi.w %d0,&SGL_LO # will operand underflow? 7364 fmov.s %fp0,%d0 # store does convert and round 7403 clr.l %d0 # pass: S.F. = 0 7464 mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode 7467 fmov.s %fp0,%d0 # store to single 7533 neg.l %d0 7534 andi.w &0x7fff,%d0 7535 bfins %d0,FP_SCR0_EX(%a6){&1:&15} 7558 clr.l %d0 # pass: zero g,r,s 7573 andi.b &0x30,%d0 # clear rnd prec 7574 ori.b &d_mode*0x10,%d0 # insert dbl prec 7575 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 7583 mov.w SRC_EX(%a0),%d0 # extract exponent 7584 andi.w &0x7fff,%d0 # strip sign 7586 cmpi.w %d0,&DBL_HI # will operand overflow? 7589 cmpi.w %d0,&DBL_LO # will operand underflow? 7605 fmov.l %fpsr,%d0 # save FPSR 7607 or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex 7611 movq.l &0x8,%d0 # pass: opsize is 8 bytes 7632 clr.l %d0 # pass: S.F. = 0 7647 mov.l %d0,L_SCR1(%a6) 7652 movq.l &0x8,%d0 # pass: opsize is 8 bytes 7668 mov.w 2+SRC_LO(%a0),%d0 7669 andi.w &0x7ff,%d0 7685 mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode 7692 movq.l &0x8,%d0 # pass: opsize is 8 bytes 7741 # d0 = hi(double precision result) # 7769 clr.l %d0 # clear d0 7770 mov.w FTEMP_EX(%a0),%d0 # get exponent 7771 subi.w &EXT_BIAS,%d0 # subtract extended precision bias 7772 addi.w &DBL_BIAS,%d0 # add double precision bias 7775 subq.w &0x1,%d0 # yes; denorm bias = DBL_BIAS - 1 7777 swap %d0 # d0 now in upper word 7778 lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp 7781 bset &0x1f,%d0 # if negative, set sign 7785 or.l %d1,%d0 # put these bits in ms word of double 7786 mov.l %d0,L_SCR1(%a6) # put the new exp back on the stack 7788 mov.l &21,%d0 # load shift count 7789 lsl.l %d0,%d1 # put lower 11 bits in upper bits 7792 bfextu %d1{&0:&21},%d0 # get ls 21 bits of double 7794 or.l %d0,%d1 # put them in double result 7795 mov.l L_SCR1(%a6),%d0 7808 # d0 = single precision result # 7834 clr.l %d0 7835 mov.w FTEMP_EX(%a0),%d0 # get exponent 7836 subi.w &EXT_BIAS,%d0 # subtract extended precision bias 7837 addi.w &SGL_BIAS,%d0 # add single precision bias 7840 subq.w &0x1,%d0 # yes; denorm bias = SGL_BIAS - 1 7842 swap %d0 # put exp in upper word of d0 7843 lsl.l &0x7,%d0 # shift it into single exp bits 7846 bset &0x1f,%d0 # if negative, put in sign first 7851 or.l %d1,%d0 # put these bits in ms word of single 7859 mov.b STAG(%a6),%d0 # fetch input type 7875 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch static field 7878 bfexts %d0{&25:&7},%d0 # extract k-factor 7879 mov.l %d0,-(%sp) 7890 mov.l (%sp)+,%d0 7901 tst.l %d0 7916 mov.l &0xc,%d0 # pass: opsize is 12 bytes 7939 cmpi.b %d0,&DENORM # is it a DENORM? 7943 cmpi.b %d0,&SNAN # is it an SNAN? 7969 # d0 rnd prec,mode # 7999 andi.b &0x30,%d0 # clear rnd prec 8000 ori.b &s_mode*0x10,%d0 # insert sgl prec 8005 andi.b &0x30,%d0 8006 ori.b &d_mode*0x10,%d0 # insert dbl prec 8010 mov.l %d0,L_SCR3(%a6) # store rnd info 8028 mov.l %d0,-(%sp) # save scale factor 1 8032 add.l %d0,(%sp) # SCALE_FACTOR = scale1 + scale2 8036 mov.l (%sp)+,%d0 # load S.F. 8037 cmp.l %d0,(tbl_fmul_ovfl.w,%pc,%d1.w*4) # would result ovfl? 8041 cmp.l %d0,(tbl_fmul_unfl.w,%pc,%d1.w*4) # would result unfl? 8073 sub.l %d0,%d1 # add scale factor 8118 mov.l L_SCR3(%a6),%d0 # pass rnd prec,mode 8120 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 8142 sub.l %d0,%d1 # add scale factor 8232 or.b %d0,FPSR_CC(%a6) # unf_res2 may have set 'Z' 8263 sub.l %d0,%d1 # add scale factor 8401 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 8403 eor.b %d0,%d1 8425 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 8427 eor.b %d0,%d1 8442 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 8444 eor.b %d0,%d1 8464 # d0 = round prec/mode # 8484 andi.b &0x30,%d0 # clear rnd prec 8485 ori.b &s_mode*0x10,%d0 # insert sgl precision 8490 andi.b &0x30,%d0 # clear rnd prec 8491 ori.b &d_mode*0x10,%d0 # insert dbl precision 8495 mov.l %d0,L_SCR3(%a6) # store rnd info 8504 andi.b &0xc0,%d0 # is precision extended? 8524 andi.b &0xc0,%d0 # is precision extended? 8548 neg.w %d0 # new exponent = -(shft val) 8549 addi.w &0x6000,%d0 # add new bias to exponent 8552 andi.w &0x7fff,%d0 # clear sign position 8553 or.w %d1,%d0 # concat new exo,old sign 8554 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 8562 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 8574 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow? 8576 cmpi.l %d0,&0x3fff-0x407e # will move in overflow? 8600 sub.l %d0,%d1 # add scale factor 8617 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow? 8619 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow? 8644 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z' 8660 sub.l %d0,%d1 # subtract scale factor 8698 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 8700 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 8715 sub.l %d0,%d1 # add scale factor 8764 fmov.l %fpsr,%d0 # no exceptions possible 8765 rol.l &0x8,%d0 # put ccodes in lo byte 8766 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 8786 # d0 rnd prec,mode # 8817 andi.b &0x30,%d0 # clear rnd prec 8818 ori.b &s_mode*0x10,%d0 # insert sgl prec 8823 andi.b &0x30,%d0 # clear rnd prec 8824 ori.b &d_mode*0x10,%d0 # insert dbl prec 8828 mov.l %d0,L_SCR3(%a6) # store rnd info 8850 mov.l %d0,-(%sp) # save scale factor 1 8855 add.l %d0,(%sp) 8859 mov.l (%sp)+,%d0 # load S.F. 8860 cmp.l %d0,(tbl_fdiv_ovfl.b,%pc,%d1.w*4) # will result overflow? 8863 cmp.l %d0,(tbl_fdiv_unfl.w,%pc,%d1.w*4) # will result underflow? 8887 sub.l %d0,%d1 # add scale factor 8900 mov.l (%sp)+,%d0 # restore scale factor 8904 mov.l %d0,-(%sp) # save scale factor 8913 fmov.l %fpsr,%d0 8916 or.l %d0,USER_FPSR(%a6) # save INEX,N 8919 mov.w (%sp),%d0 # fetch new exponent 8921 andi.l &0x7fff,%d0 # strip sign 8922 sub.l (%sp),%d0 # add scale factor 8923 cmp.l %d0,(tbl_fdiv_ovfl2.b,%pc,%d1.w*4) 8925 mov.l (%sp)+,%d0 8937 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 8939 or.b %d0,FPSR_CC(%a6) # set INF if applicable 8955 sub.l %d0,%d1 # add scale factor 9002 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set 9031 sub.l %d0,%d1 # add scale factoer 9166 mov.b SRC_EX(%a0),%d0 # result sign is exclusive 9168 eor.b %d0,%d1 9186 mov.b SRC_EX(%a0),%d0 # load both signs 9188 eor.b %d0,%d1 9206 mov.b DST_EX(%a1),%d0 # load both signs 9208 eor.b %d0,%d1 9239 # d0 = rnd prec,mode # 9258 andi.b &0x30,%d0 # clear rnd prec 9259 ori.b &s_mode*0x10,%d0 # insert sgl precision 9264 andi.b &0x30,%d0 # clear rnd prec 9265 ori.b &d_mode*0x10,%d0 # insert dbl prec 9269 mov.l %d0,L_SCR3(%a6) # store rnd info 9277 andi.b &0xc0,%d0 # is precision extended? 9287 mov.w SRC_EX(%a0),%d0 9288 eori.w &0x8000,%d0 # negate sign 9292 mov.w %d0,FP_SCR0_EX(%a6) 9301 andi.b &0xc0,%d0 # is precision extended? 9308 mov.w SRC_EX(%a0),%d0 9309 eori.w &0x8000,%d0 # negate sign 9313 mov.w %d0,FP_SCR0_EX(%a6) 9328 neg.w %d0 # new exponent = -(shft val) 9329 addi.w &0x6000,%d0 # add new bias to exponent 9332 andi.w &0x7fff,%d0 # clear sign position 9333 or.w %d1,%d0 # concat old sign, new exponent 9334 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 9342 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 9354 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow? 9356 cmpi.l %d0,&0x3fff-0x407e # will move in overflow? 9380 sub.l %d0,%d1 # add scale factor 9397 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow? 9399 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow? 9424 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z' 9441 sub.l %d0,%d1 # subtract scale factor 9478 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 9480 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 9495 sub.l %d0,%d1 # add scale factor 9544 fmov.l %fpsr,%d0 9545 rol.l &0x8,%d0 # put ccodes in lo byte 9546 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 9643 # d0 = round precision/mode # 9669 andi.b &0x30,%d0 # set prec = ext 9671 fmov.l %d0,%fpcr # set FPCR 9677 fmov.l %fpsr,%d0 # save FPSR 9678 or.l %d0,USER_FPSR(%a6) # set exception bits 9749 # d0 = round precision/mode # 9779 fmov.l %fpsr,%d0 # save FPSR 9780 or.l %d0,USER_FPSR(%a6) # set exception bits 9857 # d0 = rnd precision/mode # 9881 andi.b &0x30,%d0 # clear rnd prec 9882 ori.b &s_mode*0x10,%d0 # insert sgl precision 9887 andi.b &0x30,%d0 # clear rnd prec 9888 ori.b &d_mode*0x10,%d0 # insert dbl precision 9892 mov.l %d0,L_SCR3(%a6) # store rnd info 9900 andi.b &0xc0,%d0 # is precision extended? 9921 andi.b &0xc0,%d0 # is precision extended? 9928 mov.w SRC_EX(%a0),%d0 9929 bclr &15,%d0 # clear sign 9930 mov.w %d0,FP_SCR0_EX(%a6) # insert exponent 9946 neg.w %d0 # new exponent = -(shft val) 9947 addi.w &0x6000,%d0 # add new bias to exponent 9950 andi.w &0x7fff,%d0 # clear sign position 9951 or.w %d1,%d0 # concat old sign, new exponent 9952 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 9960 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 9972 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow? 9974 cmpi.l %d0,&0x3fff-0x407e # will move in overflow? 9998 sub.l %d0,%d1 # add scale factor 10015 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow? 10017 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow? 10039 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode 10056 sub.l %d0,%d1 # subtract scale factor 10093 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 10095 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 10110 sub.l %d0,%d1 # add scale factor 10175 # d0 = round prec/mode # 10203 fmov.l %fpsr,%d0 # save FPSR 10204 rol.l &0x8,%d0 # extract ccode bits 10205 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set) 10297 mov.l SRC_HI(%a0),%d0 10298 bset &31,%d0 # DENORM src; make into small norm 10299 mov.l %d0,FP_SCR0_HI(%a6) 10306 mov.l DST_HI(%a1),%d0 10307 bset &31,%d0 # DENORM src; make into small norm 10308 mov.l %d0,FP_SCR0_HI(%a6) 10316 mov.l DST_HI(%a1),%d0 10317 bset &31,%d0 # DENORM dst; make into small norm 10318 mov.l %d0,FP_SCR1_HI(%a6) 10319 mov.l SRC_HI(%a0),%d0 10320 bset &31,%d0 # DENORM dst; make into small norm 10321 mov.l %d0,FP_SCR0_HI(%a6) 10329 mov.b SRC_EX(%a0),%d0 # determine if like signs 10331 eor.b %d0,%d1 10335 tst.b %d0 # is src op negative? 10343 mov.b SRC_EX(%a0),%d0 # determine if like signs 10345 eor.b %d0,%d1 10349 tst.b %d0 # is src op negative? 10371 # d0 rnd prec,mode # 10391 mov.l %d0,L_SCR3(%a6) # store rnd info 10410 mov.l %d0,-(%sp) # save scale factor 1 10414 add.l (%sp)+,%d0 # SCALE_FACTOR = scale1 + scale2 10416 cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl? 10420 cmpi.l %d0,&0x3fff+0x0001 # would result unfl? 10444 sub.l %d0,%d1 # add scale factor 10476 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 10477 andi.b &0x30,%d0 # force prec = ext 10479 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 10490 sub.l %d0,%d1 # add scale factor 10545 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set 10568 sub.l %d0,%d1 # add scale factor 10712 # d0 rnd prec,mode # 10732 mov.l %d0,L_SCR3(%a6) # store rnd info 10754 mov.l %d0,-(%sp) # save scale factor 1 10759 add.l %d0,(%sp) 10763 mov.l (%sp)+,%d0 10764 cmpi.l %d0,&0x3fff-0x7ffe 10767 cmpi.l %d0,&0x3fff-0x0000 # will result underflow? 10791 sub.l %d0,%d1 # add scale factor 10815 sub.l %d0,%d1 # add scale factor 10829 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 10830 andi.b &0x30,%d0 # kill precision 10832 or.b %d0,FPSR_CC(%a6) # set INF if applicable 10844 sub.l %d0,%d1 # add scale factor 10878 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set 10901 sub.l %d0,%d1 # add scale factor 11068 andi.b &0x30,%d0 # clear rnd prec 11069 ori.b &s_mode*0x10,%d0 # insert sgl prec 11074 andi.b &0x30,%d0 # clear rnd prec 11075 ori.b &d_mode*0x10,%d0 # insert dbl prec 11079 mov.l %d0,L_SCR3(%a6) # store rnd info 11118 sub.l %d0,%d2 # add scale factor 11163 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 11165 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 11228 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set 11254 sub.l %d0,%d1 # add scale factor 11392 mov.b SRC_EX(%a0),%d0 # are the signs opposite 11394 eor.b %d0,%d1 11399 tst.b %d0 # are ZEROes positive or negative? 11453 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11455 eor.b %d1,%d0 11521 andi.b &0x30,%d0 # clear rnd prec 11522 ori.b &s_mode*0x10,%d0 # insert sgl prec 11527 andi.b &0x30,%d0 # clear rnd prec 11528 ori.b &d_mode*0x10,%d0 # insert dbl prec 11532 mov.l %d0,L_SCR3(%a6) # store rnd info 11571 sub.l %d0,%d2 # add scale factor 11616 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 11618 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 11681 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set 11707 sub.l %d0,%d1 # add scale factor 11845 mov.b SRC_EX(%a0),%d0 11847 eor.b %d1,%d0 11851 tst.b %d0 # is dst negative? 11905 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11907 eor.b %d1,%d0 11946 # d0 rnd prec,mode # 11966 andi.b &0x30,%d0 # clear rnd prec 11967 ori.b &s_mode*0x10,%d0 # insert sgl precision 11972 andi.b &0x30,%d0 # clear rnd prec 11973 ori.b &d_mode*0x10,%d0 # insert dbl precision 11977 mov.l %d0,L_SCR3(%a6) # store rnd info 11989 andi.b &0xc0,%d0 # is precision extended? 12006 andi.b &0xc0,%d0 # is precision extended? 12021 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 12034 cmpi.l %d0,&0x3fff-0x3f81 # will move in underflow? 12037 cmpi.l %d0,&0x3fff-0x407f # will move in overflow? 12061 sub.l %d0,%d1 # add scale factor 12079 cmpi.l %d0,&0x3fff-0x3c01 # will move in underflow? 12082 cmpi.l %d0,&0x3fff-0x43ff # will move in overflow? 12121 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode 12138 sub.l %d0,%d1 # subtract scale factor 12175 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 12177 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 12192 sub.l %d0,%d1 # add scale factor 12278 # d0 = value of register fetched # 12291 mov.w (tbl_fdreg.b,%pc,%d1.w*2),%d0 12292 jmp (tbl_fdreg.b,%pc,%d0.w*1) 12313 mov.l EXC_DREGS+0x0(%a6),%d0 12316 mov.l EXC_DREGS+0x4(%a6),%d0 12319 mov.l %d2,%d0 12322 mov.l %d3,%d0 12325 mov.l %d4,%d0 12328 mov.l %d5,%d0 12331 mov.l %d6,%d0 12334 mov.l %d7,%d0 12337 mov.l EXC_DREGS+0x8(%a6),%d0 12340 mov.l EXC_DREGS+0xc(%a6),%d0 12343 mov.l %a2,%d0 12346 mov.l %a3,%d0 12349 mov.l %a4,%d0 12352 mov.l %a5,%d0 12355 mov.l (%a6),%d0 12358 mov.l EXC_A7(%a6),%d0 12369 # d0 = longowrd value to store # 12377 # in d0 to the corresponding data register. D0/D1 are on the stack # 12398 mov.l %d0,EXC_DREGS+0x0(%a6) 12401 mov.l %d0,EXC_DREGS+0x4(%a6) 12404 mov.l %d0,%d2 12407 mov.l %d0,%d3 12410 mov.l %d0,%d4 12413 mov.l %d0,%d5 12416 mov.l %d0,%d6 12419 mov.l %d0,%d7 12430 # d0 = word value to store # 12438 # in d0 to the corresponding data register. D0/D1 are on the stack # 12459 mov.w %d0,2+EXC_DREGS+0x0(%a6) 12462 mov.w %d0,2+EXC_DREGS+0x4(%a6) 12465 mov.w %d0,%d2 12468 mov.w %d0,%d3 12471 mov.w %d0,%d4 12474 mov.w %d0,%d5 12477 mov.w %d0,%d6 12480 mov.w %d0,%d7 12491 # d0 = byte value to store # 12499 # in d0 to the corresponding data register. D0/D1 are on the stack # 12520 mov.b %d0,3+EXC_DREGS+0x0(%a6) 12523 mov.b %d0,3+EXC_DREGS+0x4(%a6) 12526 mov.b %d0,%d2 12529 mov.b %d0,%d3 12532 mov.b %d0,%d4 12535 mov.b %d0,%d5 12538 mov.b %d0,%d6 12541 mov.b %d0,%d7 12546 # inc_areg(): increment an address register by the value in d0 # 12552 # d0 = amount to increment by # 12560 # this routine adds the increment value in d0 to the address register # 12585 iareg0: add.l %d0,EXC_DREGS+0x8(%a6) 12587 iareg1: add.l %d0,EXC_DREGS+0xc(%a6) 12589 iareg2: add.l %d0,%a2 12591 iareg3: add.l %d0,%a3 12593 iareg4: add.l %d0,%a4 12595 iareg5: add.l %d0,%a5 12597 iareg6: add.l %d0,(%a6) 12600 cmpi.b %d0,&0x1 12602 add.l %d0,EXC_A7(%a6) 12610 # dec_areg(): decrement an address register by the value in d0 # 12616 # d0 = amount to decrement by # 12624 # this routine adds the decrement value in d0 to the address register # 12649 dareg0: sub.l %d0,EXC_DREGS+0x8(%a6) 12651 dareg1: sub.l %d0,EXC_DREGS+0xc(%a6) 12653 dareg2: sub.l %d0,%a2 12655 dareg3: sub.l %d0,%a3 12657 dareg4: sub.l %d0,%a4 12659 dareg5: sub.l %d0,%a5 12661 dareg6: sub.l %d0,(%a6) 12664 cmpi.b %d0,&0x1 12666 sub.l %d0,EXC_A7(%a6) 12682 # d0 = index of FP register to load # 12688 # Using the index in d0, load FP_SRC(a6) with a number from the # 12695 mov.w (tbl_load_fpn1.b,%pc,%d0.w*2), %d0 12696 jmp (tbl_load_fpn1.b,%pc,%d0.w*1) 12755 # d0 = index of FP register to load # 12761 # Using the index in d0, load FP_DST(a6) with a number from the # 12768 mov.w (tbl_load_fpn2.b,%pc,%d0.w*2), %d0 12769 jmp (tbl_load_fpn2.b,%pc,%d0.w*1) 12822 # store_fpreg(): store an fp value to the fpreg designated d0. # 12829 # d0 = index of floating-point register # 12836 # value in d0. The FP number can be DENORM or SNAN so we have to be # 12843 mov.w (tbl_store_fpreg.b,%pc,%d0.w*2), %d0 12844 jmp (tbl_store_fpreg.b,%pc,%d0.w*1) 12920 mov.l &0xc,%d0 # packed is 12 bytes 12924 mov.l &0xc,%d0 # pass: 12 bytes 12931 bfextu FP_SRC(%a6){&1:&15},%d0 # get exp 12932 cmpi.w %d0,&0x7fff # INF or NAN? 12939 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 12940 andi.b &0x0f,%d0 # clear all but last nybble 13051 # (*) d0: temp digit storage 13068 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend into d0 13069 add.l %d0,%d1 # d1 = d1 + d0 13093 # (*) d0: temp digit storage 13113 bfextu (%a0){&28:&4},%d0 # integer part is ls digit in long word 13114 fadd.b %d0,%fp0 # add digit to sum in fp0 13125 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend 13126 fadd.b %d0,%fp0 # fp0 = fp0 + digit 13181 # (*) d0: temp digit storage 13205 bfextu %d4{&28:&4},%d0 # get M16 in d0 13218 bfextu %d4{%d3:&4},%d0 # get digit 13224 mov.l %d1,%d0 # copy counter to d2 13226 sub.l %d0,%d1 # subtract count from exp 13242 asr.l &1,%d0 # shift lsb into carry 13247 tst.l %d0 # check if d0 is zero 13266 bfextu %d4{%d3:&4},%d0 # get digit 13272 mov.l %d1,%d0 # copy counter to d0 13274 sub.l %d0,%d1 # subtract count from exp 13290 asr.l &1,%d0 # shift lsb into carry 13295 tst.l %d0 # check if d0 is zero 13305 # (*) d0: temp 13312 # (*) d0: temp 13347 bfextu %d4{&0:&2},%d0 # {FPCR[6],FPCR[5],SM,SE} 13348 add.l %d0,%d2 # in d2 as index into RTABLE 13350 mov.b (%a1,%d2),%d0 # load new rounding bits from table 13352 bfins %d0,%d3{&26:&2} # stuff new rounding bits in FPCR 13354 asr.l &1,%d0 # write correct PTENxx table 13359 asr.l &1,%d0 # keep checking 13366 mov.l %d1,%d0 # copy exp to d0;use d0 13368 neg.l %d0 # invert it 13374 asr.l &1,%d0 # shift next bit into carry 13379 tst.l %d0 # check if d0 is zero 13409 fmov.l %fpsr,%d0 # get status register 13410 bclr &inex2_bit+8,%d0 # test for inex2 and clear it 13428 # d0 = contains the k-factor sign-extended to 32-bits. # 13551 # d0: scratch; LEN input to binstr 13584 mov.l %d0,%d7 # move k-factor to d7 13594 mov.w (%a0),%d0 13595 and.w &0x7fff,%d0 # strip sign of normalized exp 13599 sub.w &1,%d0 13607 tst.w %d0 13611 and.w &0x7fff,%d0 # strip sign of normalized exp 13612 mov.w %d0,(%a0) 13632 # d0: k-factor/exponent 13655 mov.w FP_SCR1(%a6),%d0 # move exp to d0 13658 sub.w &0x3fff,%d0 # strip off bias 13659 fadd.w %d0,%fp0 # add in exp 13694 # d0: exponent/Unchanged 13766 # d0: exponent/scratch - final is 0 13791 mov.l %d6,%d0 # calc ILOG + 1 - LEN in d0 13792 addq.l &1,%d0 # add the 1 13793 sub.l %d4,%d0 # sub off LEN 13797 tst.l %d0 # test sign of ISCALE 13800 cmp.l %d0,&0xffffecd4 # test iscale <= -4908 13802 add.l &24,%d0 # add in 24 to iscale 13805 neg.l %d0 # and take abs of ISCALE 13835 lsr.l &1,%d0 # shift next bit into carry 13840 tst.l %d0 # test if ISCALE is zero 13869 # d0: FPCR with RZ mode/Unchanged 13957 # d0: FPCR with RZ mode/FPSR with INEX2 isolated 13972 fmov.l %fpsr,%d0 # get FPSR 13975 btst &9,%d0 # check if INEX2 set 13998 # d0: FPSR with AINEX cleared/FPCR with size set to ext 14018 movm.l &0xc0c0,-(%sp) # save regs used by sintd0 {%d0-%d1/%a0-%a1} 14033 ## mov.l USER_FPCR(%a6),%d0 # ext prec/keep rnd mode 14034 ## andi.l &0x00000030,%d0 14035 ## fmov.l %d0,%fpcr 14037 fmov.l %fpsr,%d0 14038 or.w %d0,FPSR_EXCEPT(%a6) 14040 ## fmov.l %fpsr,%d0 # don't keep ccodes 14041 ## or.w %d0,FPSR_EXCEPT(%a6) 14048 movm.l (%sp)+,&0x303 # restore regs used by sint {%d0-%d1/%a0-%a1} 14066 # d0: FPCR with size set to ext/scratch final = 0 14092 mov.l %d4,%d0 # put LEN in d0 14093 subq.l &1,%d0 # d0 = LEN -1 14096 lsr.l &1,%d0 # shift next bit into carry 14101 tst.l %d0 # test if LEN is zero 14144 mov.l %d4,%d0 # put LEN in d0 14147 lsr.l &1,%d0 # shift next bit into carry 14152 tst.l %d0 # test if LEN is zero 14173 # d0: x/LEN call to binstr - final is 0 14202 mov.l (%a0),%d0 # move exponent to d0 14203 swap %d0 # put exponent in lower word 14205 sub.l &0x3ffd,%d0 # sub bias less 2 to make fract 14206 tst.l %d0 # check if > 1 14208 neg.l %d0 # make exp positive 14212 dbf.w %d0,m_loop # given in d0 14224 mov.l %d4,%d0 # put LEN in d0 for binstr call 14246 # d0: x/LEN call to binstr - final is 0 14295 mov.w (%a2),%d0 # move exp to d0 14297 sub.w &0x3ffd,%d0 # subtract off bias 14298 neg.w %d0 # make exp positive 14302 dbf.w %d0,x_loop # given in d0 14308 mov.l &4,%d0 # put 4 in d0 for binstr call 14311 mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0 14313 lsr.l %d1,%d0 # shift d0 right by 12 14314 bfins %d0,FP_SCR0(%a6){&4:&12} # put e3:e2:e1 in FP_SCR0 14315 lsr.l %d1,%d0 # shift d0 right by 12 14316 bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0 14317 tst.b %d0 # check if e4 is zero 14327 # d0: x/scratch - final is x 14346 clr.l %d0 # clr d0 for collection of signs 14350 mov.l &2,%d0 # move 2 in to d0 for SM 14354 addq.l &1,%d0 # set bit 0 in d0 for SE 14356 bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0 14418 # d0 = desired length (LEN) # 14451 # upper word of d0. If it is the ls digit, write the word # 14452 # from d0 to memory. # 14462 # d0: LEN counter 14475 movm.l &0xff00,-(%sp) # {%d0-%d7} 14481 subq.l &1,%d0 # for dbf d0 would have LEN+1 passes 14524 dbf.w %d0,loop # do loop some more! 14531 dbf.w %d0,loop # do loop some more! 14539 movm.l (%sp)+,&0xff # {%d0-%d7} 14576 movq.l &0x1,%d0 # one byte 14583 movq.l &0x2,%d0 # two bytes 14590 movq.l &0x4,%d0 # four bytes 14597 movq.l &0x8,%d0 # eight bytes 14604 movq.l &0xc,%d0 # twelve bytes 14613 movq.l &0x1,%d0 # one byte 14620 movq.l &0x2,%d0 # two bytes 14627 movq.l &0x4,%d0 # four bytes 14634 movq.l &0x8,%d0 # eight bytes 14641 mov.l &0xc,%d0 # twelve bytes 14653 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 14705 sub.l %d0,EXC_DREGS+0x8(%a6) # fix stacked a0 14708 sub.l %d0,EXC_DREGS+0xc(%a6) # fix stacked a1 14711 sub.l %d0,%a2 # fix a2 14714 sub.l %d0,%a3 # fix a3 14717 sub.l %d0,%a4 # fix a4 14720 sub.l %d0,%a5 # fix a5 14723 sub.l %d0,(%a6) # fix stacked a6 14737 sub.l %d0,%a0 14744 neg.l %d0
H A D	itest.S	53 tst.l %d0 185 tst.b %d0 209 tst.b %d0 231 tst.b %d0 255 tst.b %d0 279 tst.b %d0 303 tst.b %d0 327 tst.b %d0 351 tst.b %d0 375 tst.b %d0 379 clr.l %d0 389 # movep.w %d0,(0x0,%a0) # 397 mov.w &0xaaaa,%d0 405 movp.w %d0,(0x0,%a0) 414 cmp.w %d0,%d1 418 tst.b %d0 422 # movep.w %d0,(0x0,%a0) # 430 mov.w &0xaaaa,%d0 439 movp.w %d0,(0x0,%a0) 452 tst.b %d0 456 # movep.w %d0,(0x0,%a0) # 465 mov.w &0xaaaa,%d0 473 movp.w %d0,(0x0,%a0) 482 cmp.w %d0,%d1 486 tst.b %d0 490 # movep.w (0x0,%a0),%d0 # 505 movp.w (0x0,%a0),%d0 513 cmp.w %d0,%d1 517 tst.b %d0 521 # movep.l %d0,(0x0,%a0) # 529 mov.l &0xaaaaaaaa,%d0 539 movp.l %d0,(0x0,%a0) 552 cmp.l %d0,%d1 556 tst.b %d0 560 # movep.l %d0,(0x0,%a0) # 568 mov.l &0xaaaaaaaa,%d0 578 movp.l %d0,(0x0,%a0) 593 tst.b %d0 597 # movep.l (0x0,%a0),%d0 # 614 movp.l (0x0,%a0),%d0 622 cmp.l %d0,%d1 626 tst.b %d0 659 tst.b %d0 690 tst.b %d0 694 # movep.w %d0,(0x0,%a0) # 702 mov.w &0xaaaa,%d0 710 movp.w %d0,(0x0,%a0) 719 cmp.w %d0,%d1 723 tst.b %d0 727 # movep.w %d0,(0x8,%a0) # 735 mov.w &0xaaaa,%d0 743 movp.w %d0,(0x8,%a0) 752 cmp.w %d0,%d1 756 tst.b %d0 760 # movep.w (0x8,%a0),%d0 # 775 movp.w (0x8,%a0),%d0 783 cmp.w %d0,%d1 787 tst.b %d0 791 # movep.l %d0,(0x8,%a0) # 799 mov.l &0xaaaaaaaa,%d0 809 movp.l %d0,(0x8,%a0) 822 cmp.l %d0,%d1 826 tst.b %d0 830 # movep.l (0x8,%a0),%d0 # 847 movp.l (0x8,%a0),%d0 855 cmp.l %d0,%d1 859 tst.b %d0 863 # movep.w %d0,(-0x8,%a0) # 871 mov.w &0xaaaa,%d0 879 movp.w %d0,(-0x8,%a0) 888 cmp.w %d0,%d1 892 tst.b %d0 896 # movep.w (-0x8,%a0),%d0 # 911 movp.w (-0x8,%a0),%d0 919 cmp.w %d0,%d1 923 tst.b %d0 927 # movep.l %d0,(-0x8,%a0) # 935 mov.l &0xaaaaaaaa,%d0 945 movp.l %d0,(-0x8,%a0) 958 cmp.l %d0,%d1 962 tst.b %d0 966 # movep.l (-0x8,%a0),%d0 # 983 movp.l (-0x8,%a0),%d0 991 cmp.l %d0,%d1 995 tst.b %d0 999 clr.l %d0 1027 # tst.b %d0 1049 tst.b %d0 1073 tst.b %d0 1097 tst.b %d0 1119 tst.b %d0 1141 tst.b %d0 1165 tst.b %d0 1187 tst.b %d0 1209 tst.b %d0 1232 tst.b %d0 1256 tst.b %d0 1260 clr.l %d0 1293 tst.b %d0 1321 tst.b %d0 1348 tst.b %d0 1376 tst.b %d0 1403 tst.b %d0 1431 tst.b %d0 1435 clr.l %d0 1474 tst.b %d0 1507 tst.b %d0 1540 tst.b %d0 1575 tst.b %d0 1610 tst.b %d0 1645 tst.b %d0 1680 tst.b %d0 1715 tst.b %d0 1750 tst.b %d0 1784 tst.b %d0 1817 tst.b %d0 1852 tst.b %d0 1887 tst.b %d0 1922 tst.b %d0 1957 tst.b %d0 1961 clr.l %d0 1989 tst.b %d0 2010 tst.b %d0 2031 tst.b %d0 2052 tst.b %d0 2073 tst.b %d0 2094 tst.b %d0 2116 tst.b %d0 2137 tst.b %d0 2158 tst.b %d0 2179 tst.b %d0 2200 tst.b %d0 2221 tst.b %d0 2244 tst.b %d0 2266 tst.b %d0 2288 tst.b %d0 2310 tst.b %d0 2332 tst.b %d0 2354 tst.b %d0 2376 tst.b %d0 2397 tst.b %d0 2418 tst.b %d0 2439 tst.b %d0 2460 tst.b %d0 2481 tst.b %d0 2503 tst.b %d0 2524 tst.b %d0 2545 tst.b %d0 2566 tst.b %d0 2587 tst.b %d0 2608 tst.b %d0 2612 clr.l %d0 2641 tst.b %d0 2666 tst.b %d0 2690 tst.b %d0 2713 tst.b %d0 2736 tst.b %d0 2758 # tst.b %d0 2780 # tst.b %d0 2802 tst.b %d0 2828 tst.b %d0 2852 tst.b %d0 2876 tst.b %d0 2900 tst.b %d0 2924 tst.b %d0 2948 tst.b %d0 2977 tst.b %d0 3003 tst.b %d0 3027 tst.b %d0 3051 tst.b %d0 3075 tst.b %d0 3099 tst.b %d0 3123 tst.b %d0 3147 tst.b %d0 3171 tst.b %d0 3195 tst.b %d0 3219 tst.b %d0 3243 tst.b %d0 3267 tst.b %d0 3291 tst.b %d0 3315 tst.b %d0 3339 tst.b %d0 3363 tst.b %d0 3391 tst.b %d0 3417 tst.b %d0 3440 tst.b %d0 3463 tst.b %d0 3486 tst.b %d0 3509 tst.b %d0 3532 tst.b %d0 3559 tst.b %d0 3584 tst.b %d0 3609 tst.b %d0 3634 tst.b %d0 3659 tst.b %d0 3684 tst.b %d0 3709 tst.b %d0 3738 tst.b %d0 3765 tst.b %d0 3788 tst.b %d0 3811 tst.b %d0 3834 tst.b %d0 3857 tst.b %d0 3880 tst.b %d0 3907 tst.b %d0 3932 tst.b %d0 3955 tst.b %d0 3982 tst.b %d0 4006 tst.b %d0 4030 tst.b %d0 4054 tst.b %d0 4078 tst.b %d0 4102 tst.b %d0 4126 tst.b %d0 4150 tst.b %d0 4174 tst.b %d0 4198 tst.b %d0 4222 tst.b %d0 4247 tst.b %d0 4271 tst.b %d0 4299 tst.b %d0 4327 tst.b %d0 4355 tst.b %d0 4383 tst.b %d0 4411 tst.b %d0 4439 tst.b %d0 4467 tst.b %d0 4495 tst.b %d0 4523 tst.b %d0 4551 tst.b %d0 4576 # tst.b %d0 4605 tst.b %d0 4633 tst.b %d0 4661 tst.b %d0 4689 tst.b %d0 4717 tst.b %d0 4745 tst.b %d0 4773 tst.b %d0 4801 tst.b %d0 4829 tst.b %d0 4858 tst.b %d0 4884 tst.b %d0 4910 tst.b %d0 4936 tst.b %d0 4962 tst.b %d0 4988 tst.b %d0 5014 tst.b %d0 5040 tst.b %d0 5066 tst.b %d0 5092 tst.b %d0 5118 tst.b %d0 5144 tst.b %d0 5171 tst.b %d0 5197 # tst.b %d0 5227 tst.b %d0 5257 tst.b %d0 5284 tst.b %d0 5311 tst.b %d0 5338 tst.b %d0 5365 tst.b %d0 5392 tst.b %d0 5419 tst.b %d0 5446 tst.b %d0 5473 tst.b %d0 5500 tst.b %d0 5526 tst.b %d0 5554 tst.b %d0 5580 # tst.b %d0 5611 tst.b %d0 5615 clr.l %d0 5641 tst.b %d0 5667 tst.b %d0 5693 tst.b %d0 5719 tst.b %d0 5745 tst.b %d0 5771 tst.b %d0 5797 tst.b %d0 5823 tst.b %d0 5848 tst.b %d0 5874 tst.b %d0 5900 tst.b %d0 5927 tst.b %d0 5951 tst.b %d0 5977 tst.b %d0 6005 tst.b %d0 6032 tst.b %d0 6059 tst.b %d0 6086 tst.b %d0 6113 tst.b %d0 6140 tst.b %d0 6167 tst.b %d0 6194 tst.b %d0 6221 tst.b %d0 6248 tst.b %d0 6274 tst.b %d0 6300 tst.b %d0 6329 tst.b %d0 6332 clr.l %d0 6340 mov.l &14,%d0 6344 dbra.w %d0,chkregs_loop 6346 mov.w ICCR(%a6),%d0 6348 cmp.w %d0,%d1 6351 clr.l %d0 6355 movq.l &0x1,%d0 6360 movq.l &0x1,%d0 6373 mov.l %d0,-(%sp) 6374 mov.l (TESTTOP-0x80+0x0,%pc),%d0 6375 pea (TESTTOP-0x80,%pc,%d0) 6376 mov.l 0x4(%sp),%d0 6380 mov.l %d0,-(%sp) 6381 mov.l (TESTTOP-0x80+0x4,%pc),%d0 6382 pea (TESTTOP-0x80,%pc,%d0) 6383 mov.l 0x4(%sp),%d0
H A D	fplsp.S	565 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 578 mov.b %d0,STAG(%a6) 579 mov.b %d0,%d1 583 clr.l %d0 584 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 612 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 622 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 635 mov.b %d0,STAG(%a6) 636 mov.b %d0,%d1 640 clr.l %d0 641 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 670 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 680 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 694 mov.b %d0,STAG(%a6) 695 mov.b %d0,%d1 699 clr.l %d0 700 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 728 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 742 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 755 mov.b %d0,STAG(%a6) 756 mov.b %d0,%d1 760 clr.l %d0 761 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 789 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 799 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 812 mov.b %d0,STAG(%a6) 813 mov.b %d0,%d1 817 clr.l %d0 818 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 847 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 857 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 871 mov.b %d0,STAG(%a6) 872 mov.b %d0,%d1 876 clr.l %d0 877 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 905 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 919 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 932 mov.b %d0,STAG(%a6) 933 mov.b %d0,%d1 937 clr.l %d0 938 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 966 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 976 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 989 mov.b %d0,STAG(%a6) 990 mov.b %d0,%d1 994 clr.l %d0 995 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1024 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1034 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1048 mov.b %d0,STAG(%a6) 1049 mov.b %d0,%d1 1053 clr.l %d0 1054 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1082 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1096 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1109 mov.b %d0,STAG(%a6) 1110 mov.b %d0,%d1 1114 clr.l %d0 1115 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1143 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1153 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1166 mov.b %d0,STAG(%a6) 1167 mov.b %d0,%d1 1171 clr.l %d0 1172 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1201 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1211 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1225 mov.b %d0,STAG(%a6) 1226 mov.b %d0,%d1 1230 clr.l %d0 1231 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1259 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1273 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1286 mov.b %d0,STAG(%a6) 1287 mov.b %d0,%d1 1291 clr.l %d0 1292 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1320 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1330 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1343 mov.b %d0,STAG(%a6) 1344 mov.b %d0,%d1 1348 clr.l %d0 1349 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1378 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1388 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1402 mov.b %d0,STAG(%a6) 1403 mov.b %d0,%d1 1407 clr.l %d0 1408 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1436 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1450 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1463 mov.b %d0,STAG(%a6) 1464 mov.b %d0,%d1 1468 clr.l %d0 1469 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1497 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1507 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1520 mov.b %d0,STAG(%a6) 1521 mov.b %d0,%d1 1525 clr.l %d0 1526 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1555 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1565 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1579 mov.b %d0,STAG(%a6) 1580 mov.b %d0,%d1 1584 clr.l %d0 1585 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1613 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1627 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1640 mov.b %d0,STAG(%a6) 1641 mov.b %d0,%d1 1645 clr.l %d0 1646 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1674 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1684 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1697 mov.b %d0,STAG(%a6) 1698 mov.b %d0,%d1 1702 clr.l %d0 1703 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1732 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1742 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1756 mov.b %d0,STAG(%a6) 1757 mov.b %d0,%d1 1761 clr.l %d0 1762 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1790 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1804 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1817 mov.b %d0,STAG(%a6) 1818 mov.b %d0,%d1 1822 clr.l %d0 1823 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1851 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1861 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1874 mov.b %d0,STAG(%a6) 1875 mov.b %d0,%d1 1879 clr.l %d0 1880 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1909 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1919 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1933 mov.b %d0,STAG(%a6) 1934 mov.b %d0,%d1 1938 clr.l %d0 1939 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 1967 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1981 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1994 mov.b %d0,STAG(%a6) 1995 mov.b %d0,%d1 1999 clr.l %d0 2000 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2028 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2038 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2051 mov.b %d0,STAG(%a6) 2052 mov.b %d0,%d1 2056 clr.l %d0 2057 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2086 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2096 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2110 mov.b %d0,STAG(%a6) 2111 mov.b %d0,%d1 2115 clr.l %d0 2116 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2144 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2158 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2171 mov.b %d0,STAG(%a6) 2172 mov.b %d0,%d1 2176 clr.l %d0 2177 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2205 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2215 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2228 mov.b %d0,STAG(%a6) 2229 mov.b %d0,%d1 2233 clr.l %d0 2234 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2263 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2273 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2287 mov.b %d0,STAG(%a6) 2288 mov.b %d0,%d1 2292 clr.l %d0 2293 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2321 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2335 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2348 mov.b %d0,STAG(%a6) 2349 mov.b %d0,%d1 2353 clr.l %d0 2354 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2382 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2392 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2405 mov.b %d0,STAG(%a6) 2406 mov.b %d0,%d1 2410 clr.l %d0 2411 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2440 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2450 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2464 mov.b %d0,STAG(%a6) 2465 mov.b %d0,%d1 2469 clr.l %d0 2470 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2498 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2512 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2525 mov.b %d0,STAG(%a6) 2526 mov.b %d0,%d1 2530 clr.l %d0 2531 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2559 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2569 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2582 mov.b %d0,STAG(%a6) 2583 mov.b %d0,%d1 2587 clr.l %d0 2588 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2617 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2627 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2641 mov.b %d0,STAG(%a6) 2642 mov.b %d0,%d1 2646 clr.l %d0 2647 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2675 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2689 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2702 mov.b %d0,STAG(%a6) 2703 mov.b %d0,%d1 2707 clr.l %d0 2708 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2736 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2746 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2759 mov.b %d0,STAG(%a6) 2760 mov.b %d0,%d1 2764 clr.l %d0 2765 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2794 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2804 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2818 mov.b %d0,STAG(%a6) 2819 mov.b %d0,%d1 2823 clr.l %d0 2824 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2852 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2866 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2879 mov.b %d0,STAG(%a6) 2880 mov.b %d0,%d1 2884 clr.l %d0 2885 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2913 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2923 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2936 mov.b %d0,STAG(%a6) 2937 mov.b %d0,%d1 2941 clr.l %d0 2942 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 2971 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2981 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2995 mov.b %d0,STAG(%a6) 2996 mov.b %d0,%d1 3000 clr.l %d0 3001 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3029 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3043 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3056 mov.b %d0,STAG(%a6) 3057 mov.b %d0,%d1 3061 clr.l %d0 3062 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3090 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3100 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3113 mov.b %d0,STAG(%a6) 3114 mov.b %d0,%d1 3118 clr.l %d0 3119 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3148 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3158 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3172 mov.b %d0,STAG(%a6) 3173 mov.b %d0,%d1 3177 clr.l %d0 3178 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3206 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3220 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3233 mov.b %d0,STAG(%a6) 3234 mov.b %d0,%d1 3238 clr.l %d0 3239 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3267 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3277 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3290 mov.b %d0,STAG(%a6) 3291 mov.b %d0,%d1 3295 clr.l %d0 3296 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3325 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3335 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3349 mov.b %d0,STAG(%a6) 3350 mov.b %d0,%d1 3354 clr.l %d0 3355 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3383 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3397 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3410 mov.b %d0,STAG(%a6) 3411 mov.b %d0,%d1 3415 clr.l %d0 3416 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3444 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3454 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3467 mov.b %d0,STAG(%a6) 3468 mov.b %d0,%d1 3472 clr.l %d0 3473 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3502 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3512 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3526 mov.b %d0,STAG(%a6) 3527 mov.b %d0,%d1 3531 clr.l %d0 3532 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3560 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3574 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3587 mov.b %d0,STAG(%a6) 3588 mov.b %d0,%d1 3592 clr.l %d0 3593 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3621 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3631 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3644 mov.b %d0,STAG(%a6) 3645 mov.b %d0,%d1 3649 clr.l %d0 3650 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3679 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3689 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3703 mov.b %d0,STAG(%a6) 3704 mov.b %d0,%d1 3708 clr.l %d0 3709 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3737 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3751 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3764 mov.b %d0,STAG(%a6) 3765 mov.b %d0,%d1 3769 clr.l %d0 3770 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3798 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3808 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3821 mov.b %d0,STAG(%a6) 3822 mov.b %d0,%d1 3826 clr.l %d0 3827 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3856 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3866 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3880 mov.b %d0,STAG(%a6) 3881 mov.b %d0,%d1 3885 clr.l %d0 3886 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3914 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3928 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3941 mov.b %d0,STAG(%a6) 3942 mov.b %d0,%d1 3946 clr.l %d0 3947 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 3975 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3985 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3998 mov.b %d0,STAG(%a6) 3999 mov.b %d0,%d1 4003 clr.l %d0 4004 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4033 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4043 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4057 mov.b %d0,STAG(%a6) 4058 mov.b %d0,%d1 4062 clr.l %d0 4063 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4091 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4105 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4118 mov.b %d0,STAG(%a6) 4119 mov.b %d0,%d1 4123 clr.l %d0 4124 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4152 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4164 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4177 mov.b %d0,STAG(%a6) 4178 mov.b %d0,%d1 4182 clr.l %d0 4183 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4212 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4224 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4238 mov.b %d0,STAG(%a6) 4239 mov.b %d0,%d1 4243 clr.l %d0 4244 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4272 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4288 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4301 mov.b %d0,DTAG(%a6) 4307 mov.b %d0,STAG(%a6) 4308 mov.l %d0,%d1 4312 clr.l %d0 4313 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4344 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4354 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4367 mov.b %d0,DTAG(%a6) 4373 mov.b %d0,STAG(%a6) 4374 mov.l %d0,%d1 4378 clr.l %d0 4379 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4410 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4420 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4434 mov.b %d0,DTAG(%a6) 4441 mov.b %d0,STAG(%a6) 4442 mov.l %d0,%d1 4446 clr.l %d0 4447 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4478 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4492 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4505 mov.b %d0,DTAG(%a6) 4511 mov.b %d0,STAG(%a6) 4512 mov.l %d0,%d1 4516 clr.l %d0 4517 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4548 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4558 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4571 mov.b %d0,DTAG(%a6) 4577 mov.b %d0,STAG(%a6) 4578 mov.l %d0,%d1 4582 clr.l %d0 4583 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4614 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4624 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4638 mov.b %d0,DTAG(%a6) 4645 mov.b %d0,STAG(%a6) 4646 mov.l %d0,%d1 4650 clr.l %d0 4651 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4682 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4696 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4709 mov.b %d0,DTAG(%a6) 4715 mov.b %d0,STAG(%a6) 4716 mov.l %d0,%d1 4720 clr.l %d0 4721 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4752 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4762 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4775 mov.b %d0,DTAG(%a6) 4781 mov.b %d0,STAG(%a6) 4782 mov.l %d0,%d1 4786 clr.l %d0 4787 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4818 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4828 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4842 mov.b %d0,DTAG(%a6) 4849 mov.b %d0,STAG(%a6) 4850 mov.l %d0,%d1 4854 clr.l %d0 4855 mov.b FPCR_MODE(%a6),%d0 # pass rnd mode,prec 4886 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4903 # d0 = round precision,mode # 5123 fmov.l %d0,%fpcr # restore users round mode,prec 5185 fmov.l %d0,%fpcr # restore users round mode,prec 5208 fmov.l %d0,%fpcr # restore users round mode,prec 5215 fmov.l %d0,%fpcr # restore users round mode,prec 5350 fmov.l %d0,%fpcr 5423 fmov.l %d0,%fpcr 5441 fmov.l %d0,%fpcr 5444 fmov.l %fpcr,%d0 # d0 must have fpcr,too 5454 mov.l %d0,-(%sp) # save d0 5457 mov.l (%sp)+,%d0 # restore d0 5470 #--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that 5507 sub.l &0x00003FFF,%d1 # d0 = K 5511 sub.l &27,%d1 # d0 = L := K-27 5515 clr.l %d1 # d0 = L := 0 5612 # d0 = round precision,mode # 5832 fmov.l %d0,%fpcr # restore users round mode,prec 5871 fmov.l %d0,%fpcr # restore users round mode,prec 5883 fmov.l %d0,%fpcr # restore users round mode,prec 5901 #--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that 5938 sub.l &0x00003FFF,%d1 # d0 = K 5942 sub.l &27,%d1 # d0 = L := K-27 5946 clr.l %d1 # d0 = L := 0 6042 # d0 = round precision,mode # 6339 fmov.l %d0,%fpcr # restore users rnd mode,prec 6344 #--|X| IS IN d0 IN COMPACT FORM. FP1, d0 SAVED. 6391 fmov.l %d0,%fpcr # restore users rnd mode,prec 6398 fmov.l %d0,%fpcr # restore users rnd mode,prec 6452 fmov.l %d0,%fpcr # restore users rnd mode,prec 6471 fmov.l %d0,%fpcr 6477 fmov.l %d0,%fpcr 6492 # d0 = round precision,mode # 6571 fmov.l %d0,%fpcr 6577 fmov.l %d0,%fpcr # restore users rnd mode,prec 6593 # d0 = round precision,mode # 6643 mov.l %d0,-(%sp) # save original users fpcr 6644 clr.l %d0 6667 fmov.l %d0,%fpcr # load round mode,prec 6677 fmov.l %d0,%fpcr # load user's rnd mode/prec 6689 # d0 = round precision,mode # 7201 fmov.l %d0,%fpcr # restore user FPCR 7209 fmov.l %d0,%fpcr 7259 fmov.l %d0,%fpcr 7391 fmov.l %d0,%fpcr 7409 fmov.l %d0,%fpcr 7422 fmov.l %d0,%fpcr 7474 fmov.l %d0,%fpcr 7485 fmov.l %d0,%fpcr 7517 mov.w SRC_EX(%a0),%d0 # get the exponent 7518 bclr &0xf,%d0 # clear the sign bit 7519 subi.w &0x3fff,%d0 # subtract off the bias 7520 fmov.w %d0,%fp0 # return exp in fp0 7531 neg.w %d0 # new exp = -(shft amt) 7532 subi.w &0x3fff,%d0 # subtract off the bias 7533 fmov.w %d0,%fp0 # return exp in fp0 7539 mov.w SRC_EX(%a0),%d0 # get the exp 7540 ori.w &0x7fff,%d0 # clear old exp 7541 bclr &0xe,%d0 # make it the new exp +-3fff 7546 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 7570 # d0 = round precision,mode # 7628 mov.l %d0,-(%sp) 7629 clr.l %d0 7635 mov.l (%sp)+,%d0 7640 fmov.l %d0,%fpcr 7653 mov.l %d0,-(%sp) 7654 clr.l %d0 7659 mov.l (%sp)+,%d0 7661 fmov.l %d0,%fpcr 7674 fmov.l %d0,%fpcr 7684 # d0 = round precision,mode # 7741 movm.l &0x8040,-(%sp) # {a1/d0} 7744 clr.l %d0 7748 movm.l (%sp)+,&0x0201 # {a1/d0} 7760 fmov.l %d0,%fpcr 7778 mov.l %d0,-(%sp) 7779 clr.l %d0 7785 mov.l (%sp)+,%d0 7786 fmov.l %d0,%fpcr 7802 # d0 = round precision,mode # 7875 mov.l %d0,-(%sp) 7876 clr.l %d0 7881 mov.l (%sp)+,%d0 7889 fmov.l %d0,%fpcr # restore users round prec,mode 7913 mov.l %d0,-(%sp) 7914 clr.l %d0 7919 mov.l (%sp)+,%d0 7931 fmov.l %d0,%fpcr # restore users round prec,mode 7937 fmov.l %d0,%fpcr # restore users round prec,mode 7951 fmov.l %d0,%fpcr # restore users round prec,mode 7968 # d0 = round precision,mode # 8314 fmov.l %d0,%fpcr 8370 fmov.l %d0,%fpcr 8446 fmov.l %d0,%fpcr 8542 fmov.l %d0,%fpcr 8548 fmov.l %d0,%fpcr 8563 # d0 = round precision,mode # 8621 mov.l %d0,-(%sp) # save rnd prec,mode 8622 clr.l %d0 # pass ext prec,RN 8628 mov.l (%sp)+,%d0 # fetch old prec,mode 8629 fmov.l %d0,%fpcr # load it 8653 # d0 = round precision,mode # 8745 mov.l %d0,-(%sp) 8746 clr.l %d0 8757 mov.l %d0,-(%sp) 8758 clr.l %d0 8782 fmov.l %d0,%fpcr 8787 mov.l %d0,-(%sp) 8788 clr.l %d0 8802 mov.l %d0,-(%sp) 8803 clr.l %d0 8817 # d0 = round precision,mode # 9053 fmov.l %d0,%fpcr # restore users round prec,mode 9073 fmov.l %d0,%fpcr # set user's rounding mode/precision 9184 fmov.l %d0,%fpcr # restore users round prec,mode 9197 fmov.l %d0,%fpcr # set user's rounding mode/precision 9222 mov.l %d0,-(%sp) # store off ctrl bits for now 9228 mov.w SRC_EX(%a0),%d0 # check src bounds 9229 andi.w &0x7fff,%d0 # clr src sign bit 9230 cmpi.w %d0,&0x3fff # is src ~ ZERO? 9232 cmpi.w %d0,&0x400c # no; is src too big? 9240 fmov.l %fp0,%d0 # int src to d0 9251 mov.l %d0,-(%sp) # save src for now 9259 neg.l %d0 9260 add.l (%sp)+,%d0 # add adjustment to src 9264 cmpi.w %d0,&-0x3fff # is the shft amt really low? 9275 subi.l &-0x3fff,%d0 # how many should we shift? 9276 neg.l %d0 # make it positive 9277 cmpi.b %d0,&0x20 # is it > 32? 9279 lsr.l %d0,%d1 # no; bit stays in upper lw 9285 subi.b &0x20,%d0 # get shift count 9286 lsr.l %d0,%d1 # make low mantissa longword 9299 addi.w &0x3fff,%d0 # turn src amt into exp value 9300 swap %d0 # put exponent in high word 9303 mov.l %d0,-(%sp) # insert new lo mantissa 9306 fmov.l %fpcr,%d0 # d0 needs fpcr for t_catch2 9316 mov.l (%sp)+,%d0 # restore ctrl bits 9330 mov.l (%sp)+,%d0 9331 fmov.l %d0,%fpcr # no; load control bits 9336 mov.l (%sp)+,%d0 # load control bits into d1 9347 # d0 = round precision,mode # 9421 mov.l %d0,-(%sp) # save ctrl bits 9428 mov.l %d0,-(%sp) # save ctrl bits 9479 mov.w DST_EX(%a1),%d0 9480 mov.w %d0,SignX(%a6) 9482 eor.l %d0,%d1 9485 and.l &0x00007FFF,%d0 9488 tst.l %d0 9490 mov.l &0x00003FFE,%d0 9497 sub.l &32,%d0 9501 sub.l %d6,%d0 # (D0,D1,D2) is normalized 9508 sub.l %d6,%d0 9520 add.l &0x00003FFE,%d0 # (D0,D1,D2) normalized 9526 mov.l %d0,-(%sp) # save biased exp(X) 9527 sub.l %d3,%d0 # L := expo(X)-expo(Y) 9534 tst.l %d0 9539 mov.l (%sp)+,%d0 # restore d0 9572 tst.l %d0 # see if j = 0. 9580 subq.l &1,%d0 # j := j - 1 9589 mov.l L_SCR1(%a6),%d0 # new biased expo of R 9596 sub.l &32,%d0 9600 sub.l %d6,%d0 # (D0,D1,D2) is normalized 9608 sub.l %d6,%d0 9619 cmp.l %d0,&0x000041FE 9622 mov.w %d0,R(%a6) 9635 sub.l &0x3FFE,%d0 9636 mov.w %d0,R(%a6) 9653 cmp.l %d0,%d6 9697 mov.l (%sp)+,%d0 9698 fmov.l %d0,%fpcr 9719 cmp.l %d0,&8 # D0 is j 9722 lsl.l %d0,%d3 9760 # d0 = value of type tag # 9773 mov.w FTEMP_EX(%a0), %d0 # extract exponent 9774 andi.w &0x7fff, %d0 # strip off sign 9775 cmpi.w %d0, &0x7fff # is (EXP == MAX)? 9781 mov.b &NORM, %d0 9784 tst.w %d0 # is exponent = 0? 9792 mov.b &ZERO, %d0 9795 mov.b &DENORM, %d0 9801 mov.b &UNNORM, %d0 9806 mov.l FTEMP_HI(%a0), %d0 9807 and.l &0x7fffffff, %d0 # msb is a don't care! 9810 mov.b &INF, %d0 9813 mov.b &QNAN, %d0 9984 fmov.l %fpsr,%d0 9985 rol.l &0x8,%d0 9986 mov.b %d0,FPSR_CC(%a6) 9995 fmov.l %fpsr,%d0 9996 rol.l &0x8,%d0 9997 mov.b %d0,FPSR_CC(%a6) 10033 mov.b %d0,%d1 # fetch rnd prec,mode 10044 movm.l &0xc080,-(%sp) # save d0-d1/a0 10046 movm.l (%sp)+,&0x0103 # restore d0-d1/a0 10075 fmov.l %fpsr,%d0 10076 rol.l &0x8,%d0 10077 ori.b &neg_mask,%d0 10078 mov.b %d0,FPSR_CC(%a6) 10085 fmov.l %fpsr,%d0 10086 rol.l &0x8,%d0 10087 mov.b %d0,FPSR_CC(%a6) 10097 fmov.l %fpsr,%d0 10098 rol.l &0x8,%d0 10099 mov.b %d0,FPSR_CC(%a6) 10130 fmov.l %fpsr,%d0 10131 or.l %d0,USER_FPSR(%a6) 10136 fmov.l %fpsr,%d0 10137 or.l %d0,USER_FPSR(%a6) 10221 fmov.l %fpsr,%d0 10222 ori.l &unfinx_mask,%d0 10223 or.l %d0,USER_FPSR(%a6) 10230 fmov.l %fpsr,%d0 10231 or.l %d0,USER_FPSR(%a6) 10602 fmov.l %d0,%fpcr 10611 fmov.l %d0,%fpcr 10699 mov.b DST_EX(%a1),%d0 # get dst sign 10700 eor.b %d0,%d1 # get qbyte sign 10703 tst.b %d0 10710 mov.l %d0,-(%sp) 10712 mov.b DST_EX(%a1),%d0 # get dst sign 10713 eor.b %d0,%d1 # get qbyte sign 10719 mov.l (%sp)+,%d0 10830 # d0 = number of bit positions the mantissa was shifted # 10840 mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) 10843 bfffo %d0{&0:&32}, %d2 # how many places to shift? 10847 lsl.l %d2, %d0 # left shift hi(man) 10850 or.l %d3, %d0 # create hi(man) 10853 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 10856 mov.l %d2, %d0 # return shift amount 10871 mov.l %d2, %d0 # return shift amount 10892 # d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO # 10900 bfffo FTEMP_HI(%a0){&0:&32}, %d0 # how many shifts are needed? 10907 bfffo FTEMP_LO(%a0){&0:&32}, %d0 # is operand really a zero? 10910 add.w &32, %d0 # no; fix shift distance 10913 # d0 = # shifts needed for complete normalization 10920 cmp.w %d0, %d1 # will denorm push exp < 0? 10926 sub.w %d0, %d1 # shift exponent value 10927 mov.w FTEMP_EX(%a0), %d0 # load old exponent 10928 and.w &0x8000, %d0 # save old sign 10929 or.w %d0, %d1 # {sgn,new exp} 10934 mov.b &NORM, %d0 # return new optype tag 10944 bfextu FTEMP_HI(%a0){%d1:&32}, %d0 # extract new hi(man) 10945 mov.l %d0, FTEMP_HI(%a0) # save new hi(man) 10947 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 10948 lsl.l %d1, %d0 # extract new lo(man) 10949 mov.l %d0, FTEMP_LO(%a0) # save new lo(man) 10953 mov.b &DENORM, %d0 # return new optype tag 10962 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 10963 lsl.l %d1, %d0 # left shift lo(man) 10965 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 10970 mov.b &DENORM, %d0 # return new optype tag 10979 mov.b &ZERO, %d0 # fix optype tag
H A D	fpsp.S	98 mov.l %d0,-(%sp) 99 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0 100 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 101 mov.l 0x4(%sp),%d0 106 mov.l %d0,-(%sp) 107 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0 108 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 109 mov.l 0x4(%sp),%d0 114 mov.l %d0,-(%sp) 115 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0 116 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 117 mov.l 0x4(%sp),%d0 122 mov.l %d0,-(%sp) 123 mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0 124 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 125 mov.l 0x4(%sp),%d0 130 mov.l %d0,-(%sp) 131 mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0 132 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 133 mov.l 0x4(%sp),%d0 138 mov.l %d0,-(%sp) 139 mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0 140 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 141 mov.l 0x4(%sp),%d0 146 mov.l %d0,-(%sp) 147 mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0 148 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 149 mov.l 0x4(%sp),%d0 154 mov.l %d0,-(%sp) 155 mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0 156 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 157 mov.l 0x4(%sp),%d0 162 mov.l %d0,-(%sp) 163 mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0 164 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 165 mov.l 0x4(%sp),%d0 170 mov.l %d0,-(%sp) 171 mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0 172 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 173 mov.l 0x4(%sp),%d0 178 mov.l %d0,-(%sp) 179 mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0 180 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 181 mov.l 0x4(%sp),%d0 186 mov.l %d0,-(%sp) 187 mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0 188 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 189 mov.l 0x4(%sp),%d0 194 mov.l %d0,-(%sp) 195 mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0 196 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 197 mov.l 0x4(%sp),%d0 204 mov.l %d0,-(%sp) 205 mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0 206 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 207 mov.l 0x4(%sp),%d0 212 mov.l %d0,-(%sp) 213 mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0 214 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 215 mov.l 0x4(%sp),%d0 220 mov.l %d0,-(%sp) 221 mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0 222 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 223 mov.l 0x4(%sp),%d0 228 mov.l %d0,-(%sp) 229 mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0 230 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 231 mov.l 0x4(%sp),%d0 236 mov.l %d0,-(%sp) 237 mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0 238 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 239 mov.l 0x4(%sp),%d0 244 mov.l %d0,-(%sp) 245 mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0 246 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 247 mov.l 0x4(%sp),%d0 252 mov.l %d0,-(%sp) 253 mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0 254 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 255 mov.l 0x4(%sp),%d0 260 mov.l %d0,-(%sp) 261 mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0 262 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 263 mov.l 0x4(%sp),%d0 268 mov.l %d0,-(%sp) 269 mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0 270 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 271 mov.l 0x4(%sp),%d0 276 mov.l %d0,-(%sp) 277 mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0 278 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 279 mov.l 0x4(%sp),%d0 284 mov.l %d0,-(%sp) 285 mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0 286 pea.l (_060FPSP_TABLE-0x80,%pc,%d0) 287 mov.l 0x4(%sp),%d0 645 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 654 mov.l %d0,EXC_OPWORD(%a6) 669 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 677 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 682 cmpi.b %d0,&UNNORM # is operand an UNNORM? 686 mov.b %d0,DTAG(%a6) # save dst optype tag 697 clr.l %d0 698 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 719 bfextu EXC_CMDREG(%a6){&6:&3},%d0 733 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 748 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 767 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 786 clr.l %d0 787 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 806 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 885 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 894 mov.l %d0,EXC_OPWORD(%a6) 907 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 920 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 925 cmpi.b %d0,&UNNORM # is operand an UNNORM? 929 mov.b %d0,DTAG(%a6) # save dst optype tag 940 clr.l %d0 941 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 958 bfextu EXC_CMDREG(%a6){&6:&3},%d0 983 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1010 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1041 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1060 clr.l %d0 1061 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 1080 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1210 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 1236 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 1248 bfextu EXC_CMDREG(%a6){&0:&6},%d0 1249 cmpi.b %d0,&0x13 1271 cmpi.b %d0,&UNNORM # is operand an UNNORM? 1276 mov.b %d0,STAG(%a6) # save src optype tag 1278 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1291 cmpi.b %d0,&UNNORM # is operand an UNNORM? 1295 mov.b %d0,DTAG(%a6) # save dst optype tag 1298 clr.l %d0 1299 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1323 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions set 1328 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1329 andi.b &0x38,%d0 # extract bits 3-5 1330 cmpi.b %d0,&0x38 # is instr fcmp or ftst? 1333 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1340 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1347 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled 1348 bfffo %d0{&24:&8},%d0 # find highest priority exception 1372 # shift enabled exception field into lo byte of d0; 1385 subi.l &24,%d0 # fix offset to be 0-8 1386 cmpi.b %d0,&0x6 # is exception INEX? (6) 1399 mov.l %d0,-(%sp) # save d0 1401 mov.l (%sp)+,%d0 # restore d0 1403 mov.w (tbl_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) # create exc status 1407 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1420 mov.w &0x4,%d0 1423 mov.w &0x03,%d0 1432 bfextu EXC_CMDREG(%a6){&0:&6},%d0 # extract opclass,src fmt 1433 cmpi.b %d0,&0x11 # is class = 2 & fmt = sgl? 1435 cmpi.b %d0,&0x15 # is class = 2 & fmt = dbl? 1440 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1441 andi.w &0x7fff,%d0 # strip sign 1442 cmpi.w %d0,&0x3f80 # is |exp| == $3f80? 1444 cmpi.w %d0,&0x407f # no; is |exp| == $407f? 1454 neg.w %d0 # -shft amt 1455 addi.w &0x3f81,%d0 # adjust new exponent 1457 or.w %d0,LOCAL_EX(%a0) # insert new exponent 1470 mov.w LOCAL_EX(%a0),%d0 # fetch src exponent 1471 andi.w &0x7fff,%d0 # strip sign 1472 cmpi.w %d0,&0x3c00 # is |exp| == $3c00? 1474 cmpi.w %d0,&0x43ff # no; is |exp| == $43ff? 1486 neg.w %d0 # -shft amt 1487 addi.w &0x3c01,%d0 # adjust new exponent 1489 or.w %d0,LOCAL_EX(%a0) # insert new exponent 1500 bfextu EXC_CMDREG(%a6){&3:&3},%d0 1501 cmpi.b %d0,&0x3 1503 cmpi.b %d0,&0x7 1517 mov.w FP_SRC_EX(%a6),%d0 # get exponent 1518 andi.w &0x7fff,%d0 # strip sign 1524 mov.b %d0,STAG(%a6) 1531 clr.l %d0 1532 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1551 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1572 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1596 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1616 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled 1617 bfffo %d0{&24:&8},%d0 # find highest priority exception 1656 subi.l &24,%d0 # fix offset to be 0-8 1660 mov.w (tbl_fu_out.b,%pc,%d0.w*2),%d0 1661 jmp (tbl_fu_out.b,%pc,%d0.w*1) 1679 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1694 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1711 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1740 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1764 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1792 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1821 mov.b %d0,STAG(%a6) # save src optype tag 1823 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1836 cmpi.b %d0,&UNNORM # is operand an UNNORM? 1840 mov.b %d0,DTAG(%a6) # save dst optype tag 1843 clr.l %d0 1844 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 1868 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 1873 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension 1874 andi.b &0x38,%d0 # extract bits 3-5 1875 cmpi.b %d0,&0x38 # is instr fcmp or ftst? 1878 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 1892 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1910 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 1925 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled & set 1926 bfffo %d0{&24:&8},%d0 # find highest priority exception 1950 # shift enabled exception field into lo byte of d0; 1963 subi.l &24,%d0 # fix offset to be 0-8 1964 cmpi.b %d0,&0x6 # is exception INEX? (6 or 7) 1987 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 1991 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2007 mov.w &0x3,%d0 2011 mov.w &0x4,%d0 2018 mov.w (tbl_except_p.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2022 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2074 bfextu EXC_CMDREG(%a6){&6:&3},%d0 2081 cmpi.b %d0,&UNNORM # is operand an UNNORM? 2086 mov.b %d0,STAG(%a6) # save src optype tag 2088 clr.l %d0 2089 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode/prec 2108 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2123 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2141 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2161 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled 2162 bfffo %d0{&24:&8},%d0 # find highest priority exception 2170 cmpi.b %d0,&0x1a 2191 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2231 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2271 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2303 bfextu EXC_EXTWORD(%a6){&3:&3},%d0 # extract src specifier 2304 cmpi.b %d0,&0x1 # was src sgl? 2306 cmpi.b %d0,&0x5 # was src dbl? 2311 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2312 andi.w &0x7fff,%d0 # strip sign 2314 cmpi.w %d0,&0x3f80 2316 neg.w %d0 # make exponent negative 2317 addi.w &0x3f81,%d0 # find amt to shift 2319 lsr.l %d0,%d1 # shift it 2328 mov.w FP_SRC_EX(%a6),%d0 # fetch DENORM exponent 2329 andi.w &0x7fff,%d0 # strip sign 2331 cmpi.w %d0,&0x3c00 2336 mov.w %d0,FP_SRC_EX(%a6) # insert exponent with cleared sign 2337 clr.l %d0 # clear g,r,s 2341 mov.w &0x3c00,%d0 # new exponent 2344 bset &15,%d0 # set sign 2347 mov.w %d0,FP_SRC_EX(%a6) # insert new exponent 2458 mov.l %d0,-(%sp) # save d0 2459 movc %pcr,%d0 # load proc cr 2460 btst &0x1,%d0 # is FPU disabled? 2462 mov.l (%sp)+,%d0 # restore d0 2466 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2476 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2480 tst.w %d0 # is operation fmovem? 2505 btst &0xa,%d0 # is src fmt x or p? 2511 mov.l &0xc,%d0 # pass: 12 bytes 2523 mov.l &0xc,%d0 # pass: 12 bytes 2530 bfextu FP_SRC(%a6){&1:&15},%d0 # get exp 2531 cmpi.w %d0,&0x7fff # INF or NAN? 2536 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 2537 andi.b &0x0f,%d0 # clear all but last nybble 2554 mov.b %d0,STAG(%a6) # could be ANYTHING!!! 2555 cmpi.b %d0,&UNNORM # is operand an UNNORM? 2558 mov.b %d0,STAG(%a6) # set new optype tag 2568 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno 2573 mov.b %d0,DTAG(%a6) # could be ANYTHING!!! 2574 cmpi.b %d0,&UNNORM # is operand an UNNORM? 2577 mov.b %d0,DTAG(%a6) # set new optype tag 2591 clr.l %d0 2592 mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec 2620 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 2630 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch dst regno 2639 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2649 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enable and set 2650 bfffo %d0{&24:&8},%d0 # find highest priority exception 2666 subi.l &24,%d0 # fix offset to be 0-8 2667 cmpi.b %d0,&0x6 # is exception INEX? 2679 mov.w (tbl_iea_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) 2699 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2737 btst &14,%d0 # ctrl or data reg 2764 # right now, d0 = the size. 2772 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2773 mov.l EXC_EXTWPTR(%a6),(EXC_PC,%a6,%d0) 2774 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2776 lea (EXC_SR,%a6,%d0),%a0 2781 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2788 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2789 mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0) 2790 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2791 mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0) 2793 lea (EXC_SR-0x4,%a6,%d0),%a0 2798 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2804 # right now, d1 = size and d0 = the strg. 2807 mov.b %d0,0x1+EXC_VOFF(%a6) # store size 2811 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2814 mov.l %d0,-(%sp) # save d0 2818 clr.l %d0 2819 mov.b 0x1+EXC_VOFF(%a6),%d0 # fetch size 2820 neg.l %d0 # get negative of size 2825 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0) 2826 mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0) 2827 mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0) 2828 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0) 2830 pea (%a6,%d0) # create final sp 2834 mov.w EXC_SR(%a6),(EXC_SR,%a6,%d0) 2835 mov.l (%sp)+,(EXC_PC,%a6,%d0) 2836 mov.w &0x00f0,(EXC_VOFF,%a6,%d0) 2838 pea (0x4,%a6,%d0) # create final sp 2846 fmovm.x &0x80,(0x4+0x8,%a6,%d0) 2847 addi.l &0xc,%d0 2851 fmovm.x &0x40,(0x4+0x8,%a6,%d0) 2852 addi.l &0xc,%d0 2856 fmovm.x &0x20,(0x4+0x8,%a6,%d0) 2857 addi.l &0xc,%d0 2861 fmovm.x &0x10,(0x4+0x8,%a6,%d0) 2862 addi.l &0xc,%d0 2866 fmovm.x &0x08,(0x4+0x8,%a6,%d0) 2867 addi.l &0xc,%d0 2871 fmovm.x &0x04,(0x4+0x8,%a6,%d0) 2872 addi.l &0xc,%d0 2876 fmovm.x &0x02,(0x4+0x8,%a6,%d0) 2877 addi.l &0xc,%d0 2881 fmovm.x &0x01,(0x4+0x8,%a6,%d0) 2884 mov.l 0x8(%sp),%d0 2900 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 2951 mov.l (%sp)+,%d0 # restore d0 2955 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 2962 mov.l %d0,EXC_OPWORD(%a6) # store OPWORD and EXTWORD 2964 tst.w %d0 # is instr fmovm? 2969 mov.l &0x10,%d0 # 16 bytes of instruction 2972 btst &0xe,%d0 # is instr fmovm ctrl 2975 bfextu %d0{&19:&3},%d1 2976 mov.l &0xc,%d0 2979 addq.l &0x4,%d0 2986 clr.l %d0 2988 mov.l EXC_EXTWPTR(%a6),%d0 2989 sub.l EXC_PC(%a6),%d0 2991 mov.w %d0,EXC_VOFF(%a6) # store stack shift value 2993 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3001 mov.l %d0,-(%sp) # save d0 3004 clr.l %d0 3005 mov.w 0x12(%sp),%d0 3007 add.l %d0,0x6(%sp) # make Next PC 3009 mov.l (%sp)+,%d0 # restore d0 3016 movc %pcr,%d0 3017 btst &0x1,%d0 3022 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3056 mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp) 3059 movm.l LOCAL_SIZE+EXC_DREGS(%sp),&0x0303 # restore d0-d1/a0-a1 3113 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3123 mov.l %d0,EXC_OPWORD(%a6) 3127 btst &13,%d0 # is instr an fmove out? 3141 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3190 bfextu %d0{&19:&3},%d0 # extract dst format field 3192 mov.w (tbl_operr.b,%pc,%d0.w*2),%a0 3206 mov.b L_SCR1(%a6),%d0 # load positive default result 3222 mov.w L_SCR1(%a6),%d0 # load positive default result 3238 mov.l L_SCR1(%a6),%d0 # load positive default result 3309 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3319 mov.l %d0,EXC_OPWORD(%a6) 3323 btst &13,%d0 # is instr an fmove out? 3337 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3360 bfextu %d0{&19:&3},%d0 # extract dst format field 3362 mov.w (tbl_snan.b,%pc,%d0.w*2),%a0 3376 mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN 3377 bset &6,%d0 # set SNAN bit 3393 mov.w FP_SRC_HI(%a6),%d0 # load upper word of SNAN 3394 bset &14,%d0 # set SNAN bit 3410 mov.l FP_SRC_HI(%a6),%d0 # load upper longword of SNAN 3411 bset &30,%d0 # set SNAN bit 3429 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3430 andi.l &0x80000000,%d0 # keep sign 3431 ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit 3434 or.l %d1,%d0 # create sgl SNAN 3443 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3444 andi.l &0x80000000,%d0 # keep sign 3445 ori.l &0x7fc00000,%d0 # insert new exponent,SNAN bit 3449 or.l %d1,%d0 # create sgl SNAN 3456 mov.l FP_SRC_EX(%a6),%d0 # fetch SNAN sign 3457 andi.l &0x80000000,%d0 # keep sign 3458 ori.l &0x7ff80000,%d0 # insert new exponent,SNAN bit 3460 mov.l %d0,FP_SCR0_EX(%a6) # store to temp space 3461 mov.l &11,%d0 # load shift amt 3462 lsr.l %d0,%d1 3466 ror.l %d0,%d1 3469 lsr.l %d0,%d1 3473 movq.l &0x8,%d0 # pass: size of 8 bytes 3489 mov.l FP_SRC_HI(%a6),%d0 3490 bset &30,%d0 3491 mov.l %d0,FP_SCR0_HI(%a6) 3511 movq.l &0xc,%d0 # pass: size of extended 3534 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3601 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3611 mov.l %d0,EXC_OPWORD(%a6) 3615 btst &13,%d0 # is instr an fmove out? 3622 bfextu %d0{&19:&3},%d0 # fetch instr size 3651 mov.b %d0,STAG(%a6) # maybe NORM,DENORM 3662 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg 3667 cmpi.b %d0,&UNNORM # is operand an UNNORM? 3671 mov.b %d0,DTAG(%a6) # save dst optype tag 3674 clr.l %d0 3675 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec/mode 3688 bfextu EXC_CMDREG(%a6){&6:&3},%d0 3694 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3702 clr.l %d0 3703 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3727 clr.l %d0 3728 mov.b FPCR_MODE(%a6),%d0 # pass rnd prec,mode 3775 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3785 mov.l %d0,EXC_OPWORD(%a6) 3799 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3863 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 3870 bfextu %d0{&0:&10},%d1 # is it an fmovecr? 3874 bfextu %d0{&16:&6},%d1 # is it an fmovecr? 3886 movc %pcr,%d0 3887 btst &0x1,%d0 3890 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3904 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 3918 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4021 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1 4049 mov.l %d0,EXC_OPWORD(%a6) 4061 # bftst %d0{&7:&3} # test TYPE 4062 btst &22,%d0 # type 0 or 1 ? 4075 bfextu %d0{&16:&6},%d1 # extract upper 6 of cmdreg 4082 clr.l %d0 4083 mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode 4097 mov.b FPCR_ENABLE(%a6),%d0 # fetch exceptions enabled 4101 bfextu EXC_CMDREG(%a6){&6:&3},%d0 # fetch Dn 4107 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4148 mov.l %d0,-(%sp) # save d0 4149 mov.l EXC_A7(%a6),%d0 # load new a7' 4150 sub.l OLD_A7(%a6),%d0 # subtract old a7' 4151 mov.l 0x2+EXC_PC(%a6),(0x2+EXC_PC,%a6,%d0) # shift stack frame 4152 mov.l EXC_SR(%a6),(EXC_SR,%a6,%d0) # shift stack frame 4153 mov.w %d0,EXC_SR(%a6) # store incr number 4154 mov.l (%sp)+,%d0 # restore d0 4165 clr.l %d0 4166 mov.b FPCR_MODE(%a6),%d0 4181 and.b FPSR_EXCEPT(%a6),%d0 # keep only ones enabled and set 4182 bfffo %d0{&24:&8},%d0 # find highest priority exception 4200 subi.l &24,%d0 # fix offset to be 0-8 4201 cmpi.b %d0,&0x6 # is exception INEX? 4219 mov.l %d0,-(%sp) # save d0 4221 mov.l (%sp)+,%d0 # restore d0 4222 mov.w (tbl_funimp_except.b,%pc,%d0.w*2),2+FP_SRC(%a6) 4245 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4260 bfextu %d0{&10:&3},%d1 # extract mode field 4265 bfextu %d0{&13:&3},%d1 4305 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4322 ext.l %d0 # sign extend displacement 4364 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4412 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4433 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 4978 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 5009 # d0 = round precision,mode # 5229 fmov.l %d0,%fpcr # restore users round mode,prec 5291 fmov.l %d0,%fpcr # restore users round mode,prec 5314 fmov.l %d0,%fpcr # restore users round mode,prec 5321 fmov.l %d0,%fpcr # restore users round mode,prec 5456 fmov.l %d0,%fpcr 5529 fmov.l %d0,%fpcr 5547 fmov.l %d0,%fpcr 5550 fmov.l %fpcr,%d0 # d0 must have fpcr,too 5560 mov.l %d0,-(%sp) # save d0 5563 mov.l (%sp)+,%d0 # restore d0 5576 #--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that 5613 sub.l &0x00003FFF,%d1 # d0 = K 5617 sub.l &27,%d1 # d0 = L := K-27 5621 clr.l %d1 # d0 = L := 0 5718 # d0 = round precision,mode # 5938 fmov.l %d0,%fpcr # restore users round mode,prec 5977 fmov.l %d0,%fpcr # restore users round mode,prec 5989 fmov.l %d0,%fpcr # restore users round mode,prec 6007 #--If compact form of abs(arg) in d0=$7ffeffff, argument is so large that 6044 sub.l &0x00003FFF,%d1 # d0 = K 6048 sub.l &27,%d1 # d0 = L := K-27 6052 clr.l %d1 # d0 = L := 0 6148 # d0 = round precision,mode # 6445 fmov.l %d0,%fpcr # restore users rnd mode,prec 6450 #--|X| IS IN d0 IN COMPACT FORM. FP1, d0 SAVED. 6497 fmov.l %d0,%fpcr # restore users rnd mode,prec 6504 fmov.l %d0,%fpcr # restore users rnd mode,prec 6558 fmov.l %d0,%fpcr # restore users rnd mode,prec 6577 fmov.l %d0,%fpcr 6583 fmov.l %d0,%fpcr 6598 # d0 = round precision,mode # 6677 fmov.l %d0,%fpcr 6683 fmov.l %d0,%fpcr # restore users rnd mode,prec 6699 # d0 = round precision,mode # 6749 mov.l %d0,-(%sp) # save original users fpcr 6750 clr.l %d0 6773 fmov.l %d0,%fpcr # load round mode,prec 6783 fmov.l %d0,%fpcr # load user's rnd mode/prec 6795 # d0 = round precision,mode # 7307 fmov.l %d0,%fpcr # restore user FPCR 7315 fmov.l %d0,%fpcr 7365 fmov.l %d0,%fpcr 7497 fmov.l %d0,%fpcr 7515 fmov.l %d0,%fpcr 7528 fmov.l %d0,%fpcr 7580 fmov.l %d0,%fpcr 7591 fmov.l %d0,%fpcr 7623 mov.w SRC_EX(%a0),%d0 # get the exponent 7624 bclr &0xf,%d0 # clear the sign bit 7625 subi.w &0x3fff,%d0 # subtract off the bias 7626 fmov.w %d0,%fp0 # return exp in fp0 7637 neg.w %d0 # new exp = -(shft amt) 7638 subi.w &0x3fff,%d0 # subtract off the bias 7639 fmov.w %d0,%fp0 # return exp in fp0 7645 mov.w SRC_EX(%a0),%d0 # get the exp 7646 ori.w &0x7fff,%d0 # clear old exp 7647 bclr &0xe,%d0 # make it the new exp +-3fff 7652 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 7676 # d0 = round precision,mode # 7734 mov.l %d0,-(%sp) 7735 clr.l %d0 7741 mov.l (%sp)+,%d0 7746 fmov.l %d0,%fpcr 7759 mov.l %d0,-(%sp) 7760 clr.l %d0 7765 mov.l (%sp)+,%d0 7767 fmov.l %d0,%fpcr 7780 fmov.l %d0,%fpcr 7790 # d0 = round precision,mode # 7847 movm.l &0x8040,-(%sp) # {a1/d0} 7850 clr.l %d0 7854 movm.l (%sp)+,&0x0201 # {a1/d0} 7866 fmov.l %d0,%fpcr 7884 mov.l %d0,-(%sp) 7885 clr.l %d0 7891 mov.l (%sp)+,%d0 7892 fmov.l %d0,%fpcr 7908 # d0 = round precision,mode # 7981 mov.l %d0,-(%sp) 7982 clr.l %d0 7987 mov.l (%sp)+,%d0 7995 fmov.l %d0,%fpcr # restore users round prec,mode 8019 mov.l %d0,-(%sp) 8020 clr.l %d0 8025 mov.l (%sp)+,%d0 8037 fmov.l %d0,%fpcr # restore users round prec,mode 8043 fmov.l %d0,%fpcr # restore users round prec,mode 8057 fmov.l %d0,%fpcr # restore users round prec,mode 8074 # d0 = round precision,mode # 8420 fmov.l %d0,%fpcr 8476 fmov.l %d0,%fpcr 8552 fmov.l %d0,%fpcr 8648 fmov.l %d0,%fpcr 8654 fmov.l %d0,%fpcr 8669 # d0 = round precision,mode # 8727 mov.l %d0,-(%sp) # save rnd prec,mode 8728 clr.l %d0 # pass ext prec,RN 8734 mov.l (%sp)+,%d0 # fetch old prec,mode 8735 fmov.l %d0,%fpcr # load it 8759 # d0 = round precision,mode # 8851 mov.l %d0,-(%sp) 8852 clr.l %d0 8863 mov.l %d0,-(%sp) 8864 clr.l %d0 8888 fmov.l %d0,%fpcr 8893 mov.l %d0,-(%sp) 8894 clr.l %d0 8908 mov.l %d0,-(%sp) 8909 clr.l %d0 8923 # d0 = round precision,mode # 9159 fmov.l %d0,%fpcr # restore users round prec,mode 9179 fmov.l %d0,%fpcr # set user's rounding mode/precision 9290 fmov.l %d0,%fpcr # restore users round prec,mode 9303 fmov.l %d0,%fpcr # set user's rounding mode/precision 9312 # rounded to the mode and precision specified in d0. # 9315 # d0 = rnd prec,mode # 9327 lsr.b &0x4,%d0 # shift ctrl bits to lo 9328 mov.l %d0,%d1 # make a copy 9330 andi.w &0xc,%d0 # extract rnd prec 9331 swap %d0 # put rnd prec in hi 9332 mov.w %d1,%d0 # put rnd mode in lo 9360 tst.b %d0 # is rmode RN? 9366 cmpi.b %d0,&rp_mode # is rmode RP? 9387 tst.b %d0 # is rmode RN? 9396 cmpi.b %d0,&rp_mode # is rmode RP? 9429 tst.b %d0 # is rmode RN? 9440 cmpi.b %d0,&rp_mode # is rmode RP? 9454 swap %d0 # put rnd prec in lo word 9455 tst.b %d0 # is precision extended? 9465 swap %d0 # rnd prec in upper word 9473 mov.l %d0,%d1 9474 clr.l %d0 # clear g,r,s 9581 mov.l %d0,-(%sp) # store off ctrl bits for now 9587 mov.w SRC_EX(%a0),%d0 # check src bounds 9588 andi.w &0x7fff,%d0 # clr src sign bit 9589 cmpi.w %d0,&0x3fff # is src ~ ZERO? 9591 cmpi.w %d0,&0x400c # no; is src too big? 9599 fmov.l %fp0,%d0 # int src to d0 9610 mov.l %d0,-(%sp) # save src for now 9618 neg.l %d0 9619 add.l (%sp)+,%d0 # add adjustment to src 9623 cmpi.w %d0,&-0x3fff # is the shft amt really low? 9634 subi.l &-0x3fff,%d0 # how many should we shift? 9635 neg.l %d0 # make it positive 9636 cmpi.b %d0,&0x20 # is it > 32? 9638 lsr.l %d0,%d1 # no; bit stays in upper lw 9644 subi.b &0x20,%d0 # get shift count 9645 lsr.l %d0,%d1 # make low mantissa longword 9658 addi.w &0x3fff,%d0 # turn src amt into exp value 9659 swap %d0 # put exponent in high word 9662 mov.l %d0,-(%sp) # insert new lo mantissa 9665 fmov.l %fpcr,%d0 # d0 needs fpcr for t_catch2 9675 mov.l (%sp)+,%d0 # restore ctrl bits 9689 mov.l (%sp)+,%d0 9690 fmov.l %d0,%fpcr # no; load control bits 9695 mov.l (%sp)+,%d0 # load control bits into d1 9706 # d0 = round precision,mode # 9780 mov.l %d0,-(%sp) # save ctrl bits 9787 mov.l %d0,-(%sp) # save ctrl bits 9838 mov.w DST_EX(%a1),%d0 9839 mov.w %d0,SignX(%a6) 9841 eor.l %d0,%d1 9844 and.l &0x00007FFF,%d0 9847 tst.l %d0 9849 mov.l &0x00003FFE,%d0 9856 sub.l &32,%d0 9860 sub.l %d6,%d0 # (D0,D1,D2) is normalized 9867 sub.l %d6,%d0 9879 add.l &0x00003FFE,%d0 # (D0,D1,D2) normalized 9885 mov.l %d0,-(%sp) # save biased exp(X) 9886 sub.l %d3,%d0 # L := expo(X)-expo(Y) 9893 tst.l %d0 9898 mov.l (%sp)+,%d0 # restore d0 9931 tst.l %d0 # see if j = 0. 9939 subq.l &1,%d0 # j := j - 1 9948 mov.l L_SCR1(%a6),%d0 # new biased expo of R 9955 sub.l &32,%d0 9959 sub.l %d6,%d0 # (D0,D1,D2) is normalized 9967 sub.l %d6,%d0 9978 cmp.l %d0,&0x000041FE 9981 mov.w %d0,R(%a6) 9994 sub.l &0x3FFE,%d0 9995 mov.w %d0,R(%a6) 10012 cmp.l %d0,%d6 10056 mov.l (%sp)+,%d0 10057 fmov.l %d0,%fpcr 10078 cmp.l %d0,&8 # D0 is j 10081 lsl.l %d0,%d3 10179 mov.l %d0,%d1 # make copy of rnd prec,mode 10194 smi.b %d1 # set d0 accodingly 10200 mov.b FPCR_ENABLE(%a6),%d0 10201 andi.b &0x0a,%d0 # is UNFL or INEX enabled? 10218 addi.l &0x6000,%d0 # add extra bias 10220 or.w %d0,FP_SCR0_EX(%a6) # insert new exponent 10253 sf.b %d1 # set d0 to represent positive 10278 mov.b %d0,%d1 # fetch rnd mode/prec 10292 movm.l &0xc080,-(%sp) # save d0-d1/a0 10294 movm.l (%sp)+,&0x0103 # restore d0-d1/a0 10321 mov.b %d0,FPSR_CC(%a6) # insert new ccodes 10334 mov.b %d0,FPSR_CC(%a6) # insert new ccodes 10399 fmov.l %fpsr,%d0 10400 or.l %d0,USER_FPSR(%a6) 10410 # d0 : rnd mode,precision # 10420 lsr.b &0x4,%d0 # shift rnd prec,mode to lo bits 10421 andi.b &0xf,%d0 # strip hi rnd mode bit 10422 or.b %d1,%d0 # concat {sgn,mode,prec} 10424 mov.l %d0,%d1 # make a copy 10427 mov.b (tbl_unf_cc.b,%pc,%d0.w*1),FPSR_CC(%a6) # insert ccode bits 10621 fmov.l %d0,%fpcr 10630 fmov.l %d0,%fpcr 10696 # d0 # 10700 mov.b 1+EXC_CMDREG(%a6),%d0 10701 andi.w &0x7,%d0 10702 mov.w (tbl_sto_cos.b,%pc,%d0.w*2),%d0 10703 jmp (tbl_sto_cos.b,%pc,%d0.w*1) 10788 mov.b DST_EX(%a1),%d0 # get dst sign 10789 eor.b %d0,%d1 # get qbyte sign 10792 tst.b %d0 10799 mov.l %d0,-(%sp) 10801 mov.b DST_EX(%a1),%d0 # get dst sign 10802 eor.b %d0,%d1 # get qbyte sign 10808 mov.l (%sp)+,%d0 10943 fmov.l %fpsr,%d0 # catch resulting status 10944 or.l %d0,USER_FPSR(%a6) # store status 10968 fmov.l %fpsr,%d0 # catch resulting status 10969 or.l %d0,USER_FPSR(%a6) # store status 11344 # d0 = type of instruction that took exception # 11538 # d0 rnd prec,mode # 11568 andi.b &0x30,%d0 # clear rnd prec 11569 ori.b &s_mode*0x10,%d0 # insert sgl prec 11574 andi.b &0x30,%d0 11575 ori.b &d_mode*0x10,%d0 # insert dbl prec 11579 mov.l %d0,L_SCR3(%a6) # store rnd info 11597 mov.l %d0,-(%sp) # save scale factor 1 11601 add.l %d0,(%sp) # SCALE_FACTOR = scale1 + scale2 11605 mov.l (%sp)+,%d0 # load S.F. 11606 cmp.l %d0,(tbl_fmul_ovfl.w,%pc,%d1.w*4) # would result ovfl? 11610 cmp.l %d0,(tbl_fmul_unfl.w,%pc,%d1.w*4) # would result unfl? 11642 sub.l %d0,%d1 # add scale factor 11687 mov.l L_SCR3(%a6),%d0 # pass rnd prec,mode 11689 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 11711 sub.l %d0,%d1 # add scale factor 11801 or.b %d0,FPSR_CC(%a6) # unf_res2 may have set 'Z' 11832 sub.l %d0,%d1 # add scale factor 11970 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11972 eor.b %d0,%d1 11994 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 11996 eor.b %d0,%d1 12011 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 12013 eor.b %d0,%d1 12033 # d0 = round prec/mode # 12053 andi.b &0x30,%d0 # clear rnd prec 12054 ori.b &s_mode*0x10,%d0 # insert sgl precision 12059 andi.b &0x30,%d0 # clear rnd prec 12060 ori.b &d_mode*0x10,%d0 # insert dbl precision 12064 mov.l %d0,L_SCR3(%a6) # store rnd info 12073 andi.b &0xc0,%d0 # is precision extended? 12093 andi.b &0xc0,%d0 # is precision extended? 12117 neg.w %d0 # new exponent = -(shft val) 12118 addi.w &0x6000,%d0 # add new bias to exponent 12121 andi.w &0x7fff,%d0 # clear sign position 12122 or.w %d1,%d0 # concat new exo,old sign 12123 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 12131 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 12143 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow? 12145 cmpi.l %d0,&0x3fff-0x407e # will move in overflow? 12169 sub.l %d0,%d1 # add scale factor 12186 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow? 12188 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow? 12213 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z' 12229 sub.l %d0,%d1 # subtract scale factor 12267 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 12269 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 12284 sub.l %d0,%d1 # add scale factor 12333 fmov.l %fpsr,%d0 # no exceptions possible 12334 rol.l &0x8,%d0 # put ccodes in lo byte 12335 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 12355 # d0 rnd prec,mode # 12386 andi.b &0x30,%d0 # clear rnd prec 12387 ori.b &s_mode*0x10,%d0 # insert sgl prec 12392 andi.b &0x30,%d0 # clear rnd prec 12393 ori.b &d_mode*0x10,%d0 # insert dbl prec 12397 mov.l %d0,L_SCR3(%a6) # store rnd info 12419 mov.l %d0,-(%sp) # save scale factor 1 12424 add.l %d0,(%sp) 12428 mov.l (%sp)+,%d0 # load S.F. 12429 cmp.l %d0,(tbl_fdiv_ovfl.b,%pc,%d1.w*4) # will result overflow? 12432 cmp.l %d0,(tbl_fdiv_unfl.w,%pc,%d1.w*4) # will result underflow? 12456 sub.l %d0,%d1 # add scale factor 12469 mov.l (%sp)+,%d0 # restore scale factor 12473 mov.l %d0,-(%sp) # save scale factor 12482 fmov.l %fpsr,%d0 12485 or.l %d0,USER_FPSR(%a6) # save INEX,N 12488 mov.w (%sp),%d0 # fetch new exponent 12490 andi.l &0x7fff,%d0 # strip sign 12491 sub.l (%sp),%d0 # add scale factor 12492 cmp.l %d0,(tbl_fdiv_ovfl2.b,%pc,%d1.w*4) 12494 mov.l (%sp)+,%d0 12506 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 12508 or.b %d0,FPSR_CC(%a6) # set INF if applicable 12524 sub.l %d0,%d1 # add scale factor 12571 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set 12600 sub.l %d0,%d1 # add scale factoer 12735 mov.b SRC_EX(%a0),%d0 # result sign is exclusive 12737 eor.b %d0,%d1 12755 mov.b SRC_EX(%a0),%d0 # load both signs 12757 eor.b %d0,%d1 12775 mov.b DST_EX(%a1),%d0 # load both signs 12777 eor.b %d0,%d1 12808 # d0 = rnd prec,mode # 12827 andi.b &0x30,%d0 # clear rnd prec 12828 ori.b &s_mode*0x10,%d0 # insert sgl precision 12833 andi.b &0x30,%d0 # clear rnd prec 12834 ori.b &d_mode*0x10,%d0 # insert dbl prec 12838 mov.l %d0,L_SCR3(%a6) # store rnd info 12846 andi.b &0xc0,%d0 # is precision extended? 12856 mov.w SRC_EX(%a0),%d0 12857 eori.w &0x8000,%d0 # negate sign 12861 mov.w %d0,FP_SCR0_EX(%a6) 12870 andi.b &0xc0,%d0 # is precision extended? 12877 mov.w SRC_EX(%a0),%d0 12878 eori.w &0x8000,%d0 # negate sign 12882 mov.w %d0,FP_SCR0_EX(%a6) 12897 neg.w %d0 # new exponent = -(shft val) 12898 addi.w &0x6000,%d0 # add new bias to exponent 12901 andi.w &0x7fff,%d0 # clear sign position 12902 or.w %d1,%d0 # concat old sign, new exponent 12903 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 12911 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 12923 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow? 12925 cmpi.l %d0,&0x3fff-0x407e # will move in overflow? 12949 sub.l %d0,%d1 # add scale factor 12966 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow? 12968 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow? 12993 or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z' 13010 sub.l %d0,%d1 # subtract scale factor 13047 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 13049 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 13064 sub.l %d0,%d1 # add scale factor 13113 fmov.l %fpsr,%d0 13114 rol.l &0x8,%d0 # put ccodes in lo byte 13115 mov.b %d0,FPSR_CC(%a6) # insert correct ccodes 13212 # d0 = round precision/mode # 13238 andi.b &0x30,%d0 # set prec = ext 13240 fmov.l %d0,%fpcr # set FPCR 13246 fmov.l %fpsr,%d0 # save FPSR 13247 or.l %d0,USER_FPSR(%a6) # set exception bits 13318 # d0 = round precision/mode # 13348 fmov.l %fpsr,%d0 # save FPSR 13349 or.l %d0,USER_FPSR(%a6) # set exception bits 13426 # d0 = rnd precision/mode # 13450 andi.b &0x30,%d0 # clear rnd prec 13451 ori.b &s_mode*0x10,%d0 # insert sgl precision 13456 andi.b &0x30,%d0 # clear rnd prec 13457 ori.b &d_mode*0x10,%d0 # insert dbl precision 13461 mov.l %d0,L_SCR3(%a6) # store rnd info 13469 andi.b &0xc0,%d0 # is precision extended? 13490 andi.b &0xc0,%d0 # is precision extended? 13497 mov.w SRC_EX(%a0),%d0 13498 bclr &15,%d0 # clear sign 13499 mov.w %d0,FP_SCR0_EX(%a6) # insert exponent 13515 neg.w %d0 # new exponent = -(shft val) 13516 addi.w &0x6000,%d0 # add new bias to exponent 13519 andi.w &0x7fff,%d0 # clear sign position 13520 or.w %d1,%d0 # concat old sign, new exponent 13521 mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent 13529 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 13541 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow? 13543 cmpi.l %d0,&0x3fff-0x407e # will move in overflow? 13567 sub.l %d0,%d1 # add scale factor 13584 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow? 13586 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow? 13608 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode 13625 sub.l %d0,%d1 # subtract scale factor 13662 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 13664 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 13679 sub.l %d0,%d1 # add scale factor 13744 # d0 = round prec/mode # 13772 fmov.l %fpsr,%d0 # save FPSR 13773 rol.l &0x8,%d0 # extract ccode bits 13774 mov.b %d0,FPSR_CC(%a6) # set ccode bits(no exc bits are set) 13866 mov.l SRC_HI(%a0),%d0 13867 bset &31,%d0 # DENORM src; make into small norm 13868 mov.l %d0,FP_SCR0_HI(%a6) 13875 mov.l DST_HI(%a1),%d0 13876 bset &31,%d0 # DENORM src; make into small norm 13877 mov.l %d0,FP_SCR0_HI(%a6) 13885 mov.l DST_HI(%a1),%d0 13886 bset &31,%d0 # DENORM dst; make into small norm 13887 mov.l %d0,FP_SCR1_HI(%a6) 13888 mov.l SRC_HI(%a0),%d0 13889 bset &31,%d0 # DENORM dst; make into small norm 13890 mov.l %d0,FP_SCR0_HI(%a6) 13898 mov.b SRC_EX(%a0),%d0 # determine if like signs 13900 eor.b %d0,%d1 13904 tst.b %d0 # is src op negative? 13912 mov.b SRC_EX(%a0),%d0 # determine if like signs 13914 eor.b %d0,%d1 13918 tst.b %d0 # is src op negative? 13940 # d0 rnd prec,mode # 13960 mov.l %d0,L_SCR3(%a6) # store rnd info 13979 mov.l %d0,-(%sp) # save scale factor 1 13983 add.l (%sp)+,%d0 # SCALE_FACTOR = scale1 + scale2 13985 cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl? 13989 cmpi.l %d0,&0x3fff+0x0001 # would result unfl? 14013 sub.l %d0,%d1 # add scale factor 14045 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 14046 andi.b &0x30,%d0 # force prec = ext 14048 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 14059 sub.l %d0,%d1 # add scale factor 14114 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set 14137 sub.l %d0,%d1 # add scale factor 14281 # d0 rnd prec,mode # 14301 mov.l %d0,L_SCR3(%a6) # store rnd info 14323 mov.l %d0,-(%sp) # save scale factor 1 14328 add.l %d0,(%sp) 14332 mov.l (%sp)+,%d0 14333 cmpi.l %d0,&0x3fff-0x7ffe 14336 cmpi.l %d0,&0x3fff-0x0000 # will result underflow? 14360 sub.l %d0,%d1 # add scale factor 14384 sub.l %d0,%d1 # add scale factor 14398 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 14399 andi.b &0x30,%d0 # kill precision 14401 or.b %d0,FPSR_CC(%a6) # set INF if applicable 14413 sub.l %d0,%d1 # add scale factor 14447 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set 14470 sub.l %d0,%d1 # add scale factor 14637 andi.b &0x30,%d0 # clear rnd prec 14638 ori.b &s_mode*0x10,%d0 # insert sgl prec 14643 andi.b &0x30,%d0 # clear rnd prec 14644 ori.b &d_mode*0x10,%d0 # insert dbl prec 14648 mov.l %d0,L_SCR3(%a6) # store rnd info 14687 sub.l %d0,%d2 # add scale factor 14732 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 14734 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 14797 or.b %d0,FPSR_CC(%a6) # 'Z' bit may have been set 14823 sub.l %d0,%d1 # add scale factor 14961 mov.b SRC_EX(%a0),%d0 # are the signs opposite 14963 eor.b %d0,%d1 14968 tst.b %d0 # are ZEROes positive or negative? 15022 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 15024 eor.b %d1,%d0 15090 andi.b &0x30,%d0 # clear rnd prec 15091 ori.b &s_mode*0x10,%d0 # insert sgl prec 15096 andi.b &0x30,%d0 # clear rnd prec 15097 ori.b &d_mode*0x10,%d0 # insert dbl prec 15101 mov.l %d0,L_SCR3(%a6) # store rnd info 15140 sub.l %d0,%d2 # add scale factor 15185 mov.l L_SCR3(%a6),%d0 # pass prec:rnd 15187 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 15250 or.b %d0,FPSR_CC(%a6) # 'Z' may have been set 15276 sub.l %d0,%d1 # add scale factor 15414 mov.b SRC_EX(%a0),%d0 15416 eor.b %d1,%d0 15420 tst.b %d0 # is dst negative? 15474 mov.b SRC_EX(%a0),%d0 # exclusive or the signs 15476 eor.b %d1,%d0 15515 # d0 rnd prec,mode # 15535 andi.b &0x30,%d0 # clear rnd prec 15536 ori.b &s_mode*0x10,%d0 # insert sgl precision 15541 andi.b &0x30,%d0 # clear rnd prec 15542 ori.b &d_mode*0x10,%d0 # insert dbl precision 15546 mov.l %d0,L_SCR3(%a6) # store rnd info 15558 andi.b &0xc0,%d0 # is precision extended? 15575 andi.b &0xc0,%d0 # is precision extended? 15590 cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec 15603 cmpi.l %d0,&0x3fff-0x3f81 # will move in underflow? 15606 cmpi.l %d0,&0x3fff-0x407f # will move in overflow? 15630 sub.l %d0,%d1 # add scale factor 15648 cmpi.l %d0,&0x3fff-0x3c01 # will move in underflow? 15651 cmpi.l %d0,&0x3fff-0x43ff # will move in overflow? 15690 or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode 15707 sub.l %d0,%d1 # subtract scale factor 15744 mov.l L_SCR3(%a6),%d0 # pass: prec,mode 15746 or.b %d0,FPSR_CC(%a6) # set INF,N if applicable 15761 sub.l %d0,%d1 # add scale factor 15853 # d0 = scale amount # 15859 # do the opposite. Return this scale factor in d0. # 15872 mov.w SRC_EX(%a0),%d0 15874 mov.w %d0,FP_SCR0_EX(%a6) 15877 andi.w &0x7fff,%d0 15879 mov.w %d0,L_SCR1(%a6) # store src exponent 15882 cmp.w %d0, %d1 # is src exp >= dst exp? 15888 mov.l %d0,-(%sp) # save scale factor 15895 neg.w %d0 # new exp = -(shft val) 15896 mov.w %d0,L_SCR1(%a6) # inset new exp 15899 mov.w 2+L_SCR1(%a6),%d0 15900 subi.w &mantissalen+2,%d0 # subtract mantissalen+2 from larger exp 15902 cmp.w %d0,L_SCR1(%a6) # is difference >= len(mantissa)+2? 15905 mov.w L_SCR1(%a6),%d0 15906 add.w 0x2(%sp),%d0 # scale src exponent by scale factor 15909 or.w %d1,%d0 # concat {sgn,new exp} 15910 mov.w %d0,FP_SCR0_EX(%a6) # insert new dst exponent 15912 mov.l (%sp)+,%d0 # return SCALE factor 15919 mov.l (%sp)+,%d0 # return SCALE factor 15925 mov.l %d0,-(%sp) # save scale factor 15931 neg.w %d0 # new exp = -(shft val) 15932 mov.w %d0,2+L_SCR1(%a6) # inset new exp 15935 mov.w L_SCR1(%a6),%d0 15936 subi.w &mantissalen+2,%d0 # subtract mantissalen+2 from larger exp 15938 cmp.w %d0,2+L_SCR1(%a6) # is difference >= len(mantissa)+2? 15941 mov.w 2+L_SCR1(%a6),%d0 15942 add.w 0x2(%sp),%d0 # scale dst exponent by scale factor 15945 or.w %d1,%d0 # concat {sgn,new exp} 15946 mov.w %d0,FP_SCR1_EX(%a6) # insert new dst exponent 15948 mov.l (%sp)+,%d0 # return SCALE factor 15955 mov.l (%sp)+,%d0 # return SCALE factor 15973 # d0 = scale value # 15986 mov.w %d1,%d0 # make a copy 15990 andi.w &0x8000,%d0 # extract operand's sgn 15991 or.w &0x3fff,%d0 # insert new operand's exponent(=0) 15993 mov.w %d0,FP_SCR0_EX(%a6) # insert biased exponent 15999 mov.l &0x3fff,%d0 16000 sub.l %d1,%d0 # scale = BIAS + (-exp) 16007 neg.l %d0 # new exponent = -(shft val) 16008 mov.l %d0,%d1 # prepare for op_norm call 16026 # d0 = scale value # 16052 mov.l &0x3fff,%d0 16053 sub.l %d1,%d0 # scale = BIAS + (-exp) 16054 asr.l &0x1,%d0 # divide scale factor by 2 16060 mov.l &0x3ffe,%d0 16061 sub.l %d1,%d0 # scale = BIAS + (-exp) 16062 asr.l &0x1,%d0 # divide scale factor by 2 16069 btst &0x0,%d0 # is exp even or odd? 16074 add.l &0x3fff,%d0 16075 asr.l &0x1,%d0 # divide scale factor by 2 16081 add.l &0x3ffe,%d0 16082 asr.l &0x1,%d0 # divide scale factor by 2 16100 # d0 = scale value # 16113 mov.w %d1,%d0 # make a copy 16117 andi.w &0x8000,%d0 # extract operand's sgn 16118 or.w &0x3fff,%d0 # insert new operand's exponent(=0) 16120 mov.w %d0,FP_SCR1_EX(%a6) # insert biased exponent 16126 mov.l &0x3fff,%d0 16127 sub.l %d1,%d0 # scale = BIAS + (-exp) 16133 neg.l %d0 # new exponent = -(shft val) 16134 mov.l %d0,%d1 # prepare for op_norm call 16258 # d0 = displacement # 16280 mov.l %d0,L_SCR1(%a6) # save displacement 16282 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate 16289 mov.w (tbl_fdbcc.b,%pc,%d0.w*2),%d1 # load table 16852 # make sure that d0 isn't corrupted between calls... 16854 subq.w &0x1, %d0 # Dn - 1 -> Dn 16858 cmpi.w %d0, &-0x1 # is (Dn == -1)? 16863 mov.l L_SCR1(%a6),%d0 # fetch displacement 16864 add.l USER_FPIAR(%a6),%d0 # add instruction PC 16865 addq.l &0x4,%d0 # add instruction length 16866 mov.l %d0,EXC_PC(%a6) # set new PC 16910 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate 16917 mov.w (tbl_ftrapcc.b,%pc,%d0.w*2), %d1 # load table 17480 mov.w EXC_CMDREG(%a6),%d0 # fetch predicate 17487 mov.w (tbl_fscc.b,%pc,%d0.w*2),%d1 # load table 17548 clr.b %d0 # set false 17551 st %d0 # set true 17562 clr.b %d0 # set false 17565 st %d0 # set true 17576 clr.b %d0 # set false 17582 st %d0 # set true 17593 clr.b %d0 # set false 17596 st %d0 # set true 17610 clr.b %d0 # set false 17616 st %d0 # set true 17630 clr.b %d0 # set false 17633 st %d0 # set true 17647 clr.b %d0 # set false 17653 st %d0 # set true 17664 clr.b %d0 # set false 17667 st %d0 # set true 17681 clr.b %d0 # set false 17687 st %d0 # set true 17701 clr.b %d0 # set false 17704 st %d0 # set true 17718 clr.b %d0 # set false 17724 st %d0 # set true 17735 clr.b %d0 # set false 17738 st %d0 # set true 17752 clr.b %d0 # set false 17756 st %d0 # set true 17767 clr.b %d0 # set false 17770 st %d0 # set true 17790 clr.b %d0 # set false 17799 st %d0 # set true 17808 clr.b %d0 # set false 17820 st %d0 # set false 17834 clr.b %d0 # set false 17840 st %d0 # set true 17854 clr.b %d0 # set false 17860 st %d0 # set true 17884 clr.b %d0 # set false 17887 st %d0 # set true 17898 clr.b %d0 # set false 17901 st %d0 # set true 17912 clr.b %d0 # set false 17915 st %d0 # set true 17926 clr.b %d0 # set false 17929 st %d0 # set true 17940 clr.b %d0 # set false 17943 st %d0 # set true 17954 clr.b %d0 # set false 17957 st %d0 # set true 17968 clr.b %d0 # set false 17971 st %d0 # set true 17982 clr.b %d0 # set false 17985 st %d0 # set true 17996 clr.b %d0 # set false 17999 st %d0 # set true 18010 clr.b %d0 # set false 18013 st %d0 # set true 18024 clr.b %d0 # set false 18027 st %d0 # set true 18038 clr.b %d0 # set false 18041 st %d0 # set true 18062 mov.l %d0,%a0 # save result for a moment 18065 mov.l %d1,%d0 # make a copy 18070 mov.l %d0,%d1 18072 mov.l %a0,%d0 # pass result in d0 18089 mov.l %a0,%d0 # pass result in d0 18102 mov.l %a0,%d0 # pass result in d0 18111 movq.l &0x1,%d0 # pass amt to inc by 18120 mov.l %a0,%d0 # pass result in d0 18129 movq.l &0x1,%d0 # pass amt to dec by 18165 # d0 = size of dump # 18168 # d0 = FSLW # 18170 # d0 = FSLW # 18223 # fetch the bit string into d0... 18226 andi.l &0x000000ff,%d0 # keep only lo byte 18228 mov.l %d0,-(%sp) # save strg 18229 mov.b (tbl_fmovm_size.w,%pc,%d0),%d0 18230 mov.l %d0,-(%sp) # save size 18232 mov.l (%sp)+,%d0 # restore size 18273 sub.l %d0,%sp # subtract size of dump 18337 mov.l %d0,-(%sp) # save size 18340 mov.l (%sp)+,%d0 18341 add.l %d0,%sp # clear fpreg data from stack 18354 sub.l %d0,%sp # make room for fpregs 18358 mov.l %d0,-(%sp) # save # of bytes 18362 mov.l (%sp)+,%d0 # retrieve # of bytes 18423 add.l %d0,%sp # remove fpregs from stack 18524 mov.l %d0,%a0 # move # bytes to a0 18528 mov.w EXC_OPWORD(%a6),%d0 # fetch opcode word 18529 mov.w %d0,%d1 # make a copy 18531 andi.w &0x3f,%d0 # extract mode field 18535 mov.w (tbl_fea_mode.b,%pc,%d0.w*2),%d0 # fetch jmp distance 18536 jmp (tbl_fea_mode.b,%pc,%d0.w*1) # jmp to correct ea mode 18651 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 18652 mov.l %d0,%d1 18655 mov.l %d0,%a0 18659 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 18660 mov.l %d0,%d1 18663 mov.l %d0,%a0 18667 mov.l %a2,%d0 # Get current a2 18668 mov.l %d0,%d1 18671 mov.l %d0,%a0 18675 mov.l %a3,%d0 # Get current a3 18676 mov.l %d0,%d1 18679 mov.l %d0,%a0 18683 mov.l %a4,%d0 # Get current a4 18684 mov.l %d0,%d1 18687 mov.l %d0,%a0 18691 mov.l %a5,%d0 # Get current a5 18692 mov.l %d0,%d1 18695 mov.l %d0,%a0 18699 mov.l (%a6),%d0 # Get current a6 18700 mov.l %d0,%d1 18703 mov.l %d0,%a0 18709 mov.l EXC_A7(%a6),%d0 # Get current a7 18710 mov.l %d0,%d1 18713 mov.l %d0,%a0 18720 mov.l EXC_DREGS+0x8(%a6),%d0 # Get current a0 18721 sub.l %a0,%d0 # Decrement 18722 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value 18723 mov.l %d0,%a0 18727 mov.l EXC_DREGS+0xc(%a6),%d0 # Get current a1 18728 sub.l %a0,%d0 # Decrement 18729 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value 18730 mov.l %d0,%a0 18734 mov.l %a2,%d0 # Get current a2 18735 sub.l %a0,%d0 # Decrement 18736 mov.l %d0,%a2 # Save decr value 18737 mov.l %d0,%a0 18741 mov.l %a3,%d0 # Get current a3 18742 sub.l %a0,%d0 # Decrement 18743 mov.l %d0,%a3 # Save decr value 18744 mov.l %d0,%a0 18748 mov.l %a4,%d0 # Get current a4 18749 sub.l %a0,%d0 # Decrement 18750 mov.l %d0,%a4 # Save decr value 18751 mov.l %d0,%a0 18755 mov.l %a5,%d0 # Get current a5 18756 sub.l %a0,%d0 # Decrement 18757 mov.l %d0,%a5 # Save decr value 18758 mov.l %d0,%a0 18762 mov.l (%a6),%d0 # Get current a6 18763 sub.l %a0,%d0 # Decrement 18764 mov.l %d0,(%a6) # Save decr value 18765 mov.l %d0,%a0 18771 mov.l EXC_A7(%a6),%d0 # Get current a7 18772 sub.l %a0,%d0 # Decrement 18773 mov.l %d0,EXC_A7(%a6) # Save decr value 18774 mov.l %d0,%a0 18788 mov.w %d0,%a0 # sign extend displacement 18801 mov.w %d0,%a0 # sign extend displacement 18814 mov.w %d0,%a0 # sign extend displacement 18827 mov.w %d0,%a0 # sign extend displacement 18840 mov.w %d0,%a0 # sign extend displacement 18853 mov.w %d0,%a0 # sign extend displacement 18866 mov.w %d0,%a0 # sign extend displacement 18879 mov.w %d0,%a0 # sign extend displacement 18893 mov.l %d0,-(%sp) 18897 bsr.l _imem_read_word # fetch extword in d0 18904 btst &0x8,%d0 18907 mov.l %d0,L_SCR1(%a6) # hold opword 18909 mov.l %d0,%d1 18921 ext.l %d0 # sign extend word index 18927 lsl.l %d1,%d0 # shift index by scale 18930 add.l %d2,%d0 # index + disp 18931 add.l %d0,%a0 # An + (index + disp) 18947 mov.w %d0,%a0 # return <ea> in a0 18961 mov.l %d0,%a0 # return <ea> in a0 18975 mov.w %d0,%a0 # sign extend displacement 19000 btst &0x8,%d0 # is disp only 8 bits? 19003 mov.l %d0,L_SCR1(%a6) # store opword 19005 mov.l %d0,%d1 # make extword copy 19017 ext.l %d0 # sign extend word index 19023 lsl.l %d1,%d0 # shift index by scale 19026 add.l %d2,%d0 # disp + index 19027 add.l %d0,%a0 # An + (index + disp) 19037 btst &0x6,%d0 # is the index suppressed? 19042 mov.l %d0,%d5 # put extword in d5 19050 mov.l %d0,L_SCR1(%a6) # save d0 (opword) 19051 bfextu %d0{&16:&4},%d1 # fetch dreg index 19055 mov.l %d0,%d2 # put index in d2 19064 bfextu %d5{&21:&2},%d0 19065 lsl.l %d0,%d2 19076 bfextu %d5{&26:&2},%d0 # get bd size 19079 cmpi.b %d0,&0x2 19100 ext.l %d0 # sign extend bd 19103 add.l %d0,%d3 # base += bd 19107 bfextu %d5{&30:&2},%d0 # is od suppressed? 19110 cmpi.b %d0,&0x2 19131 ext.l %d0 # sign extend od 19135 clr.l %d0 19138 mov.l %d0,%d4 19149 add.l %d2,%d0 # <ea> += index 19150 add.l %d4,%d0 # <ea> += od 19161 add.l %d4,%d0 # ea += od 19166 mov.l %d3,%d0 19168 mov.l %d0,%a0 19178 mov.w &0x0101,%d0 19187 mov.w &0x00e1,%d0 19192 mov.w &0x0161,%d0 19237 mov.b EXC_EXTWORD(%a6),%d0 # fetch reg select bits 19238 cmpi.b %d0,&0x9c # fpcr & fpsr & fpiar ? 19240 cmpi.b %d0,&0x98 # fpcr & fpsr ? 19242 cmpi.b %d0,&0x94 # fpcr & fpiar ? 19254 mov.l %d0,USER_FPSR(%a6) # store new FPSR to stack 19262 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 19274 mov.l %d0,USER_FPCR(%a6) # store new FPCR to stack 19282 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to stack 19294 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 19302 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 19314 mov.l %d0,USER_FPCR(%a6) # store new FPCR to mem 19322 mov.l %d0,USER_FPSR(%a6) # store new FPSR to mem 19330 mov.l %d0,USER_FPIAR(%a6) # store new FPIAR to mem 19342 # d0 = number of bytes to adjust <ea> by # 19364 mov.l %d0, %a0 # move # bytes to %a0 19366 mov.b 1+EXC_OPWORD(%a6), %d0 # fetch opcode word 19367 mov.l %d0, %d1 # make a copy 19369 andi.w &0x38, %d0 # extract mode field 19372 cmpi.b %d0,&0x18 # is mode (An)+ ? 19375 cmpi.b %d0,&0x20 # is mode -(An) ? 19378 or.w %d1,%d0 # concat mode,reg 19379 cmpi.b %d0,&0x3c # is mode #<data>? 19396 mov.l %a0,%d0 # pass amt to inc by 19407 mov.l %a0,%d0 # pass amt to dec by 19412 cmpi.b %d0,&0xc # is opsize ext or packed? 19449 mov.b 1+EXC_OPWORD(%a6),%d0 # fetch opcode word 19450 mov.l %d0,%d1 # make a copy 19452 andi.w &0x38,%d0 # extract mode field 19455 cmpi.b %d0,&0x18 # is mode (An)+ ? 19458 cmpi.b %d0,&0x20 # is mode -(An) ? 19616 # bfextu EXC_CMDREG(%a6){&0:&3}, %d0 # extract opclass 19617 # cmpi.b %d0, &0x2 # which class is it? ('000,'010,'011) 19629 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch extension word lo 19630 btst &0x5,%d0 # testing extension bits 19632 btst &0x4,%d0 # (bit 5 == 1) 19634 and.w &0x007f,%d0 # extract extension bits {6:0} 19635 cmpi.w %d0,&0x0038 # is it an fcmp (dyadic) ? 19639 bfextu EXC_CMDREG(%a6){&6:&3}, %d0 # extract dst field 19644 cmpi.b %d0, &UNNORM # is dst fpreg an UNNORM? 19647 mov.b %d0, DTAG(%a6) # store the dst optype tag 19650 bfextu EXC_CMDREG(%a6){&3:&3}, %d0 # extract src field 19655 cmpi.b %d0, &UNNORM # is src fpreg an UNNORM? 19658 mov.b %d0, STAG(%a6) # store the src optype tag 19672 mov.w EXC_CMDREG(%a6),%d0 # fetch extension word 19673 btst &0x5,%d0 # testing extension bits 19675 btst &0x4,%d0 # (bit 5 == 1) 19677 and.w &0x007f,%d0 # extract extension bits {6:0} 19678 cmpi.w %d0,&0x0038 # is it an fcmp (dyadic) ? 19682 bfextu EXC_CMDREG(%a6){&6:&3}, %d0 # extract dst field 19687 cmpi.b %d0, &UNNORM # is dst fpreg an UNNORM? 19690 mov.b %d0, DTAG(%a6) # store the dst optype tag 19693 bfextu EXC_CMDREG(%a6){&3:&3}, %d0 # extract src type field 19702 mov.w (tbl_op010_dreg.b,%pc,%d0.w*2), %d0 # jmp based on optype 19703 jmp (tbl_op010_dreg.b,%pc,%d0.w*1) # fetch src from dreg 19724 bsr.l fetch_dreg # fetch long in d0 19725 fmov.l %d0, %fp0 # load a long 19737 bsr.l fetch_dreg # fetch word in d0 19738 fmov.w %d0, %fp0 # load a word 19750 bsr.l fetch_dreg # fetch word in d0 19751 fmov.b %d0, %fp0 # load a byte 19766 bsr.l fetch_dreg # fetch sgl in d0 19767 mov.l %d0,L_SCR1(%a6) 19771 mov.b %d0, STAG(%a6) # save the src tag 19773 cmpi.b %d0, &SNAN # is it an SNAN? 19776 cmpi.b %d0, &DENORM # is it a DENORM? 19795 # %d0 : src type field # 19800 mov.w (tbl_fp_type.b,%pc,%d0.w*2), %d0 # index by src type field 19801 jmp (tbl_fp_type.b,%pc,%d0.w*1) 19822 movq.l &0x4, %d0 # pass: 4 (bytes) 19834 fmov.l %d0, %fp0 # read into %fp0;convert to xprec 19858 movq.l &0x2, %d0 # pass: 2 (bytes) 19870 fmov.w %d0, %fp0 # read into %fp0;convert to xprec 19894 movq.l &0x1, %d0 # pass: 1 (byte) 19906 fmov.b %d0, %fp0 # read into %fp0;convert to xprec 19930 movq.l &0x4, %d0 # pass: 4 (bytes) 19937 mov.l %d0, L_SCR1(%a6) # store src op on stack 19945 mov.b %d0, STAG(%a6) # save src optype tag on stack 19947 cmpi.b %d0, &DENORM # is it a sgl DENORM? 19950 cmpi.b %d0, &SNAN # is it a sgl SNAN? 19969 bfextu (%a0){&9:&23}, %d0 # fetch sgl hi(_mantissa) 19970 lsl.l &0x8, %d0 19971 mov.l %d0, FP_SRC_HI(%a6) # set ext hi(_mantissa) 19983 sub.w %d0, %d1 # exp = 0x3f81 - shft amt. 19993 bfextu (%a0){&9:&23}, %d0 19994 lsl.l &0x8, %d0 # extract and insert hi(man) 19995 mov.l %d0, FP_SRC_HI(%a6) 20012 movq.l &0x8, %d0 # pass: 8 (bytes) 20019 movq.l &0x8, %d0 # pass: # bytes to read 20028 mov.b %d0, STAG(%a6) # set src optype tag 20030 cmpi.b %d0, &DENORM # is it a dbl DENORM? 20033 cmpi.b %d0, &SNAN # is it a dbl SNAN? 20042 movq.l &0x8, %d0 # pass: # bytes to read 20054 bfextu (%a0){&12:&31}, %d0 # fetch hi(_mantissa) 20055 mov.l %d0, FP_SRC_HI(%a6) 20056 bfextu 4(%a0){&11:&21}, %d0 # fetch lo(_mantissa) 20058 lsl.l %d1, %d0 20059 mov.l %d0, FP_SRC_LO(%a6) 20069 sub.w %d0, %d1 # exp = 0x3c01 - shft amt. 20080 bfextu (%a0){&12:&31}, %d0 # fetch hi(_mantissa) 20081 mov.l %d0, FP_SRC_HI(%a6) 20082 bfextu 4(%a0){&11:&21}, %d0 # fetch lo(_mantissa) 20084 lsl.l %d1, %d0 20085 mov.l %d0, FP_SRC_LO(%a6) 20101 mov.l &0xc, %d0 # pass: 12 (bytes) 20105 mov.l &0xc, %d0 # pass: # of bytes to read 20114 cmpi.b %d0, &UNNORM # is the src op an UNNORM? 20117 mov.b %d0, STAG(%a6) # store the src optype tag 20122 mov.b %d0, STAG(%a6) # store the src optype tag 20137 cmpi.b %d0,&UNNORM # is the src op an UNNORM ZERO? 20140 mov.b %d0,STAG(%a6) # store the src optype tag 20145 mov.b %d0,STAG(%a6) # store the src optype tag 20169 # d0 = round prec,mode # 20229 fmov.l %d0,%fpcr # insert rnd prec,mode 20231 fmov.b %fp0,%d0 # exec move out w/ correct rnd mode 20275 fmov.l %d0,%fpcr # insert rnd prec:mode 20277 fmov.w %fp0,%d0 # exec move out w/ correct rnd mode 20321 fmov.l %d0,%fpcr # insert rnd prec:mode 20323 fmov.l %fp0,%d0 # exec move out w/ correct rnd mode 20378 mov.l &0xc,%d0 # pass: opsize is 12 bytes 20399 mov.b FPCR_ENABLE(%a6),%d0 20400 andi.b &0x0a,%d0 # is UNFL or INEX enabled? 20419 neg.w %d0 # new exp = -(shft amt) 20420 andi.w &0x7fff,%d0 20422 or.w %d0,FP_SCR0_EX(%a6) # insert new exponent 20434 andi.b &0x30,%d0 # clear rnd prec 20435 ori.b &s_mode*0x10,%d0 # insert sgl prec 20436 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 20444 mov.w SRC_EX(%a0),%d0 # extract exponent 20445 andi.w &0x7fff,%d0 # strip sign 20447 cmpi.w %d0,&SGL_HI # will operand overflow? 20450 cmpi.w %d0,&SGL_LO # will operand underflow? 20463 fmov.s %fp0,%d0 # store does convert and round 20502 clr.l %d0 # pass: S.F. = 0 20563 mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode 20566 fmov.s %fp0,%d0 # store to single 20632 neg.l %d0 20633 andi.w &0x7fff,%d0 20634 bfins %d0,FP_SCR0_EX(%a6){&1:&15} 20657 clr.l %d0 # pass: zero g,r,s 20672 andi.b &0x30,%d0 # clear rnd prec 20673 ori.b &d_mode*0x10,%d0 # insert dbl prec 20674 mov.l %d0,L_SCR3(%a6) # save rnd prec,mode on stack 20682 mov.w SRC_EX(%a0),%d0 # extract exponent 20683 andi.w &0x7fff,%d0 # strip sign 20685 cmpi.w %d0,&DBL_HI # will operand overflow? 20688 cmpi.w %d0,&DBL_LO # will operand underflow? 20704 fmov.l %fpsr,%d0 # save FPSR 20706 or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex 20710 movq.l &0x8,%d0 # pass: opsize is 8 bytes 20731 clr.l %d0 # pass: S.F. = 0 20746 mov.l %d0,L_SCR1(%a6) 20751 movq.l &0x8,%d0 # pass: opsize is 8 bytes 20767 mov.w 2+SRC_LO(%a0),%d0 20768 andi.w &0x7ff,%d0 20784 mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode 20791 movq.l &0x8,%d0 # pass: opsize is 8 bytes 20840 # d0 = hi(double precision result) # 20868 clr.l %d0 # clear d0 20869 mov.w FTEMP_EX(%a0),%d0 # get exponent 20870 subi.w &EXT_BIAS,%d0 # subtract extended precision bias 20871 addi.w &DBL_BIAS,%d0 # add double precision bias 20874 subq.w &0x1,%d0 # yes; denorm bias = DBL_BIAS - 1 20876 swap %d0 # d0 now in upper word 20877 lsl.l &0x4,%d0 # d0 in proper place for dbl prec exp 20880 bset &0x1f,%d0 # if negative, set sign 20884 or.l %d1,%d0 # put these bits in ms word of double 20885 mov.l %d0,L_SCR1(%a6) # put the new exp back on the stack 20887 mov.l &21,%d0 # load shift count 20888 lsl.l %d0,%d1 # put lower 11 bits in upper bits 20891 bfextu %d1{&0:&21},%d0 # get ls 21 bits of double 20893 or.l %d0,%d1 # put them in double result 20894 mov.l L_SCR1(%a6),%d0 20907 # d0 = single precision result # 20933 clr.l %d0 20934 mov.w FTEMP_EX(%a0),%d0 # get exponent 20935 subi.w &EXT_BIAS,%d0 # subtract extended precision bias 20936 addi.w &SGL_BIAS,%d0 # add single precision bias 20939 subq.w &0x1,%d0 # yes; denorm bias = SGL_BIAS - 1 20941 swap %d0 # put exp in upper word of d0 20942 lsl.l &0x7,%d0 # shift it into single exp bits 20945 bset &0x1f,%d0 # if negative, put in sign first 20950 or.l %d1,%d0 # put these bits in ms word of single 20958 mov.b STAG(%a6),%d0 # fetch input type 20974 mov.b 1+EXC_CMDREG(%a6),%d0 # fetch static field 20977 bfexts %d0{&25:&7},%d0 # extract k-factor 20978 mov.l %d0,-(%sp) 20989 mov.l (%sp)+,%d0 21000 tst.l %d0 21015 mov.l &0xc,%d0 # pass: opsize is 12 bytes 21038 cmpi.b %d0,&DENORM # is it a DENORM? 21042 cmpi.b %d0,&SNAN # is it an SNAN? 21062 # d0 = value of register fetched # 21075 mov.w (tbl_fdreg.b,%pc,%d1.w*2),%d0 21076 jmp (tbl_fdreg.b,%pc,%d0.w*1) 21097 mov.l EXC_DREGS+0x0(%a6),%d0 21100 mov.l EXC_DREGS+0x4(%a6),%d0 21103 mov.l %d2,%d0 21106 mov.l %d3,%d0 21109 mov.l %d4,%d0 21112 mov.l %d5,%d0 21115 mov.l %d6,%d0 21118 mov.l %d7,%d0 21121 mov.l EXC_DREGS+0x8(%a6),%d0 21124 mov.l EXC_DREGS+0xc(%a6),%d0 21127 mov.l %a2,%d0 21130 mov.l %a3,%d0 21133 mov.l %a4,%d0 21136 mov.l %a5,%d0 21139 mov.l (%a6),%d0 21142 mov.l EXC_A7(%a6),%d0 21153 # d0 = longowrd value to store # 21161 # in d0 to the corresponding data register. D0/D1 are on the stack # 21182 mov.l %d0,EXC_DREGS+0x0(%a6) 21185 mov.l %d0,EXC_DREGS+0x4(%a6) 21188 mov.l %d0,%d2 21191 mov.l %d0,%d3 21194 mov.l %d0,%d4 21197 mov.l %d0,%d5 21200 mov.l %d0,%d6 21203 mov.l %d0,%d7 21214 # d0 = word value to store # 21222 # in d0 to the corresponding data register. D0/D1 are on the stack # 21243 mov.w %d0,2+EXC_DREGS+0x0(%a6) 21246 mov.w %d0,2+EXC_DREGS+0x4(%a6) 21249 mov.w %d0,%d2 21252 mov.w %d0,%d3 21255 mov.w %d0,%d4 21258 mov.w %d0,%d5 21261 mov.w %d0,%d6 21264 mov.w %d0,%d7 21275 # d0 = byte value to store # 21283 # in d0 to the corresponding data register. D0/D1 are on the stack # 21304 mov.b %d0,3+EXC_DREGS+0x0(%a6) 21307 mov.b %d0,3+EXC_DREGS+0x4(%a6) 21310 mov.b %d0,%d2 21313 mov.b %d0,%d3 21316 mov.b %d0,%d4 21319 mov.b %d0,%d5 21322 mov.b %d0,%d6 21325 mov.b %d0,%d7 21330 # inc_areg(): increment an address register by the value in d0 # 21336 # d0 = amount to increment by # 21344 # this routine adds the increment value in d0 to the address register # 21369 iareg0: add.l %d0,EXC_DREGS+0x8(%a6) 21371 iareg1: add.l %d0,EXC_DREGS+0xc(%a6) 21373 iareg2: add.l %d0,%a2 21375 iareg3: add.l %d0,%a3 21377 iareg4: add.l %d0,%a4 21379 iareg5: add.l %d0,%a5 21381 iareg6: add.l %d0,(%a6) 21384 cmpi.b %d0,&0x1 21386 add.l %d0,EXC_A7(%a6) 21394 # dec_areg(): decrement an address register by the value in d0 # 21400 # d0 = amount to decrement by # 21408 # this routine adds the decrement value in d0 to the address register # 21433 dareg0: sub.l %d0,EXC_DREGS+0x8(%a6) 21435 dareg1: sub.l %d0,EXC_DREGS+0xc(%a6) 21437 dareg2: sub.l %d0,%a2 21439 dareg3: sub.l %d0,%a3 21441 dareg4: sub.l %d0,%a4 21443 dareg5: sub.l %d0,%a5 21445 dareg6: sub.l %d0,(%a6) 21448 cmpi.b %d0,&0x1 21450 sub.l %d0,EXC_A7(%a6) 21466 # d0 = index of FP register to load # 21472 # Using the index in d0, load FP_SRC(a6) with a number from the # 21479 mov.w (tbl_load_fpn1.b,%pc,%d0.w*2), %d0 21480 jmp (tbl_load_fpn1.b,%pc,%d0.w*1) 21539 # d0 = index of FP register to load # 21545 # Using the index in d0, load FP_DST(a6) with a number from the # 21552 mov.w (tbl_load_fpn2.b,%pc,%d0.w*2), %d0 21553 jmp (tbl_load_fpn2.b,%pc,%d0.w*1) 21606 # store_fpreg(): store an fp value to the fpreg designated d0. # 21613 # d0 = index of floating-point register # 21620 # value in d0. The FP number can be DENORM or SNAN so we have to be # 21627 mov.w (tbl_store_fpreg.b,%pc,%d0.w*2), %d0 21628 jmp (tbl_store_fpreg.b,%pc,%d0.w*1) 21682 # d0 = rounding precision # 21688 # d0 = guard,round,sticky # 21718 lsr.b &0x2, %d0 # shift prec to lo bits 21719 mov.w (tbl_thresh.b,%pc,%d0.w*2), %d1 # load prec threshold 21720 mov.w %d1, %d0 # copy d1 into d0 21721 sub.w FTEMP_EX(%a0), %d0 # diff = threshold - exp 21722 cmpi.w %d0, &66 # is diff > 65? (mant + g,r bits) 21725 clr.l %d0 # clear g,r,s 21728 bset &29, %d0 # yes; set sticky bit 21739 mov.l &0x20000000, %d0 # set sticky bit in return value 21750 # %d0{31:29} : initial guard,round,sticky # 21754 # %d0{31:29} : final guard,round,sticky # 21769 mov.l %d0, GRS(%a6) # place g,r,s after it 21775 mov.l %d1, %d0 # copy the denorm threshold 21788 mov.l GRS(%a6), %d0 # restore original g,r,s 21794 # %d0 = denorm threshold 21817 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 21818 mov.l &32, %d0 21819 sub.w %d1, %d0 # %d0 = 32 - %d1 21827 bfextu FTEMP_HI(%a0){&0:%d0}, %d2 # %d2 = new FTEMP_HI 21828 bfextu FTEMP_HI(%a0){%d0:&32}, %d1 # %d1 = new FTEMP_LO 21829 bfextu FTEMP_LO2(%a6){%d0:&32}, %d0 # %d0 = new G,R,S 21834 bftst %d0{&2:&30} # were bits shifted off? 21836 bset &rnd_stky_bit, %d0 # yes; set sticky bit 21839 and.l &0xe0000000, %d0 # clear all but G,R,S 21846 # %d0 = denorm threshold 21869 mov.w %d0, FTEMP_EX(%a0) # exponent = denorm threshold 21871 mov.l &0x20, %d0 21872 sub.w %d1, %d0 # %d0 = 32 - %d1 21880 bfextu FTEMP_HI(%a0){&0:%d0}, %d2 # %d2 = new FTEMP_LO 21881 bfextu FTEMP_HI(%a0){%d0:&32}, %d1 # %d1 = new G,R,S 21885 bftst FTEMP_LO2(%a6){%d0:&31} # were any bits shifted off? 21888 mov.l %d1, %d0 # move new G,R,S to %d0 21892 mov.l %d1, %d0 # move new G,R,S to %d0 21893 bset &rnd_stky_bit, %d0 # set sticky bit 21898 and.l &0xe0000000, %d0 # clear all but G,R,S 21906 # %d0 = denorm threshold 21910 mov.w %d0, FTEMP_EX(%a0) # insert denorm threshold 21924 mov.l &0x20000000, %d0 # set sticky bit 21948 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 21949 mov.l %d0, %d1 # make a copy 21950 and.l &0xc0000000, %d0 # extract G,R 21976 mov.l FTEMP_HI(%a0), %d0 # fetch hi(mantissa) 21977 and.l &0x80000000, %d0 # extract R bit 21978 lsr.l &0x1, %d0 # shift high bit into R bit 22004 bset &rnd_stky_bit,%d0 # set new sticky bit 22027 # d0{31:29} = contains the g,r,s bits (extended) # 22034 # a0 is preserved and the g-r-s bits in d0 are cleared. # 22053 tst.l %d0 # are G,R,S zero? 22080 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 22097 mov.l &0xffffffff, %d0 # force g,r,s to be all f's 22112 asl.l &0x1, %d0 # shift g-bit to c-bit 22136 tst.l %d0 # test for rs = 0 22158 tst.l %d0 # test rs = 0 22179 tst.l %d0 # test for rs = 0 22204 # d0 = extended precision g,r,s (in d0{31:29}) 22207 # d0{31:29} = guard, round, sticky 22211 # only. All registers except d0 are kept intact. d0 becomes an 22212 # updated guard,round,sticky in d0{31:29} 22226 # %d0 actually already hold g,r,s since _round() had it before calling 22260 tst.l %d0 # test original g,r,s 22283 tst.l %d0 # test word original g,r,s 22290 mov.l %d3, %d0 # return grs to d0 22311 # d0 = number of bit positions the mantissa was shifted # 22321 mov.l FTEMP_HI(%a0), %d0 # load hi(mantissa) 22324 bfffo %d0{&0:&32}, %d2 # how many places to shift? 22328 lsl.l %d2, %d0 # left shift hi(man) 22331 or.l %d3, %d0 # create hi(man) 22334 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 22337 mov.l %d2, %d0 # return shift amount 22352 mov.l %d2, %d0 # return shift amount 22373 # d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO # 22381 bfffo FTEMP_HI(%a0){&0:&32}, %d0 # how many shifts are needed? 22388 bfffo FTEMP_LO(%a0){&0:&32}, %d0 # is operand really a zero? 22391 add.w &32, %d0 # no; fix shift distance 22394 # d0 = # shifts needed for complete normalization 22401 cmp.w %d0, %d1 # will denorm push exp < 0? 22407 sub.w %d0, %d1 # shift exponent value 22408 mov.w FTEMP_EX(%a0), %d0 # load old exponent 22409 and.w &0x8000, %d0 # save old sign 22410 or.w %d0, %d1 # {sgn,new exp} 22415 mov.b &NORM, %d0 # return new optype tag 22425 bfextu FTEMP_HI(%a0){%d1:&32}, %d0 # extract new hi(man) 22426 mov.l %d0, FTEMP_HI(%a0) # save new hi(man) 22428 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 22429 lsl.l %d1, %d0 # extract new lo(man) 22430 mov.l %d0, FTEMP_LO(%a0) # save new lo(man) 22434 mov.b &DENORM, %d0 # return new optype tag 22443 mov.l FTEMP_LO(%a0), %d0 # fetch old lo(man) 22444 lsl.l %d1, %d0 # left shift lo(man) 22446 mov.l %d0, FTEMP_HI(%a0) # store new hi(man) 22451 mov.b &DENORM, %d0 # return new optype tag 22460 mov.b &ZERO, %d0 # fix optype tag 22474 # d0 = value of type tag # 22487 mov.w FTEMP_EX(%a0), %d0 # extract exponent 22488 andi.w &0x7fff, %d0 # strip off sign 22489 cmpi.w %d0, &0x7fff # is (EXP == MAX)? 22495 mov.b &NORM, %d0 22498 tst.w %d0 # is exponent = 0? 22506 mov.b &ZERO, %d0 22509 mov.b &DENORM, %d0 22520 mov.b &ZERO, %d0 22523 mov.b &UNNORM, %d0 22528 mov.l FTEMP_HI(%a0), %d0 22529 and.l &0x7fffffff, %d0 # msb is a don't care! 22532 mov.b &INF, %d0 22537 mov.b &QNAN, %d0 22540 mov.b &SNAN, %d0 22554 # d0 = value of type tag # 22565 mov.l FTEMP(%a0), %d0 22566 mov.l %d0, %d1 22568 andi.l &0x7ff00000, %d0 22571 cmpi.l %d0, &0x7ff00000 22575 mov.b &NORM, %d0 22583 mov.b &ZERO, %d0 22586 mov.b &DENORM, %d0 22594 mov.b &INF, %d0 22600 mov.b &SNAN, %d0 22603 mov.b &QNAN, %d0 22617 # d0 = value of type tag # 22628 mov.l FTEMP(%a0), %d0 22629 mov.l %d0, %d1 22631 andi.l &0x7f800000, %d0 22634 cmpi.l %d0, &0x7f800000 22638 mov.b &NORM, %d0 22644 mov.b &ZERO, %d0 22647 mov.b &DENORM, %d0 22653 mov.b &INF, %d0 22659 mov.b &SNAN, %d0 22662 mov.b &QNAN, %d0 22679 # d0 = scale factor # 22684 # d0.b = result FPSR_cc which caller may or may not want to save # 22690 # according to the scale factor passed in d0. Then, round the # 22693 # d0 in case the caller doesn't want to save them (as is the case for # 22708 sub.w %d0, %d1 22713 mov.l 0x4(%sp),%d0 # pass rnd prec. 22714 andi.w &0x00c0,%d0 22715 lsr.w &0x4,%d0 22739 clr.l %d0 22745 bset &z_bit, %d0 # yes; set zero ccode bit 22772 sub.w %d0,%d1 22777 clr.l %d0 # force rnd prec = ext 22799 clr.l %d0 22805 bset &z_bit,%d0 # yes; set zero ccode bit 22835 # d0 = rnd mode/prec # 22837 # hi(d0) = rnd prec # 22838 # lo(d0) = rnd mode # 22842 # d0.b = condition code bits # 22849 # resulting condition codes are returned in d0 in case the caller # 22857 lsr.b &0x4,%d0 # shift prec/mode 22858 or.b %d0,%d1 # concat the two 22859 mov.w %d1,%d0 # make a copy 22866 or.b %d0, %d1 # insert rnd mode 22867 swap %d0 22868 or.b %d0, %d1 # insert rnd prec 22869 mov.w %d1, %d0 # make a copy 22877 mov.b (tbl_ovfl_cc.b,%pc,%d0.w*1), %d0 # fetch result ccodes 22960 mov.l &0xc,%d0 # packed is 12 bytes 22964 mov.l &0xc,%d0 # pass: 12 bytes 22971 bfextu FP_SRC(%a6){&1:&15},%d0 # get exp 22972 cmpi.w %d0,&0x7fff # INF or NAN? 22979 mov.b 3+FP_SRC(%a6),%d0 # get byte 4 22980 andi.b &0x0f,%d0 # clear all but last nybble 23091 # (*) d0: temp digit storage 23108 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend into d0 23109 add.l %d0,%d1 # d1 = d1 + d0 23133 # (*) d0: temp digit storage 23153 bfextu (%a0){&28:&4},%d0 # integer part is ls digit in long word 23154 fadd.b %d0,%fp0 # add digit to sum in fp0 23165 bfextu %d4{%d3:&4},%d0 # get the digit and zero extend 23166 fadd.b %d0,%fp0 # fp0 = fp0 + digit 23221 # (*) d0: temp digit storage 23245 bfextu %d4{&28:&4},%d0 # get M16 in d0 23258 bfextu %d4{%d3:&4},%d0 # get digit 23264 mov.l %d1,%d0 # copy counter to d2 23266 sub.l %d0,%d1 # subtract count from exp 23282 asr.l &1,%d0 # shift lsb into carry 23287 tst.l %d0 # check if d0 is zero 23306 bfextu %d4{%d3:&4},%d0 # get digit 23312 mov.l %d1,%d0 # copy counter to d0 23314 sub.l %d0,%d1 # subtract count from exp 23330 asr.l &1,%d0 # shift lsb into carry 23335 tst.l %d0 # check if d0 is zero 23345 # (*) d0: temp 23352 # (*) d0: temp 23387 bfextu %d4{&0:&2},%d0 # {FPCR[6],FPCR[5],SM,SE} 23388 add.l %d0,%d2 # in d2 as index into RTABLE 23390 mov.b (%a1,%d2),%d0 # load new rounding bits from table 23392 bfins %d0,%d3{&26:&2} # stuff new rounding bits in FPCR 23394 asr.l &1,%d0 # write correct PTENxx table 23399 asr.l &1,%d0 # keep checking 23406 mov.l %d1,%d0 # copy exp to d0;use d0 23408 neg.l %d0 # invert it 23414 asr.l &1,%d0 # shift next bit into carry 23419 tst.l %d0 # check if d0 is zero 23449 fmov.l %fpsr,%d0 # get status register 23450 bclr &inex2_bit+8,%d0 # test for inex2 and clear it 23468 # d0 = contains the k-factor sign-extended to 32-bits. # 23591 # d0: scratch; LEN input to binstr 23624 mov.l %d0,%d7 # move k-factor to d7 23634 mov.w (%a0),%d0 23635 and.w &0x7fff,%d0 # strip sign of normalized exp 23639 sub.w &1,%d0 23647 tst.w %d0 23651 and.w &0x7fff,%d0 # strip sign of normalized exp 23652 mov.w %d0,(%a0) 23672 # d0: k-factor/exponent 23695 mov.w FP_SCR1(%a6),%d0 # move exp to d0 23698 sub.w &0x3fff,%d0 # strip off bias 23699 fadd.w %d0,%fp0 # add in exp 23734 # d0: exponent/Unchanged 23806 # d0: exponent/scratch - final is 0 23831 mov.l %d6,%d0 # calc ILOG + 1 - LEN in d0 23832 addq.l &1,%d0 # add the 1 23833 sub.l %d4,%d0 # sub off LEN 23837 tst.l %d0 # test sign of ISCALE 23840 cmp.l %d0,&0xffffecd4 # test iscale <= -4908 23842 add.l &24,%d0 # add in 24 to iscale 23845 neg.l %d0 # and take abs of ISCALE 23875 lsr.l &1,%d0 # shift next bit into carry 23880 tst.l %d0 # test if ISCALE is zero 23909 # d0: FPCR with RZ mode/Unchanged 23997 # d0: FPCR with RZ mode/FPSR with INEX2 isolated 24012 fmov.l %fpsr,%d0 # get FPSR 24015 btst &9,%d0 # check if INEX2 set 24038 # d0: FPSR with AINEX cleared/FPCR with size set to ext 24058 movm.l &0xc0c0,-(%sp) # save regs used by sintd0 {%d0-%d1/%a0-%a1} 24073 ## mov.l USER_FPCR(%a6),%d0 # ext prec/keep rnd mode 24074 ## andi.l &0x00000030,%d0 24075 ## fmov.l %d0,%fpcr 24077 fmov.l %fpsr,%d0 24078 or.w %d0,FPSR_EXCEPT(%a6) 24080 ## fmov.l %fpsr,%d0 # don't keep ccodes 24081 ## or.w %d0,FPSR_EXCEPT(%a6) 24088 movm.l (%sp)+,&0x303 # restore regs used by sint {%d0-%d1/%a0-%a1} 24106 # d0: FPCR with size set to ext/scratch final = 0 24132 mov.l %d4,%d0 # put LEN in d0 24133 subq.l &1,%d0 # d0 = LEN -1 24136 lsr.l &1,%d0 # shift next bit into carry 24141 tst.l %d0 # test if LEN is zero 24184 mov.l %d4,%d0 # put LEN in d0 24187 lsr.l &1,%d0 # shift next bit into carry 24192 tst.l %d0 # test if LEN is zero 24213 # d0: x/LEN call to binstr - final is 0 24242 mov.l (%a0),%d0 # move exponent to d0 24243 swap %d0 # put exponent in lower word 24245 sub.l &0x3ffd,%d0 # sub bias less 2 to make fract 24246 tst.l %d0 # check if > 1 24248 neg.l %d0 # make exp positive 24252 dbf.w %d0,m_loop # given in d0 24264 mov.l %d4,%d0 # put LEN in d0 for binstr call 24286 # d0: x/LEN call to binstr - final is 0 24335 mov.w (%a2),%d0 # move exp to d0 24337 sub.w &0x3ffd,%d0 # subtract off bias 24338 neg.w %d0 # make exp positive 24342 dbf.w %d0,x_loop # given in d0 24348 mov.l &4,%d0 # put 4 in d0 for binstr call 24351 mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0 24353 lsr.l %d1,%d0 # shift d0 right by 12 24354 bfins %d0,FP_SCR0(%a6){&4:&12} # put e3:e2:e1 in FP_SCR0 24355 lsr.l %d1,%d0 # shift d0 right by 12 24356 bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0 24357 tst.b %d0 # check if e4 is zero 24367 # d0: x/scratch - final is x 24386 clr.l %d0 # clr d0 for collection of signs 24390 mov.l &2,%d0 # move 2 in to d0 for SM 24394 addq.l &1,%d0 # set bit 0 in d0 for SE 24396 bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0 24458 # d0 = desired length (LEN) # 24491 # upper word of d0. If it is the ls digit, write the word # 24492 # from d0 to memory. # 24502 # d0: LEN counter 24515 movm.l &0xff00,-(%sp) # {%d0-%d7} 24521 subq.l &1,%d0 # for dbf d0 would have LEN+1 passes 24564 dbf.w %d0,loop # do loop some more! 24571 dbf.w %d0,loop # do loop some more! 24579 movm.l (%sp)+,&0xff # {%d0-%d7} 24616 movq.l &0x1,%d0 # one byte 24623 movq.l &0x2,%d0 # two bytes 24630 movq.l &0x4,%d0 # four bytes 24637 movq.l &0x8,%d0 # eight bytes 24644 movq.l &0xc,%d0 # twelve bytes 24653 movq.l &0x1,%d0 # one byte 24660 movq.l &0x2,%d0 # two bytes 24667 movq.l &0x4,%d0 # four bytes 24674 movq.l &0x8,%d0 # eight bytes 24681 mov.l &0xc,%d0 # twelve bytes 24693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1 24745 sub.l %d0,EXC_DREGS+0x8(%a6) # fix stacked a0 24748 sub.l %d0,EXC_DREGS+0xc(%a6) # fix stacked a1 24751 sub.l %d0,%a2 # fix a2 24754 sub.l %d0,%a3 # fix a3 24757 sub.l %d0,%a4 # fix a4 24760 sub.l %d0,%a5 # fix a5 24763 sub.l %d0,(%a6) # fix stacked a6 24777 sub.l %d0,%a0 24784 neg.l %d0
H A D	ilsp.S	203 mov.b NDIVISOR(%a6), %d0 204 eor.b %d0, NDIVIDEND(%a6) # chk if quotient is negative 227 # here, the result is in d1 and d0. the current strategy is to save 264 divu.w &0x0,%d0 # force a divbyzero exception 374 mov.w %d4,%d0 377 tst.w %d0 # is upper word set? 519 mov.l 0x8(%a6),%d0 # store multiplier in d0 546 mov.l %d0,%d2 # mr in d2 547 mov.l %d0,%d3 # mr in d3 553 mulu.w %d1,%d0 # [1] lo(mr) * lo(md) 562 swap %d0 # hi([1]) <==> lo([1]) 563 add.w %d1,%d0 # hi([1]) + lo([2]) 565 add.w %d2,%d0 # hi([1]) + lo([3]) 567 swap %d0 # lo([1]) <==> hi([1]) 588 # here, the result is in d1 and d0. the current strategy is to save 592 exg %d1,%d0 606 clr.l %d0 630 mov.l 0x8(%a6),%d0 # store multiplier in d0 637 tst.l %d0 # is multiplier negative? 639 neg.l %d0 # make multiplier positive 672 mov.l %d0,%d2 # mr in d2 673 mov.l %d0,%d3 # mr in d3 679 mulu.w %d1,%d0 # [1] lo(mr) * lo(md) 688 swap %d0 # hi([1]) <==> lo([1]) 689 add.w %d1,%d0 # hi([1]) + lo([2]) 691 add.w %d2,%d0 # hi([1]) + lo([3]) 693 swap %d0 # lo([1]) <==> hi([1]) 711 not.l %d0 # negate lo(result) bits 713 addq.l &1,%d0 # add 1 to lo(result) 725 # here, the result is in d1 and d0. the current strategy is to save 729 exg %d1,%d0 743 clr.l %d0 800 mov.b ([0xc,%a6],0x0),%d0 803 extb.l %d0 # sign extend lo bnd 819 mov.w ([0xc,%a6],0x0),%d0 822 ext.l %d0 # sign extend lo bnd 838 mov.l ([0xc,%a6],0x0),%d0 854 mov.b ([0xc,%a6],0x0),%d0 857 extb.l %d0 # sign extend lo bnd 877 mov.w ([0xc,%a6],0x0),%d0 880 ext.l %d0 # sign extend lo bnd 900 mov.l ([0xc,%a6],0x0),%d0 911 sub.l %d0, %d2 # (Rn - lo) 914 sub.l %d0, %d1 # (hi - lo)
/linux-4.4.14/drivers/scsi/
H A D	mac_scsi.c	177 " move.w %1,%%d0\n" \ 178 " neg.b %%d0\n" \ 179 " and.w #3,%%d0\n" \ 180 " sub.w %%d0,%2\n" \ 183 " 2: dbf %%d0,1b\n" \ 184 " move.w %2,%%d0\n" \ 185 " lsr.w #5,%%d0\n" \ 195 " 4: dbf %%d0,3b\n" \ 196 " move.w %2,%%d0\n" \ 197 " lsr.w #2,%%d0\n" \ 198 " and.w #7,%%d0\n" \ 201 " 6: dbf %%d0,5b\n" \ 229 : "d0") 271 " move.w %0,%%d0\n" \ 272 " neg.b %%d0\n" \ 273 " and.w #3,%%d0\n" \ 274 " sub.w %%d0,%2\n" \ 277 " 2: dbf %%d0,1b\n" \ 278 " move.w %2,%%d0\n" \ 279 " lsr.w #5,%%d0\n" \ 289 " 4: dbf %%d0,3b\n" \ 290 " move.w %2,%%d0\n" \ 291 " lsr.w #2,%%d0\n" \ 292 " and.w #7,%%d0\n" \ 295 " 6: dbf %%d0,5b\n" \ 323 : "d0")
/linux-4.4.14/arch/m68k/68360/
H A D	head-ram.S	113 move.l #_dprbase, %d0 114 andi.l #MCU_SIM_MBAR_BA_MASK, %d0 115 ori.l #MCU_SIM_MBAR_AS_MASK, %d0 116 moves.l %d0, %a0@ 139 move.w #16384, %d0 141 subi.w #1, %d0 162 move.l #MCU_SIM_GMR, %d0 163 move.l %d0, GMR 166 move.l #RAMEND, %d0 167 subi.l #__ramstart, %d0 168 subq.l #0x01, %d0 169 eori.l #SIM_OR_MASK, %d0 170 ori.l #SIM_OR0_MASK, %d0 171 move.l %d0, OR0 173 move.l #__ramstart, %d0 174 ori.l #SIM_BR0_MASK, %d0 175 move.l %d0, BR0 178 move.l #ROMEND, %d0 179 subi.l #__rom_start, %d0 180 subq.l #0x01, %d0 181 eori.l #SIM_OR_MASK, %d0 182 ori.l #SIM_OR1_MASK, %d0 183 move.l %d0, OR1 185 move.l #__rom_start, %d0 186 ori.l #SIM_BR1_MASK, %d0 187 move.l %d0, BR1 195 move.l %a0@, %d0 196 move.l %d0, %a1@ 214 move.l %a0@, %d0 216 move.l %d0, %a1@ 237 move.l #RAMEND, %d0 238 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/ 239 move.l %d0, _ramend /* Different from RAMEND.*/
H A D	entry.S	47 movel #-ENOSYS,%d0 54 1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 72 movel %sp@(PT_OFF_ORIG_D0),%d0 79 cmpl #NR_syscalls,%d0 81 lsl #2,%d0 83 movel %a0@(%d0), %a0 85 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ 128 movew %sp@(PT_OFF_FORMATVEC), %d0 129 and.l #0x3ff, %d0 130 lsr.l #0x02, %d0 133 movel %d0,%sp@- /* put vector # on stack*/
H A D	head-rom.S	125 move.l #_dprbase, %d0 126 andi.l #MCU_SIM_MBAR_BA_MASK, %d0 127 ori.l #MCU_SIM_MBAR_AS_MASK, %d0 128 moves.l %d0, %a0@ 154 move.w #16384, %d0 156 subi.w #1, %d0 177 move.l #MCU_SIM_GMR, %d0 178 move.l %d0, GMR 181 move.l #0x00400000, %d0 182 subq.l #0x01, %d0 183 eori.l #SIM_OR_MASK, %d0 184 ori.l #SIM_OR0_MASK, %d0 185 move.l %d0, OR0 187 move.l #__rom_start, %d0 188 ori.l #SIM_BR0_MASK, %d0 189 move.l %d0, BR0 205 move.l %a0@, %d0 206 move.l %d0, %a1@ 224 move.l %a0@, %d0 226 move.l %d0, %a1@ 247 move.l #RAMEND, %d0 248 sub.l #0x1000, %d0 /* Reserve 4K for stack space.*/ 249 move.l %d0, _ramend /* Different from RAMEND.*/
/linux-4.4.14/include/asm-generic/
H A D	xor.h	109 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_2() local 110 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_2() 118 d0 ^= p2[0]; xor_32regs_2() 126 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_2() 146 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_3() local 147 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_3() 155 d0 ^= p2[0]; xor_32regs_3() 163 d0 ^= p3[0]; xor_32regs_3() 171 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_3() 192 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_4() local 193 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_4() 201 d0 ^= p2[0]; xor_32regs_4() 209 d0 ^= p3[0]; xor_32regs_4() 217 d0 ^= p4[0]; xor_32regs_4() 225 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_4() 247 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_5() local 248 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_5() 256 d0 ^= p2[0]; xor_32regs_5() 264 d0 ^= p3[0]; xor_32regs_5() 272 d0 ^= p4[0]; xor_32regs_5() 280 d0 ^= p5[0]; xor_32regs_5() 288 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_5() 440 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_p_2() local 445 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_p_2() 453 d0 ^= p2[0]; xor_32regs_p_2() 461 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_p_2() 487 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_p_3() local 493 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_p_3() 501 d0 ^= p2[0]; xor_32regs_p_3() 509 d0 ^= p3[0]; xor_32regs_p_3() 517 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_p_3() 545 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_p_4() local 552 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_p_4() 560 d0 ^= p2[0]; xor_32regs_p_4() 568 d0 ^= p3[0]; xor_32regs_p_4() 576 d0 ^= p4[0]; xor_32regs_p_4() 584 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_p_4() 614 register long d0, d1, d2, d3, d4, d5, d6, d7; xor_32regs_p_5() local 622 d0 = p1[0]; /* Pull the stuff into registers */ xor_32regs_p_5() 630 d0 ^= p2[0]; xor_32regs_p_5() 638 d0 ^= p3[0]; xor_32regs_p_5() 646 d0 ^= p4[0]; xor_32regs_p_5() 654 d0 ^= p5[0]; xor_32regs_p_5() 662 p1[0] = d0; /* Store the result (in bursts) */ xor_32regs_p_5()
/linux-4.4.14/arch/m68k/68000/
H A D	entry.S	51 movel #-ENOSYS,%d0 58 1: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 76 movel %sp@(PT_OFF_ORIG_D0),%d0 83 cmpl #NR_syscalls,%d0 85 lsl #2,%d0 87 movel %a0@(%d0), %a0 89 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ 132 movew %sp@(PT_OFF_FORMATVEC), %d0 133 and #0x3ff, %d0 143 movew %sp@(PT_OFF_FORMATVEC), %d0 144 and #0x3ff, %d0 154 movew %sp@(PT_OFF_FORMATVEC), %d0 155 and #0x3ff, %d0 165 movew %sp@(PT_OFF_FORMATVEC), %d0 166 and #0x3ff, %d0 176 movew %sp@(PT_OFF_FORMATVEC), %d0 177 and #0x3ff, %d0 187 movew %sp@(PT_OFF_FORMATVEC), %d0 188 and #0x3ff, %d0 198 movew %sp@(PT_OFF_FORMATVEC), %d0 199 and #0x3ff, %d0 209 movew %sp@(PT_OFF_FORMATVEC), %d0 210 and #0x3ff, %d0 213 movel %d0,%sp@- /* put vector # on stack*/
H A D	head.S	72 moveq #0, %d0 73 movew %d0, 0xfffff618 /* Watchdog off */ 100 moveq #0, %d0 101 movew #16384, %d0 /* PLL settle wait loop */ 103 subw #1, %d0 131 movel #0x007FFFFF, %d0 /* IMR */ 132 movel %d0, 0xfffff304 133 moveb 0xfffff42b, %d0 134 andb #0xe0, %d0 135 moveb %d0, 0xfffff42b 210 movel 8(%a0), %d0 /* get size of ROMFS */ 211 addql #8, %d0 /* allow for rounding */ 212 andl #0xfffffffc, %d0 /* whole words */ 214 addl %d0, %a0 /* copy from end */ 215 addl %d0, %a1 /* copy from end */
/linux-4.4.14/drivers/net/wan/
H A D	wanxlfw.S	199 movel OR1, %d0 200 andl #0xF00007FF, %d0 // mask AMxx bits 201 orl #0xFFFF800 & ~(MAX_RAM_SIZE - 1), %d0 // update RAM bank size 202 movel %d0, OR1 206 clrl %d0 // D0 = 4 * port 207 init_1: tstl ch_status_addr(%d0) 209 addl #VALUE_WINDOW, ch_status_addr(%d0) 210 init_2: addl #4, %d0 211 cmpl #4 * 4, %d0 260 main_1: clrl %d0 // D0 = 4 * port 283 addl #4, %d0 // D0 = 4 * next port 284 cmpl #4 * 4, %d0 293 movel ch_status_addr(%d0), %a0 // A0 = port status address 298 clrl tx_in(%d0) 299 clrl tx_out(%d0) 300 clrl tx_count(%d0) 301 clrl rx_in(%d0) 304 andl clocking_mask(%d0), %d1 307 orl clocking_txfromrx(%d0), %d1 311 orl clocking_ext(%d0), %d1 315 orw #STATUS_CABLE_DTR, csr_output(%d0) // DTR on 319 movel first_buffer(%d0), %d1 // D1 = starting buffer address 320 movel tx_first_bd(%d0), %a1 // A1 = starting TX BD address 348 movel scc_base_addr(%d0), %a1 // A1 = SCC_BASE address 349 movel scc_reg_addr(%d0), %a2 // A2 = SCC_REGS address 354 movel tx_first_bd(%d0), %d1 368 movew #2, parity_bytes(%d0) 378 movew #4, parity_bytes(%d0) 388 movew #2, parity_bytes(%d0) 398 movew #4, parity_bytes(%d0) 406 clrw parity_bytes(%d0) 419 movel %d0, %d1 435 movel scc_reg_addr(%d0), %a0 // A0 = SCC_REGS address 439 andw #~STATUS_CABLE_DTR, csr_output(%d0) // DTR off 442 movel ch_status_addr(%d0), %d1 450 cmpl #TX_BUFFERS, tx_count(%d0) 453 movel tx_out(%d0), %d1 456 addl ch_status_addr(%d0), %d2 464 addl tx_first_bd(%d0), %d1 // D1 = current tx_out BD addr 473 movel tx_out(%d0), %d1 478 tx_1: movel %d1, tx_out(%d0) 480 addl #1, tx_count(%d0) 489 rx: movel rx_in(%d0), %d1 // D1 = rx_in BD# 491 addl rx_first_bd(%d0), %d1 // D1 = current rx_in BD address 499 tstw parity_bytes(%d0) 508 subw parity_bytes(%d0), %d3 // D3 = packet length 526 movel packet_full(%d0), (%d2) // update desc stat 541 movel rx_in(%d0), %d1 546 rx_2: movel %d1, rx_in(%d0) 550 movel ch_status_addr(%d0), %d2 555 movel ch_status_addr(%d0), %d2 565 tx_end: tstl tx_count(%d0) 568 movel tx_in(%d0), %d1 571 addl tx_first_bd(%d0), %d1 // D1 = current tx_in BD address 577 orl bell_tx(%d0), %d6 // signal host that TX desc freed 578 subl #1, tx_count(%d0) 579 movel tx_in(%d0), %d1 585 movel %d1, tx_in(%d0) 589 addl ch_status_addr(%d0), %d2 608 movel %d0, -(%sp) 611 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly 612 btstl #4, %d0 // transfer done? 619 movel %d0, -(%sp) 622 movel PLX_DMA_CMD_STS, %d0 // do not btst PLX register directly 623 btstl #12, %d0 // transfer done? 631 movel (%sp)+, %d0 643 movel %d0, -(%sp) 645 movel PLX_DOORBELL_TO_CARD, %d0 646 movel %d0, PLX_DOORBELL_TO_CARD // confirm all requests 647 orl %d0, channel_stats 651 movel (%sp)+, %d0 687 movel %d0, -(%sp) 693 clrl %d0 // D0 = 4 * port 728 movew csr_output(%d0), %d2 734 cmpw old_csr_output(%d0), %d1 736 movew %d1, old_csr_output(%d0) 741 andw dcd_mask(%d0), %d1 752 movel ch_status_addr(%d0), %a1 756 movel bell_cable(%d0), PLX_DOORBELL_FROM_CARD // signal the host 760 addl #4, %d0 // D0 = 4 * next port 761 cmpl #4 * 4, %d0 768 movel (%sp)+, %d0 784 movel #128 * 1024, %d0 // D0 = RAM size tested 786 cmpl #MAX_RAM_SIZE, %d0 788 movel %d0, %a0 793 lsll #1, %d0 803 movel %d0, %a0 // A0 = fill ptr 804 subl #firmware_end + 4, %d0 805 lsrl #2, %d0 806 movel %d0, %d1 // D1 = DBf counter 816 dbnew %d0, ram_test_loop 818 subl #0x10000, %d0 819 cmpl #0xFFFFFFFF, %d0
/linux-4.4.14/arch/m68k/lib/
H A D	mulsi3.S	67 #define d0 REG (d0) define 89 movew sp@(4), d0 /* x0 -> d0 */ 90 muluw sp@(10), d0 /* x0*y1 */ 94 addw d1, d0 96 addl d1, d0 98 swap d0 99 clrw d0 102 addl d1, d0
H A D	udivsi3.S	67 #define d0 REG (d0) define 92 movel sp@(8), d0 /* d0 = dividend */ 96 movel d0, d2 100 movew d2, d0 /* save high quotient */ 101 swap d0 104 movew d2, d0 109 lsrl IMM (1), d0 /* shift dividend */ 112 divu d1, d0 /* now we have 16 bit divisor */ 113 andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */ 119 mulu d0, d1 /* low part, 32 bits */ 121 mulu d0, d2 /* high part, at most 17 bits */ 129 L5: subql IMM (1), d0 /* adjust quotient */ 140 movel a6@(8),d0 144 L1: addl d0,d0 | shift reg pair (p,a) one bit left 149 bset IMM (0),d0 | set the low order bit of a to 1,
H A D	modsi3.S	67 #define d0 REG (d0) define 90 movel sp@(4), d0 /* d0 = dividend */ 92 movel d0, sp@- 98 movel d0, sp@- 99 jbsr SYM (__mulsi3) /* d0 = (a/b)*b */ 102 mulsl d1,d0 105 subl d0, d1 /* d1 = a - (a/b)*b */ 106 movel d1, d0
H A D	umodsi3.S	67 #define d0 REG (d0) define 90 movel sp@(4), d0 /* d0 = dividend */ 92 movel d0, sp@- 98 movel d0, sp@- 99 jbsr SYM (__mulsi3) /* d0 = (a/b)*b */ 102 mulsl d1,d0 105 subl d0, d1 /* d1 = a - (a/b)*b */ 106 movel d1, d0
H A D	divsi3.S	67 #define d0 REG (d0) define 100 L1: movel sp@(8), d0 /* d0 = dividend */ 102 negl d0 110 movel d0, sp@- 116 negl d0
/linux-4.4.14/arch/nios2/kernel/
H A D	misaligned.c	70 u8 a, b, d0, d1, d2, d3; handle_unaligned_c() local 98 fault |= __get_user(d0, (u8 *)(addr+0)); handle_unaligned_c() 100 val = (d1 << 8) | d0; handle_unaligned_c() 106 d0 = val >> 0; handle_unaligned_c() 108 *(u8 *)(addr+0) = d0; handle_unaligned_c() 111 fault |= __put_user(d0, (u8 *)(addr+0)); handle_unaligned_c() 116 fault |= __get_user(d0, (u8 *)(addr+0)); handle_unaligned_c() 118 val = (short)((d1 << 8) | d0); handle_unaligned_c() 126 d0 = val >> 0; handle_unaligned_c() 128 *(u8 *)(addr+0) = d0; handle_unaligned_c() 133 fault |= __put_user(d0, (u8 *)(addr+0)); handle_unaligned_c() 140 fault |= __get_user(d0, (u8 *)(addr+0)); handle_unaligned_c() 144 val = (d3 << 24) | (d2 << 16) | (d1 << 8) | d0; handle_unaligned_c()
/linux-4.4.14/arch/unicore32/include/uapi/asm/
H A D	byteorder.h	14 * 0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31 16 * d0...d31
/linux-4.4.14/arch/frv/include/asm/
H A D	math-emu.h	160 lea (FPD_FPREG,FPDATA,%d0.w*4),%a0 161 lea (%a0,%d0.w*8),%a0 244 movem.l %d0/%d1/%a0/%a1,-(%sp) 247 moveq #\bit,%d0 248 andw #7,%d0 249 btst %d0,fp_debugprint+((31-\bit)/8) 260 movem.l (%sp)+,%d0/%d1/%a0/%a1 266 movem.l %d0/%a0,-(%sp) 269 moveq #'+',%d0 272 moveq #'-',%d0 273 .Lx1\@: printf \bit," %c",1,%d0 274 move.l (4,%a0),%d0 275 bclr #31,%d0 280 .Lx3\@: printf \bit,"%08x%08x",2,%d0,%a0@(8) 281 move.w (2,%a0),%d0 282 ext.l %d0 283 printf \bit,"E%04x",1,%d0 287 movem.l (%sp)+,%d0/%a0
/linux-4.4.14/include/uapi/linux/
H A D	uuid.h	35 #define UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ 40 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }}) 42 #define UUID_BE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \ 47 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }})
/linux-4.4.14/arch/x86/um/
H A D	delay.c	38 int d0; __const_udelay() local 42 : "=d" (xloops), "=&a" (d0) __const_udelay()
/linux-4.4.14/arch/mn10300/unit-asb2303/include/unit/
H A D	leds.h	34 mov 0x43,d0 ; \ 35 movbu d0,(ASB2303_7SEGLEDS)
/linux-4.4.14/drivers/media/tuners/
H A D	qt1010_priv.h	54 1a d0 set frequency: 125 kHz scale, n*125 kHz 62 22 d0 ? 63 23 d0 ? 64 24 d0 ?
/linux-4.4.14/arch/mn10300/include/asm/
H A D	syscall.h	30 regs->d0 = regs->orig_d0; syscall_rollback() 36 unsigned long error = regs->d0; syscall_get_error() 43 return regs->d0; syscall_get_return_value() 50 regs->d0 = (long) error ?: val; syscall_set_return_value()
H A D	elf.h	81 _ur->a1 = 0; _ur->a0 = 0; _ur->d1 = 0; _ur->d0 = 0; \ 126 pr_reg[23] = regs->d0; \
H A D	gdb-stub.h	80 u32 d0, d1, d2, d3, a0, a1, a2, a3; member in struct:gdb_regs
/linux-4.4.14/lib/mpi/
H A D	mpih-div.c	103 mpi_limb_t d1, d0; mpihelp_divrem() local 107 d0 = dp[0]; mpihelp_divrem() 111 if (n1 >= d1 && (n1 > d1 || n0 >= d0)) { mpihelp_divrem() 112 sub_ddmmss(n1, n0, n1, n0, d1, d0); mpihelp_divrem() 133 add_ssaaaa(n1, n0, r - d0, mpihelp_divrem() 134 np[0], 0, d0); mpihelp_divrem() 138 n1 = d0 - (d0 != 0 ? 1 : 0); mpihelp_divrem() 139 n0 = -d0; mpihelp_divrem() 142 umul_ppmm(n1, n0, d0, q); mpihelp_divrem() 150 sub_ddmmss(n1, n0, n1, n0, 0, d0); mpihelp_divrem()
/linux-4.4.14/drivers/block/
H A D	swim_asm.S	68 moveq #-1, %d0 144 moveq #0, %d0 148 moveq #-1, %d0 240 movel #sector_size, %d0 242 subl %d4, %d0 246 moveq #-1, %d0
/linux-4.4.14/drivers/video/fbdev/
H A D	atafb_utils.h	43 subl #65536,d0 replaced by clrw d0; subql #1,d0 for dbcc 225 "1: movem.l (%0)+,%%d0/%%d1/%%a0/%%a1\n" fast_memmove() 226 " movem.l %%d0/%%d1/%%a0/%%a1,%1@\n" fast_memmove() 233 : "d0", "d1", "a0", "a1", "memory"); fast_memmove() 237 " movem.l %0@,%%d0/%%d1/%%a0/%%a1\n" fast_memmove() 238 " movem.l %%d0/%%d1/%%a0/%%a1,-(%1)\n" fast_memmove() 244 : "d0", "d1", "a0", "a1", "memory"); fast_memmove()
H A D	amifb.c	1999 asm volatile ("moveql #0,%%d0 ; movew %%d0,%0@(%2:w:2) ; movew %%d0,%0@+" ami_set_var_cursorinfo() 2000 : "=a" (lspr) : "0" (lspr), "d" (delta) : "d0"); ami_set_var_cursorinfo() 2605 unsigned long d0, d1; bitcpy() local 2671 d0 = *src++; bitcpy() 2673 *dst = comp(d0 << left | d1 >> right, *dst, bitcpy() 2678 d0 = *src++; bitcpy() 2682 *dst = comp(d0 >> right, *dst, first); bitcpy() 2688 *dst = comp(d0 << left | d1 >> right, *dst, bitcpy() 2690 d0 = d1; bitcpy() 2700 *dst++ = d0 << left | d1 >> right; bitcpy() 2701 d0 = d1; bitcpy() 2703 *dst++ = d0 << left | d1 >> right; bitcpy() 2704 d0 = d1; bitcpy() 2706 *dst++ = d0 << left | d1 >> right; bitcpy() 2707 d0 = d1; bitcpy() 2709 *dst++ = d0 << left | d1 >> right; bitcpy() 2710 d0 = d1; bitcpy() 2715 *dst++ = d0 << left | d1 >> right; bitcpy() 2716 d0 = d1; bitcpy() 2723 *dst = comp(d0 << left, *dst, last); bitcpy() 2727 *dst = comp(d0 << left | d1 >> right, bitcpy() 2745 unsigned long d0, d1; bitcpy_rev() local 2822 d0 = *src--; bitcpy_rev() 2824 *dst = comp(d0 >> right | d1 << left, *dst, bitcpy_rev() 2829 d0 = *src--; bitcpy_rev() 2833 *dst = comp(d0 << left, *dst, first); bitcpy_rev() 2839 *dst = comp(d0 >> right | d1 << left, *dst, bitcpy_rev() 2841 d0 = d1; bitcpy_rev() 2851 *dst-- = d0 >> right | d1 << left; bitcpy_rev() 2852 d0 = d1; bitcpy_rev() 2854 *dst-- = d0 >> right | d1 << left; bitcpy_rev() 2855 d0 = d1; bitcpy_rev() 2857 *dst-- = d0 >> right | d1 << left; bitcpy_rev() 2858 d0 = d1; bitcpy_rev() 2860 *dst-- = d0 >> right | d1 << left; bitcpy_rev() 2861 d0 = d1; bitcpy_rev() 2866 *dst-- = d0 >> right | d1 << left; bitcpy_rev() 2867 d0 = d1; bitcpy_rev() 2874 *dst = comp(d0 >> right, *dst, last); bitcpy_rev() 2878 *dst = comp(d0 >> right | d1 << left, bitcpy_rev() 2897 unsigned long d0, d1; bitcpy_not() local 2963 d0 = ~*src++; bitcpy_not() 2965 *dst = comp(d0 << left | d1 >> right, *dst, bitcpy_not() 2970 d0 = ~*src++; bitcpy_not() 2974 *dst = comp(d0 >> right, *dst, first); bitcpy_not() 2980 *dst = comp(d0 << left | d1 >> right, *dst, bitcpy_not() 2982 d0 = d1; bitcpy_not() 2992 *dst++ = d0 << left | d1 >> right; bitcpy_not() 2993 d0 = d1; bitcpy_not() 2995 *dst++ = d0 << left | d1 >> right; bitcpy_not() 2996 d0 = d1; bitcpy_not() 2998 *dst++ = d0 << left | d1 >> right; bitcpy_not() 2999 d0 = d1; bitcpy_not() 3001 *dst++ = d0 << left | d1 >> right; bitcpy_not() 3002 d0 = d1; bitcpy_not() 3007 *dst++ = d0 << left | d1 >> right; bitcpy_not() 3008 d0 = d1; bitcpy_not() 3015 *dst = comp(d0 << left, *dst, last); bitcpy_not() 3019 *dst = comp(d0 << left | d1 >> right, bitcpy_not()
/linux-4.4.14/arch/x86/crypto/
H A D	poly1305-sse2-x86_64.S	45 #define d0 %r8 define 145 # d0 = t1[0] + t1[1] + t3[0] 152 movq t1,d0 216 # d1 += d0 >> 26 217 mov d0,%rax 220 # h0 = d0 & 0x3ffffff 221 mov d0,%rbx 299 #undef d0 300 #define d0 %r13 define 415 # d0 = t1[0] + t1[1] 419 movq t1,d0 521 # d1 += d0 >> 26 522 mov d0,%rax 525 # h0 = d0 & 0x3ffffff 526 mov d0,%rbx
H A D	poly1305-avx2-x86_64.S	78 #define d0 %r9 define 233 # d0 = t1[0] + t1[1] + t[2] + t[3] 238 vmovq t1x,d0 324 # d1 += d0 >> 26 325 mov d0,%rax 328 # h0 = d0 & 0x3ffffff 329 mov d0,%rbx
/linux-4.4.14/arch/x86/include/asm/
H A D	string_32.h	34 int d0, d1, d2; __memcpy() local 41 : "=&c" (d0), "=&D" (d1), "=&S" (d2) __memcpy() 209 int d0, d1; __memset_generic() local 212 : "=&c" (d0), "=&D" (d1) __memset_generic() 229 int d0, d1; __constant_c_memset() local 238 : "=&c" (d0), "=&D" (d1) __constant_c_memset() 281 : "=&c" (d0), "=&D" (d1) \ __constant_c_and_count_memset() 286 int d0, d1; __constant_c_and_count_memset() local
H A D	string_64.h	11 unsigned long d0, d1, d2; __inline_memcpy() local 20 : "=&c" (d0), "=&D" (d1), "=&S" (d2) __inline_memcpy()
/linux-4.4.14/arch/m68k/mm/
H A D	memory.c	232 asm volatile ("movec %/cacr,%/d0\n\t" cache_clear() 233 "oriw %0,%/d0\n\t" cache_clear() 234 "movec %/d0,%/cacr" cache_clear() 236 : "d0"); cache_clear() 287 asm volatile ("movec %/cacr,%/d0\n\t" cache_push() 288 "oriw %0,%/d0\n\t" cache_push() 289 "movec %/d0,%/cacr" cache_push() 291 : "d0"); cache_push()
/linux-4.4.14/arch/mn10300/unit-asb2305/include/unit/
H A D	leds.h	33 mov 0x43077f1d,d0 ; \ 34 mov d0,(ASB2305_7SEGLEDS)
/linux-4.4.14/arch/mn10300/unit-asb2364/include/unit/
H A D	leds.h	40 mov 0x43077f1d,d0 ; \ 41 mov d0,(ASB2364_7SEGLEDS)
/linux-4.4.14/arch/m68k/atari/
H A D	config.c	390 " moveq #0,%%d0\n" config_atari() 392 " movec %%d0,%%itt0\n" config_atari() 393 " movec %%d0,%%dtt0\n" config_atari() 397 : "d0"); config_atari() 537 " move.l %0,%%d0\n" atari_reset() 538 " and.l #0xff000000,%%d0\n" atari_reset() 539 " or.w #0xe020,%%d0\n" /* map 16 MB, enable, cacheable */ atari_reset() 541 " movec %%d0,%%itt0\n" atari_reset() 542 " movec %%d0,%%dtt0\n" atari_reset() 546 : "d0"); atari_reset() 549 " moveq #0,%%d0\n" atari_reset() 556 " movec %%d0,%%tc\n" atari_reset() 562 " move.l #0xffc000,%%d0\n" /* whole insn space cacheable */ atari_reset() 563 " movec %%d0,%%itt0\n" atari_reset() 564 " movec %%d0,%%itt1\n" atari_reset() 565 " or.w #0x40,%/d0\n" /* whole data space non-cacheable/ser. */ atari_reset() 566 " movec %%d0,%%dtt0\n" atari_reset() 567 " movec %%d0,%%dtt1\n" atari_reset() 572 : "d0"); atari_reset()
/linux-4.4.14/drivers/net/wireless/ath/wil6210/
H A D	txrx.h	285 u32 d0; member in struct:vring_tx_dma 294 /* TSO type used in dma descriptor d0 bits 11-12 */ 346 u32 d0; member in struct:vring_rx_mac 418 u32 d0; member in struct:vring_rx_dma 444 return WIL_GET_BITS(d->mac.d0, 0, 3); wil_rxdesc_tid() 449 return WIL_GET_BITS(d->mac.d0, 4, 6); wil_rxdesc_cid() 454 return WIL_GET_BITS(d->mac.d0, 8, 9); wil_rxdesc_mid() 459 return WIL_GET_BITS(d->mac.d0, 10, 11); wil_rxdesc_ftype() 464 return WIL_GET_BITS(d->mac.d0, 12, 15); wil_rxdesc_subtype() 470 return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2); wil_rxdesc_fc1() 475 return WIL_GET_BITS(d->mac.d0, 16, 27); wil_rxdesc_seq() 480 return WIL_GET_BITS(d->mac.d0, 28, 31); wil_rxdesc_ext_subtype() 500 return WIL_GET_BITS(d->dma.d0, 16, 29); wil_rxdesc_phy_length()
H A D	txrx.c	239 d->dma.d0 = RX_DMA_D0_CMD_DMA_RT | RX_DMA_D0_CMD_DMA_IT; wil_vring_alloc_skb() 1088 d->dma.d0 = (vring_index << DMA_CFG_DESC_TX_0_QID_POS); wil_tx_desc_map() 1121 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); wil_tx_desc_offload_setup_tso() 1123 d->dma.d0 |= (tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK); wil_tx_desc_offload_setup_tso() 1126 d->dma.d0 |= (BIT(DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS)) | wil_tx_desc_offload_setup_tso() 1128 d->dma.d0 |= (is_ipv4 << DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS); wil_tx_desc_offload_setup_tso() 1132 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); wil_tx_desc_offload_setup_tso() 1134 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); wil_tx_desc_offload_setup_tso() 1170 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS); wil_tx_desc_offload_setup() 1172 d->dma.d0 |= wil_tx_desc_offload_setup() 1177 d->dma.d0 |= wil_tx_desc_offload_setup() 1186 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS); wil_tx_desc_offload_setup() 1188 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS); wil_tx_desc_offload_setup() 1195 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS) | wil_tx_last_desc() 1202 d->dma.d0 |= wil_tso_type_lst << wil_set_tx_desc_last_tso() 1579 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS); __wil_tx_vring() 1580 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS); __wil_tx_vring() 1581 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS); __wil_tx_vring()
/linux-4.4.14/fs/cifs/
H A D	cifs_uniupr.h	40 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0d0-0df */ 56 -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, -79, 0, -1, /* 1d0-1df */ 157 32, 32, 32, 32, 32, 32, 32, 0, 32, 32, 32, 32, 32, 32, 32, 0, /* 0d0-0df */ 173 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0, /* 1d0-1df */
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A D	adc.h	30 unsigned d0, unsigned d1,
/linux-4.4.14/fs/jfs/
H A D	jfs_uniupr.c	39 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 0d0-0df */ 55 -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1, 0, -1,-79, 0, -1, /* 1d0-1df */
/linux-4.4.14/arch/mips/alchemy/devboards/
H A D	db1000.c	499 int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1; db1000_dev_setup() local 506 d0 = 0; /* GPIO number, NOT irq! */ db1000_dev_setup() 513 d0 = 0; /* GPIO number, NOT irq! */ db1000_dev_setup() 548 d0 = 0; /* GPIO number, NOT irq! */ db1000_dev_setup() 556 d0 = 1; /* GPIO number, NOT irq! */ db1000_dev_setup() 569 d0 = 9; /* GPIO number, NOT irq! */ db1000_dev_setup() 596 c0, d0, /*s0*/0, 0, 0); db1000_dev_setup()
/linux-4.4.14/arch/powerpc/crypto/
H A D	aes-tab-4k.S	86 .long R(bb, d0, d0, 6b), R(c5, ef, ef, 2a) 147 .long R(ae, 57, 57, f9), R(69, b9, b9, d0) 161 .long R(84, 42, 42, c6), R(d0, 68, 68, b8) 244 .long R(0d, 86, 52, ec), R(77, c1, e3, d0) 257 .long R(9f, 5d, 80, be), R(69, d0, 93, 7c) 270 .long R(e0, 90, d0, b0), R(33, a7, d8, 15) 296 .long R(48, 6c, 5c, 74), R(d0, b8, 57, 42)
H A D	aes-spe-modes.S	138 #define GF128_MUL(d0, d1, d2, d3, t0) \ 146 rlwimi d1,d0,0,0,0; \ 147 slwi d0,d0,1; /* shift left 128 bit */ \ 149 xor d0,d0,t0; 151 #define START_KEY(d0, d1, d2, d3) \ 157 xor rD0,d0,rW0; \
/linux-4.4.14/drivers/ipack/devices/
H A D	scc2698.h	26 u8 d0, mr; /* Mode register 1/2*/ member in struct:scc2698_channel::__anon5475 33 u8 d0, mr; /* Mode register 1/2 */ member in struct:scc2698_channel::__anon5476 51 u8 d0, mra; /* Mode register 1/2 (a) */ member in struct:scc2698_block::__anon5477 69 u8 d0, mra; /* Mode register 1/2 (a) */ member in struct:scc2698_block::__anon5478
/linux-4.4.14/crypto/
H A D	poly1305_generic.c	111 u64 d0, d1, d2, d3, d4; poly1305_blocks() local 147 d0 = mlt(h0, r0) + mlt(h1, s4) + mlt(h2, s3) + poly1305_blocks() 159 d1 += sr(d0, 26); h0 = and(d0, 0x3ffffff); poly1305_blocks()
/linux-4.4.14/arch/m68k/include/uapi/asm/
H A D	ptrace.h	38 long d0; member in struct:pt_regs
/linux-4.4.14/arch/mn10300/include/uapi/asm/
H A D	sigcontext.h	21 unsigned long d0; member in struct:sigcontext
H A D	ptrace.h	71 unsigned long d0; /* syscall ret */ member in struct:pt_regs
/linux-4.4.14/arch/h8300/include/asm/
H A D	switch_to.h	12 * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
/linux-4.4.14/arch/m68k/emu/
H A D	natfeat.c	32 "1: moveq.l #0,%d0\n"
H A D	nfeth.c	25 GET_VERSION = 0,/* no parameters, return NFAPI_VERSION in d0 */ 26 XIF_INTLEVEL, /* no parameters, return Interrupt Level in d0 */
/linux-4.4.14/arch/m68k/amiga/
H A D	config.c	538 " move.l %0,%%d0\n" amiga_reset() 539 " and.l #0xff000000,%%d0\n" amiga_reset() 540 " or.w #0xe020,%%d0\n" /* map 16 MB, enable, cacheable */ amiga_reset() 542 " movec %%d0,%%itt0\n" amiga_reset() 543 " movec %%d0,%%dtt0\n" amiga_reset() 548 : "d0"); amiga_reset() 563 " moveq #0,%%d0\n" amiga_reset() 565 " movec %%d0,%%tc\n" /* disable MMU */ amiga_reset() 569 : "d0"); amiga_reset()
/linux-4.4.14/drivers/parisc/
H A D	iosapic.c	621 u32 d0, d1; iosapic_mask_irq() local 624 iosapic_rd_irt_entry(vi, &d0, &d1); iosapic_mask_irq() 625 d0 |= IOSAPIC_IRDT_ENABLE; iosapic_mask_irq() 626 iosapic_wr_irt_entry(vi, d0, d1); iosapic_mask_irq() 633 u32 d0, d1; iosapic_unmask_irq() local 638 iosapic_set_irt_data(vi, &d0, &d1); iosapic_unmask_irq() 639 iosapic_wr_irt_entry(vi, d0, d1); iosapic_unmask_irq() 654 for (d0=0x10; d0<0x1e; d0++) { iosapic_unmask_irq() 655 d1 = iosapic_read(isp->addr, d0); iosapic_unmask_irq() 686 u32 d0, d1, dummy_d0; iosapic_set_affinity_irq() local 700 iosapic_rd_irt_entry(vi, &d0, &d1); iosapic_set_affinity_irq() 702 iosapic_wr_irt_entry(vi, d0, d1); iosapic_set_affinity_irq()
/linux-4.4.14/drivers/staging/lustre/lustre/obdclass/
H A D	cl_io.c	245 static int cl_lock_descr_sort(const struct cl_lock_descr *d0, cl_lock_descr_sort() argument 248 return lu_fid_cmp(cl_lock_descr_fid(d0), cl_lock_descr_fid(d1)) ?: cl_lock_descr_sort() 249 __diff_normalize(d0->cld_start, d1->cld_start); cl_lock_descr_sort() 252 static int cl_lock_descr_cmp(const struct cl_lock_descr *d0, cl_lock_descr_cmp() argument 257 ret = lu_fid_cmp(cl_lock_descr_fid(d0), cl_lock_descr_fid(d1)); cl_lock_descr_cmp() 260 if (d0->cld_end < d1->cld_start) cl_lock_descr_cmp() 262 if (d0->cld_start > d0->cld_end) cl_lock_descr_cmp() 267 static void cl_lock_descr_merge(struct cl_lock_descr *d0, cl_lock_descr_merge() argument 270 d0->cld_start = min(d0->cld_start, d1->cld_start); cl_lock_descr_merge() 271 d0->cld_end = max(d0->cld_end, d1->cld_end); cl_lock_descr_merge() 273 if (d1->cld_mode == CLM_WRITE && d0->cld_mode != CLM_WRITE) cl_lock_descr_merge() 274 d0->cld_mode = CLM_WRITE; cl_lock_descr_merge() 276 if (d1->cld_mode == CLM_GROUP && d0->cld_mode != CLM_GROUP) cl_lock_descr_merge() 277 d0->cld_mode = CLM_GROUP; cl_lock_descr_merge()
/linux-4.4.14/arch/x86/kernel/
H A D	process_32.c	72 unsigned long d0, d1, d2, d3, d6, d7; __show_regs() local 108 get_debugreg(d0, 0); __show_regs() 116 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && __show_regs() 121 d0, d1, d2, d3); __show_regs()
H A D	process_64.c	61 unsigned long d0, d1, d2, d3, d6, d7; __show_regs() local 105 get_debugreg(d0, 0); __show_regs() 113 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && __show_regs() 117 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", d0, d1, d2); __show_regs()
/linux-4.4.14/drivers/platform/x86/
H A D	samsung-laptop.c	59 u32 d0; member in struct:sabi_data::__anon8815::__anon8816 298 * d0, d1, d2, d3 - data fields 306 * echo 0x0582 > d0 413 command, in->d0, in->d1, in->d2, in->d3); sabi_command() 426 writel(in->d0, samsung->sabi_iface + SABI_IFACE_DATA); sabi_command() 455 out->d0 = readl(samsung->sabi_iface + SABI_IFACE_DATA); sabi_command() 463 out->d0, out->d1, out->d2, out->d3); sabi_command() 475 struct sabi_data in = { { { .d0 = 0, .d1 = 0, .d2 = 0, .d3 = 0 } } }; sabi_set_commandb() 1071 data.d0 = 0xaabb; kbd_backlight_enable() 1078 if (data.d0 != 0xccdd) kbd_backlight_enable() 1106 data.d0 = 0x82 | ((brightness & 0xFF) << 8); kbd_backlight_write() 1263 sdata->d0, sdata->d1, sdata->d2, sdata->d3); show_call() 1274 sdata->d0, sdata->d1, sdata->d2, sdata->d3); show_call() 1320 dent = debugfs_create_u32("d0", S_IRUGO | S_IWUSR, samsung->debug.root, samsung_debugfs_init() 1321 &samsung->debug.data.d0); samsung_debugfs_init()
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
H A D	ar9003_aic.c	116 (0x1f & 0x1f); /* -01 dB: 4'd1, 5'd31, 00 dB: 4'd0, 5'd31 */ ar9003_aic_gain_table() 122 (0x1e & 0x1f); /* -07 dB: 4'd1, 5'd30, -06 dB: 4'd0, 5'd30 */ ar9003_aic_gain_table() 128 (0xf & 0x1f); /* -13 dB: 4'd1, 5'd15, -12 dB: 4'd0, 5'd15 */ ar9003_aic_gain_table() 134 (0x7 & 0x1f); /* -19 dB: 4'd1, 5'd07, -18 dB: 4'd0, 5'd07 */ ar9003_aic_gain_table() 146 (0x1 & 0x1f); /* -31 dB: 4'd1, 5'd01, -30 dB: 4'd0, 5'd01 */ ar9003_aic_gain_table()
/linux-4.4.14/drivers/media/pci/mantis/
H A D	mantis_ioc.c	52 dprintk(MANTIS_ERROR, 1, "ERROR: i2c read: < err=%i d0=0x%02x d1=0x%02x >", read_eeprom_bytes()
H A D	mantis_core.c	50 "ERROR: i2c read: < err=%i d0=0x%02x d1=0x%02x >", read_eeprom_byte()
/linux-4.4.14/arch/x86/crypto/sha-mb/
H A D	sha1_x8_avx2.S	75 # r3 = {d7 d6 d5 d4 d3 d2 d1 d0} 82 # r0 = {h0 g0 f0 e0 d0 c0 b0 a0} 96 vshufps $0x44, \r3, \r2, \t1 # t1 = {d5 d4 c5 c4 d1 d0 c1 c0} 101 vshufps $0x88, \t1, \t0, \t0 # t0 = {d4 c4 b4 a4 d0 c0 b0 a0}
/linux-4.4.14/arch/arm/mach-sa1100/
H A D	cerf.c	51 .name = "cerf:d0",
/linux-4.4.14/drivers/input/keyboard/
H A D	hpps2atkbd.h	62 /* d0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, 97 /* d0 */ KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
/linux-4.4.14/arch/powerpc/lib/
H A D	memcpy_64.S	117 # s1<< in r8, d0=(s0<<|s1>>) in r7, s3 in r0, s2 in r9, nix in r6 & r12 135 # d0=(s0<<|s1>>) in r12, s1<< in r6, s2>> in r7, s2<< in r8, s3 in r9
/linux-4.4.14/arch/m68k/mac/
H A D	macints.c	323 printk("d0: %08lx d1: %08lx d2: %08lx d3: %08lx\n", mac_nmi_handler() 324 fp->d0, fp->d1, fp->d2, fp->d3); mac_nmi_handler()
/linux-4.4.14/tools/testing/selftests/powerpc/copyloops/
H A D	memcpy_64.S	117 # s1<< in r8, d0=(s0<<|s1>>) in r7, s3 in r0, s2 in r9, nix in r6 & r12 135 # d0=(s0<<|s1>>) in r12, s1<< in r6, s2>> in r7, s2<< in r8, s3 in r9
/linux-4.4.14/drivers/devfreq/event/
H A D	exynos-ppmu.c	87 PPMU_EVENT(d0-cpu), 88 PPMU_EVENT(d0-general), 89 PPMU_EVENT(d0-rt),
/linux-4.4.14/arch/arm/crypto/
H A D	aes-ce-core.S	338 veor d0, d0, d1 339 vst1.8 {d0}, [r0, :64]
/linux-4.4.14/drivers/media/platform/ti-vpe/
H A D	csc.c	25 * a0, b0, c0, a1, b1, c1, a2, b2, c2, d0, d1, d2
/linux-4.4.14/arch/mips/include/asm/txx9/
H A D	tx4927pcic.h	68 u32 unused7[12]; /* +1d0 */
/linux-4.4.14/arch/metag/lib/
H A D	checksum.c	23 * specify d0 and d1 as scratch registers. Letting gcc

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