Lines Matching refs:d0
67 #define d0 REG (d0) macro
92 movel sp@(8), d0 /* d0 = dividend */
96 movel d0, d2
100 movew d2, d0 /* save high quotient */
101 swap d0
104 movew d2, d0
109 lsrl IMM (1), d0 /* shift dividend */
112 divu d1, d0 /* now we have 16 bit divisor */
113 andl IMM (0xffff), d0 /* mask out divisor, ignore remainder */
119 mulu d0, d1 /* low part, 32 bits */
121 mulu d0, d2 /* high part, at most 17 bits */
129 L5: subql IMM (1), d0 /* adjust quotient */
140 movel a6@(8),d0
144 L1: addl d0,d0 | shift reg pair (p,a) one bit left
149 bset IMM (0),d0 | set the low order bit of a to 1,