Searched refs:coherent (Results 1 - 200 of 301) sorted by relevance

12

/linux-4.4.14/arch/c6x/mm/
H A DMakefile5 obj-y := init.o dma-coherent.o
H A Ddma-coherent.c28 * DMA coherent memory management, can be redefined using the memdma=
43 * Return a DMA coherent and contiguous memory chunk from the DMA memory
73 * Allocate DMA coherent memory space and return both the kernel
100 * Free DMA coherent memory as defined by the above mapping.
117 * Initialise the coherent DMA memory allocator using the given uncached region.
/linux-4.4.14/arch/mips/include/asm/mach-generic/
H A Dkmalloc.h8 * Set this one if any device in the system might do non-coherent DMA.
/linux-4.4.14/drivers/base/
H A DMakefile12 obj-$(CONFIG_HAVE_GENERIC_DMA_COHERENT) += dma-coherent.o
H A Ddma-mapping.c15 #include <asm-generic/dma-coherent.h>
54 * @dev: Device to allocate coherent memory for
93 * @dev: Device to free coherent memory for
179 * @dev: Device to declare coherent memory for
180 * @phys_addr: Physical address of coherent memory to be declared
181 * @device_addr: Device address of coherent memory to be declared
182 * @size: Size of coherent memory to be declared
213 * @dev: Device to release declared coherent memory for
244 * Create userspace mapping for the DMA-coherent memory.
334 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); dma_common_free_remap()
H A Ddma-coherent.c141 * dma_alloc_from_coherent() - try to allocate memory from the per-device coherent area
150 * to support allocation from per-device coherent memory pools.
201 * dma_release_from_coherent() - try to free the memory allocated from per-device coherent memory pool
207 * coherent memory pool and if so, releases that memory.
233 * per-device coherent memory pool to userspace
241 * coherent memory pool and if so, maps that memory to the provided vma.
/linux-4.4.14/drivers/cpuidle/
H A Dcpuidle-cps.c20 STATE_WAIT = 0, /* MIPS wait instruction, coherent */
21 STATE_NC_WAIT, /* MIPS wait instruction, non-coherent */
83 .desc = "non-coherent MIPS wait",
137 pr_cont("coherent wait\n"); cps_cpuidle_init()
140 pr_cont("non-coherent wait\n"); cps_cpuidle_init()
/linux-4.4.14/drivers/net/ethernet/mellanox/mlx4/
H A Dicm.c78 void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent) mlx4_free_icm() argument
86 if (coherent) mlx4_free_icm()
128 gfp_t gfp_mask, int coherent) mlx4_alloc_icm()
135 /* We use sg_set_buf for coherent allocs, which assumes low memory */ mlx4_alloc_icm()
136 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM)); mlx4_alloc_icm()
176 if (coherent) mlx4_alloc_icm()
194 if (coherent) mlx4_alloc_icm()
211 if (!coherent && chunk) { mlx4_alloc_icm()
223 mlx4_free_icm(dev, icm, coherent); mlx4_alloc_icm()
265 __GFP_NOWARN, table->coherent); mlx4_table_get()
273 mlx4_free_icm(dev, table->icm[i], table->coherent); mlx4_table_get()
299 mlx4_free_icm(dev, table->icm[i], table->coherent); mlx4_table_put()
407 table->coherent = use_coherent; mlx4_init_icm_table()
458 mlx4_free_icm(dev, table->icm[i], table->coherent); mlx4_cleanup_icm_table()
127 mlx4_alloc_icm(struct mlx4_dev *dev, int npages, gfp_t gfp_mask, int coherent) mlx4_alloc_icm() argument
H A Dicm.h71 gfp_t gfp_mask, int coherent);
72 void mlx4_free_icm(struct mlx4_dev *dev, struct mlx4_icm *icm, int coherent);
/linux-4.4.14/arch/tile/include/asm/
H A Dcache.h30 * TILEPro I/O is not always coherent (networking typically uses coherent
33 * TILE-Gx I/O is always coherent when used on hash-for-home pages.
54 * of initialization by making those pages read-only and non-coherent.
H A Ddma-mapping.h109 * dma_alloc_noncoherent() is #defined to return coherent memory,
H A Dcacheflush.h49 * broadcast to make the L1I coherent everywhere. This includes
/linux-4.4.14/arch/arc/mm/
H A Ddma.c12 * I/O is inherently non-coherent on ARC. So a coherent DMA buffer is
58 * IOC relies on all data (even coherent DMA data) being in cache dma_alloc_coherent()
65 * -For coherent data, Read/Write to buffers terminate early in cache dma_alloc_coherent()
H A Dcache.c595 * -In SMP, if hardware caches are coherent
634 * Make memory coherent with L1 cache by flushing/invalidating L1 lines
/linux-4.4.14/kernel/trace/
H A Dtrace_clock.c25 * trace_clock_local(): the simplest and least coherent tracing clock.
36 * lockless clock. It is not guaranteed to be coherent across trace_clock_local()
75 * trace_clock_global(): special globally coherent trace clock
80 * Used by plugins that need globally coherent timestamps.
/linux-4.4.14/arch/ia64/include/asm/
H A Dagp.h13 * in coherent mode, which lets us map the AGP memory as normal (write-back) memory
H A Ddma-mapping.h53 * IA-64 is cache-coherent, so this is mostly a no-op. However, we do need to dma_cache_sync()
H A Dtlb.h13 * (1) Flush (virtual) caches --- ensures virtual memory is coherent with kernel memory
H A Dpgtable.h316 * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
/linux-4.4.14/drivers/infiniband/hw/mthca/
H A Dmthca_memfree.c88 void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent) mthca_free_icm() argument
96 if (coherent) mthca_free_icm()
138 gfp_t gfp_mask, int coherent) mthca_alloc_icm()
145 /* We use sg_set_buf for coherent allocs, which assumes low memory */ mthca_alloc_icm()
146 BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM)); mthca_alloc_icm()
173 if (coherent) mthca_alloc_icm()
184 if (coherent) mthca_alloc_icm()
206 if (!coherent && chunk) { mthca_alloc_icm()
218 mthca_free_icm(dev, icm, coherent); mthca_alloc_icm()
236 __GFP_NOWARN, table->coherent); mthca_table_get()
244 mthca_free_icm(dev, table->icm[i], table->coherent); mthca_table_get()
271 mthca_free_icm(dev, table->icm[i], table->coherent); mthca_table_put()
379 table->coherent = use_coherent; mthca_alloc_icm_table()
397 mthca_free_icm(dev, table->icm[i], table->coherent); mthca_alloc_icm_table()
416 mthca_free_icm(dev, table->icm[i], table->coherent); mthca_alloc_icm_table()
433 mthca_free_icm(dev, table->icm[i], table->coherent); mthca_free_icm_table()
137 mthca_alloc_icm(struct mthca_dev *dev, int npages, gfp_t gfp_mask, int coherent) mthca_alloc_icm() argument
H A Dmthca_memfree.h69 int coherent; member in struct:mthca_icm_table
83 gfp_t gfp_mask, int coherent);
84 void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent);
/linux-4.4.14/arch/x86/include/asm/
H A Dagp.h8 * Functions to keep the agpgart mappings coherent with the MMU. The
H A Dcmpxchg_32.h21 * side to see the coherent 64bit value.
/linux-4.4.14/arch/xtensa/include/asm/
H A Ddma-mapping.h16 #include <asm-generic/dma-coherent.h>
/linux-4.4.14/arch/arc/include/uapi/asm/
H A Dsignal.h21 * -Cache line Flush (to make I/D Cache lines coherent)
/linux-4.4.14/include/linux/
H A Ddmapool.h4 * Allocation pools for DMAable (coherent) memory.
H A Darm-cci.h2 * CCI cache coherent interconnect support
H A Ddma-mapping.h112 * Set both the DMA mask and the coherent DMA mask to the same thing.
114 * as the DMA API guarantees that the coherent DMA mask can be set to
140 bool coherent) { }
205 /* flags for the coherent memory api */
138 arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, struct iommu_ops *iommu, bool coherent) arch_setup_dma_ops() argument
H A Ddma-iommu.h35 int dma_direction_to_prot(enum dma_data_direction dir, bool coherent);
H A Ddma-buf.h67 * mapping needs to be coherent - if the exporter doesn't directly
H A Dmmu_notifier.h47 * coherent with the other read and write operations happening
H A Diommu.h88 IOMMU_CAP_CACHE_COHERENCY, /* IOMMU can enforce cache coherent DMA
/linux-4.4.14/arch/mips/kernel/
H A Dpm-cps.c28 * cps_nc_entry_fn - type of a generated non-coherent state entry function
30 * @nc_ready_count: pointer to a non-coherent mapping of the core ready_count
32 * The code entering & exiting non-coherent states is generated at runtime
44 * The entry point of the generated non-coherent idle state entry/exit
54 * Indicates the number of coupled VPEs ready to operate in a non-coherent
163 /* Indicate that this CPU might not be coherent */ cps_pm_enter_state()
167 /* Create a non-coherent mapping of the core ready_count */ cps_pm_enter_state()
181 /* Remove the non-coherent mapping of ready_count */ cps_pm_enter_state()
184 /* Indicate that this CPU is definitely coherent */ cps_pm_enter_state()
188 * If this VPE is the first to leave the non-coherent wait state then cps_pm_enter_state()
602 /* The core is coherent, time to return to C code */ cps_gen_entry_code()
685 /* A CM is required for all non-coherent states */ cps_pm_init()
687 pr_warn("pm-cps: no CM, non-coherent states unavailable\n"); cps_pm_init()
693 * non-coherent core then the VPE may end up processing interrupts cps_pm_init()
694 * whilst non-coherent. That would be bad. cps_pm_init()
699 pr_warn("pm-cps: non-coherent wait unavailable\n"); cps_pm_init()
H A Dsmp-cps.c82 /* Set a coherent default CCA (CWB) */ cps_smp_setup()
91 /* Make core 0 coherent with everything */ cps_smp_setup()
114 /* The CCA is coherent, multi-core is fine */ cps_prepare_cpus()
119 /* CCA is not coherent, multi-core is not usable */ cps_prepare_cpus()
220 /* U6 == coherent execution, ie. the core is up */ boot_core()
429 * - A sibling VPE entering a non-coherent state. cps_cpu_die()
H A Dcps-vec.S176 /* Enter the coherent domain */
187 * We're up, cached & coherent. Perform any further required core-level
/linux-4.4.14/arch/sparc/include/asm/
H A Ddma-mapping.h16 /* Since dma_{alloc,free}_noncoherent() allocated coherent memory, this dma_cache_sync()
/linux-4.4.14/drivers/of/
H A Ddevice.c89 bool coherent; of_dma_configure() local
134 * Limit coherent and dma mask based on size and default mask of_dma_configure()
142 coherent = of_dma_is_coherent(np); of_dma_configure()
143 dev_dbg(dev, "device is%sdma coherent\n", of_dma_configure()
144 coherent ? " " : " not "); of_dma_configure()
150 arch_setup_dma_ops(dev, dma_addr, size, iommu, coherent); of_dma_configure()
H A Daddress.c1008 * of_dma_is_coherent - Check if device is coherent
1011 * It returns true if "dma-coherent" property was found
1019 if (of_property_read_bool(node, "dma-coherent")) { of_dma_is_coherent()
/linux-4.4.14/arch/arm64/mm/
H A Ddma-mapping.c33 bool coherent) __get_dma_pgprot()
35 if (!coherent || dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs)) __get_dma_pgprot()
58 WARN(1, "coherent pool not initialised!\n"); __alloc_from_pool()
144 bool coherent = is_device_dma_coherent(dev); __dma_alloc() local
149 if (!coherent && !gfpflags_allow_blocking(flags)) { __dma_alloc()
163 /* no need for non-cacheable mapping if coherent */ __dma_alloc()
164 if (coherent) __dma_alloc()
170 /* create a coherent mapping */ __dma_alloc()
417 pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n", atomic_pool_init()
545 bool coherent = is_device_dma_coherent(dev); __iommu_alloc_attrs() local
546 int ioprot = dma_direction_to_prot(DMA_BIDIRECTIONAL, coherent); __iommu_alloc_attrs()
563 pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL, coherent); __iommu_alloc_attrs()
581 if (coherent) { __iommu_alloc_attrs()
592 if (coherent) __iommu_alloc_attrs()
613 * allocations by non-coherent devices. __iommu_free_attrs()
615 * coherent devices. __iommu_free_attrs()
699 bool coherent = is_device_dma_coherent(dev); __iommu_map_page() local
700 int prot = dma_direction_to_prot(dir, coherent); __iommu_map_page()
752 bool coherent = is_device_dma_coherent(dev); __iommu_map_sg_attrs() local
758 dma_direction_to_prot(dir, coherent)); __iommu_map_sg_attrs()
988 struct iommu_ops *iommu, bool coherent) arch_setup_dma_ops()
993 dev->archdata.dma_coherent = coherent; arch_setup_dma_ops()
32 __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot, bool coherent) __get_dma_pgprot() argument
987 arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, struct iommu_ops *iommu, bool coherent) arch_setup_dma_ops() argument
H A Dcache.S32 * Ensure that the I and D caches are coherent within specified region.
45 * Ensure that the I and D caches are coherent within specified region.
/linux-4.4.14/arch/powerpc/mm/
H A Ddma-noncoherent.c14 * and provide non-coherent implementations for the DMA API. -Matt
151 * Allocate DMA-coherent memory space and return both the kernel remapped
170 dev_warn(dev, "coherent DMA mask is unset\n"); __dma_alloc_coherent()
175 dev_warn(dev, "coherent DMA mask %#llx is smaller " __dma_alloc_coherent()
187 printk(KERN_WARNING "coherent allocation too big (requested %#x mask %#Lx)\n", __dma_alloc_coherent()
271 printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", __dma_free_coherent()
308 printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", __dma_free_coherent()
H A Dpgtable_32.c193 /* Non-cacheable page cannot be coherent */ __ioremap_caller()
/linux-4.4.14/drivers/crypto/ccp/
H A Dccp-platform.c32 int coherent; member in struct:ccp_platform
128 ccp_platform->coherent = (attr == DEV_DMA_COHERENT); ccp_platform_probe()
129 if (ccp_platform->coherent) ccp_platform_probe()
/linux-4.4.14/arch/metag/kernel/
H A Ddma.c17 * and provide non-coherent implementations for the DMA API. -Matt
56 dev_warn(dev, "coherent DMA mask is unset\n"); get_coherent_dma_mask()
171 * Allocate DMA-coherent memory space and return both the kernel remapped
195 pr_warn("coherent allocation too big (requested %#x mask %#Lx)\n", dma_alloc_coherent()
288 pr_err("%s: freeing wrong coherent size (%ld != %d)\n", dma_free_coherent()
328 pr_err("%s: trying to free invalid coherent area: %p\n", dma_free_coherent()
H A Dsmp.c189 * For the local data cache to be coherent the threads must also have setup_smp_cache()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dmmu-40x.h51 #define TLB_M 0x00000002 /* Memory is coherent */
H A Dmmu-44x.h41 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
87 #define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */
H A Duninorth.h61 * Obviously, the GART is not cache coherent and so any change to it
63 * cachable). AGP memory itself doesn't seem to be cache coherent neither.
H A Ddma-mapping.h56 * Cache coherent cores.
H A Dcputable.h254 /* We need to mark all pages as being coherent if we're SMP or we have a
/linux-4.4.14/arch/mips/include/asm/
H A Dbcache.h14 /* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
H A Dpm-cps.h27 CPS_PM_NC_WAIT, /* MIPS wait instruction, non-coherent */
H A Dio.h569 * The caches on some architectures aren't dma-coherent and have need to
573 * - dma_cache_wback_inv(start, size) makes caches and coherent by
577 * - dma_cache_wback(start, size) makes caches and coherent by
H A Dpgtable-bits.h235 /* No penalty for being coherent on the SB1, so just
/linux-4.4.14/arch/sh/mm/
H A Dkmap.c27 /* cache the first coherent kmap pte */ kmap_coherent_init()
H A Dconsistent.c6 * Declared coherent memory functions based on arch/x86/kernel/pci-dma_32.c
/linux-4.4.14/arch/mips/alchemy/common/
H A Ddma.c128 { AU1100_SD0_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
129 { AU1100_SD0_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR }, /* coherent */
130 { AU1100_SD1_PHYS_ADDR + 0x00, DMA_DS | DMA_DW8 }, /* coherent */
131 { AU1100_SD1_PHYS_ADDR + 0x04, DMA_DS | DMA_DW8 | DMA_DR } /* coherent */
H A Dsetup.c59 /* Au1200 AB USB does not support coherent memory */ plat_mem_setup()
H A Dusb.c43 #define USBCFG_UCAM (1 << 7) /* coherent access (undoc) */
86 #define USB_SBUS_CTRL_SBCA 0x04 /* coherent access */
310 /* set coherent access bit */ au1300_usb_init()
/linux-4.4.14/arch/mn10300/mm/
H A Ddma-alloc.c50 /* map the coherent memory through the uncached memory window */ dma_alloc_coherent()
/linux-4.4.14/arch/arm/mach-mvebu/
H A Dcoherency.c138 * fabric, and therefore before they are coherent with armada_370_coherency_init()
199 * Add the PL310 property "arm,io-coherent". This makes sure the armada_375_380_coherency_init()
209 p->name = kstrdup("arm,io-coherent", GFP_KERNEL); armada_375_380_coherency_init()
261 pr_warn("Can't make current CPU cache coherent.\n"); set_cpu_coherent()
/linux-4.4.14/arch/mips/mm/
H A Ddma-default.c61 * Warning on the terminology - Linux calls an uncached area coherent;
63 * coherent.
66 * condition. However this function is only called on non-I/O-coherent
140 * XXX: seems like the coherent and non-coherent implementations could mips_dma_alloc_coherent()
H A Dc-r4k.c1493 /* don't need to worry about L2, fully coherent */ setup_scache()
1600 * coherent update on write will be used. Not all processors have coherency_setup()
1714 * We want to run CMP kernels on core with and without coherent r4k_cache_init()
/linux-4.4.14/arch/arm/include/asm/
H A Ddma-mapping.h128 struct iommu_ops *iommu, bool coherent);
206 * arm_dma_mmap - map a coherent DMA allocation into user space
214 * Map a coherent DMA buffer previously allocated by dma_alloc_coherent
215 * into user space. The coherent DMA buffer must not be freed by the
224 * coherent DMA pool above the default value of 256KiB. It must be called
H A Dmcpm.h197 * disabled only. The CPU is no longer cache coherent with the rest of the
204 * with their own cpu_cache_disable. The cluster is no longer cache coherent
H A Dcacheflush.h449 * - The CPU is obviously no longer coherent with the other CPUs.
510 * Ensure that the specified area of memory is coherent across the secure set_kernel_text_ro()
H A Dpgtable-2level.h127 #define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
/linux-4.4.14/drivers/parisc/
H A Dccio-rm-dma.c3 * DMA management routines for first generation cache-coherent machines.
15 * (PCX-U/U+ are not coherent with U2 in real mode.)
H A Dccio-dma.c3 ** DMA management routines for first generation cache-coherent machines.
502 ** do special things to work on non-coherent platforms...linux has to
561 register unsigned long ci; /* coherent index */ ccio_io_pdir_entry()
609 ** See PDC_MODEL/option 0/SW_CAP word for "Non-coherent IO-PDIR bit". ccio_io_pdir_entry()
682 ** See PDC_MODEL/option 0/SW_CAP for "Non-coherent IO-PDIR bit". ccio_mark_invalid()
937 ** w/o this association, we wouldn't have coherent DMA! ccio_map_sg()
H A Dsba_iommu.c571 register unsigned ci; /* coherent index */ sba_io_pdir_entry()
584 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set sba_io_pdir_entry()
853 ** are *not* coherent in all cases. May be hwrev dependent. sba_unmap_single()
973 ** w/o this association, we wouldn't have coherent DMA! sba_map_sg()
1755 * If the PDC_MODEL capabilities has Non-coherent IO-PDIR bit set sba_common_init()
1762 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n"); sba_common_init()
/linux-4.4.14/arch/xtensa/kernel/
H A Dpci-dma.c2 * DMA coherent memory allocation.
161 /* We currently don't support coherent memory outside KSEG */ xtensa_dma_alloc()
/linux-4.4.14/arch/metag/tbx/
H A Dtbictxfpu.S61 /* Save the relevant bits of TXDEFR (Assumes TXDEFR is coherent) ... */
141 /* Restore FPU related parts of TXDEFR. Assumes TXDEFR is coherent */
/linux-4.4.14/arch/hexagon/kernel/
H A Ddma.c60 * mm/init.c to create DMA coherent space. Use that as the VA hexagon_dma_alloc_coherent()
168 * DMA is not cache coherent so sync is necessary; this
/linux-4.4.14/arch/arm/xen/
H A Dmm.c151 * - The device doesn't support coherent DMA request xen_arch_need_swiotlb()
159 * require a bounce buffer because the device doesn't support coherent xen_arch_need_swiotlb()
/linux-4.4.14/arch/unicore32/mm/
H A Dflush.c66 * coherent with the kernels mapping. __flush_dcache_page()
H A Dcache-ucv2.S86 * Ensure that the I and D caches are coherent within specified
/linux-4.4.14/include/asm-generic/
H A Ddma-mapping-common.h9 #include <asm-generic/dma-coherent.h>
198 * dma_mmap_attrs - map a coherent DMA allocation into user space
206 * Map a coherent DMA buffer previously allocated by dma_alloc_attrs
207 * into user space. The coherent DMA buffer must not be freed by the
/linux-4.4.14/arch/parisc/include/asm/
H A Dldcw.h25 long as the ",CO" (coherent operation) completer is specified, then the
H A Dpdc.h51 cc_cst : 3, /* 0 = incoherent D-cache, 1=coherent D-cache */
64 tc_cst : 3, /* 0 = incoherent operations, else coherent operations */
H A Ddma-mapping.h26 ** to support 4 different coherent dma models with one binary (they will
H A Dpci.h136 ** are I/O coherent, it generally doesn't matter...but sometimes
/linux-4.4.14/arch/arm64/include/asm/
H A Ddma-mapping.h51 struct iommu_ops *iommu, bool coherent);
/linux-4.4.14/drivers/iommu/
H A Ddma-iommu.c134 * @coherent: Is the DMA master cache-coherent?
138 int dma_direction_to_prot(enum dma_data_direction dir, bool coherent) dma_direction_to_prot() argument
140 int prot = coherent ? IOMMU_CACHE : 0; dma_direction_to_prot()
273 * given VA/PA are visible to the given non-coherent device.
H A Darm-smmu-v3.c2471 bool coherent; arm_smmu_device_probe() local
2524 * The dma-coherent property is used in preference to the ID arm_smmu_device_probe()
2527 coherent = of_dma_is_coherent(smmu->dev->of_node); arm_smmu_device_probe()
2528 if (coherent) arm_smmu_device_probe()
2531 if (!!(reg & IDR0_COHACC) != coherent) arm_smmu_device_probe()
2532 dev_warn(smmu->dev, "IDR0.COHACC overridden by dma-coherent property (%s)\n", arm_smmu_device_probe()
2533 coherent ? "true" : "false"); arm_smmu_device_probe()
H A Dipmmu-vmsa.c317 * TODO: Add support for coherent walk through CCI with DVM and remove ipmmu_domain_init_context()
H A Darm-smmu.c1274 * Return true here as the SMMU can always send out coherent arm_smmu_capable()
1586 "\t(IDR0.CTTW overridden by dma-coherent property)\n"); arm_smmu_device_cfg_probe()
/linux-4.4.14/arch/arm/mm/
H A Ddma-mapping.c217 dev_warn(dev, "coherent DMA mask is unset\n"); get_coherent_dma_mask()
341 * Set architecture specific coherent pool size only if init_dma_coherent_pool_size()
349 * Initialise the coherent pool for atomic allocations.
380 pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n", atomic_pool_init()
389 pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n", atomic_pool_init()
501 WARN(1, "coherent pool not initialised!\n"); __alloc_from_pool()
627 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", __dma_alloc()
672 * Allocate DMA-coherent memory space and return both the kernel remapped
717 * Create userspace mapping for the DMA-coherent memory.
1453 WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); arm_iommu_free_attrs()
1601 * Map a set of i/o coherent buffers described by scatterlist in streaming
2070 static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) arm_get_iommu_dma_map_ops() argument
2072 return coherent ? &iommu_coherent_ops : &iommu_ops; arm_get_iommu_dma_map_ops()
2125 static struct dma_map_ops *arm_get_dma_map_ops(bool coherent) arm_get_dma_map_ops() argument
2127 return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; arm_get_dma_map_ops()
2131 struct iommu_ops *iommu, bool coherent) arch_setup_dma_ops()
2135 dev->archdata.dma_coherent = coherent; arch_setup_dma_ops()
2137 dma_ops = arm_get_iommu_dma_map_ops(coherent); arch_setup_dma_ops()
2139 dma_ops = arm_get_dma_map_ops(coherent); arch_setup_dma_ops()
2130 arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, struct iommu_ops *iommu, bool coherent) arch_setup_dma_ops() argument
H A Dcache-v6.S106 * Ensure that the I and D caches are coherent within specified
122 * Ensure that the I and D caches are coherent within specified
H A Dflush.c207 * coherent with the kernels mapping. __flush_dcache_page()
305 * - VIPT non-aliasing cache: fully coherent so nothing required.
H A Dcache-v7.S245 * Ensure that the I and D caches are coherent within specified
261 * Ensure that the I and D caches are coherent within specified
H A Dproc-xsc3.S404 orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit
H A Dcache-l2x0.c1276 * coherent, and potentially harmful in certain situations (PCIe/PL310
1724 of_property_read_bool(np, "arm,io-coherent")) l2x0_of_init()
/linux-4.4.14/arch/mips/include/asm/mach-au1x00/
H A Dau1xxx_dbdma.h72 #define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */
118 #define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
119 #define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
/linux-4.4.14/arch/mips/netlogic/common/
H A Dreset.S177 beq t0, t1, 2f /* does not need to set coherent */
181 beq t0, t1, 2f /* does not need to set coherent */
184 /* set bit in SYS coherent register for the core */
/linux-4.4.14/drivers/tty/serial/cpm_uart/
H A Dcpm_uart_cpm1.c108 "cpm_uart_cpm1.c: could not allocate coherent memory\n"); cpm_uart_allocbuf()
H A Dcpm_uart_cpm2.c143 "cpm_uart_cpm.c: could not allocate coherent memory\n"); cpm_uart_allocbuf()
/linux-4.4.14/drivers/usb/core/
H A Dbuffer.c53 * memory allocators. It initializes some pools of dma-coherent memory that
/linux-4.4.14/drivers/char/xillybus/
H A Dxillybus_of.c138 if (of_property_read_bool(dev->of_node, "dma-coherent")) xilly_drv_probe()
/linux-4.4.14/arch/c6x/include/asm/
H A Ddma-mapping.h16 #include <asm-generic/dma-coherent.h>
/linux-4.4.14/include/drm/ttm/
H A Dttm_placement.h62 * TTM_PL_FLAG_CACHED indicates cache-coherent mappings
/linux-4.4.14/arch/m68k/include/asm/
H A Ddma-mapping.h52 /* we use coherent allocation, so not much to do here. */ dma_cache_sync()
/linux-4.4.14/arch/metag/include/asm/
H A Dpgtable-bits.h21 /* Sys coherent bit - this bit is never used by Linux */
H A Dcacheflush.h105 * make the i-cache coherent, we should use the PG_arch_1 bit like flush_dcache_page()
/linux-4.4.14/arch/cris/include/asm/
H A Ddma-mapping.h17 #include <asm-generic/dma-coherent.h>
/linux-4.4.14/arch/ia64/sn/pci/
H A Dpci_dma.c64 * sn_dma_alloc_coherent - allocate memory for coherent DMA
71 * coherent DMA traffic to/from a PCI device. On SN platforms, this means
131 * sn_pci_free_coherent - free memory associated with coherent DMAable region
217 * coherent, so we just need to free any ATEs associated with this mapping.
H A Dtioca_provider.c277 * 63:60 - Coretalk Packet Type - 0x1 for Mem Get/Put (coherent)
278 * 0x2 for PIO (non-coherent)
/linux-4.4.14/sound/parisc/
H A Dharmony.h13 int coherent; member in struct:harmony_buffer
/linux-4.4.14/drivers/net/ethernet/aurora/
H A Dnb8800.h183 * Allocated from coherent memory.
200 * Allocated from coherent memory.
/linux-4.4.14/arch/xtensa/mm/
H A Dcache.c46 * The Xtensa architecture doesn't keep the instruction cache coherent with
48 * are coherent. The kernel clears this bit whenever a page is added to the
/linux-4.4.14/sound/core/
H A Dmemalloc.c82 /* allocate the coherent DMA pages */ snd_malloc_dev_pages()
98 /* free the coherent DMA pages */ snd_free_dev_pages()
/linux-4.4.14/arch/powerpc/kernel/
H A Ddma.c139 /* The coherent mask may be smaller than the real mask, check if dma_direct_alloc_coherent()
294 * support a fallback for coherent allocations. There dma_set_coherent_mask()
H A Dfsl_booke_entry_mapping.S156 * The mapping only needs to be cache-coherent on SMP, except on
157 * Freescale e500mc derivatives where it's also needed for coherent DMA.
H A Dvdso.c94 * with a coherent icache
/linux-4.4.14/arch/mips/netlogic/xlp/
H A Dwakeup.c67 /* On 9XX, mark coherent first */ xlp_wakeup_core()
84 /* Poll for CPU to mark itself coherent on other type of XLP */ xlp_wakeup_core()
/linux-4.4.14/drivers/net/wireless/ath/ath10k/
H A Dswap.c121 ath10k_err(ar, "failed to allocate dma coherent memory\n"); ath10k_swap_code_seg_alloc()
H A Dce.h87 /* Start of DMA-coherent area reserved for descriptors */
96 * Points into reserved DMA-coherent area, above.
H A Dce.c903 * coherent DMA are unsupported ath10k_ce_alloc_src_ring()
949 * coherent DMA are unsupported ath10k_ce_alloc_dest_ring()
/linux-4.4.14/arch/sparc/mm/
H A Dswift.S173 * I/O nor TLB-walk coherent. Also it has
H A Diommu.c118 /* To be coherent on HyperSparc, the page color of DVMA sbus_iommu_init()
375 * completely not I/O DMA coherent, and some have iommu_map_dma_area()
H A Dhypersparc.S256 /* HyperSparc is IO cache coherent. */
/linux-4.4.14/arch/arc/include/asm/
H A Ddma-mapping.h14 #include <asm-generic/dma-coherent.h>
/linux-4.4.14/arch/sparc/kernel/
H A Dmodule.c215 /* Cheetah's I-cache is fully coherent. */ module_finalize()
H A Dioport.c55 /* This function must make sure that caches and memory are coherent after DMA
/linux-4.4.14/arch/microblaze/include/asm/
H A Dmmu.h121 # define TLB_M 0x00000002 /* Memory is coherent */
/linux-4.4.14/arch/powerpc/boot/
H A Doflib.c173 /* 0x12 == coherent + read/write */ of_claim()
/linux-4.4.14/arch/arm/mach-highbank/
H A Dhighbank.c110 if (of_property_read_bool(dev->of_node, "dma-coherent")) { highbank_platform_notifier()
/linux-4.4.14/arch/tile/mm/
H A Dhomecache.c273 * non-coherent PTE, but the underlying page is not pte_set_home()
277 * just keep the PTE coherent. pte_set_home()
/linux-4.4.14/arch/c6x/kernel/
H A Dsetup.c393 * Disable caching for dma coherent memory taken from kernel memory.
399 /* Initialize the coherent memory allocator */
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_ringbuffer.h187 /* Some chipsets are not quite as coherent as advertised and need
191 * monotonic, even if not coherent.
H A Di915_gem.c331 * remains coherent i.e. in the GTT domain, like shmem_pwrite. i915_gem_phys_pwrite()
3192 * a coherent view of memory, we must:
3574 * Stolen memory is always coherent with the GPU as it is explicitly i915_gem_clflush_object()
3575 * marked as wc by the system, or the system is cache-coherent. i915_gem_clflush_object()
3671 /* Flush and acquire obj->pages so that we are coherent through i915_gem_object_set_to_gtt_domain()
3686 * coherent writes from the GPU, by effectively invalidating the i915_gem_object_set_to_gtt_domain()
3723 * across all GTT and the contents of the backing storage will be coherent,
3725 * coherent for all users, we only allow a single cache level to be set
3730 * that all direct access to the scanout remains coherent.
3804 * coherent. In such cases, existing GTT mmaps i915_gem_object_set_cache_level()
3827 * object is now coherent at its new cache level (with respect i915_gem_object_set_cache_level()
3948 /* The display engine is not coherent with the LLC cache on gen6. As i915_gem_object_pin_to_display_plane()
4433 * display scanout are coherent with the CPU in i915_gem_alloc_object()
H A Di915_gem_gtt.h340 * portion of the GTT which can be mapped by the CPU and remain both coherent
/linux-4.4.14/arch/mips/pci/
H A Dpci-alchemy.c430 /* Au1500 revisions older than AD have borked coherent PCI */ alchemy_pci_probe()
437 dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); alchemy_pci_probe()
/linux-4.4.14/drivers/usb/host/
H A Dohci-sm501.c131 dev_err(dev, "cannot declare coherent memory\n"); ohci_hcd_sm501_drv_probe()
H A Dehci-fsl.c271 * wholly rely on hardware to deal with cache coherent ehci_fsl_usb_setup()
/linux-4.4.14/drivers/staging/android/uapi/
H A Dion.h191 * this will make the buffer in memory coherent.
/linux-4.4.14/drivers/net/ethernet/mellanox/mlx5/core/
H A Den_rx.c223 /* avoid accessing cq (dma coherent memory) if not needed */ mlx5e_poll_rx_cq()
H A Den_tx.c324 /* avoid accessing cq (dma coherent memory) if not needed */ mlx5e_poll_tx_cq()
/linux-4.4.14/drivers/dma/ppc4xx/
H A Dadma.h169 #define PPC440SPE_COHERENT 3 /* src/dst are coherent */
/linux-4.4.14/arch/alpha/include/asm/
H A Dmmu_context.h55 * made coherent by assigning a new, unused ASN to the currently
/linux-4.4.14/include/uapi/drm/
H A Di915_drm.h751 * coherent with the CS before execution. If this flag is passed,
820 * GPU access is not coherent with cpu caches. Default for machines without an
827 * GPU access is coherent with cpu caches and furthermore the data is cached in
835 * Special GPU caching mode which is coherent with the scanout engines.
/linux-4.4.14/arch/mips/include/asm/netlogic/xlp-hal/
H A Diomap.h57 /* coherent inter chip */
/linux-4.4.14/arch/mips/include/asm/netlogic/xlr/
H A Dfmn.h285 * caches are coherent with IO, so no cache flush needed. nlm_fmn_send()
/linux-4.4.14/arch/metag/mm/
H A Dinit.c103 * code through the data cache and they may not be coherent. At user_gateway_init()
H A Dcache.c54 * It's conceivable the user has configured a globally coherent cache metag_lnkget_probe()
/linux-4.4.14/arch/microblaze/mm/
H A Dconsistent.c105 pr_warn("ERROR: Your cache coherent area is CACHED!!!\n"); consistent_alloc()
/linux-4.4.14/arch/mips/ath79/
H A Dirq.c225 * these devices typically allocate coherent DMA memory, however the
/linux-4.4.14/arch/nios2/mm/
H A Dcacheflush.c165 * coherent with the kernels mapping. __flush_dcache_page()
/linux-4.4.14/arch/openrisc/kernel/
H A Ddma.c68 * Alloc "coherent" memory, which for OpenRISC means simply uncached.
/linux-4.4.14/drivers/staging/rdma/ipath/
H A Dipath_user_sdma.c65 struct page *page; /* may be NULL (coherent mem) */
268 /* free coherent mem from cache... */ ipath_user_sdma_free_pkt_frag()
/linux-4.4.14/drivers/gpu/drm/msm/
H A Dmsm_gem.c101 * because display controller, GPU, etc. are not coherent: get_pages()
117 * because display controller, GPU, etc. are not coherent: put_pages()
/linux-4.4.14/arch/x86/kernel/
H A Damd_gart_64.c477 /* allocate and map a coherent mapping */
509 /* free a coherent mapping */
/linux-4.4.14/arch/ia64/mm/
H A Dinit.c62 return; /* i-cache is already coherent with d-cache */ __ia64_sync_icache_dcache()
69 * Since DMA is i-cache coherent, any (complete) pages that were written via
/linux-4.4.14/arch/mips/include/asm/octeon/
H A Dcvmx-fpa.h60 /* the ID of the device on the non-coherent bus */
H A Docteon.h240 * the coherent bus in order. */
H A Dcvmx-pko.h137 /* The ID of the device on the non-coherent bus */
/linux-4.4.14/arch/sh/drivers/pci/
H A Dpci-sh7780.c339 * Disable the cache snoop controller for non-coherent DMA. sh7780_pci_init()
/linux-4.4.14/arch/arm/mach-omap2/
H A Domap4-common.c76 * accesses) are properly synchronised with writes to DMA coherent memory
H A Dsleep44xx.S203 * In non-coherent mode CPU can lock-up and lead to
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Datombios_encoders.c946 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ amdgpu_atombios_encoder_setup_dig_transmitter()
1008 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ amdgpu_atombios_encoder_setup_dig_transmitter()
1061 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ amdgpu_atombios_encoder_setup_dig_transmitter()
2058 /* coherent mode by default */ amdgpu_atombios_encoder_get_dig_info()
/linux-4.4.14/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_drv.c242 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
527 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", vmw_dma_select_mode()
567 * No coherent page pool vmw_dma_select_mode()
H A Dvmwgfx_cmdbuf.c72 * able to make a contigous coherent DMA memory allocation, @handle. Immutable.
75 * a contigous coherent DMA memory allocation. Immutable.
H A Dvmwgfx_drv.h232 vmw_dma_alloc_coherent, /* Use TTM coherent pages */
260 * @addrs: DMA addresses to the pages if coherent pages are used.
/linux-4.4.14/drivers/staging/most/mostcore/
H A Dcore.c171 * most_free_mbo_coherent - free an MBO and its coherent buffer
1262 * This allocates buffer objects including the containing DMA coherent
1294 pr_info("WARN: No DMA coherent buffer.\n"); arm_mbo_chain()
/linux-4.4.14/drivers/staging/comedi/
H A Dcomedidev.h223 * @dma_addr: DMA address of page if in DMA coherent memory.
237 * @dma_dir: DMA direction used to allocate pages of DMA coherent memory,
242 * conventional memory or DMA coherent memory, depending on the attached,
/linux-4.4.14/drivers/gpu/drm/nouveau/
H A Dnouveau_bo.c446 * TTM buffers allocated using the DMA API already had a coherent nouveau_bo_unmap()
464 /* Don't waste time looping if the object is coherent */ nouveau_bo_sync_for_device()
484 /* Don't waste time looping if the object is coherent */ nouveau_bo_sync_for_cpu()
/linux-4.4.14/drivers/crypto/
H A Dgeode-aes.c80 * we need to turn on the coherent flags, otherwise geode_aes_crypt()
H A Dmxs-dcp.c947 /* Allocate coherent helper block. */ mxs_dcp_probe()
/linux-4.4.14/arch/tile/kernel/
H A Dpci-dma.c26 * Allocate what Linux calls "coherent" memory. On TILEPro this is
/linux-4.4.14/arch/sh/include/asm/
H A Dpgtable_64.h91 * PTEL coherent flags.
/linux-4.4.14/arch/openrisc/include/asm/
H A Dpgtable.h119 * CC : Cache coherent
/linux-4.4.14/arch/parisc/kernel/
H A Dcache.c309 * to flush one address here for them all to become coherent */ flush_dcache_page()
/linux-4.4.14/arch/arm/mach-vexpress/
H A Dspc.c482 * Multi-cluster systems may need this data when non-coherent, during ve_spc_init()
/linux-4.4.14/arch/arm/common/
H A Ddmabounce.c295 * we need to ensure that the data will be coherent unmap_single()
/linux-4.4.14/sound/soc/codecs/
H A Dsti-sas.c358 * get MCLK input frequency to check that MCLK-FS ratio is coherent
/linux-4.4.14/drivers/net/ethernet/aeroflex/
H A Dgreth.c1467 /* Allocate TX descriptor ring in coherent memory */ greth_of_probe()
1476 /* Allocate RX descriptor ring in coherent memory */ greth_of_probe()
/linux-4.4.14/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-main.c618 pdata->coherent = (attr == DEV_DMA_COHERENT); xgbe_probe()
619 if (pdata->coherent) { xgbe_probe()
/linux-4.4.14/mm/
H A Dtruncate.c665 * blocks). This way, pagecache will always stay logically coherent
773 * blocks). This way, pagecache will always stay logically coherent
/linux-4.4.14/include/acpi/
H A Dactbl2.h712 #define ACPI_IORT_NODE_COHERENT 0x00000001 /* The device node is fully coherent */
713 #define ACPI_IORT_NODE_NOT_COHERENT 0x00000000 /* The device node is not coherent */
/linux-4.4.14/arch/arm/plat-omap/
H A Ddma.c851 * is no guarantee that data in coherent DMA memory will be visible omap_start_dma()
905 * after DMA has been disabled. This is important for coherent omap_stop_dma()
/linux-4.4.14/drivers/scsi/aic7xxx/
H A Daic79xx_osm.h206 * not have an API to sync "coherent" memory. Perhaps we need
H A Daic7xxx_osm.h219 * not have an API to sync "coherent" memory. Perhaps we need
/linux-4.4.14/drivers/misc/sgi-gru/
H A Dgrutables.h37 * The entire GRU memory space is fully coherent and cacheable by the cpus.
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Datombios_encoders.c1235 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */ atombios_dig_transmitter_setup2()
1297 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */ atombios_dig_transmitter_setup2()
1350 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */ atombios_dig_transmitter_setup2()
2705 /* coherent mode by default */ radeon_atombios_set_dig_info()
/linux-4.4.14/drivers/net/irda/
H A Dau1k_ir.c224 However, the Au1000 data cache is coherent (when programmed
/linux-4.4.14/drivers/dma/
H A Dcppi41.c417 * that the DMA descriptor in coherent memory made to the main memory cppi41_dma_issue_pending()
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Dpsb_drv.h108 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
/linux-4.4.14/arch/sparc/net/
H A Dbpf_jit_comp.c23 /* Cheetah's I-cache is fully coherent. */ bpf_flush_icache()
/linux-4.4.14/drivers/char/agp/
H A Damd64-agp.c118 * keep the rest coherent anyway. Or at least should do.
/linux-4.4.14/fs/quota/
H A Dquota.c696 /* XFS quotas are fully coherent now, making this call a noop */ do_quotactl()
/linux-4.4.14/arch/powerpc/kvm/
H A De500_mmu_host.c684 * The real address will be mapped by a cacheable, memory coherent, kvmppc_load_last_inst()
/linux-4.4.14/arch/mips/include/asm/pci/
H A Dbridge.h812 u64 coherent:1; member in struct:ate_u::ate_s
/linux-4.4.14/arch/mips/lib/
H A Dmemcpy.S23 * dma-coherent systems.
/linux-4.4.14/drivers/xen/
H A Dswiotlb-xen.c47 #include <asm/xen/page-coherent.h>
/linux-4.4.14/drivers/usb/musb/
H A Dcppi_dma.c659 /* BDs live in DMA-coherent memory, but writes might be pending */ cppi_next_tx_segment()
898 /* BDs live in DMA-coherent memory, but writes might be pending */ cppi_next_rx_segment()
/linux-4.4.14/drivers/staging/wilc1000/
H A Dwilc_wlan.c1412 /* Allocate a DMA coherent buffer. */ wilc_wlan_firmware_download()
1441 /* Copy firmware into a DMA coherent buffer */ wilc_wlan_firmware_download()
/linux-4.4.14/drivers/infiniband/hw/qib/
H A Dqib_user_sdma.c93 struct page *page; /* may be NULL (coherent mem) */
651 /* free coherent mem from cache... */ qib_user_sdma_free_pkt_frag()
/linux-4.4.14/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc.c1050 mfc_err("Failed to declare coherent memory for\n" s5p_mfc_alloc_memdevs()
1067 pr_err("Failed to declare coherent memory for\n" s5p_mfc_alloc_memdevs()
/linux-4.4.14/drivers/gpu/drm/omapdrm/
H A Domap_gem.c243 * DSS, GPU, etc. are not cache coherent: omap_gem_attach_pages()
281 * DSS, GPU, etc. are not cache coherent: omap_gem_detach_pages()
/linux-4.4.14/drivers/net/ethernet/micrel/
H A Dks8695net.c142 * @ring_base: The base pointer of the dma coherent memory for the rings
806 * This unallocates io memory regions, dma-coherent regions etc
/linux-4.4.14/lib/
H A Ddma-debug.c60 * @type: single, page, sg, coherent
154 "scather-gather", "coherent" };

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