1#ifndef _ASM_POWERPC_MMU_44X_H_ 2#define _ASM_POWERPC_MMU_44X_H_ 3/* 4 * PPC440 support 5 */ 6 7#include <asm/page.h> 8 9#define PPC44x_MMUCR_TID 0x000000ff 10#define PPC44x_MMUCR_STS 0x00010000 11 12#define PPC44x_TLB_PAGEID 0 13#define PPC44x_TLB_XLAT 1 14#define PPC44x_TLB_ATTRIB 2 15 16/* Page identification fields */ 17#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */ 18#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */ 19#define PPC44x_TLB_TS 0x00000100 /* Translation address space */ 20#define PPC44x_TLB_1K 0x00000000 /* Page sizes */ 21#define PPC44x_TLB_4K 0x00000010 22#define PPC44x_TLB_16K 0x00000020 23#define PPC44x_TLB_64K 0x00000030 24#define PPC44x_TLB_256K 0x00000040 25#define PPC44x_TLB_1M 0x00000050 26#define PPC44x_TLB_16M 0x00000070 27#define PPC44x_TLB_256M 0x00000090 28 29/* Translation fields */ 30#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */ 31#define PPC44x_TLB_ERPN_MASK 0x0000000f 32 33/* Storage attribute and access control fields */ 34#define PPC44x_TLB_ATTR_MASK 0x0000ff80 35#define PPC44x_TLB_U0 0x00008000 /* User 0 */ 36#define PPC44x_TLB_U1 0x00004000 /* User 1 */ 37#define PPC44x_TLB_U2 0x00002000 /* User 2 */ 38#define PPC44x_TLB_U3 0x00001000 /* User 3 */ 39#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */ 40#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */ 41#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */ 42#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */ 43#define PPC44x_TLB_E 0x00000080 /* Memory is little endian */ 44 45#define PPC44x_TLB_PERM_MASK 0x0000003f 46#define PPC44x_TLB_UX 0x00000020 /* User execution */ 47#define PPC44x_TLB_UW 0x00000010 /* User write */ 48#define PPC44x_TLB_UR 0x00000008 /* User read */ 49#define PPC44x_TLB_SX 0x00000004 /* Super execution */ 50#define PPC44x_TLB_SW 0x00000002 /* Super write */ 51#define PPC44x_TLB_SR 0x00000001 /* Super read */ 52 53/* Number of TLB entries */ 54#define PPC44x_TLB_SIZE 64 55 56/* 47x bits */ 57#define PPC47x_MMUCR_TID 0x0000ffff 58#define PPC47x_MMUCR_STS 0x00010000 59 60/* Page identification fields */ 61#define PPC47x_TLB0_EPN_MASK 0xfffff000 /* Effective Page Number */ 62#define PPC47x_TLB0_VALID 0x00000800 /* Valid flag */ 63#define PPC47x_TLB0_TS 0x00000400 /* Translation address space */ 64#define PPC47x_TLB0_4K 0x00000000 65#define PPC47x_TLB0_16K 0x00000010 66#define PPC47x_TLB0_64K 0x00000030 67#define PPC47x_TLB0_1M 0x00000070 68#define PPC47x_TLB0_16M 0x000000f0 69#define PPC47x_TLB0_256M 0x000001f0 70#define PPC47x_TLB0_1G 0x000003f0 71#define PPC47x_TLB0_BOLTED_R 0x00000008 /* tlbre only */ 72 73/* Translation fields */ 74#define PPC47x_TLB1_RPN_MASK 0xfffff000 /* Real Page Number */ 75#define PPC47x_TLB1_ERPN_MASK 0x000003ff 76 77/* Storage attribute and access control fields */ 78#define PPC47x_TLB2_ATTR_MASK 0x0003ff80 79#define PPC47x_TLB2_IL1I 0x00020000 /* Memory is guarded */ 80#define PPC47x_TLB2_IL1D 0x00010000 /* Memory is guarded */ 81#define PPC47x_TLB2_U0 0x00008000 /* User 0 */ 82#define PPC47x_TLB2_U1 0x00004000 /* User 1 */ 83#define PPC47x_TLB2_U2 0x00002000 /* User 2 */ 84#define PPC47x_TLB2_U3 0x00001000 /* User 3 */ 85#define PPC47x_TLB2_W 0x00000800 /* Caching is write-through */ 86#define PPC47x_TLB2_I 0x00000400 /* Caching is inhibited */ 87#define PPC47x_TLB2_M 0x00000200 /* Memory is coherent */ 88#define PPC47x_TLB2_G 0x00000100 /* Memory is guarded */ 89#define PPC47x_TLB2_E 0x00000080 /* Memory is little endian */ 90#define PPC47x_TLB2_PERM_MASK 0x0000003f 91#define PPC47x_TLB2_UX 0x00000020 /* User execution */ 92#define PPC47x_TLB2_UW 0x00000010 /* User write */ 93#define PPC47x_TLB2_UR 0x00000008 /* User read */ 94#define PPC47x_TLB2_SX 0x00000004 /* Super execution */ 95#define PPC47x_TLB2_SW 0x00000002 /* Super write */ 96#define PPC47x_TLB2_SR 0x00000001 /* Super read */ 97#define PPC47x_TLB2_U_RWX (PPC47x_TLB2_UX|PPC47x_TLB2_UW|PPC47x_TLB2_UR) 98#define PPC47x_TLB2_S_RWX (PPC47x_TLB2_SX|PPC47x_TLB2_SW|PPC47x_TLB2_SR) 99#define PPC47x_TLB2_S_RW (PPC47x_TLB2_SW | PPC47x_TLB2_SR) 100#define PPC47x_TLB2_IMG (PPC47x_TLB2_I | PPC47x_TLB2_M | PPC47x_TLB2_G) 101 102#ifndef __ASSEMBLY__ 103 104extern unsigned int tlb_44x_hwater; 105extern unsigned int tlb_44x_index; 106 107typedef struct { 108 unsigned int id; 109 unsigned int active; 110 unsigned long vdso_base; 111} mm_context_t; 112 113#endif /* !__ASSEMBLY__ */ 114 115#ifndef CONFIG_PPC_EARLY_DEBUG_44x 116#define PPC44x_EARLY_TLBS 1 117#else 118#define PPC44x_EARLY_TLBS 2 119#define PPC44x_EARLY_DEBUG_VIRTADDR (ASM_CONST(0xf0000000) \ 120 | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff)) 121#endif 122 123/* Size of the TLBs used for pinning in lowmem */ 124#define PPC_PIN_SIZE (1 << 28) /* 256M */ 125 126#if (PAGE_SHIFT == 12) 127#define PPC44x_TLBE_SIZE PPC44x_TLB_4K 128#define PPC47x_TLBE_SIZE PPC47x_TLB0_4K 129#define mmu_virtual_psize MMU_PAGE_4K 130#elif (PAGE_SHIFT == 14) 131#define PPC44x_TLBE_SIZE PPC44x_TLB_16K 132#define PPC47x_TLBE_SIZE PPC47x_TLB0_16K 133#define mmu_virtual_psize MMU_PAGE_16K 134#elif (PAGE_SHIFT == 16) 135#define PPC44x_TLBE_SIZE PPC44x_TLB_64K 136#define PPC47x_TLBE_SIZE PPC47x_TLB0_64K 137#define mmu_virtual_psize MMU_PAGE_64K 138#elif (PAGE_SHIFT == 18) 139#define PPC44x_TLBE_SIZE PPC44x_TLB_256K 140#define mmu_virtual_psize MMU_PAGE_256K 141#else 142#error "Unsupported PAGE_SIZE" 143#endif 144 145#define mmu_linear_psize MMU_PAGE_256M 146 147#define PPC44x_PGD_OFF_SHIFT (32 - PGDIR_SHIFT + PGD_T_LOG2) 148#define PPC44x_PGD_OFF_MASK_BIT (PGDIR_SHIFT - PGD_T_LOG2) 149#define PPC44x_PTE_ADD_SHIFT (32 - PGDIR_SHIFT + PTE_SHIFT + PTE_T_LOG2) 150#define PPC44x_PTE_ADD_MASK_BIT (32 - PTE_T_LOG2 - PTE_SHIFT) 151 152#endif /* _ASM_POWERPC_MMU_44X_H_ */ 153