| /linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_init_ops.h | 57 REG_WR(bp, addr + i*4, data[i]); in bnx2x_init_str_wr()
265 REG_WR(bp, addr, op->write.val); in bnx2x_init_block()
497 REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l); in bnx2x_init_pxp_arb()
498 REG_WR(bp, read_arb_addr[i].add, in bnx2x_init_pxp_arb()
500 REG_WR(bp, read_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
508 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
511 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
514 REG_WR(bp, write_arb_addr[i].ubound, in bnx2x_init_pxp_arb()
519 REG_WR(bp, write_arb_addr[i].l, in bnx2x_init_pxp_arb()
523 REG_WR(bp, write_arb_addr[i].add, in bnx2x_init_pxp_arb()
[all …]
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| D | bnx2x_main.c | 304 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
305 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
464 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
466 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
853 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
871 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
889 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
1402 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1412 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1509 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
[all …]
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| D | bnx2x_link.c | 231 REG_WR(bp, reg, val); in bnx2x_bits_en()
240 REG_WR(bp, reg, val); in bnx2x_bits_dis()
268 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
387 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
409 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
413 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
460 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
471 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
475 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
[all …]
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| D | bnx2x_init.h | 233 REG_WR(bp, BNX2X_Q_VOQ_REG_ADDR(pf_q_num), new_cos); in bnx2x_map_q_cos()
238 REG_WR(bp, reg_addr, reg_bit_map & (~q_bit_map)); in bnx2x_map_q_cos()
243 REG_WR(bp, reg_addr, reg_bit_map | q_bit_map); in bnx2x_map_q_cos()
255 REG_WR(bp, reg_addr, reg_bit_map); in bnx2x_map_q_cos()
689 REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val); in bnx2x_set_mcp_parity()
713 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, in bnx2x_disable_blocks_parity()
736 REG_WR(bp, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
737 REG_WR(bp, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
738 REG_WR(bp, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
739 REG_WR(bp, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in bnx2x_clear_blocks_parity()
[all …]
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| D | bnx2x_sriov.c | 102 REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags); in bnx2x_vf_igu_ack_sb()
108 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_vf_igu_ack_sb()
700 REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0); in bnx2x_vf_enable_internal()
706 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
707 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
708 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
709 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid); in bnx2x_vf_semi_clear_err()
731 REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f)); in bnx2x_vf_pglue_clear_err()
742 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_vf_igu_reset()
743 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_vf_igu_reset()
[all …]
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| D | bnx2x_cmn.h | 522 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, in bnx2x_update_rx_prod()
655 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); in bnx2x_igu_ack_sb_gen()
676 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); in bnx2x_hc_ack_sb()
948 REG_WR(bp, PRS_REG_VLAN_TYPE_0, ETH_P_8021AD); in bnx2x_func_start()
949 REG_WR(bp, PBF_REG_VLAN_TYPE_0, ETH_P_8021AD); in bnx2x_func_start()
950 REG_WR(bp, NIG_REG_LLH_E1HOV_TYPE_1, ETH_P_8021AD); in bnx2x_func_start()
1224 REG_WR(bp, addr + (i * 4), data[i]); in __storm_memset_struct()
1335 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + in bnx2x_link_sync_notify()
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| D | bnx2x_ethtool.c | 851 REG_WR(bp, write_addr[j], page_addr[i]); in bnx2x_read_pages_regs()
1220 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_acquire_nvram_lock()
1253 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_release_nvram_lock()
1282 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, in bnx2x_enable_nvram_access()
1294 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE, in bnx2x_disable_nvram_access()
1309 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in bnx2x_nvram_read_dword()
1312 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR, in bnx2x_nvram_read_dword()
1316 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); in bnx2x_nvram_read_dword()
1581 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in bnx2x_nvram_write_dword()
1584 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val); in bnx2x_nvram_write_dword()
[all …]
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| D | bnx2x.h | 169 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) macro
201 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
206 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
213 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
222 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
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| D | bnx2x_cmn.c | 1489 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_rx_rings()
1492 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_rx_rings()
2576 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1); in bnx2x_load_cnic()
2606 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_load_cnic()
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| D | bnx2x_sp.c | 827 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_FUNC_MEM_ENABLE : in bnx2x_set_mac_in_nig()
3356 REG_WR(bp, MC_HASH_OFFSET(bp, i), mc_filter[i]); in bnx2x_mcast_setup_e1h()
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| D | bnx2x_dcb.c | 68 REG_WR(bp, addr + i, *buff); in bnx2x_write_data()
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| /linux-4.4.14/drivers/media/radio/wl128x/ |
| D | fmdrv_tx.c | 39 ret = fmc_send_cmd(fmdev, MONO_SET, REG_WR, &payload, in fm_tx_set_stereo_mono()
54 ret = fmc_send_cmd(fmdev, RDS_DATA_SET, REG_WR, rds_text, in set_rds_text()
61 ret = fmc_send_cmd(fmdev, DISPLAY_MODE, REG_WR, &payload, in set_rds_text()
76 ret = fmc_send_cmd(fmdev, PI_SET, REG_WR, &payload, in set_rds_data_mode()
83 ret = fmc_send_cmd(fmdev, DI_SET, REG_WR, &payload, in set_rds_data_mode()
99 ret = fmc_send_cmd(fmdev, RDS_CONFIG_DATA_SET, REG_WR, &payload, in set_rds_len()
134 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, in fm_tx_set_rds_mode()
171 ret = fmc_send_cmd(fmdev, RDS_DATA_ENB, REG_WR, &payload, in fm_tx_set_radio_text()
191 ret = fmc_send_cmd(fmdev, TA_SET, REG_WR, &payload, in fm_tx_set_af()
211 ret = fmc_send_cmd(fmdev, TX_BAND_SET, REG_WR, &payload, in fm_tx_set_region()
[all …]
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| D | fmdrv_rx.c | 62 ret = fmc_send_cmd(fmdev, AUDIO_ENABLE_SET, REG_WR, &payload, in fm_rx_set_freq()
69 ret = fmc_send_cmd(fmdev, HILO_SET, REG_WR, &payload, in fm_rx_set_freq()
77 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, in fm_rx_set_freq()
91 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_rx_set_freq()
98 ret = fmc_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, in fm_rx_set_freq()
133 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_rx_set_freq()
159 ret = fmc_send_cmd(fmdev, CHANL_BW_SET, REG_WR, &payload, in fm_rx_set_channel_spacing()
214 ret = fmc_send_cmd(fmdev, FREQ_SET, REG_WR, &payload, in fm_rx_seek()
221 ret = fmc_send_cmd(fmdev, SEARCH_DIR_SET, REG_WR, &payload, in fm_rx_seek()
235 ret = fmc_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_rx_seek()
[all …]
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| D | fmdrv_common.c | 885 if (!fm_send_cmd(fmdev, RDS_PI_SET, REG_WR, &payload, sizeof(payload), NULL)) in fm_irq_afjump_set_pi()
904 if (!fm_send_cmd(fmdev, RDS_PI_MASK_SET, REG_WR, &payload, sizeof(payload), NULL)) in fm_irq_afjump_set_pimask()
923 if (!fm_send_cmd(fmdev, AF_FREQ_SET, REG_WR, &payload, sizeof(payload), NULL)) in fm_irq_afjump_setfreq()
938 if (!fm_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, sizeof(payload), NULL)) in fm_irq_afjump_enableint()
952 if (!fm_send_cmd(fmdev, TUNER_MODE_SET, REG_WR, &payload, in fm_irq_start_afjump()
1033 if (!fm_send_cmd(fmdev, INT_MASK_SET, REG_WR, &payload, in fm_irq_send_intmsk_cmd()
1229 ret = fmc_send_cmd(fmdev, FM_POWER_MODE, REG_WR, &payload, in fm_power_down()
1338 if (fmc_send_cmd(fmdev, FM_POWER_MODE, REG_WR, &payload, in fm_power_up()
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| D | fmdrv_common.h | 29 #define REG_WR 0x0 macro
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| /linux-4.4.14/arch/cris/arch-v32/kernel/ |
| D | time.c | 112 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in reset_watchdog()
127 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in stop_watchdog()
154 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl); in handle_watchdog_bite()
182 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_switch_state()
194 REG_WR(timer, timer_base, rw_tmr0_div, evt); in crisv32_clkevt_next_event()
195 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
198 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_clkevt_next_event()
217 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_interrupt()
218 REG_WR(timer, timer_base, rw_ack_intr, ack); in crisv32_timer_interrupt()
261 REG_WR(timer, timer_base, rw_tmr0_ctrl, ctrl); in crisv32_timer_init()
[all …]
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| D | debugport.c | 149 REG_WR (ser, p->instance, rw_tr_baud_div, tr_baud_div); in start_port()
150 REG_WR (ser, p->instance, rw_rec_baud_div, rec_baud_div); in start_port()
151 REG_WR (ser, p->instance, rw_tr_dma_en, tr_dma_en); in start_port()
152 REG_WR (ser, p->instance, rw_tr_ctrl, tr_ctrl); in start_port()
153 REG_WR (ser, p->instance, rw_rec_ctrl, rec_ctrl); in start_port()
169 REG_WR(ser, kgdb_port->instance, rw_ack_intr, ack_intr); in getDebugChar()
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| D | fasttimer.c | 146 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); in start_timer_trig()
157 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); in start_timer_trig()
160 REG_WR(timer, regi_timer0, rw_trig, trig); in start_timer_trig()
162 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); in start_timer_trig()
172 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); in start_timer_trig()
178 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); in start_timer_trig()
179 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); in start_timer_trig()
339 REG_WR(timer, regi_timer0, rw_intr_mask, intr_mask); in timer_trig_handler()
344 REG_WR(timer, regi_timer0, rw_trig_cfg, trig_cfg); in timer_trig_handler()
348 REG_WR(timer, regi_timer0, rw_ack_intr, ack_intr); in timer_trig_handler()
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| D | kgdb.c | 1531 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1535 REG_WR(ser, regi_ser0, rw_intr_mask, ser_intr_mask); in kgdb_init()
1543 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1547 REG_WR(ser, regi_ser1, rw_intr_mask, ser_intr_mask); in kgdb_init()
1555 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1559 REG_WR(ser, regi_ser2, rw_intr_mask, ser_intr_mask); in kgdb_init()
1567 REG_WR(intr_vect, regi_irq, rw_mask, intr_mask); in kgdb_init()
1571 REG_WR(ser, regi_ser3, rw_intr_mask, ser_intr_mask); in kgdb_init()
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| D | process.c | 76 REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl); in hard_reset_now()
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| /linux-4.4.14/drivers/tty/serial/ |
| D | etraxfs-uart.c | 22 REG_WR(ser, instance, reg, var); \
65 REG_WR(ser, up->regi_ser, rw_tr_dma_en, tr_dma_en); in cris_console_write()
86 REG_WR(ser, up->regi_ser, rw_tr_dma_en, old); in cris_console_write()
168 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); in crisv32_serial_set_rts()
221 REG_WR(ser, regi_ser, rw_ack_intr, ack_intr); in etraxfs_uart_send_xchar()
225 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); in etraxfs_uart_send_xchar()
231 REG_WR(ser, regi_ser, rw_dout, dout); in etraxfs_uart_send_xchar()
245 REG_WR(ser, regi_ser, rw_xoff_clr, xoff_clr); in etraxfs_uart_send_xchar()
258 REG_WR(ser, regi_ser, rw_tr_dma_en, tr_dma_en); in etraxfs_uart_send_xchar()
262 REG_WR(ser, regi_ser, rw_tr_ctrl, prev_tr_ctrl); in etraxfs_uart_send_xchar()
[all …]
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| /linux-4.4.14/arch/cris/arch-v32/drivers/ |
| D | iop_fw_load.c | 89 REG_WR(iop_spu, regi_iop_spu0, rw_ctrl, spu_ctrl); in iop_fw_load_spu()
93 REG_WR(iop_spu, regi_iop_spu1, rw_ctrl, spu_ctrl); in iop_fw_load_spu()
98 REG_WR(iop_sw_cpu, regi_iop_sw_cpu, rw_mc_ctrl, mc_ctrl); in iop_fw_load_spu()
150 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); in iop_fw_load_mpu()
156 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_SWX_IIR_INSTR(0, 4, 0)); in iop_fw_load_mpu()
177 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_HALT()); in iop_start_mpu()
187 REG_WR(iop_mpu, regi_iop_mpu, rw_instr, MPU_DI()); in iop_start_mpu()
191 REG_WR(iop_mpu, regi_iop_mpu, rw_ctrl, mpu_ctrl); in iop_start_mpu()
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| D | sync_serial.c | 321 REG_WR(sser, port->regi_sser, rw_cfg, cfg); in sync_serial_start_port()
322 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); in sync_serial_start_port()
323 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); in sync_serial_start_port()
367 REG_WR(sser, port->regi_sser, rw_cfg, cfg); in initialize_port()
377 REG_WR(sser, port->regi_sser, rw_frm_cfg, frm_cfg); in initialize_port()
391 REG_WR(sser, port->regi_sser, rw_tr_cfg, tr_cfg); in initialize_port()
397 REG_WR(sser, port->regi_sser, rw_rec_cfg, rec_cfg); in initialize_port()
505 REG_WR(dma, port->regi_dmain, rw_cfg, cfg); in sync_serial_open()
506 REG_WR(dma, port->regi_dmaout, rw_cfg, cfg); in sync_serial_open()
508 REG_WR(dma, port->regi_dmain, rw_intr_mask, intr_mask); in sync_serial_open()
[all …]
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| D | cryptocop.c | 1906 REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); in dma_done_interrupt()
1975 REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); in init_cryptocop()
1977 REG_WR(strcop, regi_strcop, rw_cfg, strcop_cfg); in init_cryptocop()
1980 REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ in init_cryptocop()
1981 REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ in init_cryptocop()
1988 REG_WR(dma, IN_DMA_INST, rw_intr_mask, intr_mask_in); in init_cryptocop()
1991 REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); in init_cryptocop()
2009 REG_WR(dma, IN_DMA_INST, rw_ack_intr, ack_intr); in release_cryptocop()
2012 REG_WR(dma, IN_DMA_INST, rw_cfg, dma_cfg); /* input DMA */ in release_cryptocop()
2013 REG_WR(dma, OUT_DMA_INST, rw_cfg, dma_cfg); /* output DMA */ in release_cryptocop()
[all …]
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| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/ |
| D | dma.h | 78 REG_WR( dma, inst, rw_cfg, e); } while( 0 )
84 REG_WR( dma, inst, rw_cfg, r); } while( 0 )
90 REG_WR( dma, inst, rw_cfg, s); } while( 0 )
96 REG_WR( dma, inst, rw_cfg, c); } while( 0 )
103 REG_WR(dma, inst, rw_stream_cmd, __x); \
125 REG_WR( dma, inst, rw_cmd, c ); } while( 0 )
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| D | marb_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
282 #ifndef REG_WR
283 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | irq_nmi_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | strcop_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | config_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | rt_trace_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | marb_bp_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | ata_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | bif_slave_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | ser_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | bif_core_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | eth_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | sser_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | dma_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | extmem_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | bif_dma_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| /linux-4.4.14/arch/cris/boot/compressed/ |
| D | misc.c | 138 REG_WR(ser, regi_ser, rw_dout, dout); in serout()
248 REG_WR(ser, regi_ser, rw_xoff, xoff); in serial_setup()
270 REG_WR(ser, regi_ser, rw_tr_ctrl, tr_ctrl); in serial_setup()
271 REG_WR(ser, regi_ser, rw_tr_baud_div, tr_baud); in serial_setup()
272 REG_WR(ser, regi_ser, rw_rec_ctrl, rec_ctrl); in serial_setup()
273 REG_WR(ser, regi_ser, rw_rec_baud_div, rec_baud); in serial_setup()
297 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in decompress_kernel()
323 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in decompress_kernel()
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| /linux-4.4.14/arch/cris/arch-v32/drivers/mach-a3/ |
| D | nandflash.c | 83 REG_WR(pio, regi_pio, rw_dout, dout); in crisv32_hwcontrol()
133 REG_WR(pio, regi_pio, rw_man_ctrl, man_ctrl); in crisv32_nand_flash_probe()
134 REG_WR(pio, regi_pio, rw_dout, dout); in crisv32_nand_flash_probe()
135 REG_WR(pio, regi_pio, rw_oe, oe); in crisv32_nand_flash_probe()
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| /linux-4.4.14/arch/cris/arch-v32/mm/ |
| D | l2cache.c | 19 REG_WR(l2cache, regi_l2cache, rw_ctrl, ctrl); in l2cache_init()
25 REG_WR(l2cache, regi_l2cache, rw_cfg, cfg); in l2cache_init()
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| /linux-4.4.14/arch/cris/arch-v32/drivers/mach-fs/ |
| D | nandflash.c | 78 REG_WR(gio, regi_gio, rw_pa_dout, dout); in crisv32_hwcontrol()
138 REG_WR(gio, regi_gio, rw_pa_oe, pa_oe); in crisv32_nand_flash_probe()
142 REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg); in crisv32_nand_flash_probe()
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| /linux-4.4.14/drivers/cpufreq/ |
| D | cris-artpec3-cpufreq.c | 43 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in cris_freq_target()
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); in cris_sdram_freq_notifier()
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| D | cris-etraxfs-cpufreq.c | 43 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); in cris_freq_target()
86 REG_WR(bif_core, regi_bif_core, rw_sdram_timing, timing); in cris_sdram_freq_notifier()
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| /linux-4.4.14/arch/cris/arch-v32/mach-fs/ |
| D | arbiter.c | 307 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); in crisv32_arbiter_watch()
341 REG_WR(marb, regi_marb, rw_intr_mask, intr_mask); in crisv32_arbiter_unwatch()
395 REG_WR(marb_bp, watch->instance, rw_ack, ack); in crisv32_arbiter_irq()
396 REG_WR(marb, regi_marb, rw_ack_intr, ack_intr); in crisv32_arbiter_irq()
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| D | dma.c | 218 REG_WR(config, regi_config, rw_clk_ctrl, clk_ctrl); in crisv32_request_dma()
219 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); in crisv32_request_dma()
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| D | pinmux.c | 63 REG_WR(pinmux, regi_pinmux, rw_pa, pa); in crisv32_pinmux_init()
169 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_alloc_fixed()
304 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_dealloc_fixed()
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-fs/mach/hwregs/ |
| D | marb_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
282 #ifndef REG_WR
283 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | strmux_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | config_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | marb_bp_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | timer_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | intr_vect_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | bif_slave_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | gio_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | bif_core_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | pinmux_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | bif_dma_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/ |
| D | marb_bar_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
304 #ifndef REG_WR
305 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | strmux_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | l2cache_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | clkgen_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | marb_foo_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
430 #ifndef REG_WR
431 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | timer_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | ddr2_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | pinmux_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | pio_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | intr_vect_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | gio_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| /linux-4.4.14/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/ |
| D | iop_version_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sap_in_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sap_out_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_spu_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_cpu_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_mpu_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_cfg_defs.h | 20 #ifndef REG_WR
21 #define REG_WR( scope, inst, reg, val ) \ macro
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| /linux-4.4.14/arch/cris/include/arch-v32/arch/hwregs/iop/ |
| D | iop_version_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_scrc_in_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_scrc_out_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_trigger_grp_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_fifo_in_extra_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_fifo_out_extra_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sap_in_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_mpu_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_crc_par_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_fifo_in_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_timer_grp_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_fifo_out_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sap_out_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_dmc_out_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_dmc_in_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_spu_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_spu_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_cpu_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_mpu_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
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| D | iop_sw_cfg_defs.h | 23 #ifndef REG_WR
24 #define REG_WR( scope, inst, reg, val ) \ macro
|
| /linux-4.4.14/arch/cris/arch-v32/mach-a3/ |
| D | dma.c | 173 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in crisv32_request_dma()
174 REG_WR(strmux, regi_strmux, rw_cfg, strmux_cfg); in crisv32_request_dma()
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| D | arbiter.c | 568 REG_WR(marb_foo_bp, watch->instance, rw_ack, ack); in crisv32_foo_arbiter_irq()
569 REG_WR(marb_foo, regi_marb_foo, rw_ack_intr, ack_intr); in crisv32_foo_arbiter_irq()
624 REG_WR(marb_bar_bp, watch->instance, rw_ack, ack); in crisv32_bar_arbiter_irq()
625 REG_WR(marb_bar, regi_marb_bar, rw_ack_intr, ack_intr); in crisv32_bar_arbiter_irq()
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| D | pinmux.c | 203 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_alloc_fixed()
204 REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, clk_ctrl); in crisv32_pinmux_alloc_fixed()
362 REG_WR(pinmux, regi_pinmux, rw_hwprot, hwprot); in crisv32_pinmux_dealloc_fixed()
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| /linux-4.4.14/drivers/net/ethernet/qlogic/qed/ |
| D | qed_hw.c | 161 REG_WR(p_hwfn, in qed_ptt_set_win()
204 REG_WR(p_hwfn, bar_addr, val); in qed_wr()
300 REG_WR(p_hwfn, in qed_fid_pretend()
318 REG_WR(p_hwfn, in qed_port_pretend()
335 REG_WR(p_hwfn, in qed_port_unpretend()
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| D | qed.h | 480 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) macro
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| D | qed_init_ops.c | 501 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE, in qed_gtt_init()
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| D | qed_dev.c | 370 REG_WR(p_hwfn, addr, 0); in qed_final_cleanup()
390 REG_WR(p_hwfn, addr, 0); in qed_final_cleanup()
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| /linux-4.4.14/drivers/scsi/bnx2i/ |
| D | bnx2i.h | 130 #define REG_WR(__hba, offset, val) \ macro
|