Lines Matching refs:REG_WR
304 REG_WR(bp, addr, U64_LO(mapping)); in __storm_memset_dma_mapping()
305 REG_WR(bp, addr + 4, U64_HI(mapping)); in __storm_memset_dma_mapping()
464 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i)); in bnx2x_post_dmae()
466 REG_WR(bp, dmae_reg_go_c[idx], 1); in bnx2x_post_dmae()
853 REG_WR(bp, HC_REG_INT_MASK + port*4, 0); in bnx2x_hc_int_disable()
871 REG_WR(bp, addr, val); in bnx2x_hc_int_disable()
889 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_disable()
1402 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command); in bnx2x_send_final_clnup()
1412 REG_WR(bp, comp_addr, 0); in bnx2x_send_final_clnup()
1509 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); in bnx2x_pf_flr_clnup()
1541 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_pf_flr_clnup()
1577 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1584 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF); in bnx2x_hc_int_enable()
1590 REG_WR(bp, addr, val); in bnx2x_hc_int_enable()
1607 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1608 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_hc_int_enable()
1646 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1655 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_igu_int_enable()
1671 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1672 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_igu_int_enable()
1744 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_trylock_hw_lock()
2019 REG_WR(bp, hw_lock_control_reg + 4, resource_bit); in bnx2x_acquire_hw_lock()
2064 REG_WR(bp, hw_lock_control_reg, resource_bit); in bnx2x_release_hw_lock()
2146 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_gpio()
2192 REG_WR(bp, MISC_REG_GPIO, gpio_reg); in bnx2x_set_mult_gpio()
2241 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg); in bnx2x_set_gpio_int()
2286 REG_WR(bp, MISC_REG_SPIO, spio_reg); in bnx2x_set_spio()
2334 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_dropless_fc()
2836 REG_WR(bp, addr_to_write + i*sizeof(u32), in bnx2x_handle_afex_cmd()
2939 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + BP_PORT(bp) * 8, in bnx2x_handle_update_svid_cmd()
2987 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2988 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); in bnx2x_pmf_update()
2990 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val); in bnx2x_pmf_update()
2991 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val); in bnx2x_pmf_update()
3075 REG_WR(bp, XSEM_REG_FAST_MEMORY + in bnx2x_func_init()
3293 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3298 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + in bnx2x_pf_init()
3343 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_e1h_disable()
3351 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_e1h_enable()
3941 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK); in bnx2x_acquire_alr()
3959 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0); in bnx2x_release_alr()
4012 REG_WR(bp, aeu_addr, aeu_mask); in bnx2x_attn_int_asserted()
4031 REG_WR(bp, nig_int_mask_addr, 0); in bnx2x_attn_int_asserted()
4053 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); in bnx2x_attn_int_asserted()
4057 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); in bnx2x_attn_int_asserted()
4061 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); in bnx2x_attn_int_asserted()
4066 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); in bnx2x_attn_int_asserted()
4070 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); in bnx2x_attn_int_asserted()
4074 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); in bnx2x_attn_int_asserted()
4088 REG_WR(bp, reg_addr, asserted); in bnx2x_attn_int_asserted()
4107 REG_WR(bp, nig_int_mask_addr, nig_mask); in bnx2x_attn_int_asserted()
4150 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4169 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted0()
4200 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted1()
4244 REG_WR(bp, reg_offset, val); in bnx2x_attn_int_deasserted2()
4261 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_attn_int_deasserted3()
4321 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0); in bnx2x_attn_int_deasserted3()
4322 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0); in bnx2x_attn_int_deasserted3()
4323 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0); in bnx2x_attn_int_deasserted3()
4324 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0); in bnx2x_attn_int_deasserted3()
4330 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0); in bnx2x_attn_int_deasserted3()
4349 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); in bnx2x_attn_int_deasserted3()
4387 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT); in bnx2x_set_reset_global()
4401 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT)); in bnx2x_clear_reset_global()
4433 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_done()
4453 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_reset_in_progress()
4501 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_set_pf_load()
4538 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val); in bnx2x_clear_pf_load()
4894 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, in bnx2x_check_blocks_with_parity3()
5163 REG_WR(bp, reg_addr, val); in bnx2x_attn_int_deasserted()
5179 REG_WR(bp, reg_addr, aeu_mask); in bnx2x_attn_int_deasserted()
5815 REG_WR(bp, addr + i, fill); in bnx2x_fill()
5829 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_fp_sb_data()
5874 REG_WR(bp, BAR_CSTRORM_INTMEM + in bnx2x_wr_sp_sb_data()
6069 REG_WR(bp, reg_offset, U64_LO(section)); in bnx2x_init_def_sb()
6070 REG_WR(bp, reg_offset + 4, U64_HI(section)); in bnx2x_init_def_sb()
6072 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); in bnx2x_init_def_sb()
6073 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); in bnx2x_init_def_sb()
6288 REG_WR(bp, BAR_USTRORM_INTMEM + in bnx2x_init_internal_common()
6684 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6685 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6686 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6687 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6690 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6739 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0); in bnx2x_int_mem_test()
6740 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0); in bnx2x_int_mem_test()
6741 REG_WR(bp, CFC_REG_DEBUG0, 0x1); in bnx2x_int_mem_test()
6742 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0); in bnx2x_int_mem_test()
6745 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); in bnx2x_int_mem_test()
6775 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); in bnx2x_int_mem_test()
6794 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); in bnx2x_int_mem_test()
6796 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); in bnx2x_int_mem_test()
6802 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_int_mem_test()
6805 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff); in bnx2x_int_mem_test()
6806 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1); in bnx2x_int_mem_test()
6807 REG_WR(bp, CFC_REG_DEBUG0, 0x0); in bnx2x_int_mem_test()
6808 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1); in bnx2x_int_mem_test()
6819 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6821 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40); in bnx2x_enable_blocks_attention()
6823 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6824 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6825 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6832 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00); in bnx2x_enable_blocks_attention()
6833 REG_WR(bp, QM_REG_QM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6834 REG_WR(bp, TM_REG_TM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6835 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6836 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6837 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6840 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6841 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6842 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6845 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6846 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6847 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6848 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6858 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val); in bnx2x_enable_blocks_attention()
6860 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0); in bnx2x_enable_blocks_attention()
6861 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0); in bnx2x_enable_blocks_attention()
6862 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6867 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); in bnx2x_enable_blocks_attention()
6869 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6870 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0); in bnx2x_enable_blocks_attention()
6872 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ in bnx2x_enable_blocks_attention()
6880 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_reset_common()
6888 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val); in bnx2x_reset_common()
6957 REG_WR(bp, MISC_REG_SPIO_INT, val); in bnx2x_setup_fan_failure_detection()
6962 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val); in bnx2x_setup_fan_failure_detection()
6970 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val); in bnx2x_pf_disable()
6971 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_pf_disable()
6972 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0); in bnx2x_pf_disable()
6998 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, val); in bnx2x_config_endianity()
6999 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, val); in bnx2x_config_endianity()
7000 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, val); in bnx2x_config_endianity()
7001 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, val); in bnx2x_config_endianity()
7002 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, val); in bnx2x_config_endianity()
7005 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0); in bnx2x_config_endianity()
7007 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, val); in bnx2x_config_endianity()
7008 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, val); in bnx2x_config_endianity()
7009 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, val); in bnx2x_config_endianity()
7010 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, val); in bnx2x_config_endianity()
7045 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff); in bnx2x_init_hw_common()
7052 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val); in bnx2x_init_hw_common()
7071 REG_WR(bp, in bnx2x_init_hw_common()
7088 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0); in bnx2x_init_hw_common()
7097 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1); in bnx2x_init_hw_common()
7206 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7207 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN); in bnx2x_init_hw_common()
7208 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); in bnx2x_init_hw_common()
7211 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7212 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0); in bnx2x_init_hw_common()
7260 REG_WR(bp, QM_REG_SOFT_RESET, 1); in bnx2x_init_hw_common()
7261 REG_WR(bp, QM_REG_SOFT_RESET, 0); in bnx2x_init_hw_common()
7270 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0); in bnx2x_init_hw_common()
7275 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf); in bnx2x_init_hw_common()
7278 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan); in bnx2x_init_hw_common()
7285 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7286 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7287 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7288 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7289 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7294 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7306 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7309 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, in bnx2x_init_hw_common()
7322 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_init_hw_common()
7324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, in bnx2x_init_hw_common()
7336 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE); in bnx2x_init_hw_common()
7337 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA); in bnx2x_init_hw_common()
7338 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6); in bnx2x_init_hw_common()
7339 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926); in bnx2x_init_hw_common()
7340 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4); in bnx2x_init_hw_common()
7342 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, in bnx2x_init_hw_common()
7347 REG_WR(bp, SRC_REG_SOFT_RST, 1); in bnx2x_init_hw_common()
7352 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672); in bnx2x_init_hw_common()
7353 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); in bnx2x_init_hw_common()
7354 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b); in bnx2x_init_hw_common()
7355 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a); in bnx2x_init_hw_common()
7356 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116); in bnx2x_init_hw_common()
7357 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b); in bnx2x_init_hw_common()
7358 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf); in bnx2x_init_hw_common()
7359 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); in bnx2x_init_hw_common()
7360 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f); in bnx2x_init_hw_common()
7361 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7); in bnx2x_init_hw_common()
7363 REG_WR(bp, SRC_REG_SOFT_RST, 0); in bnx2x_init_hw_common()
7373 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val); in bnx2x_init_hw_common()
7376 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF); in bnx2x_init_hw_common()
7378 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0); in bnx2x_init_hw_common()
7381 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000); in bnx2x_init_hw_common()
7386 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36); in bnx2x_init_hw_common()
7392 REG_WR(bp, 0x2814, 0xffffffff); in bnx2x_init_hw_common()
7393 REG_WR(bp, 0x3820, 0xffffffff); in bnx2x_init_hw_common()
7396 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, in bnx2x_init_hw_common()
7399 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, in bnx2x_init_hw_common()
7403 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, in bnx2x_init_hw_common()
7413 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp)); in bnx2x_init_hw_common()
7417 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp)); in bnx2x_init_hw_common()
7438 REG_WR(bp, CFC_REG_DEBUG0, 0); in bnx2x_init_hw_common()
7501 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_init_hw_port()
7513 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_port()
7530 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20); in bnx2x_init_hw_port()
7531 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); in bnx2x_init_hw_port()
7554 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); in bnx2x_init_hw_port()
7555 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); in bnx2x_init_hw_port()
7559 REG_WR(bp, (BP_PORT(bp) ? in bnx2x_init_hw_port()
7567 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7570 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7573 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7581 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7605 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_init_hw_port()
7608 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); in bnx2x_init_hw_port()
7610 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); in bnx2x_init_hw_port()
7613 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1); in bnx2x_init_hw_port()
7615 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0); in bnx2x_init_hw_port()
7625 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7626 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_port()
7640 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); in bnx2x_init_hw_port()
7644 REG_WR(bp, reg, in bnx2x_init_hw_port()
7649 REG_WR(bp, reg, in bnx2x_init_hw_port()
7660 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7664 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7670 REG_WR(bp, BP_PORT(bp) ? in bnx2x_init_hw_port()
7675 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_init_hw_port()
7679 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, in bnx2x_init_hw_port()
7694 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE : in bnx2x_init_hw_port()
7698 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0); in bnx2x_init_hw_port()
7699 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); in bnx2x_init_hw_port()
7700 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); in bnx2x_init_hw_port()
7711 REG_WR(bp, reg_addr, val); in bnx2x_init_hw_port()
7757 REG_WR(bp, igu_addr_data, data); in bnx2x_igu_clear_sb_gen()
7762 REG_WR(bp, igu_addr_ctl, ctl); in bnx2x_igu_clear_sb_gen()
7794 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); in bnx2x_init_searcher()
7834 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7842 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7849 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7864 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_reset_nic_mode()
7870 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN : in bnx2x_reset_nic_mode()
7873 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE + in bnx2x_reset_nic_mode()
7881 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE : in bnx2x_reset_nic_mode()
7925 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, in bnx2x_clean_pglue_errors()
7956 REG_WR(bp, addr, val); in bnx2x_init_hw_func()
7984 REG_WR(bp, PRS_REG_NIC_MODE, 0); in bnx2x_init_hw_func()
7988 REG_WR(bp, PRS_REG_NIC_MODE, 1); in bnx2x_init_hw_func()
8012 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); in bnx2x_init_hw_func()
8014 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf); in bnx2x_init_hw_func()
8038 REG_WR(bp, QM_REG_PF_EN, 1); in bnx2x_init_hw_func()
8041 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8042 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8043 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8044 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func); in bnx2x_init_hw_func()
8050 REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */ in bnx2x_init_hw_func()
8064 REG_WR(bp, PBF_REG_DISABLE_PF, 0); in bnx2x_init_hw_func()
8071 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1); in bnx2x_init_hw_func()
8075 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port * 8, 1); in bnx2x_init_hw_func()
8076 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, in bnx2x_init_hw_func()
8086 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8088 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8089 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_init_hw_func()
8096 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); in bnx2x_init_hw_func()
8099 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8100 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_init_hw_func()
8137 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8167 REG_WR(bp, addr, 0); in bnx2x_init_hw_func()
8191 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in bnx2x_init_hw_func()
8192 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in bnx2x_init_hw_func()
8193 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0); in bnx2x_init_hw_func()
8194 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0); in bnx2x_init_hw_func()
8195 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0); in bnx2x_init_hw_func()
8196 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0); in bnx2x_init_hw_func()
8201 REG_WR(bp, 0x2114, 0xffffffff); in bnx2x_init_hw_func()
8202 REG_WR(bp, 0x2120, 0xffffffff); in bnx2x_init_hw_func()
8964 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), in bnx2x_reset_func()
8969 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8970 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0); in bnx2x_reset_func()
8972 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0); in bnx2x_reset_func()
8973 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0); in bnx2x_reset_func()
8978 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0); in bnx2x_reset_func()
9021 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); in bnx2x_reset_port()
9024 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); in bnx2x_reset_port()
9026 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_reset_port()
9030 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); in bnx2x_reset_port()
9248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_disable_ptp()
9252 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9254 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9256 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_disable_ptp()
9258 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_disable_ptp()
9262 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_disable_ptp()
9323 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0); in bnx2x_chip_cleanup()
9443 REG_WR(bp, addr, val); in bnx2x_disable_close_the_gate()
9448 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val); in bnx2x_disable_close_the_gate()
9460 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close); in bnx2x_set_234_gates()
9462 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); in bnx2x_set_234_gates()
9469 REG_WR(bp, HC_REG_CONFIG_1, in bnx2x_set_234_gates()
9474 REG_WR(bp, HC_REG_CONFIG_0, in bnx2x_set_234_gates()
9481 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, in bnx2x_set_234_gates()
9542 REG_WR(bp, shmem + validity_offset, 0); in bnx2x_reset_mcp_prep()
9602 REG_WR(bp, PXP2_REG_RD_START_INIT, 0); in bnx2x_pxp_prep()
9603 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0); in bnx2x_pxp_prep()
9697 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_process_kill_chip_reset()
9700 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, in bnx2x_process_kill_chip_reset()
9706 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_process_kill_chip_reset()
9712 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); in bnx2x_process_kill_chip_reset()
9794 REG_WR(bp, MISC_REG_UNPREPARED, 0); in bnx2x_process_kill()
9820 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); in bnx2x_process_kill()
10363 REG_WR(bp, vals->umac_addr[port], 0); in bnx2x_prev_unload_close_umac()
10403 REG_WR(bp, vals->bmac_addr, wb_data[0]); in bnx2x_prev_unload_close_mac()
10404 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]); in bnx2x_prev_unload_close_mac()
10409 REG_WR(bp, vals->emac_addr, 0); in bnx2x_prev_unload_close_mac()
10416 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10418 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI, in bnx2x_prev_unload_close_mac()
10422 REG_WR(bp, vals->xmac_addr, 0); in bnx2x_prev_unload_close_mac()
10479 REG_WR(bp, addr, tmp_reg); in bnx2x_prev_unload_undi_inc()
10735 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0); in bnx2x_prev_unload_common()
10741 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); in bnx2x_prev_unload_common()
10775 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val); in bnx2x_prev_unload_common()
10777 REG_WR(bp, mac_vals.umac_addr[0], mac_vals.umac_val[0]); in bnx2x_prev_unload_common()
10779 REG_WR(bp, mac_vals.umac_addr[1], mac_vals.umac_val[1]); in bnx2x_prev_unload_common()
10781 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val); in bnx2x_prev_unload_common()
10783 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]); in bnx2x_prev_unload_common()
10784 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); in bnx2x_prev_unload_common()
10816 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB, in bnx2x_prev_unload()
10821 REG_WR(bp, hw_lock_reg, 0xffffffff); in bnx2x_prev_unload()
11899 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val); in bnx2x_get_hwinfo()
11900 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f); in bnx2x_get_hwinfo()
13162 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0); in bnx2x_init_dev()
13163 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0); in bnx2x_init_dev()
13164 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0); in bnx2x_init_dev()
13165 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0); in bnx2x_init_dev()
13168 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0); in bnx2x_init_dev()
13169 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0); in bnx2x_init_dev()
13170 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0); in bnx2x_init_dev()
13171 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0); in bnx2x_init_dev()
13179 REG_WR(bp, in bnx2x_init_dev()
14368 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1); in bnx2x_notify_link_changed()
14746 REG_WR(bp, scratch_offset + i, in bnx2x_drv_ctl()
15060 REG_WR(bp, pretend_reg, pretend_func_val); in bnx2x_pretend_func()
15084 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_ptp_task()
15115 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_set_rx_ts()
15216 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15218 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15238 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15240 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15248 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15250 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15258 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15260 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15269 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp_filters()
15271 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp_filters()
15282 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp_filters()
15327 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
15329 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
15331 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK : in bnx2x_configure_ptp()
15333 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK : in bnx2x_configure_ptp()
15337 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST : in bnx2x_configure_ptp()
15341 REG_WR(bp, port ? NIG_REG_P1_PTP_EN : in bnx2x_configure_ptp()
15357 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID : in bnx2x_configure_ptp()
15359 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID : in bnx2x_configure_ptp()