102 	REG_WR(bp, igu_addr_data, cmd_data.sb_id_and_flags);  in bnx2x_vf_igu_ack_sb()
108 	REG_WR(bp, igu_addr_ctl, ctl);  in bnx2x_vf_igu_ack_sb()
700 	REG_WR(bp, PGLUE_B_REG_INTERNAL_VFID_ENABLE, enable ? 1 : 0);  in bnx2x_vf_enable_internal()
706 	REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
707 	REG_WR(bp, USEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
708 	REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
709 	REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, abs_vfid);  in bnx2x_vf_semi_clear_err()
731 	REG_WR(bp, was_err_reg, 1 << (abs_vfid & 0x1f));  in bnx2x_vf_pglue_clear_err()
742 	REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);  in bnx2x_vf_igu_reset()
743 	REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);  in bnx2x_vf_igu_reset()
744 	REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);  in bnx2x_vf_igu_reset()
745 	REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);  in bnx2x_vf_igu_reset()
746 	REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);  in bnx2x_vf_igu_reset()
747 	REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);  in bnx2x_vf_igu_reset()
753 	REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);  in bnx2x_vf_igu_reset()
766 		REG_WR(bp, IGU_REG_PROD_CONS_MEMORY + igu_sb_id * 4, 0);  in bnx2x_vf_igu_reset()
802 	REG_WR(bp, PBF_REG_DISABLE_VF, 0);  in bnx2x_vf_enable_traffic()
1004 	REG_WR(bp, DORQ_REG_VF_NORM_VF_BASE, 0);  in bnx2x_iov_init_dq()
1005 	REG_WR(bp, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS));  in bnx2x_iov_init_dq()
1010 	REG_WR(bp, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID);  in bnx2x_iov_init_dq()
1013 	REG_WR(bp, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND);  in bnx2x_iov_init_dq()
1018 	REG_WR(bp, DORQ_REG_VF_NORM_CID_OFST, 3);  in bnx2x_iov_init_dq()
1024 	REG_WR(bp, DORQ_REG_VF_TYPE_MASK_0, 1);  in bnx2x_iov_init_dq()
1025 	REG_WR(bp, DORQ_REG_VF_TYPE_VALUE_0, 0);  in bnx2x_iov_init_dq()
1026 	REG_WR(bp, DORQ_REG_VF_TYPE_MIN_MCID_0, 0);  in bnx2x_iov_init_dq()
1027 	REG_WR(bp, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff);  in bnx2x_iov_init_dq()
1032 	REG_WR(bp, DORQ_REG_VF_USAGE_CT_LIMIT, 64);  in bnx2x_iov_init_dq()
1038 		REG_WR(bp, DMAE_REG_BACKWARD_COMP_EN, 0);  in bnx2x_iov_init_dmae()
1955 	REG_WR(bp, reg, val);  in bnx2x_vf_qtbl_set_q()
1976 	REG_WR(bp, IGU_REG_VF_CONFIGURATION, val);  in bnx2x_vf_igu_disable()
2113 	REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT + vf->abs_vfid * 4 , 0);  in bnx2x_vf_init()
2469 			REG_WR(bp, address, igu_entry);  in bnx2x_enable_sriov()
2497 		REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,  in bnx2x_enable_sriov()