1/*
2 *  arch/cris/arch-v32/drivers/nandflash.c
3 *
4 *  Copyright (c) 2004
5 *
6 *  Derived from drivers/mtd/nand/spia.c
7 *	  Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/slab.h>
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/mtd/mtd.h>
19#include <linux/mtd/nand.h>
20#include <linux/mtd/partitions.h>
21#include <arch/memmap.h>
22#include <hwregs/reg_map.h>
23#include <hwregs/reg_rdwr.h>
24#include <hwregs/gio_defs.h>
25#include <hwregs/bif_core_defs.h>
26#include <asm/io.h>
27
28#define CE_BIT 4
29#define CLE_BIT 5
30#define ALE_BIT 6
31#define BY_BIT 7
32
33struct mtd_info_wrapper {
34	struct mtd_info info;
35	struct nand_chip chip;
36};
37
38/* Bitmask for control pins */
39#define PIN_BITMASK ((1 << CE_BIT) | (1 << CLE_BIT) | (1 << ALE_BIT))
40
41/* Bitmask for mtd nand control bits */
42#define CTRL_BITMASK (NAND_NCE | NAND_CLE | NAND_ALE)
43
44
45static struct mtd_info *crisv32_mtd;
46/*
47 *	hardware specific access to control-lines
48 */
49static void crisv32_hwcontrol(struct mtd_info *mtd, int cmd,
50			      unsigned int ctrl)
51{
52	unsigned long flags;
53	reg_gio_rw_pa_dout dout;
54	struct nand_chip *this = mtd->priv;
55
56	local_irq_save(flags);
57
58	/* control bits change */
59	if (ctrl & NAND_CTRL_CHANGE) {
60		dout = REG_RD(gio, regi_gio, rw_pa_dout);
61		dout.data &= ~PIN_BITMASK;
62
63#if (CE_BIT == 4 && NAND_NCE == 1 &&  \
64     CLE_BIT == 5 && NAND_CLE == 2 && \
65     ALE_BIT == 6 && NAND_ALE == 4)
66		/* Pins in same order as control bits, but shifted.
67		 * Optimize for this case; works for 2.6.18 */
68		dout.data |= ((ctrl & CTRL_BITMASK) ^ NAND_NCE) << CE_BIT;
69#else
70		/* the slow way */
71		if (!(ctrl & NAND_NCE))
72			dout.data |= (1 << CE_BIT);
73		if (ctrl & NAND_CLE)
74			dout.data |= (1 << CLE_BIT);
75		if (ctrl & NAND_ALE)
76			dout.data |= (1 << ALE_BIT);
77#endif
78		REG_WR(gio, regi_gio, rw_pa_dout, dout);
79	}
80
81	/* command to chip */
82	if (cmd != NAND_CMD_NONE)
83		writeb(cmd, this->IO_ADDR_W);
84
85	local_irq_restore(flags);
86}
87
88/*
89*	read device ready pin
90*/
91static int crisv32_device_ready(struct mtd_info *mtd)
92{
93	reg_gio_r_pa_din din = REG_RD(gio, regi_gio, r_pa_din);
94	return ((din.data & (1 << BY_BIT)) >> BY_BIT);
95}
96
97/*
98 * Main initialization routine
99 */
100struct mtd_info *__init crisv32_nand_flash_probe(void)
101{
102	void __iomem *read_cs;
103	void __iomem *write_cs;
104
105	reg_bif_core_rw_grp3_cfg bif_cfg = REG_RD(bif_core, regi_bif_core,
106		rw_grp3_cfg);
107	reg_gio_rw_pa_oe pa_oe = REG_RD(gio, regi_gio, rw_pa_oe);
108	struct mtd_info_wrapper *wrapper;
109	struct nand_chip *this;
110	int err = 0;
111
112	/* Allocate memory for MTD device structure and private data */
113	wrapper = kzalloc(sizeof(struct mtd_info_wrapper), GFP_KERNEL);
114	if (!wrapper) {
115		printk(KERN_ERR "Unable to allocate CRISv32 NAND MTD "
116			"device structure.\n");
117		err = -ENOMEM;
118		return NULL;
119	}
120
121	read_cs = ioremap(MEM_CSP0_START | MEM_NON_CACHEABLE, 8192);
122	write_cs = ioremap(MEM_CSP1_START | MEM_NON_CACHEABLE, 8192);
123
124	if (!read_cs || !write_cs) {
125		printk(KERN_ERR "CRISv32 NAND ioremap failed\n");
126		err = -EIO;
127		goto out_mtd;
128	}
129
130	/* Get pointer to private data */
131	this = &wrapper->chip;
132	crisv32_mtd = &wrapper->info;
133
134	pa_oe.oe |= 1 << CE_BIT;
135	pa_oe.oe |= 1 << ALE_BIT;
136	pa_oe.oe |= 1 << CLE_BIT;
137	pa_oe.oe &= ~(1 << BY_BIT);
138	REG_WR(gio, regi_gio, rw_pa_oe, pa_oe);
139
140	bif_cfg.gated_csp0 = regk_bif_core_rd;
141	bif_cfg.gated_csp1 = regk_bif_core_wr;
142	REG_WR(bif_core, regi_bif_core, rw_grp3_cfg, bif_cfg);
143
144	/* Link the private data with the MTD structure */
145	crisv32_mtd->priv = this;
146
147	/* Set address of NAND IO lines */
148	this->IO_ADDR_R = read_cs;
149	this->IO_ADDR_W = write_cs;
150	this->cmd_ctrl = crisv32_hwcontrol;
151	this->dev_ready = crisv32_device_ready;
152	/* 20 us command delay time */
153	this->chip_delay = 20;
154	this->ecc.mode = NAND_ECC_SOFT;
155
156	/* Enable the following for a flash based bad block table */
157	/* this->bbt_options = NAND_BBT_USE_FLASH; */
158
159	/* Scan to find existence of the device */
160	if (nand_scan(crisv32_mtd, 1)) {
161		err = -ENXIO;
162		goto out_ior;
163	}
164
165	return crisv32_mtd;
166
167out_ior:
168	iounmap((void *)read_cs);
169	iounmap((void *)write_cs);
170out_mtd:
171	kfree(wrapper);
172	return NULL;
173}
174
175