Lines Matching refs:REG_WR
231 REG_WR(bp, reg, val); in bnx2x_bits_en()
240 REG_WR(bp, reg, val); in bnx2x_bits_dis()
268 REG_WR(bp, params->lfa_base + in bnx2x_check_lfa()
387 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); in bnx2x_get_epio()
409 REG_WR(bp, MCP_REG_MCPR_GP_OUTPUTS, gp_output); in bnx2x_set_epio()
413 REG_WR(bp, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); in bnx2x_set_epio()
460 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
471 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
475 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
480 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
483 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
484 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
487 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
491 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
492 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
494 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
495 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
497 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
545 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
547 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
549 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
551 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
553 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
555 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
559 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
561 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
563 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, in bnx2x_ets_e3b0_set_credit_upper_bound_nig()
587 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
588 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
590 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
591 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
596 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : in bnx2x_ets_e3b0_nig_disabled()
603 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
604 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
607 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, in bnx2x_ets_e3b0_nig_disabled()
609 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
620 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
622 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
624 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_nig_disabled()
633 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : in bnx2x_ets_e3b0_nig_disabled()
635 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : in bnx2x_ets_e3b0_nig_disabled()
637 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : in bnx2x_ets_e3b0_nig_disabled()
639 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : in bnx2x_ets_e3b0_nig_disabled()
643 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : in bnx2x_ets_e3b0_nig_disabled()
646 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
647 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
648 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
681 REG_WR(bp, base_upper_bound + (i << 2), credit_upper_bound); in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
707 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
710 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
715 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
718 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
720 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : in bnx2x_ets_e3b0_pbf_disabled()
724 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_pbf_disabled()
727 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_pbf_disabled()
741 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
808 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : in bnx2x_ets_e3b0_cli_map()
811 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : in bnx2x_ets_e3b0_cli_map()
814 REG_WR(bp, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : in bnx2x_ets_e3b0_cli_map()
818 REG_WR(bp, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : in bnx2x_ets_e3b0_cli_map()
891 REG_WR(bp, nig_reg_adress_crd_weight, cos_bw_nig); in bnx2x_ets_e3b0_set_cos_bw()
893 REG_WR(bp, pbf_reg_adress_crd_weight, cos_bw_pbf); in bnx2x_ets_e3b0_set_cos_bw()
1115 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1118 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1124 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1126 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1129 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1249 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1256 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1258 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, in bnx2x_ets_bw_limit_common()
1260 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, in bnx2x_ets_bw_limit_common()
1264 REG_WR(bp, PBF_REG_ETS_ENABLED, 1); in bnx2x_ets_bw_limit_common()
1267 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1275 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1278 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1280 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, in bnx2x_ets_bw_limit_common()
1309 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); in bnx2x_ets_bw_limit()
1310 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); in bnx2x_ets_bw_limit()
1312 REG_WR(bp, PBF_REG_COS0_WEIGHT, cos0_credit_weight); in bnx2x_ets_bw_limit()
1313 REG_WR(bp, PBF_REG_COS1_WEIGHT, cos1_credit_weight); in bnx2x_ets_bw_limit()
1330 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1334 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1336 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1338 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1341 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); in bnx2x_ets_strict()
1351 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); in bnx2x_ets_strict()
1394 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1395 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1396 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1402 REG_WR(bp, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); in bnx2x_update_pfc_xmac()
1403 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); in bnx2x_update_pfc_xmac()
1404 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); in bnx2x_update_pfc_xmac()
1408 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_LO, in bnx2x_update_pfc_xmac()
1413 REG_WR(bp, xmac_base + XMAC_REG_CTRL_SA_HI, in bnx2x_update_pfc_xmac()
1449 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); in bnx2x_set_mdio_clk()
1487 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_init()
1490 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_emac_init()
1528 REG_WR(bp, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, in bnx2x_set_xumac_nig()
1530 REG_WR(bp, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, in bnx2x_set_xumac_nig()
1532 REG_WR(bp, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : in bnx2x_set_xumac_nig()
1552 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_set_umac_rxtx()
1562 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_umac_enable()
1566 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_umac_enable()
1572 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_umac_enable()
1605 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1611 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, in bnx2x_umac_enable()
1613 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1615 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1619 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR0, in bnx2x_umac_enable()
1624 REG_WR(bp, umac_base + UMAC_REG_MAC_ADDR1, in bnx2x_umac_enable()
1632 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1641 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, val); in bnx2x_umac_enable()
1646 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1677 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1681 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1687 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 1); in bnx2x_xmac_init()
1690 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1693 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1698 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 3); in bnx2x_xmac_init()
1703 REG_WR(bp, MISC_REG_XMAC_PHY_PORT_MODE, 1); in bnx2x_xmac_init()
1707 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_xmac_init()
1711 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_xmac_init()
1730 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1732 REG_WR(bp, xmac_base + XMAC_REG_PFC_CTRL_HI, in bnx2x_set_xmac_rxtx()
1740 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_set_xmac_rxtx()
1762 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1768 REG_WR(bp, xmac_base + XMAC_REG_RX_LSS_CTRL, in bnx2x_xmac_enable()
1771 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1772 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_xmac_enable()
1777 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1780 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1787 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1788 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1790 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1805 REG_WR(bp, xmac_base + XMAC_REG_CTRL, val); in bnx2x_xmac_enable()
1825 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_emac_enable()
1829 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); in bnx2x_emac_enable()
1839 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); in bnx2x_emac_enable()
1841 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); in bnx2x_emac_enable()
1846 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1915 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 1); in bnx2x_emac_enable()
1923 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1926 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1927 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1928 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1931 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1938 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_emac_enable()
1939 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1941 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
2105 REG_WR(bp, nig_reg_rx_priority_mask_add, priority_mask); in bnx2x_pfc_nig_rx_priority_mask()
2113 REG_WR(bp, params->shmem_base + in bnx2x_update_mng()
2123 REG_WR(bp, params->shmem2_base + in bnx2x_update_link_attr()
2177 REG_WR(bp, port ? NIG_REG_BRB1_PAUSE_IN_EN : in bnx2x_update_pfc_nig()
2179 REG_WR(bp, port ? NIG_REG_LLFC_OUT_EN_1 : in bnx2x_update_pfc_nig()
2181 REG_WR(bp, port ? NIG_REG_LLFC_ENABLE_1 : in bnx2x_update_pfc_nig()
2183 REG_WR(bp, port ? NIG_REG_PAUSE_ENABLE_1 : in bnx2x_update_pfc_nig()
2186 REG_WR(bp, port ? NIG_REG_PPP_ENABLE_1 : in bnx2x_update_pfc_nig()
2189 REG_WR(bp, port ? NIG_REG_LLH1_XCM_MASK : in bnx2x_update_pfc_nig()
2192 REG_WR(bp, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : in bnx2x_update_pfc_nig()
2196 REG_WR(bp, port ? NIG_REG_XCM1_OUT_EN : in bnx2x_update_pfc_nig()
2200 REG_WR(bp, port ? NIG_REG_P1_HWPFC_ENABLE : in bnx2x_update_pfc_nig()
2211 REG_WR(bp, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2215 REG_WR(bp, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : in bnx2x_update_pfc_nig()
2219 REG_WR(bp, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : in bnx2x_update_pfc_nig()
2273 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); in bnx2x_update_pfc()
2417 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_bmac_enable()
2422 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, in bnx2x_bmac_enable()
2426 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2434 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2435 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2441 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); in bnx2x_bmac_enable()
2442 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2443 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2444 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2445 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2446 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2487 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2511 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); in bnx2x_pbf_update()
2513 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2520 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2522 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, thresh); in bnx2x_pbf_update()
2534 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, init_crd); in bnx2x_pbf_update()
2539 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2541 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2544 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2607 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_write()
2614 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl22_write()
2629 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_write()
2643 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, in bnx2x_cl22_read()
2650 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl22_read()
2668 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); in bnx2x_cl22_read()
2695 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2716 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); in bnx2x_cl45_read()
2771 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2791 REG_WR(bp, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); in bnx2x_cl45_write()
2918 REG_WR(bp, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), in bnx2x_eee_set_timers()
2968 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2985 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
3009 REG_WR(bp, params->shmem2_base + in bnx2x_update_mng_eee()
3113 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3117 REG_WR(bp, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); in bnx2x_bsc_read()
3124 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3148 REG_WR(bp, MCP_REG_MCPR_IMC_COMMAND, val); in bnx2x_bsc_read()
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3324 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3326 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3329 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3341 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_serdes_deassert()
3343 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_serdes_deassert()
3347 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3359 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3360 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3377 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); in bnx2x_xgxs_deassert()
3379 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); in bnx2x_xgxs_deassert()
6124 REG_WR(bp, NIG_REG_LATCH_STATUS_0 + port*8, in bnx2x_rearm_latch_signal()
6272 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6293 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6335 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6336 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6366 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6367 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6387 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 1); in bnx2x_set_led()
6392 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6394 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6399 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6413 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, in bnx2x_set_led()
6417 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6420 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6423 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, in bnx2x_set_led()
6425 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + in bnx2x_set_led()
6437 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 in bnx2x_set_led()
6439 REG_WR(bp, NIG_REG_LED_CONTROL_TRAFFIC_P0 + in bnx2x_set_led()
6441 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + in bnx2x_set_led()
6622 REG_WR(params->bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, in bnx2x_int_link_reset()
6663 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_update_link_down()
6667 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6677 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), in bnx2x_update_link_down()
6679 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), in bnx2x_update_link_down()
6728 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + in bnx2x_update_link_up()
6730 REG_WR(bp, MISC_REG_CPMU_LP_DR_ENABLE, 1); in bnx2x_update_link_up()
6731 REG_WR(bp, MISC_REG_CPMU_LP_MASK_ENT_P0 + in bnx2x_update_link_up()
6767 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6798 REG_WR(bp, addr, val); in bnx2x_chng_link_count()
6860 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
7001 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, in bnx2x_link_update()
7088 REG_WR(bp, ver_addr, spirom_ver); in bnx2x_save_spirom_version()
8250 REG_WR(bp, sync_offset, media_types); in bnx2x_get_edc_mode()
8611 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8614 REG_WR(bp, MISC_REG_LCPLL_E40_PWRDWN, 1); in bnx2x_warpcore_hw_reset()
8615 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8616 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
11324 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); in bnx2x_54618se_config_loopback()
11329 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
12535 REG_WR(bp, sync_offset, media_types); in bnx2x_phy_probe()
12562 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_bmac_loopback()
12581 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_emac_loopback()
12607 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12622 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12672 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12685 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); in bnx2x_set_rx_filter()
12688 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, in bnx2x_set_rx_filter()
12692 REG_WR(bp, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : in bnx2x_set_rx_filter()
12731 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12735 REG_WR(bp, GRCBASE_MISC + in bnx2x_avoid_link_flap()
12759 REG_WR(bp, params->lfa_base + in bnx2x_avoid_link_flap()
12763 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12782 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12786 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12790 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12795 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12806 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12825 REG_WR(bp, params->lfa_base + in bnx2x_cannot_avoid_link_flap()
12939 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); in bnx2x_link_reset()
12943 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12944 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
12955 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
12994 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, in bnx2x_link_reset()
12996 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
12997 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
13003 REG_WR(bp, xmac_base + XMAC_REG_CTRL, in bnx2x_link_reset()
13023 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_lfa_reset()
13058 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
13204 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_8726_common_init_phy()
13470 REG_WR(bp, MISC_REG_GEN_PURP_HWG, val | 1); in bnx2x_common_init_phy()
13573 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); in bnx2x_analyze_link_error()
13586 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13635 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13636 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, in bnx2x_check_half_open_conn()
13927 REG_WR(bp, sync_offset, vars->aeu_int_mask); in bnx2x_init_mod_abs_int()
13940 REG_WR(bp, offset, aeu_mask); in bnx2x_init_mod_abs_int()
13945 REG_WR(bp, MISC_REG_GPIO_EVENT_EN, val); in bnx2x_init_mod_abs_int()