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Searched refs:PLL (Results 1 – 117 of 117) sorted by relevance

/linux-4.4.14/Documentation/dvb/
Dcards.txt14 tuner/PLL chips, and not all combinations are supported. Often
15 the demodulator and tuner/PLL chip are inside a metal box for
23 - cx24110 : Conexant HM1221/HM1811 (cx24110 or cx24106 demod, cx24108 PLL)
24 - grundig_29504-491 : Grundig 29504-491 (Philips TDA8083 demodulator), tsa5522 PLL
26 - stv0299 : Alps BSRU6 (tsa5059 PLL), LG TDQB-S00x (tsa5059 PLL),
27 LG TDQF-S001F (sl1935 PLL), Philips SU1278 (tua6100 PLL),
28 Philips SU1278SH (tsa5059 PLL), Samsung TBMU24112IMB, Technisat Sky2Pc with bios Rev. 2.6
30 - ves1820 : various (ves1820 demodulator, sp5659c or spXXXX PLL)
31 - at76c651 : Atmel AT76c651(B) with DAT7021 PLL
33 - alps_tdlb7 : Alps TDLB7 (sp8870 demodulator, sp5659 PLL)
[all …]
Dtechnisat.txt42 b.) => "Generic I2C PLL based tuners"
46 b.) => "Generic I2C PLL based tuners"
60 b.) => "Generic I2C PLL based tuners"
64 b.) => "Generic I2C PLL based tuners"
71 b.) => "Generic I2C PLL based tuners"
DREADME.dvb-usb99 PLL
/linux-4.4.14/drivers/clk/mediatek/
Dclk-mt8135.c604 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, _pd_shift, _tuner_reg,… macro
622 PLL(CLK_APMIXED_ARMPLL1, "armpll1", 0x200, 0x218, 0x80000001, 0, 21, 0x204, 24, 0x0, 0x204, 0),
623 PLL(CLK_APMIXED_ARMPLL2, "armpll2", 0x2cc, 0x2e4, 0x80000001, 0, 21, 0x2d0, 24, 0x0, 0x2d0, 0),
624 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x21c, 0x234, 0xf0000001, HAVE_RST_BAR, 21, 0x21c, 6, 0x0, 0x2…
625 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x238, 0x250, 0xf3000001, HAVE_RST_BAR, 7, 0x238, 6, 0x0, 0x23…
626 …PLL(CLK_APMIXED_MMPLL, "mmpll", 0x254, 0x26c, 0xf0000001, HAVE_RST_BAR, 21, 0x254, 6, 0x0, 0x258, …
627 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x278, 0x290, 0x80000001, 0, 21, 0x278, 6, 0x0, 0x27c, 0),
628 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x294, 0x2ac, 0x80000001, 0, 31, 0x294, 6, 0x0, 0x298, 0),
629 PLL(CLK_APMIXED_LVDSPLL, "lvdspll", 0x2b0, 0x2c8, 0x80000001, 0, 21, 0x2b0, 6, 0x0, 0x2b4, 0),
630 PLL(CLK_APMIXED_AUDPLL, "audpll", 0x2e8, 0x300, 0x80000001, 0, 31, 0x2e8, 6, 0x2f8, 0x2ec, 0),
[all …]
Dclk-mt8173.c1027 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ macro
1044 …PLL(CLK_APMIXED_ARMCA15PLL, "armca15pll", 0x200, 0x20c, 0x00000001, 0, 21, 0x204, 24, 0x0, 0x204, …
1045 PLL(CLK_APMIXED_ARMCA7PLL, "armca7pll", 0x210, 0x21c, 0x00000001, 0, 21, 0x214, 24, 0x0, 0x214, 0),
1046 …PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x220, 0x22c, 0xf0000101, HAVE_RST_BAR, 21, 0x220, 4, 0x0, 0x2…
1047 …PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x230, 0x23c, 0xfe000001, HAVE_RST_BAR, 7, 0x230, 4, 0x0, 0x23…
1049 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x250, 0x25c, 0x00000001, 0, 21, 0x250, 4, 0x0, 0x254, 0),
1050 PLL(CLK_APMIXED_VENCPLL, "vencpll", 0x260, 0x26c, 0x00000001, 0, 21, 0x260, 4, 0x0, 0x264, 0),
1051 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x270, 0x27c, 0x00000001, 0, 21, 0x270, 4, 0x0, 0x274, 0),
1052 PLL(CLK_APMIXED_MPLL, "mpll", 0x280, 0x28c, 0x00000001, 0, 21, 0x280, 4, 0x0, 0x284, 0),
1053 PLL(CLK_APMIXED_VCODECPLL, "vcodecpll", 0x290, 0x29c, 0x00000001, 0, 21, 0x290, 4, 0x0, 0x294, 0),
[all …]
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dbrcm,iproc-clocks.txt8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
22 clock control registers required for the PLL
25 The input parent clock phandle for the PLL. For most iProc PLLs, this is an
89 PLL and leaf clock compatible strings for Cygnus are:
96 The following table defines the set of PLL/clock index and ID for Cygnus.
136 PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
141 The following table defines the set of PLL/clock index and ID for Northstar and
166 PLL and leaf clock compatible strings for Northstar 2 are:
[all …]
Dvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
Dxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 Required properties for SoC or PCP PLL clocks:
14 - reg : shall be the physical PLL register address for the pll clock.
18 - clock-output-names : shall be the name of the PLL referenced by derive
20 Optional properties for PLL clocks:
21 - clock-names : shall be the name of the PLL. If missing, use the device name.
Dbrcm,bcm2835-cprman.txt8 oscillator, a level of PLL dividers that produce channels off of the
10 the PLL channels. Most other hardware components source from the
12 the PLL dividers directly.
Dqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
97 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
98 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
105 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
106 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
112 * 0 - equal to the PLL frequency
113 * 1 - equal to the PLL frequency divided by 2
114 * 2 - equal to the PLL frequency divided by 4
Dkeystone-pll.txt3 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
6 PLL is controlled by a PLL controller registers along with memory mapped
Dclk-s5pv210-audss.txt15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
16 not specified (i.e. xusbxti is used for PLL reference), it is fixed to
18 - fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
Dmoxa,moxart-clock.txt7 MOXA ART SoCs allow to determine PLL output and APB frequencies
11 PLL:
Daltr_socfpga.txt9 "altr,socfpga-pll-clock" - for a PLL clock
11 PLL clock.
Dst,nomadik.txt23 PLL nodes: these nodes represent the two PLLs on the system,
27 Required properties for the two PLL nodes:
Drenesas,h8s2678-pll-clock.txt1 Renesas H8S2678 PLL clock
Dclock-bindings.txt114 * and the high frequency switched PLL output for register
125 low-frequency reference clock, a PLL device to generate a higher frequency
129 * The PLL is both a clock provider and a clock consumer. It uses the clock
133 register clock connected to the PLL clock (the "pll-switched" signal)
Dti-keystone-pllctrl.txt5 the NETCP modules) requires a PLL Controller to manage the various clock
Dclk-exynos-audss.txt20 - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
22 - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
Dcalxeda.txt9 "calxeda,hb-pll-clock" - for a PLL clock
Dqca,ath79-pll.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
Dti,cdce706.txt1 Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
Dexynos5410-clock.txt25 - "fin_pll" - PLL input clock from XXTI
Dti,cdce925.txt37 /* PLL options to get SSC 1% centered */
Drenesas,r8a7779-cpg-clocks.txt3 The CPG generates core clocks for the R8A7779. It includes one PLL and
Dat91-clock.txt150 1 (AT91_PMC_LOCKA) -> PLL A ready
151 2 (AT91_PMC_LOCKB) -> PLL B ready
153 6 (AT91_PMC_LOCKU) -> UTMI PLL clock ready
289 0 -> PLL A
290 1 -> PLL B
Drenesas,rz-cpg-clocks.txt3 The CPG generates core clocks for the RZ SoCs. It includes the PLL, variable
Dmt8173-cpu-dvfs.txt8 source (usually MAINPLL) when the original CPU PLL is under
Dsamsung,s3c64xx-clock.txt31 - "fin_pll" - PLL input clock (xtal/extclk) - required,
Dsunxi.txt10 "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
11 "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
12 "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
Dexynos7-clock.txt20 - "fin_pll" - PLL input clock from XXTI
Dexynos5260-clock.txt20 - "fin_pll" - PLL input clock from XXTI
/linux-4.4.14/Documentation/devicetree/bindings/sound/
Dtas2552.txt18 internal 1.8MHz. This CLKIN is used by the PLL. In addition to PLL, the PDM
19 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
21 defined values to selct and configure the PLL and PDM reference clocks.
Dingenic,jz4740-i2s.txt6 - clocks : AIC and I2S PLL clock specifiers.
Dadi,adau1701.txt15 the ADAU's PLL config pins are connected to.
Dpcm512x.txt26 given pll-in pin and PLL output on the given pll-out pin. An
/linux-4.4.14/drivers/iio/frequency/
DKconfig5 # Phase-Locked Loop (PLL) frequency synthesizers
9 menu "Frequency Synthesizers DDS/PLL"
26 # Phase-Locked Loop (PLL) frequency synthesizers
29 menu "Phase-Locked Loop (PLL) frequency synthesizers"
/linux-4.4.14/drivers/clk/samsung/
Dclk-exynos5410.c171 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
173 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
175 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
177 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
179 [kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
Dclk-s5pv210.c757 [apll] = PLL(pll_4508, FOUT_APLL, "fout_apll", "fin_pll",
759 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
761 [epll] = PLL(pll_4600, FOUT_EPLL, "fout_epll", "fin_pll",
763 [vpll] = PLL(pll_4502, FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
769 [apll] = PLL(pll_4502, FOUT_APLL, "fout_apll", "fin_pll",
771 [mpll] = PLL(pll_4502, FOUT_MPLL, "fout_mpll", "fin_pll",
773 [epll] = PLL(pll_4500, FOUT_EPLL, "fout_epll", "fin_pll",
775 [vpll] = PLL(pll_4500, FOUT_VPLL, "fout_vpll", "fin_pll",
Dclk-exynos5420.c1225 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1227 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1229 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1231 [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1233 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1235 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1237 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1239 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1241 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1243 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
[all …]
Dclk-s3c2410.c197 [mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
199 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
263 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
265 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
Dclk-exynos4415.c913 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
915 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
917 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "mout_g3d_pllsrc",
919 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "fin_pll",
921 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll",
999 PLL(pll_35xx, CLK_DMC_FOUT_MPLL, "fout_mpll", "fin_pll",
1001 PLL(pll_35xx, CLK_DMC_FOUT_BPLL, "fout_bpll", "fin_pll",
Dclk-s3c2443.c224 [mpll] = PLL(pll_6552_s3c2416, 0, "mpll", "mpllref",
226 [epll] = PLL(pll_6553, 0, "epll", "epllref",
278 [mpll] = PLL(pll_3000, 0, "mpll", "mpllref",
280 [epll] = PLL(pll_2126, 0, "epll", "epllref",
Dclk-exynos3250.c729 PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
731 PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
733 PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
735 PLL(pll_35xx, CLK_FOUT_UPLL, "fout_upll", "fin_pll",
899 PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll",
901 PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
Dclk-exynos5250.c750 [bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
752 [gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,
754 [cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
756 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
758 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",
Dclk-exynos5260.c383 PLL(pll_2550xx, EGL_FOUT_EGL_PLL, "fout_egl_pll", "fin_pll",
635 PLL(pll_2550, G3D_FOUT_G3D_PLL, "fout_g3d_pll", "fin_pll",
953 PLL(pll_2550xx, KFC_FOUT_KFC_PLL, "fout_kfc_pll", "fin_pll",
1150 PLL(pll_2550xx, MIF_FOUT_MEM_PLL, "fout_mem_pll", "fin_pll",
1153 PLL(pll_2550xx, MIF_FOUT_BUS_PLL, "fout_bus_pll", "fin_pll",
1156 PLL(pll_2550xx, MIF_FOUT_MEDIA_PLL, "fout_media_pll", "fin_pll",
1817 PLL(pll_2550xx, TOP_FOUT_DISP_PLL, "fout_disp_pll", "fin_pll",
1820 PLL(pll_2650xx, TOP_FOUT_AUD_PLL, "fout_aud_pll", "fin_pll",
Dclk-s3c2412.c147 [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
149 [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
Dclk-exynos7.c178 PLL(pll_1451x, 0, "fout_bus0_pll", "fin_pll", BUS0_PLL_LOCK,
180 PLL(pll_1452x, 0, "fout_cc_pll", "fin_pll", CC_PLL_LOCK,
182 PLL(pll_1452x, 0, "fout_bus1_pll", "fin_pll", BUS1_DPLL_LOCK,
184 PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
186 PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
Dclk-s3c64xx.c367 [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
369 [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
371 [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
Dclk-exynos4.c1351 [apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",
1353 [mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",
1355 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll",
1357 [vpll] = PLL(pll_36xx, CLK_FOUT_VPLL, "fout_vpll", "fin_pll",
Dclk-exynos5433.c788 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
790 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
844 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
1049 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1051 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1053 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1055 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
2589 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
3282 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3577 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
[all …]
Dclk.h316 #define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \ macro
/linux-4.4.14/Documentation/arm/Samsung-S3C24XX/
DCPUfreq.txt15 PLL to feed the ARM, memory and peripherals via a series of dividers
17 newer version where there is a separate PLL and clock divider for the
26 system. Each CPU registers a driver to control the PLL, clock dividers
38 SoC and the driver as each device has different PLL and clock chains
45 The SLOW mode where the PLL is turned off altogether and the
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-bus-iio-frequency-adf43507 the fractional-N PLL. It is assumed that the algorithm
16 applications, the reference frequency used by the PLL may
21 down the PLL and its RFOut buffers during REFin changes.
Dsysfs-bus-iio475 a DDS or PLL should use out_altvoltage.
/linux-4.4.14/Documentation/devicetree/bindings/cpufreq/
Dtegra124-cpufreq.txt13 - pll_x: Fast PLL clocksource.
14 - pll_p: Auxiliary PLL used during fast PLL rate changes.
/linux-4.4.14/Documentation/devicetree/bindings/c6x/
Dclocks.txt1 C6X PLL Clock Controllers
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
/linux-4.4.14/arch/unicore32/kernel/
Dsleep.S103 @ prepare PMCR for PLL changing
106 @ prepare for closing PLL
122 @ change PLL
129 @ wait for PLL changing complete
138 @ close PLL
/linux-4.4.14/Documentation/devicetree/bindings/media/i2c/
Dadv7343.txt14 micro ampere level. All DACs and the internal PLL
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
17 internal PLL 1 circuit to be powered down and the
/linux-4.4.14/drivers/clk/meson/
Dmeson8b-clkc.c149 PLL(MESON8B_REG_PLL_FIXED, CLKID_PLL_FIXED, "fixed_pll",
151 PLL(MESON8B_REG_PLL_VID, CLKID_PLL_VID, "vid_pll",
153 PLL(MESON8B_REG_PLL_SYS, CLKID_PLL_SYS, "sys_pll",
Dclkc.h134 #define PLL(_ro, _ci, _cn, _cp, _f, _c) \ macro
/linux-4.4.14/arch/arm/boot/dts/
Dvexpress-v2p-ca15-tc1.dts130 /* CPU PLL reference clock */
148 /* HDLCD PLL reference clock */
166 /* SYS PLL reference clock */
175 /* DDR2 PLL reference clock */
Dvexpress-v2p-ca15_a7.dts231 /* A15 PLL 0 reference clock */
240 /* A15 PLL 1 reference clock */
249 /* A7 PLL 0 reference clock */
258 /* A7 PLL 1 reference clock */
276 /* HDLCD PLL reference clock */
294 /* SYS PLL reference clock */
303 /* DDR2 PLL reference clock */
Dbcm-cygnus-clock.dtsi44 /* Cygnus ARM PLL */
Dstih416-clock.dtsi498 * A9 PLL
726 * DDR PLL
742 * GPU PLL
Dstih407-clock.dtsi37 * A9 PLL.
Dstih410-clock.dtsi39 * A9 PLL.
Dstih418-clock.dtsi39 * A9 PLL.
Darmada-370-xp.dtsi326 /* 2 GHz fixed main PLL */
Darm-realview-pb1176.dts102 /* FIXME: this actually hangs off the PLL clocks */
Dstih415-clock.dtsi495 * A9 PLL
Darmada-39x.dtsi507 /* 2 GHz fixed main PLL */
Darmada-38x.dtsi624 /* 2 GHz fixed main PLL */
Darmada-375.dtsi68 /* 2 GHz fixed main PLL */
/linux-4.4.14/Documentation/devicetree/bindings/net/
Drockchip-dwmac.txt11 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
12 <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
24 is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
/linux-4.4.14/drivers/clk/rockchip/
Dclk-rk3188.c215 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
217 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
219 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
221 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
226 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
228 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
230 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),
232 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
Dclk-rk3368.c138 [apllb] = PLL(pll_rk3066, PLL_APLLB, "apllb", mux_pll_p, 0, RK3368_PLL_CON(0),
140 [aplll] = PLL(pll_rk3066, PLL_APLLL, "aplll", mux_pll_p, 0, RK3368_PLL_CON(4),
142 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
144 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
146 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
148 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3368_PLL_CON(20),
Dclk-rk3288.c204 [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK3288_PLL_CON(0),
206 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
208 [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3288_PLL_CON(8),
210 [gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3288_PLL_CON(12),
212 [npll] = PLL(pll_rk3066, PLL_NPLL, "npll", mux_pll_p, 0, RK3288_PLL_CON(16),
Dclk.h141 #define PLL(_type, _id, _name, _pnames, _flags, _con, _mode, _mshift, \ macro
/linux-4.4.14/drivers/gpu/drm/msm/
DKconfig37 bool "Enable DSI PLL driver in MSM DRM"
41 Choose this option to enable DSI PLL driver which provides DSI
/linux-4.4.14/drivers/media/common/b2c2/
Dflexcop-fe-tuner.c81 #if FE_SUPPORTED(MT312) && FE_SUPPORTED(PLL)
197 #if FE_SUPPORTED(STV0299) && FE_SUPPORTED(PLL)
421 #if FE_SUPPORTED(MT352) && FE_SUPPORTED(PLL)
476 #if FE_SUPPORTED(NXT200X) && FE_SUPPORTED(PLL)
519 #if FE_SUPPORTED(STV0297) && FE_SUPPORTED(PLL)
/linux-4.4.14/arch/arm/mach-s3c24xx/
DKconfig117 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
120 Compile in support for changing the PLL frequency from the
121 S3C24XX series CPUfreq driver. The PLL takes time to settle
124 This also means that the PLL tables for the selected CPU(s) will
166 Select the PLL table for the S3C2410
427 PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
434 PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
/linux-4.4.14/drivers/clk/
DKconfig116 Given a target output frequency, the driver will set the PLL and
155 Sypport for the APM X-Gene SoC reference, PLL, and device clocks.
189 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
/linux-4.4.14/Documentation/
DSM501.txt68 must be sourced from the same PLL, although they can then
71 attach if the PLL selection is different.
/linux-4.4.14/drivers/net/wireless/brcm80211/brcmsmac/
Daiutils.h104 #define PLL 0x2 /* main chip pll */ macro
/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Dmtk-sd.txt21 - assigned-clocks: PLL of the source clock
/linux-4.4.14/Documentation/devicetree/bindings/display/msm/
Dedp.txt6 - reg: Physical base address and length of the registers of controller and PLL
Ddsi.txt54 - reg: Physical base address and length of the registers of PLL, PHY and PHY
/linux-4.4.14/arch/blackfin/mach-bf533/
DKconfig29 int "PLL WAKEUP ERROR"
/linux-4.4.14/arch/blackfin/
DKconfig425 comment "Clock/PLL Setup"
451 bool "Bypass PLL"
460 If this is set the clock will be divided by 2, before it goes to the PLL.
475 This controls the frequency of the on-chip PLL. This can be between 1 and 64.
476 PLL Frequency = (Crystal Frequency) * (this setting)
484 Core Frequency = (PLL frequency) / (this setting)
509 System Clock = (PLL frequency) / (this setting)
540 DDR Clock = (PLL frequency) / (this setting)
1265 The PLL and system clock (SCLK) continue to operate at a very low
1280 The PLL and system clock (SCLK), however, continue to operate in
[all …]
/linux-4.4.14/drivers/clk/pistachio/
Dclk.h122 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ macro
/linux-4.4.14/Documentation/devicetree/bindings/clock/st/
Dst,quadfs.txt4 This version contains a programmable PLL which can generate up to 216, 432
/linux-4.4.14/Documentation/devicetree/bindings/pci/
Dnvidia,tegra20-pcie.txt71 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
79 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
99 - avdd-pex-pll-supply: Power supply for dedicated (internal) PCIe PLL. Must
Dlayerscape-pci.txt7 which is used to describe the PLL settings at the time of chip-reset.
/linux-4.4.14/Documentation/devicetree/bindings/display/ti/
Dti,dra7-dss.txt20 Some DRA7xx SoCs have one dedicated video PLL, some have two. These properties
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi-mt65xx.txt18 The first should be one of the following. It's PLL.
/linux-4.4.14/Documentation/sound/alsa/soc/
Dclocking.txt13 (e.g. crystal, PLL, CPU clock) and is responsible for producing the correct
/linux-4.4.14/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_400MHz_32MB21 # NOTE: Please change the master clock source from PLL-clock to Xin-clock
22 # and switch off PLL, before resetting the clock gear ratio.
Ddot.gdbinit_200MHz_16MB21 # NOTE: Please change the master clock source from PLL-clock to Xin-clock
22 # and switch off PLL, before resetting the clock gear ratio.
Ddot.gdbinit_300MHz_32MB21 # NOTE: Please change the master clock source from PLL-clock to Xin-clock
22 # and switch off PLL, before resetting the clock gear ratio.
/linux-4.4.14/Documentation/devicetree/bindings/ufs/
Dufs-qcom.txt17 - vdda-pll-supply : phandle to PHY PLL and Power-Gen block power supply
/linux-4.4.14/arch/arm/mach-sa1100/
Dsleep.S53 @ delay 90us and set CPU PLL to lowest speed
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dsamsung-mipi-csis.txt14 - vddio-supply : MIPI CSIS I/O and PLL voltage supply (e.g. 1.8V);
/linux-4.4.14/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt16 - adi,power-up-frequency: If set in Hz the PLL tunes to
/linux-4.4.14/Documentation/devicetree/bindings/display/exynos/
Dexynos_dsim.txt20 - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
/linux-4.4.14/arch/sh/include/mach-kfr2r09/mach/
Dpartner-jet-setup.txt30 LIST "The PLL and FLL values are updated here for the optimal"
/linux-4.4.14/arch/blackfin/mach-bf561/
DKconfig22 int "PLL Wakeup Interrupt"
/linux-4.4.14/drivers/staging/sm750fb/
Dddk750_chip.c215 ulReg = FIELD_SET(ulReg, VGA_CONFIGURATION, PLL, PANEL); in ddk750_initHw()
/linux-4.4.14/drivers/media/dvb-frontends/
DKconfig207 tristate "Infineon TUA6100 PLL"
211 A DVB-S PLL chip.
689 comment "Digital terrestrial only tuners/PLL"
693 tristate "Generic I2C PLL based tuners"
697 This module drives a number of tuners based on PLL chips with a
/linux-4.4.14/Documentation/power/
Ds2ram.txt62 PLL's, and it just _hangs_. Using the regular VGA console and letting X
/linux-4.4.14/arch/m68k/
DKconfig.cpu444 PLL and can have their frequency programmed at run time, others
445 use internal dividers. In general the kernel won't setup a PLL
/linux-4.4.14/Documentation/video4linux/bttv/
DInsmod-options16 0: don't use PLL
/linux-4.4.14/arch/m32r/platforms/mappi/
Ddot.gdbinit.smp85 # PLL
/linux-4.4.14/Documentation/sound/alsa/
Dhdspm.txt163 RME-PLL is very good, there are almost no problems with
/linux-4.4.14/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-host1x.txt141 - pll-supply: regulator for PLL
/linux-4.4.14/drivers/scsi/aic7xxx/
Daic79xx.reg534 * PCI PLL Delay.
/linux-4.4.14/
DMAINTAINERS804 APTINA CAMERA SENSOR PLL