1Qualcomm Technologies Inc. adreno/snapdragon DSI output
2
3DSI Controller:
4Required properties:
5- compatible:
6  * "qcom,mdss-dsi-ctrl"
7- reg: Physical base address and length of the registers of controller
8- reg-names: The names of register regions. The following regions are required:
9  * "dsi_ctrl"
10- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
11  be 0 or 1, since we have 2 DSI controllers at most for now.
12- interrupts: The interrupt signal from the DSI block.
13- power-domains: Should be <&mmcc MDSS_GDSC>.
14- clocks: device clocks
15  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
16- clock-names: the following clocks are required:
17  * "bus_clk"
18  * "byte_clk"
19  * "core_clk"
20  * "core_mmss_clk"
21  * "iface_clk"
22  * "mdp_core_clk"
23  * "pixel_clk"
24- vdd-supply: phandle to vdd regulator device node
25- vddio-supply: phandle to vdd-io regulator device node
26- vdda-supply: phandle to vdda regulator device node
27- qcom,dsi-phy: phandle to DSI PHY device node
28
29Optional properties:
30- panel@0: Node of panel connected to this DSI controller.
31  See files in Documentation/devicetree/bindings/display/panel/ for each supported
32  panel.
33- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
34  driving a panel which needs 2 DSI links.
35- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
36  the master link of the 2-DSI panel.
37- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
38  driving a 2-DSI panel whose 2 links need receive command simultaneously.
39- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
40  through MDP block
41- pinctrl-names: the pin control state names; should contain "default"
42- pinctrl-0: the default pinctrl state (active)
43- pinctrl-n: the "sleep" pinctrl state
44- port: DSI controller output port. This contains one endpoint subnode, with its
45  remote-endpoint set to the phandle of the connected panel's endpoint.
46  See Documentation/devicetree/bindings/graph.txt for device graph info.
47
48DSI PHY:
49Required properties:
50- compatible: Could be the following
51  * "qcom,dsi-phy-28nm-hpm"
52  * "qcom,dsi-phy-28nm-lp"
53  * "qcom,dsi-phy-20nm"
54- reg: Physical base address and length of the registers of PLL, PHY and PHY
55  regulator
56- reg-names: The names of register regions. The following regions are required:
57  * "dsi_pll"
58  * "dsi_phy"
59  * "dsi_phy_regulator"
60- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
61  be 0 or 1, since we have 2 DSI PHYs at most for now.
62- power-domains: Should be <&mmcc MDSS_GDSC>.
63- clocks: device clocks
64  See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
65- clock-names: the following clocks are required:
66  * "iface_clk"
67- vddio-supply: phandle to vdd-io regulator device node
68
69Optional properties:
70- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
71  regulator is wanted.
72
73Example:
74	mdss_dsi0: qcom,mdss_dsi@fd922800 {
75		compatible = "qcom,mdss-dsi-ctrl";
76		qcom,dsi-host-index = <0>;
77		interrupt-parent = <&mdss_mdp>;
78		interrupts = <4 0>;
79		reg-names = "dsi_ctrl";
80		reg = <0xfd922800 0x200>;
81		power-domains = <&mmcc MDSS_GDSC>;
82		clock-names =
83			"bus_clk",
84			"byte_clk",
85			"core_clk",
86			"core_mmss_clk",
87			"iface_clk",
88			"mdp_core_clk",
89			"pixel_clk";
90		clocks =
91			<&mmcc MDSS_AXI_CLK>,
92			<&mmcc MDSS_BYTE0_CLK>,
93			<&mmcc MDSS_ESC0_CLK>,
94			<&mmcc MMSS_MISC_AHB_CLK>,
95			<&mmcc MDSS_AHB_CLK>,
96			<&mmcc MDSS_MDP_CLK>,
97			<&mmcc MDSS_PCLK0_CLK>;
98		vdda-supply = <&pma8084_l2>;
99		vdd-supply = <&pma8084_l22>;
100		vddio-supply = <&pma8084_l12>;
101
102		qcom,dsi-phy = <&mdss_dsi_phy0>;
103
104		qcom,dual-dsi-mode;
105		qcom,master-dsi;
106		qcom,sync-dual-dsi;
107
108		pinctrl-names = "default", "sleep";
109		pinctrl-0 = <&mdss_dsi_active>;
110		pinctrl-1 = <&mdss_dsi_suspend>;
111
112		panel: panel@0 {
113			compatible = "sharp,lq101r1sx01";
114			reg = <0>;
115			link2 = <&secondary>;
116
117			power-supply = <...>;
118			backlight = <...>;
119
120			port {
121				panel_in: endpoint {
122					remote-endpoint = <&dsi0_out>;
123				};
124			};
125		};
126
127		port {
128			dsi0_out: endpoint {
129				remote-endpoint = <&panel_in>;
130			};
131		};
132	};
133
134	mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
135		compatible = "qcom,dsi-phy-28nm-hpm";
136		qcom,dsi-phy-index = <0>;
137		reg-names =
138			"dsi_pll",
139			"dsi_phy",
140			"dsi_phy_regulator";
141		reg =   <0xfd922a00 0xd4>,
142			<0xfd922b00 0x2b0>,
143			<0xfd922d80 0x7b>;
144		clock-names = "iface_clk";
145		clocks = <&mmcc MDSS_AHB_CLK>;
146		vddio-supply = <&pma8084_l12>;
147
148		qcom,dsi-phy-regulator-ldo-mode;
149	};
150