Searched refs:c7 (Results 1 - 94 of 94) sorted by relevance

/linux-4.1.27/arch/arm/mm/
H A Dproc-arm1020.S99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
159 mcr p15, 0, ip, c7, c10, 4 @ drain WB
167 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
169 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
189 mcr p15, 0, ip, c7, c10, 4
190 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
191 mcr p15, 0, ip, c7, c10, 4 @ drain WB
198 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
200 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
229 mcr p15, 0, ip, c7, c10, 4
232 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
233 mcr p15, 0, ip, c7, c10, 4 @ drain WB
236 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
241 mcr p15, 0, ip, c7, c10, 4 @ drain WB
258 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
259 mcr p15, 0, ip, c7, c10, 4 @ drain WB
264 mcr p15, 0, ip, c7, c10, 4 @ drain WB
285 mcrne p15, 0, ip, c7, c10, 4
286 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
287 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
289 mcrne p15, 0, ip, c7, c10, 4
290 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
291 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
292 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
297 mcr p15, 0, ip, c7, c10, 4 @ drain WB
314 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
315 mcr p15, 0, ip, c7, c10, 4 @ drain WB
320 mcr p15, 0, ip, c7, c10, 4 @ drain WB
335 mcr p15, 0, ip, c7, c10, 4
336 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
337 mcr p15, 0, ip, c7, c10, 4 @ drain WB
342 mcr p15, 0, ip, c7, c10, 4 @ drain WB
379 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
380 mcr p15, 0, ip, c7, c10, 4 @ drain WB
400 mcr p15, 0, r3, c7, c10, 4
405 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
407 mcr p15, 0, ip, c7, c10, 4
418 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
420 mcr p15, 0, r1, c7, c10, 4 @ drain WB
422 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
437 mcr p15, 0, r0, c7, c10, 4
438 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
440 mcr p15, 0, r0, c7, c10, 4 @ drain WB
447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
448 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
450 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm946.S61 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
62 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
63 mcr p15, 0, ip, c7, c10, 4 @ drain WB
77 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
87 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
107 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
111 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
118 mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
119 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
141 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
142 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
145 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
148 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
149 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
187 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
188 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
192 mcr p15, 0, r0, c7, c10, 4 @ drain WB
208 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
213 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
214 mcr p15, 0, r0, c7, c10, 4 @ drain WB
232 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
234 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
237 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
241 mcr p15, 0, r0, c7, c10, 4 @ drain WB
257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
262 mcr p15, 0, r0, c7, c10, 4 @ drain WB
279 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
281 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
286 mcr p15, 0, r0, c7, c10, 4 @ drain WB
321 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
326 mcr p15, 0, r0, c7, c10, 4 @ drain WB
332 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
333 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
334 mcr p15, 0, r0, c7, c10, 4 @ drain WB
340 mcr p15, 0, r0, c6, c7, 0
H A Dcache-v6.S43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
137 USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
144 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
146 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
151 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
180 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
182 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
189 mcr p15, 0, r0, c7, c10, 4
212 mcrne p15, 0, r0, c7, c10, 1 @ clean D line
214 mcrne p15, 0, r0, c7, c11, 1 @ clean unified line
223 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D line
225 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
229 mcr p15, 0, r0, c7, c6, 1 @ invalidate D line
231 mcr p15, 0, r0, c7, c7, 1 @ invalidate unified line
241 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
256 mcr p15, 0, r0, c7, c10, 1 @ clean D line
258 mcr p15, 0, r0, c7, c11, 1 @ clean unified line
264 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
280 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
282 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
292 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
H A Dproc-arm926.S83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
84 mcr p15, 0, ip, c7, c10, 4 @ drain WB
86 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
105 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
148 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
176 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
177 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
180 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
181 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
183 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
184 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
218 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
219 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
223 mcr p15, 0, r0, c7, c10, 4 @ drain WB
238 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
243 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
263 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
265 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
268 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
272 mcr p15, 0, r0, c7, c10, 4 @ drain WB
288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
293 mcr p15, 0, r0, c7, c10, 4 @ drain WB
308 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
310 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
315 mcr p15, 0, r0, c7, c10, 4 @ drain WB
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
355 mcr p15, 0, r0, c7, c10, 4 @ drain WB
372 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
375 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
378 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
379 mcr p15, 0, ip, c7, c10, 4 @ drain WB
381 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
396 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
398 mcr p15, 0, r0, c7, c10, 4 @ drain WB
417 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
418 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
432 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
434 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dcache-fa.S48 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
69 mcr p15, 0, ip, c7, c14, 0 @ clean/invalidate D cache
71 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
72 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
73 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
74 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
95 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
100 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
101 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
102 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
130 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
131 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
136 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB
137 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
138 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
152 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
158 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
175 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
178 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D entry
179 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
184 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
197 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
202 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
212 1: mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D entry
217 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
H A Dproc-arm925.S123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
143 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
157 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
180 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
184 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
189 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
210 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
211 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
214 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
217 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
218 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
221 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
227 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
255 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
256 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
260 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
280 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
300 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
302 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
305 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
309 mcr p15, 0, r0, c7, c10, 4 @ drain WB
325 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
330 mcr p15, 0, r0, c7, c10, 4 @ drain WB
345 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
347 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
352 mcr p15, 0, r0, c7, c10, 4 @ drain WB
387 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
392 mcr p15, 0, r0, c7, c10, 4 @ drain WB
409 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
413 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
417 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
418 mcr p15, 0, ip, c7, c10, 4 @ drain WB
420 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
435 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
437 mcr p15, 0, r0, c7, c10, 4 @ drain WB
450 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
451 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
453 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm1022.S90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
156 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
178 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
185 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
187 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
218 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
226 mcr p15, 0, ip, c7, c10, 4 @ drain WB
243 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
248 mcr p15, 0, ip, c7, c10, 4 @ drain WB
269 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
271 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
272 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
277 mcr p15, 0, ip, c7, c10, 4 @ drain WB
294 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
299 mcr p15, 0, ip, c7, c10, 4 @ drain WB
314 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
319 mcr p15, 0, ip, c7, c10, 4 @ drain WB
356 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
378 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
386 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
388 mcr p15, 0, r1, c7, c10, 4 @ drain WB
390 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
405 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
414 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
416 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm1026.S90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
91 mcr p15, 0, ip, c7, c10, 4 @ drain WB
93 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
108 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
123 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
151 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
173 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
180 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
182 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
212 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
215 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
220 mcr p15, 0, ip, c7, c10, 4 @ drain WB
237 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
242 mcr p15, 0, ip, c7, c10, 4 @ drain WB
263 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
265 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
266 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
271 mcr p15, 0, ip, c7, c10, 4 @ drain WB
288 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
293 mcr p15, 0, ip, c7, c10, 4 @ drain WB
308 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
313 mcr p15, 0, ip, c7, c10, 4 @ drain WB
350 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
371 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
375 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
377 mcr p15, 0, r1, c7, c10, 4 @ drain WB
379 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
394 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
403 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
405 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-mohawk.S75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
76 mcr p15, 0, ip, c7, c10, 4 @ drain WB
77 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
94 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
95 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
105 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
129 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
130 mcrne p15, 0, ip, c7, c10, 0 @ drain write buffer
151 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
152 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
154 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
155 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
160 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
190 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
191 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
195 mcr p15, 0, r0, c7, c10, 4 @ drain WB
210 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
215 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
216 mcr p15, 0, r0, c7, c10, 4 @ drain WB
234 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
236 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
238 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
242 mcr p15, 0, r0, c7, c10, 4 @ drain WB
257 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
279 mcr p15, 0, r0, c7, c10, 4 @ drain WB
313 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
317 mcr p15, 0, r0, c7, c10, 4 @ drain WB
330 mcr p15, 0, ip, c7, c14, 0 @ clean & invalidate all D cache
331 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
332 mcr p15, 0, ip, c7, c10, 4 @ drain WB
335 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
347 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB
370 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
371 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
372 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
373 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
390 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
391 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs
H A Dcopypage-feroceon.c33 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
37 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
41 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
45 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
49 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
53 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
57 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
61 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_copy_user_page()
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB\n\ feroceon_copy_user_page()
98 mcr p15, 0, %0, c7, c14, 1 @ clean and invalidate D line\n\ feroceon_clear_user_highpage()
101 mcr p15, 0, r1, c7, c10, 4 @ drain WB" feroceon_clear_user_highpage()
H A Dproc-arm920.S91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
92 mcr p15, 0, ip, c7, c10, 4 @ drain WB
94 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
109 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
122 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
146 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
152 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
153 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
172 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
174 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
179 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
207 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
208 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
212 mcr p15, 0, r0, c7, c10, 4 @ drain WB
227 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
233 mcr p15, 0, r0, c7, c10, 4 @ drain WB
252 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
254 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
255 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
259 mcr p15, 0, r0, c7, c10, 4 @ drain WB
274 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
278 mcr p15, 0, r0, c7, c10, 4 @ drain WB
291 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
295 mcr p15, 0, r0, c7, c10, 4 @ drain WB
331 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
351 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
359 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
365 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
366 mcr p15, 0, ip, c7, c10, 4 @ drain WB
368 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
382 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
383 mcr p15, 0, r0, c7, c10, 4 @ drain WB
402 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
403 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
417 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
419 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-fa526.S63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
64 mcr p15, 0, ip, c7, c10, 4 @ drain WB
66 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
88 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
92 mcr p15, 0, r0, c7, c10, 4 @ drain WB
109 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
111 mcr p15, 0, ip, c7, c14, 0 @ clean and invalidate whole D cache
113 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
114 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
115 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
116 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
118 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
132 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
134 mcr p15, 0, r0, c7, c10, 4 @ drain WB
142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
143 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
145 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
147 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
153 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
154 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
155 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
H A Dproc-arm922.S93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
94 mcr p15, 0, ip, c7, c10, 4 @ drain WB
96 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
111 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
124 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
148 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
154 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
174 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
176 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
181 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
209 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
214 mcr p15, 0, r0, c7, c10, 4 @ drain WB
229 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
234 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
235 mcr p15, 0, r0, c7, c10, 4 @ drain WB
254 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
256 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
257 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
261 mcr p15, 0, r0, c7, c10, 4 @ drain WB
276 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
280 mcr p15, 0, r0, c7, c10, 4 @ drain WB
293 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
297 mcr p15, 0, r0, c7, c10, 4 @ drain WB
334 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
355 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
363 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
369 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
370 mcr p15, 0, ip, c7, c10, 4 @ drain WB
372 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
386 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
387 mcr p15, 0, r0, c7, c10, 4 @ drain WB
394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
395 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
397 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-arm1020e.S99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
100 mcr p15, 0, ip, c7, c10, 4 @ drain WB
102 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
117 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
132 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
155 mcr p15, 0, ip, c7, c10, 4 @ drain WB
158 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
166 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
168 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
188 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
195 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
197 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
227 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
235 mcr p15, 0, ip, c7, c10, 4 @ drain WB
252 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
257 mcr p15, 0, ip, c7, c10, 4 @ drain WB
278 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
280 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
281 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
286 mcr p15, 0, ip, c7, c10, 4 @ drain WB
303 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
308 mcr p15, 0, ip, c7, c10, 4 @ drain WB
323 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
328 mcr p15, 0, ip, c7, c10, 4 @ drain WB
365 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
385 mcr p15, 0, r3, c7, c10, 4
390 mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
402 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
404 mcr p15, 0, r1, c7, c10, 4 @ drain WB
406 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
421 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
430 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
432 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-feroceon.S82 mcr p15, 0, r0, c7, c10, 4 @ drain WB
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
105 mcr p15, 0, ip, c7, c10, 4 @ drain WB
107 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
125 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
126 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
136 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
162 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
170 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
171 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
190 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
191 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
193 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
194 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
200 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
229 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
230 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
234 mcr p15, 0, r0, c7, c10, 4 @ drain WB
250 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
255 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
256 mcr p15, 0, r0, c7, c10, 4 @ drain WB
269 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
270 mcr p15, 0, r0, c7, c10, 4 @ drain WB
290 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
292 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
293 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
297 mcr p15, 0, r0, c7, c10, 4 @ drain WB
304 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
306 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
329 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
333 mcr p15, 0, r0, c7, c10, 4 @ drain WB
346 mcr p15, 0, r0, c7, c10, 4 @ drain WB
360 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
364 mcr p15, 0, r0, c7, c10, 4 @ drain WB
377 mcr p15, 0, r0, c7, c10, 4 @ drain WB
452 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
463 mcr p15, 0, r0, c7, c10, 4 @ drain WB
488 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
489 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
492 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
508 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
513 mcr p15, 0, r0, c7, c10, 4 @ drain WB
532 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
533 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
546 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
547 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
549 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dproc-sa110.S68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
69 mcr p15, 0, ip, c7, c10, 4 @ drain WB
71 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
120 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
141 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
157 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
158 mcr p15, 0, r0, c7, c10, 4 @ drain WB
165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
166 mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4
168 mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4
H A Dcopypage-fa.c28 mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_copy_user_page()
32 mcr p15, 0, r0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_copy_user_page()
36 mcr p15, 0, r2, c7, c10, 4 @ 1 drain WB\n\ fa_copy_user_page()
69 mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_clear_user_highpage()
72 mcr p15, 0, %0, c7, c14, 1 @ 1 clean and invalidate D line\n\ fa_clear_user_highpage()
76 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" fa_clear_user_highpage()
H A Dproc-arm940.S54 mcr p15, 0, ip, c7, c5, 0 @ flush I cache
55 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
56 mcr p15, 0, ip, c7, c10, 4 @ drain WB
70 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
80 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
112 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
116 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
123 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
124 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
166 2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
171 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
172 mcr p15, 0, r0, c7, c10, 4 @ drain WB
188 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
193 mcr p15, 0, ip, c7, c10, 4 @ drain WB
211 2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
217 mcr p15, 0, ip, c7, c10, 4 @ drain WB
235 mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
237 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
243 mcr p15, 0, ip, c7, c10, 4 @ drain WB
279 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
280 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
281 mcr p15, 0, r0, c7, c10, 4 @ drain WB
287 mcr p15, 0, r0, c6, c7, 0
293 mcr p15, 0, r0, c6, c7, 1
H A Dproc-xscale.S94 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
96 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
98 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
100 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
162 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
181 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
193 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
217 mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
218 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
239 mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line
240 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
241 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
246 mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB
247 mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
265 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
270 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
271 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
286 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
287 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
292 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
293 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
307 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
308 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
313 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
314 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
331 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
333 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
334 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
338 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
351 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
355 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
368 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
369 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
373 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
457 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
475 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
476 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
478 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
548 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
549 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
563 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
564 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
565 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
H A Dproc-xsc3.S71 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
121 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
140 mcr p14, 0, r0, c7, c0, 0 @ go to idle
152 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
176 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
177 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
178 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
199 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
200 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
205 mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
206 mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
207 mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
227 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
232 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
233 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
234 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
248 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
253 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
254 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
255 mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
272 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
274 mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
275 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
279 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
292 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
296 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
309 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
313 mcr p15, 0, r0, c7, c10, 4 @ data write barrier
347 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
365 mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
366 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
367 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
370 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
433 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
434 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
435 mcr p15, 0, ip, c7, c5, 4 @ flush prefetch buffer
436 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
453 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
454 mcr p15, 0, ip, c7, c10, 4 @ data write barrier
455 mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
456 mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
H A Dcache-v4wb.S61 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
80 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
97 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
114 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
119 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
120 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
125 mcrne p15, 0, ip, c7, c10, 4 @ drain write buffer
166 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
167 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
172 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
173 mcr p15, 0, r0, c7, c10, 4 @ drain WB
191 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
193 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
194 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
198 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
211 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
215 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
H A Dtlb-v6.S40 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
53 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
58 mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
71 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
81 mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
86 mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
87 mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
H A Dproc-sa1100.S76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
77 mcr p15, 0, ip, c7, c10, 4 @ drain WB
79 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
130 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
152 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
168 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
169 mcr p15, 0, r0, c7, c10, 4 @ drain WB
188 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
189 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
205 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
207 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
H A Dcopypage-v4wb.c32 1: mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_copy_user_page()
37 mcr p15, 0, r0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_copy_user_page()
44 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB\n\ v4wb_copy_user_page()
77 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_clear_user_highpage()
80 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4wb_clear_user_highpage()
85 mcr p15, 0, r1, c7, c10, 4 @ 1 drain WB" v4wb_clear_user_highpage()
H A Dcopypage-xscale.c66 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ mc_copy_user_page()
68 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ mc_copy_user_page()
77 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ mc_copy_user_page()
79 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ mc_copy_user_page()
122 mcr p15, 0, ip, c7, c10, 1 @ clean D line\n\ xscale_mc_clear_user_highpage()
124 mcr p15, 0, ip, c7, c6, 1 @ invalidate D line\n\ xscale_mc_clear_user_highpage()
H A Dcache-v4wt.S51 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
73 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
74 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
92 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
94 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
125 1: mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
143 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache
160 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dcopypage-v4wt.c40 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ v4wt_copy_user_page()
78 mcr p15, 0, r2, c7, c7, 0 @ flush ID cache" v4wt_clear_user_highpage()
H A Dproc-v6.S64 mcr p15, 0, r1, c7, c5, 4 @ ISB
78 mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
79 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
83 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
105 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
106 mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
156 mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
157 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
158 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
159 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
173 mcr p15, 0, ip, c7, c5, 4 @ ISB
208 mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
209 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
210 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
212 mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
220 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
H A Dproc-arm720.S80 mcr p15, 0, r1, c7, c7, 0 @ invalidate cache
82 mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4)
107 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
109 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
124 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
152 mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4)
H A Dcache-v7.S58 mcr p15, 0, r5, c7, c6, 2
77 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
78 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
157 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
190 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
191 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
208 ALT_SMP(mcr p15, 0, r0, c7, c1, 0) @ invalidate I-cache inner shareable
209 ALT_UP(mcr p15, 0, r0, c7, c5, 0) @ I+BTB cache invalidate
281 USER( mcr p15, 0, r12, c7, c11, 1 ) @ clean D line to the point of unification
290 USER( mcr p15, 0, r12, c7, c5, 1 ) @ invalidate I line
295 ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
296 ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
334 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
361 mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
365 mcrne p15, 0, r1, c7, c14, 1 @ clean & invalidate D / U line
367 mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
389 mcr p15, 0, r0, c7, c10, 1 @ clean D / U line
411 mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
H A Dcopypage-xsc3.c47 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ xsc3_mc_copy_user_page()
57 mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\ xsc3_mc_copy_user_page()
98 1: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\ xsc3_mc_clear_user_highpage()
H A Dcopypage-v4mc.c50 1: mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ mc_copy_user_page()
55 mcr p15, 0, %1, c7, c6, 1 @ 1 invalidate D line\n\ mc_copy_user_page()
98 1: mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4_mc_clear_user_highpage()
101 mcr p15, 0, %0, c7, c6, 1 @ 1 invalidate D line\n\ v4_mc_clear_user_highpage()
H A Dcache-xsc3l2.c45 __asm__("mcr p15, 1, %0, c7, c11, 1" : : "r" (addr)); xsc3_l2_clean_mva()
50 __asm__("mcr p15, 1, %0, c7, c7, 1" : : "r" (addr)); xsc3_l2_inv_mva()
63 __asm__("mcr p15, 1, %0, c7, c11, 2" : : "r"(set_way)); xsc3_l2_inv_all()
173 __asm__("mcr p15, 1, %0, c7, c15, 2" : : "r"(set_way)); xsc3_l2_flush_all()
H A Dcache-tauros2.c42 __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); tauros2_clean_pa()
47 __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); tauros2_clean_inv_pa()
52 __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); tauros2_inv_pa()
118 "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" tauros2_disable()
128 "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" tauros2_resume()
H A Dproc-arm740.S55 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
72 mcr p15, 0, r0, c6, c7
H A Dflush.c34 " mcr p15, 0, %2, c7, c10, 4" flush_pfn_alias()
59 asm( "mcr p15, 0, %0, c7, c14, 0\n" flush_cache_mm()
60 " mcr p15, 0, %0, c7, c10, 4" flush_cache_mm()
75 asm( "mcr p15, 0, %0, c7, c14, 0\n" flush_cache_range()
76 " mcr p15, 0, %0, c7, c10, 4" flush_cache_range()
H A Dproc-v7-2level.S44 mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
111 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
H A Dproc-v7.S82 2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
120 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
127 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
429 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
431 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
H A Dproc-v7-3level.S99 ALT_UP (mcr p15, 0, r0, c7, c10, 1) @ flush_pte
H A Dcache-feroceon-l2.c268 __asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); __invalidate_icache()
/linux-4.1.27/arch/arm/boot/compressed/
H A Dhead-xscale.S26 mcr p15, 0, r0, c7, c10, 4 @ drain WB
27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
H A Dhead-sa1100.S40 mcr p15, 0, r0, c7, c10, 4 @ drain WB
41 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
H A Dhead.S618 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
619 mcr p15, 0, r0, c6, c7, 1
631 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
632 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
633 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
642 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
643 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
648 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
658 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
671 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
742 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
743 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
750 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
762 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
764 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
784 mcr p15, 0, r0, c7, c5, 4 @ ISB
788 mcr p15, 0, r0, c7, c5, 4 @ ISB
796 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
797 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
798 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
803 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
1050 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
1051 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
1052 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
1060 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1069 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
1070 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
1086 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
1088 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
1089 mcr p15, 0, r0, c7, c10, 4 @ DSB
1090 mcr p15, 0, r0, c7, c5, 4 @ ISB
1111 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
1114 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
1121 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
1122 mcr p15, 0, ip, c7, c10, 4 @ drain WB
1129 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
1130 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1131 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1137 mcreq p15, 0, r1, c7, c14, 0 @ clean+invalidate D
1138 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
1139 mcreq p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
1140 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1150 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
1153 mcr p15, 0, r10, c7, c10, 5 @ DMB
1167 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
1185 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
1199 mcr p15, 0, r10, c7, c10, 4 @ DSB
1200 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
1201 mcr p15, 0, r10, c7, c10, 4 @ DSB
1202 mcr p15, 0, r10, c7, c5, 4 @ ISB
1208 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
1210 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
1211 mcr p15, 0, r0, c7, c10, 4 @ drain WB
1243 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
1244 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
1245 mcr p15, 0, r1, c7, c10, 4 @ drain WB
1253 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
/linux-4.1.27/arch/arm/include/asm/
H A Dbarrier.h21 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
23 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
25 #define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
28 #define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
30 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
35 #define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
H A Dtlbflush.h327 tlb_op(TLB_V4_U_FULL | TLB_V6_U_FULL, "c8, c7, 0", zero); __local_flush_tlb_all()
341 tlb_op(TLB_V7_UIS_FULL, "c8, c7, 0", zero); local_flush_tlb_all()
374 tlb_op(TLB_V4_U_FULL, "c8, c7, 0", zero); __local_flush_tlb_mm()
380 tlb_op(TLB_V6_U_ASID, "c8, c7, 2", asid); __local_flush_tlb_mm()
394 tlb_op(TLB_V7_UIS_ASID, "c8, c7, 2", asid); local_flush_tlb_mm()
428 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", uaddr); __local_flush_tlb_page()
435 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", uaddr); __local_flush_tlb_page()
451 tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", uaddr); local_flush_tlb_page()
483 tlb_op(TLB_V4_U_PAGE, "c8, c7, 1", kaddr); __local_flush_tlb_kernel_page()
489 tlb_op(TLB_V6_U_PAGE, "c8, c7, 1", kaddr); __local_flush_tlb_kernel_page()
504 tlb_op(TLB_V7_UIS_PAGE, "c8, c7, 1", kaddr); local_flush_tlb_kernel_page()
540 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); __local_flush_bp_all()
550 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero)); local_flush_bp_all()
560 asm("mcr p15, 0, %0, c7, c1, 6" : : "r" (zero)); __flush_bp_all()
580 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd); flush_pmd_entry()
591 tlb_op(TLB_DCLEAN, "c7, c10, 1 @ flush_pmd", pmd); clean_pmd_entry()
H A Dassembler.h266 mcr p15, 0, r0, c7, c5, 4
282 ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
H A Dcacheflush.h188 asm("mcr p15, 0, %0, c7, c5, 0" \
193 asm("mcr p15, 0, %0, c7, c1, 0" \
/linux-4.1.27/arch/arm/include/asm/hardware/
H A Dcp14.h57 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
72 #define RCP14_DBGBVR7() MRC14(0, c0, c7, 4)
88 #define RCP14_DBGBCR7() MRC14(0, c0, c7, 5)
104 #define RCP14_DBGWVR7() MRC14(0, c0, c7, 6)
120 #define RCP14_DBGWCR7() MRC14(0, c0, c7, 7)
137 #define RCP14_DBGBXVR7() MRC14(0, c1, c7, 1)
152 #define RCP14_DBGITCTRL() MRC14(0, c7, c0, 4)
153 #define RCP14_DBGCLAIMSET() MRC14(0, c7, c8, 6)
154 #define RCP14_DBGCLAIMCLR() MRC14(0, c7, c9, 6)
155 #define RCP14_DBGAUTHSTATUS() MRC14(0, c7, c14, 6)
156 #define RCP14_DBGDEVID2() MRC14(0, c7, c0, 7)
157 #define RCP14_DBGDEVID1() MRC14(0, c7, c1, 7)
158 #define RCP14_DBGDEVID() MRC14(0, c7, c2, 7)
162 #define WCP14_DBGVCR(val) MCR14(val, 0, c0, c7, 0)
177 #define WCP14_DBGBVR7(val) MCR14(val, 0, c0, c7, 4)
193 #define WCP14_DBGBCR7(val) MCR14(val, 0, c0, c7, 5)
209 #define WCP14_DBGWVR7(val) MCR14(val, 0, c0, c7, 6)
225 #define WCP14_DBGWCR7(val) MCR14(val, 0, c0, c7, 7)
241 #define WCP14_DBGBXVR7(val) MCR14(val, 0, c1, c7, 1)
254 #define WCP14_DBGITCTRL(val) MCR14(val, 0, c7, c0, 4)
255 #define WCP14_DBGCLAIMSET(val) MCR14(val, 0, c7, c8, 6)
256 #define WCP14_DBGCLAIMCLR(val) MCR14(val, 0, c7, c9, 6)
288 #define RCP14_ETMTECR2() MRC14(1, c0, c7, 0)
304 #define RCP14_ETMACVR7() MRC14(1, c0, c7, 1)
320 #define RCP14_ETMACTR7() MRC14(1, c0, c7, 2)
352 #define RCP14_ETMCNTENR3() MRC14(1, c0, c7, 5)
367 #define RCP14_ETMSQR() MRC14(1, c0, c7, 6)
383 #define RCP14_ETMIMPSPEC7() MRC14(1, c0, c7, 7)
400 #define RCP14_ETMITCTRL() MRC14(1, c7, c0, 4)
401 #define RCP14_ETMCLAIMSET() MRC14(1, c7, c8, 6)
402 #define RCP14_ETMCLAIMCLR() MRC14(1, c7, c9, 6)
403 #define RCP14_ETMLSR() MRC14(1, c7, c13, 6)
404 #define RCP14_ETMAUTHSTATUS() MRC14(1, c7, c14, 6)
405 #define RCP14_ETMDEVID() MRC14(1, c7, c2, 7)
406 #define RCP14_ETMDEVTYPE() MRC14(1, c7, c3, 7)
407 #define RCP14_ETMPIDR4() MRC14(1, c7, c4, 7)
408 #define RCP14_ETMPIDR5() MRC14(1, c7, c5, 7)
409 #define RCP14_ETMPIDR6() MRC14(1, c7, c6, 7)
410 #define RCP14_ETMPIDR7() MRC14(1, c7, c7, 7)
411 #define RCP14_ETMPIDR0() MRC14(1, c7, c8, 7)
412 #define RCP14_ETMPIDR1() MRC14(1, c7, c9, 7)
413 #define RCP14_ETMPIDR2() MRC14(1, c7, c10, 7)
414 #define RCP14_ETMPIDR3() MRC14(1, c7, c11, 7)
415 #define RCP14_ETMCIDR0() MRC14(1, c7, c12, 7)
416 #define RCP14_ETMCIDR1() MRC14(1, c7, c13, 7)
417 #define RCP14_ETMCIDR2() MRC14(1, c7, c14, 7)
418 #define RCP14_ETMCIDR3() MRC14(1, c7, c15, 7)
425 #define WCP14_ETMTECR2(val) MCR14(val, 1, c0, c7, 0)
441 #define WCP14_ETMACVR7(val) MCR14(val, 1, c0, c7, 1)
457 #define WCP14_ETMACTR7(val) MCR14(val, 1, c0, c7, 2)
489 #define WCP14_ETMCNTENR3(val) MCR14(val, 1, c0, c7, 5)
504 #define WCP14_ETMSQR(val) MCR14(val, 1, c0, c7, 6)
520 #define WCP14_ETMIMPSPEC7(val) MCR14(val, 1, c0, c7, 7)
536 #define WCP14_ETMITCTRL(val) MCR14(val, 1, c7, c0, 4)
537 #define WCP14_ETMCLAIMSET(val) MCR14(val, 1, c7, c8, 6)
538 #define WCP14_ETMCLAIMCLR(val) MCR14(val, 1, c7, c9, 6)
540 #define WCP14_ETMLAR(val) MCR14(val, 1, c7, c12, 6)
H A Diop3xx.h280 asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val)); read_wdtcr()
285 asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val)); write_wdtcr()
/linux-4.1.27/arch/arm/mach-imx/
H A Dhotplug.c25 "mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower()
26 " mcr p15, 0, %1, c7, c10, 4\n" cpu_enter_lowpower()
H A Dmm-imx3.c51 "mcr p15, 0, %0, c7, c5, 0\n" imx3_idle()
54 "mcr p15, 0, %0, c7, c14, 0\n" imx3_idle()
57 "mcr p15, 0, %0, c7, c0, 4\n" imx3_idle()
H A Dsuspend-imx6.S312 mcr p15, 0, r6, c7, c5, 0
313 mcr p15, 0, r6, c7, c5, 6
/linux-4.1.27/arch/arm/mach-pxa/include/mach/
H A Dmtd-xip.h33 #define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
/linux-4.1.27/arch/arm/mach-realview/
H A Dhotplug.c23 " mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower()
24 " mcr p15, 0, %1, c7, c10, 4\n" cpu_enter_lowpower()
/linux-4.1.27/arch/arm/mach-s3c24xx/
H A Dsleep-s3c2412.S52 mcr p15, 0, r0, c7, c10, 4
53 mcrne p15, 0, r0, c7, c0, 4
/linux-4.1.27/arch/arm/mach-vexpress/
H A Dhotplug.c23 "mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower()
24 " mcr p15, 0, %1, c7, c10, 4\n" cpu_enter_lowpower()
/linux-4.1.27/arch/powerpc/crypto/
H A Daes-tab-4k.S62 .long R(08, 04, 04, 0c), R(95, c7, c7, 52)
114 .long R(8c, 46, 46, ca), R(c7, ee, ee, 29)
137 .long R(73, b4, b4, c7), R(97, c6, c6, 51)
231 .long R(0e, 09, 0d, 0b), R(f2, 8b, c7, ad)
242 .long R(ae, f9, 32, 11), R(c7, 29, a1, 6d)
249 .long R(87, 49, 4e, c7), R(d9, 38, d1, c1)
286 .long R(18, 14, ce, 79), R(73, c7, 37, bf)
/linux-4.1.27/arch/arm/mach-pxa/
H A Dstandby.S30 1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
64 mcr p14, 0, r0, c7, c0, 0
H A Dsleep.S31 mcr p14, 0, r0, c7, c0, 0 @ enter sleep
169 mcr p14, 0, r1, c7, c0, 0 @ PWRMODE
/linux-4.1.27/arch/arm/mach-s5pv210/
H A Dpm.c55 "mcr p15, 0, %0, c7, c10, 5\n\t" s5pv210_cpu_suspend()
56 "mcr p15, 0, %0, c7, c10, 4\n\t" s5pv210_cpu_suspend()
/linux-4.1.27/arch/arm/mach-spear/
H A Dhotplug.c24 " mcr p15, 0, %1, c7, c5, 0\n" cpu_enter_lowpower()
/linux-4.1.27/arch/arm/mach-omap1/include/mach/
H A Dmtd-xip.h59 #define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (1))
/linux-4.1.27/arch/arm/mach-omap1/
H A Dsleep.S73 mcr p15, 0, r0, c7, c10, 4
119 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
202 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
228 mcr p15, 0, r0, c7, c10, 4
268 mcr p15, 0, r2, c7, c0, 4 @ wait for interrupt
H A Dpm.c139 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); omap1_pm_idle()
/linux-4.1.27/arch/arm64/kernel/
H A Darmv8_deprecated.c476 * dmb - mcr p15, 0, Rt, c7, c10, 5 cp15barrier_handler()
477 * dsb - mcr p15, 0, Rt, c7, c10, 4 cp15barrier_handler()
482 "mcr p15, 0, Rt, c7, c10, 5 ; dmb", regs->pc); cp15barrier_handler()
486 "mcr p15, 0, Rt, c7, c10, 4 ; dsb", regs->pc); cp15barrier_handler()
491 * isb - mcr p15, 0, Rt, c7, c5, 4 cp15barrier_handler()
497 "mcr p15, 0, Rt, c7, c5, 4 ; isb", regs->pc); cp15barrier_handler()
/linux-4.1.27/arch/unicore32/kernel/
H A Dsleep.S24 movc r3, p0.c7, #0 @ PID
174 movc p0.c7, r3, #0 @ PID
/linux-4.1.27/arch/arm/mach-omap2/
H A Dsleep24xx.S69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
77 mcr p15, 0, r3, c7, c0, 4 @ wait for interrupt
H A Dsram242x.S152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
H A Dsram243x.S152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
181 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
H A Dpm24xx.c157 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc"); omap2_enter_mpu_retention()
/linux-4.1.27/arch/arm/kvm/
H A Dinit.S103 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
149 mcr p15, 4, r0, c8, c7, 0 @ TLBIALLH
H A Dinterrupts.S92 mcr p15, 0, r0, c7, c1, 0
443 mrrc p15, 0, r0, r1, c7 @ PAR
447 mcr p15, 0, r2, c7, c8, 0 @ ATS1CPR
449 mrrc p15, 0, r0, r1, c7 @ PAR
458 mcrr p15, 0, r0, r1, c7 @ PAR
467 mcrr p15, 0, r0, r1, c7 @ PAR
H A Dinterrupts_head.S306 mrrc p15, 0, r4, r5, c7 @ PAR
340 mcrr p15, 0, r4, r5, c7 @ PAR
/linux-4.1.27/arch/arm/mach-s3c64xx/
H A Dpm.c276 "mcr p15, 0, %0, c7, c10, 5\n\t" s3c64xx_cpu_suspend()
277 "mcr p15, 0, %0, c7, c10, 4\n\t" s3c64xx_cpu_suspend()
278 "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); s3c64xx_cpu_suspend()
/linux-4.1.27/drivers/mtd/maps/
H A Dpxa2xx-flash.c37 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start)); pxa2xx_map_inval_cache()
/linux-4.1.27/arch/x86/crypto/sha-mb/
H A Dsha1_x8_avx2.S74 # r2 = {c7 c6 c5 c4 c3 c2 c1 c0}
89 # r7 = {h7 g7 f7 e7 d7 c7 b7 a7}
97 vshufps $0xEE, \r3, \r2, \r2 # r2 = {d7 d6 c7 c6 d3 d2 c3 c2}
100 vshufps $0xDD, \r2, \r0, \r0 # r0 = {d7 c7 b7 a7 d3 c3 b3 a3}
/linux-4.1.27/arch/arm/mach-at91/
H A Dpm_suspend.S66 mcr p15, 0, tmp1, c7, c0, 4
92 mcr p15, 0, tmp1, c7, c10, 4
H A Dpm.c241 "1: mcr p15, 0, %0, c7, c10, 4\n\t" at91rm9200_standby()
244 " mcr p15, 0, %0, c7, c0, 4\n\t" at91rm9200_standby()
/linux-4.1.27/arch/arm/mach-vt8500/
H A Dvt8500.c72 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (0)); vt8500_power_off()
/linux-4.1.27/tools/power/x86/turbostat/
H A Dturbostat.c153 unsigned long long c7; member in struct:core_data
284 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz SMI %Busy CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
326 outp += sprintf(outp, " CPU%%c7"); print_header()
415 outp += sprintf(outp, "c7: %016llX\n", c->c7); dump_counters()
556 outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc); format_counters()
711 old->c7 = new->c7 - old->c7; delta_core()
766 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) delta_thread()
771 - core_delta->c6 - core_delta->c7; delta_thread()
829 c->c7 = 0; clear_counters()
873 average.cores.c7 += c->c7; sum_counters()
933 average.cores.c7 /= topo.num_cores; compute_average()
1037 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) get_counters()
/linux-4.1.27/drivers/media/tuners/
H A Dtda9887.c93 #define cAudioGain0 0x00 // bit c7
94 #define cAudioGain6 0x80 // bit c7
/linux-4.1.27/arch/arm/mach-iop13xx/include/mach/
H A Diop13xx.h31 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val)); read_wdtcr()
36 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val)); write_wdtcr()
/linux-4.1.27/drivers/cpufreq/
H A Dsa1110-cpufreq.c277 asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); sa1110_target()
/linux-4.1.27/arch/sh/kernel/
H A Dftrace.c36 * 8c011064: 02 c7 mova 8c011070 <a+0x10>,r0
/linux-4.1.27/arch/alpha/kernel/
H A Dsys_sio.c251 * 53c7,8xx.c DOES. alphabook1_init_pci()
/linux-4.1.27/drivers/firmware/
H A Dqcom_scm.c249 asm ("mcr p15, 0, %0, c7, c6, 1" : : "r" (start) qcom_scm_inv_range()
/linux-4.1.27/arch/arm/mach-tegra/
H A Dsleep-tegra20.S300 mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
/linux-4.1.27/drivers/iommu/
H A Domap-iommu.c601 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pgd" flush_iopgd_range()
611 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pte" flush_iopte_range()
/linux-4.1.27/arch/x86/kernel/
H A Duprobes.c243 * c6-c7 - Group 11 - only reg = 0 is OK
390 * Encoding: 0f c7/1 modrm riprel_analyze()
/linux-4.1.27/drivers/media/pci/zoran/
H A Dzoran_card.c1231 "%s: Zoran ZR360%c7 (rev %d), irq: %d, memory: 0x%08llx\n", zoran_probe()
/linux-4.1.27/drivers/media/usb/dvb-usb/
H A Daf9005-fe.c852 read eepr c7 (2) af9005_fe_init()
/linux-4.1.27/arch/arm/kernel/
H A Dhw_breakpoint.c987 ARM_DBG_WRITE(c0, c7, 0, 0); reset_ctrl_regs()
/linux-4.1.27/drivers/usb/musb/
H A Dcppi_dma.c55 asm("mcr p15, 0, r0, c7, c10, 4 @ drain write buffer\n"); cpu_drain_writebuffer()
/linux-4.1.27/drivers/gpu/drm/i915/
H A Di915_reg.h4797 * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff|

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