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Searched refs:SPORT0_MRCS3 (Results 1 – 33 of 33) sorted by relevance

/linux-4.1.27/arch/blackfin/mach-bf533/boards/
Dstamp.c379 .end = SPORT0_MRCS3+4,
449 .end = SPORT0_MRCS3+4,
Dblackstamp.c273 .end = SPORT0_MRCS3+4,
Dcm_bf533.c300 .end = SPORT0_MRCS3+4,
/linux-4.1.27/arch/blackfin/mach-bf537/boards/
Dcm_bf537e.c594 .end = SPORT0_MRCS3+4,
658 .end = SPORT0_MRCS3+4,
Dminotaur.c418 .end = SPORT0_MRCS3+4,
Dcm_bf537u.c486 .end = SPORT0_MRCS3+4,
Dtcm_bf537.c488 .end = SPORT0_MRCS3+4,
Dstamp.c2354 .end = SPORT0_MRCS3+4,
2418 .end = SPORT0_MRCS3+4,
/linux-4.1.27/arch/blackfin/mach-bf548/include/mach/
DdefBF547.h59 #define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Regis… macro
DcdefBF547.h95 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
96 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/linux-4.1.27/arch/blackfin/mach-bf518/boards/
Dtcm-bf518.c501 .end = SPORT0_MRCS3+4,
Dezbrd.c579 .end = SPORT0_MRCS3+4,
/linux-4.1.27/arch/blackfin/mach-bf533/include/mach/
DdefBF532.h143 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ macro
DcdefBF532.h612 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
613 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
/linux-4.1.27/arch/blackfin/mach-bf527/boards/
Dezbrd.c622 .end = SPORT0_MRCS3+4,
Dad7160eval.c602 .end = SPORT0_MRCS3+4,
Dtll6527m.c725 .end = SPORT0_MRCS3+4,
Dcm_bf527.c748 .end = SPORT0_MRCS3+4,
Dezkit.c1007 .end = SPORT0_MRCS3+4,
/linux-4.1.27/arch/blackfin/mach-bf538/boards/
Dezkit.c285 .end = SPORT0_MRCS3+4,
/linux-4.1.27/arch/blackfin/mach-bf518/include/mach/
DdefBF512.h181 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ macro
DcdefBF512.h294 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
295 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/linux-4.1.27/arch/blackfin/mach-bf527/include/mach/
DdefBF522.h178 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ macro
DcdefBF522.h311 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
312 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/linux-4.1.27/arch/blackfin/mach-bf548/boards/
Dcm_bf548.c561 .end = SPORT0_MRCS3+4,
Dezkit.c704 .end = SPORT0_MRCS3+4,
/linux-4.1.27/arch/blackfin/mach-bf561/include/mach/
DdefBF561.h255 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ macro
DcdefBF561.h422 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
423 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
/linux-4.1.27/arch/blackfin/mach-bf537/include/mach/
DdefBF534.h157 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ macro
DcdefBF534.h276 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
277 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3,val)
/linux-4.1.27/arch/blackfin/mach-bf538/include/mach/
DdefBF538.h147 #define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */ macro
DcdefBF538.h258 #define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
259 #define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
/linux-4.1.27/arch/blackfin/mach-bf609/boards/
Dezkit.c477 .end = SPORT0_MRCS3+4,