1/*
2 * Copyright 2004-20010 Analog Devices Inc.
3 *                2005 National ICT Australia (NICTA)
4 *                      Aidan Williams <aidan@nicta.com.au>
5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <linux/device.h>
10#include <linux/export.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/mtd/physmap.h>
15#include <linux/spi/spi.h>
16#include <linux/spi/flash.h>
17#include <linux/i2c.h>
18#include <linux/irq.h>
19#include <linux/interrupt.h>
20#include <linux/usb/musb.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/nand.h>
27#include <asm/portmux.h>
28#include <asm/dpmc.h>
29
30
31/*
32 * Name the Board for the /proc/cpuinfo
33 */
34const char bfin_board_name[] = "ADI BF527-AD7160EVAL";
35
36/*
37 *  Driver needs to know address, irq and flag pin.
38 */
39
40#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
41static struct resource musb_resources[] = {
42	[0] = {
43		.start	= 0xffc03800,
44		.end	= 0xffc03cff,
45		.flags	= IORESOURCE_MEM,
46	},
47	[1] = {	/* general IRQ */
48		.start	= IRQ_USB_INT0,
49		.end	= IRQ_USB_INT0,
50		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
51	},
52	[2] = {	/* DMA IRQ */
53		.start	= IRQ_USB_DMA,
54		.end	= IRQ_USB_DMA,
55		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
56	},
57};
58
59static struct musb_hdrc_config musb_config = {
60	.multipoint	= 0,
61	.dyn_fifo	= 0,
62	.soft_con	= 1,
63	.dma		= 1,
64	.num_eps	= 8,
65	.dma_channels	= 8,
66	.gpio_vrsel	= GPIO_PG13,
67	/* Some custom boards need to be active low, just set it to "0"
68	 * if it is the case.
69	 */
70	.gpio_vrsel_active	= 1,
71	.clkin          = 24,           /* musb CLKIN in MHZ */
72};
73
74static struct musb_hdrc_platform_data musb_plat = {
75#if defined(CONFIG_USB_MUSB_OTG)
76	.mode		= MUSB_OTG,
77#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
78	.mode		= MUSB_HOST,
79#elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
80	.mode		= MUSB_PERIPHERAL,
81#endif
82	.config		= &musb_config,
83};
84
85static u64 musb_dmamask = ~(u32)0;
86
87static struct platform_device musb_device = {
88	.name		= "musb-blackfin",
89	.id		= 0,
90	.dev = {
91		.dma_mask		= &musb_dmamask,
92		.coherent_dma_mask	= 0xffffffff,
93		.platform_data		= &musb_plat,
94	},
95	.num_resources	= ARRAY_SIZE(musb_resources),
96	.resource	= musb_resources,
97};
98#endif
99
100#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
101static struct resource bf52x_ra158z_resources[] = {
102	{
103		.start = IRQ_PPI_ERROR,
104		.end = IRQ_PPI_ERROR,
105		.flags = IORESOURCE_IRQ,
106	},
107};
108
109static struct platform_device bf52x_ra158z_device = {
110	.name		= "bfin-ra158z",
111	.id		= -1,
112	.num_resources	= ARRAY_SIZE(bf52x_ra158z_resources),
113	.resource	= bf52x_ra158z_resources,
114};
115#endif
116
117#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
118static struct mtd_partition ad7160eval_partitions[] = {
119	{
120		.name       = "bootloader(nor)",
121		.size       = 0x40000,
122		.offset     = 0,
123	}, {
124		.name       = "linux kernel(nor)",
125		.size       = 0x1C0000,
126		.offset     = MTDPART_OFS_APPEND,
127	}, {
128		.name       = "file system(nor)",
129		.size       = MTDPART_SIZ_FULL,
130		.offset     = MTDPART_OFS_APPEND,
131	}
132};
133
134static struct physmap_flash_data ad7160eval_flash_data = {
135	.width      = 2,
136	.parts      = ad7160eval_partitions,
137	.nr_parts   = ARRAY_SIZE(ad7160eval_partitions),
138};
139
140static struct resource ad7160eval_flash_resource = {
141	.start = 0x20000000,
142	.end   = 0x203fffff,
143	.flags = IORESOURCE_MEM,
144};
145
146static struct platform_device ad7160eval_flash_device = {
147	.name          = "physmap-flash",
148	.id            = 0,
149	.dev = {
150		.platform_data = &ad7160eval_flash_data,
151	},
152	.num_resources = 1,
153	.resource      = &ad7160eval_flash_resource,
154};
155#endif
156
157#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
158static struct mtd_partition partition_info[] = {
159	{
160		.name = "linux kernel(nand)",
161		.offset = 0,
162		.size = 4 * 1024 * 1024,
163	},
164	{
165		.name = "file system(nand)",
166		.offset = MTDPART_OFS_APPEND,
167		.size = MTDPART_SIZ_FULL,
168	},
169};
170
171static struct bf5xx_nand_platform bf5xx_nand_platform = {
172	.data_width = NFC_NWIDTH_8,
173	.partitions = partition_info,
174	.nr_partitions = ARRAY_SIZE(partition_info),
175	.rd_dly = 3,
176	.wr_dly = 3,
177};
178
179static struct resource bf5xx_nand_resources[] = {
180	{
181		.start = NFC_CTL,
182		.end = NFC_DATA_RD + 2,
183		.flags = IORESOURCE_MEM,
184	},
185	{
186		.start = CH_NFC,
187		.end = CH_NFC,
188		.flags = IORESOURCE_IRQ,
189	},
190};
191
192static struct platform_device bf5xx_nand_device = {
193	.name = "bf5xx-nand",
194	.id = 0,
195	.num_resources = ARRAY_SIZE(bf5xx_nand_resources),
196	.resource = bf5xx_nand_resources,
197	.dev = {
198		.platform_data = &bf5xx_nand_platform,
199	},
200};
201#endif
202
203#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
204static struct platform_device rtc_device = {
205	.name = "rtc-bfin",
206	.id   = -1,
207};
208#endif
209
210#if IS_ENABLED(CONFIG_BFIN_MAC)
211#include <linux/bfin_mac.h>
212static const unsigned short bfin_mac_peripherals[] = P_RMII0;
213
214static struct bfin_phydev_platform_data bfin_phydev_data[] = {
215	{
216		.addr = 1,
217		.irq = IRQ_MAC_PHYINT,
218	},
219};
220
221static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
222	.phydev_number = 1,
223	.phydev_data = bfin_phydev_data,
224	.phy_mode = PHY_INTERFACE_MODE_RMII,
225	.mac_peripherals = bfin_mac_peripherals,
226};
227
228static struct platform_device bfin_mii_bus = {
229	.name = "bfin_mii_bus",
230	.dev = {
231		.platform_data = &bfin_mii_bus_data,
232	}
233};
234
235static struct platform_device bfin_mac_device = {
236	.name = "bfin_mac",
237	.dev = {
238		.platform_data = &bfin_mii_bus,
239	}
240};
241#endif
242
243
244#if IS_ENABLED(CONFIG_MTD_M25P80)
245static struct mtd_partition bfin_spi_flash_partitions[] = {
246	{
247		.name = "bootloader(spi)",
248		.size = 0x00040000,
249		.offset = 0,
250		.mask_flags = MTD_CAP_ROM
251	}, {
252		.name = "linux kernel(spi)",
253		.size = MTDPART_SIZ_FULL,
254		.offset = MTDPART_OFS_APPEND,
255	}
256};
257
258static struct flash_platform_data bfin_spi_flash_data = {
259	.name = "m25p80",
260	.parts = bfin_spi_flash_partitions,
261	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
262	.type = "m25p16",
263};
264
265/* SPI flash chip (m25p64) */
266static struct bfin5xx_spi_chip spi_flash_chip_info = {
267	.enable_dma = 0,         /* use dma transfer with this chip*/
268};
269#endif
270
271#if IS_ENABLED(CONFIG_MMC_SPI)
272static struct bfin5xx_spi_chip  mmc_spi_chip_info = {
273	.enable_dma = 0,
274};
275#endif
276
277#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
278static struct platform_device bfin_i2s = {
279	.name = "bfin-i2s",
280	.id = CONFIG_SND_BF5XX_SPORT_NUM,
281	/* TODO: add platform data here */
282};
283#endif
284
285static struct spi_board_info bfin_spi_board_info[] __initdata = {
286#if IS_ENABLED(CONFIG_MTD_M25P80)
287	{
288		/* the modalias must be the same as spi device driver name */
289		.modalias = "m25p80", /* Name of spi_driver for this device */
290		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
291		.bus_num = 0, /* Framework bus number */
292		.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
293		.platform_data = &bfin_spi_flash_data,
294		.controller_data = &spi_flash_chip_info,
295		.mode = SPI_MODE_3,
296	},
297#endif
298#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X)
299	{
300		.modalias = "ad183x",
301		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
302		.bus_num = 0,
303		.chip_select = 4,
304	},
305#endif
306#if IS_ENABLED(CONFIG_MMC_SPI)
307	{
308		.modalias = "mmc_spi",
309		.max_speed_hz = 30000000,     /* max spi clock (SCK) speed in HZ */
310		.bus_num = 0,
311		.chip_select = GPIO_PH3 + MAX_CTRL_CS,
312		.controller_data = &mmc_spi_chip_info,
313		.mode = SPI_MODE_3,
314	},
315#endif
316#if IS_ENABLED(CONFIG_SPI_SPIDEV)
317	{
318		.modalias = "spidev",
319		.max_speed_hz = 3125000,     /* max spi clock (SCK) speed in HZ */
320		.bus_num = 0,
321		.chip_select = 1,
322	},
323#endif
324};
325
326#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
327/* SPI controller data */
328static struct bfin5xx_spi_master bfin_spi0_info = {
329	.num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
330	.enable_dma = 1,  /* master has the ability to do dma transfer */
331	.pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
332};
333
334/* SPI (0) */
335static struct resource bfin_spi0_resource[] = {
336	[0] = {
337		.start = SPI0_REGBASE,
338		.end   = SPI0_REGBASE + 0xFF,
339		.flags = IORESOURCE_MEM,
340		},
341	[1] = {
342		.start = CH_SPI,
343		.end   = CH_SPI,
344		.flags = IORESOURCE_DMA,
345	},
346	[2] = {
347		.start = IRQ_SPI,
348		.end   = IRQ_SPI,
349		.flags = IORESOURCE_IRQ,
350	},
351};
352
353static struct platform_device bfin_spi0_device = {
354	.name = "bfin-spi",
355	.id = 0, /* Bus number */
356	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
357	.resource = bfin_spi0_resource,
358	.dev = {
359		.platform_data = &bfin_spi0_info, /* Passed to driver */
360	},
361};
362#endif  /* spi master and devices */
363
364#if IS_ENABLED(CONFIG_SERIAL_BFIN)
365#ifdef CONFIG_SERIAL_BFIN_UART0
366static struct resource bfin_uart0_resources[] = {
367	{
368		.start = UART0_THR,
369		.end = UART0_GCTL+2,
370		.flags = IORESOURCE_MEM,
371	},
372	{
373		.start = IRQ_UART0_TX,
374		.end = IRQ_UART0_TX,
375		.flags = IORESOURCE_IRQ,
376	},
377	{
378		.start = IRQ_UART0_RX,
379		.end = IRQ_UART0_RX,
380		.flags = IORESOURCE_IRQ,
381	},
382	{
383		.start = IRQ_UART0_ERROR,
384		.end = IRQ_UART0_ERROR,
385		.flags = IORESOURCE_IRQ,
386	},
387	{
388		.start = CH_UART0_TX,
389		.end = CH_UART0_TX,
390		.flags = IORESOURCE_DMA,
391	},
392	{
393		.start = CH_UART0_RX,
394		.end = CH_UART0_RX,
395		.flags = IORESOURCE_DMA,
396	},
397};
398
399static unsigned short bfin_uart0_peripherals[] = {
400	P_UART0_TX, P_UART0_RX, 0
401};
402
403static struct platform_device bfin_uart0_device = {
404	.name = "bfin-uart",
405	.id = 0,
406	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
407	.resource = bfin_uart0_resources,
408	.dev = {
409		.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
410	},
411};
412#endif
413#ifdef CONFIG_SERIAL_BFIN_UART1
414static struct resource bfin_uart1_resources[] = {
415	{
416		.start = UART1_THR,
417		.end = UART1_GCTL+2,
418		.flags = IORESOURCE_MEM,
419	},
420	{
421		.start = IRQ_UART1_TX,
422		.end = IRQ_UART1_TX,
423		.flags = IORESOURCE_IRQ,
424	},
425	{
426		.start = IRQ_UART1_RX,
427		.end = IRQ_UART1_RX,
428		.flags = IORESOURCE_IRQ,
429	},
430	{
431		.start = IRQ_UART1_ERROR,
432		.end = IRQ_UART1_ERROR,
433		.flags = IORESOURCE_IRQ,
434	},
435	{
436		.start = CH_UART1_TX,
437		.end = CH_UART1_TX,
438		.flags = IORESOURCE_DMA,
439	},
440	{
441		.start = CH_UART1_RX,
442		.end = CH_UART1_RX,
443		.flags = IORESOURCE_DMA,
444	},
445#ifdef CONFIG_BFIN_UART1_CTSRTS
446	{	/* CTS pin */
447		.start = GPIO_PF9,
448		.end = GPIO_PF9,
449		.flags = IORESOURCE_IO,
450	},
451	{	/* RTS pin */
452		.start = GPIO_PF10,
453		.end = GPIO_PF10,
454		.flags = IORESOURCE_IO,
455	},
456#endif
457};
458
459static unsigned short bfin_uart1_peripherals[] = {
460	P_UART1_TX, P_UART1_RX, 0
461};
462
463static struct platform_device bfin_uart1_device = {
464	.name = "bfin-uart",
465	.id = 1,
466	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
467	.resource = bfin_uart1_resources,
468	.dev = {
469		.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
470	},
471};
472#endif
473#endif
474
475#if IS_ENABLED(CONFIG_BFIN_SIR)
476#ifdef CONFIG_BFIN_SIR0
477static struct resource bfin_sir0_resources[] = {
478	{
479		.start = 0xFFC00400,
480		.end = 0xFFC004FF,
481		.flags = IORESOURCE_MEM,
482	},
483	{
484		.start = IRQ_UART0_RX,
485		.end = IRQ_UART0_RX+1,
486		.flags = IORESOURCE_IRQ,
487	},
488	{
489		.start = CH_UART0_RX,
490		.end = CH_UART0_RX+1,
491		.flags = IORESOURCE_DMA,
492	},
493};
494
495static struct platform_device bfin_sir0_device = {
496	.name = "bfin_sir",
497	.id = 0,
498	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
499	.resource = bfin_sir0_resources,
500};
501#endif
502#ifdef CONFIG_BFIN_SIR1
503static struct resource bfin_sir1_resources[] = {
504	{
505		.start = 0xFFC02000,
506		.end = 0xFFC020FF,
507		.flags = IORESOURCE_MEM,
508	},
509	{
510		.start = IRQ_UART1_RX,
511		.end = IRQ_UART1_RX+1,
512		.flags = IORESOURCE_IRQ,
513	},
514	{
515		.start = CH_UART1_RX,
516		.end = CH_UART1_RX+1,
517		.flags = IORESOURCE_DMA,
518	},
519};
520
521static struct platform_device bfin_sir1_device = {
522	.name = "bfin_sir",
523	.id = 1,
524	.num_resources = ARRAY_SIZE(bfin_sir1_resources),
525	.resource = bfin_sir1_resources,
526};
527#endif
528#endif
529
530#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
531#include <linux/input/ad7160.h>
532static const struct ad7160_platform_data bfin_ad7160_ts_info = {
533	.sensor_x_res = 854,
534	.sensor_y_res = 480,
535	.pressure = 100,
536	.filter_coef = 3,
537	.coord_pref = AD7160_ORIG_TOP_LEFT,
538	.first_touch_window = 5,
539	.move_window = 3,
540	.event_cabs = AD7160_EMIT_ABS_MT_TRACKING_ID |
541			AD7160_EMIT_ABS_MT_PRESSURE |
542			AD7160_TRACKING_ID_ASCENDING,
543	.finger_act_ctrl = 0x64,
544	.haptic_effect1_ctrl = AD7160_HAPTIC_SLOT_A(60) |
545				AD7160_HAPTIC_SLOT_A_LVL_HIGH |
546				AD7160_HAPTIC_SLOT_B(60) |
547				AD7160_HAPTIC_SLOT_B_LVL_LOW,
548
549	.haptic_effect2_ctrl = AD7160_HAPTIC_SLOT_A(20) |
550				AD7160_HAPTIC_SLOT_A_LVL_HIGH |
551				AD7160_HAPTIC_SLOT_B(80) |
552				AD7160_HAPTIC_SLOT_B_LVL_LOW |
553				AD7160_HAPTIC_SLOT_C(120) |
554				AD7160_HAPTIC_SLOT_C_LVL_HIGH |
555				AD7160_HAPTIC_SLOT_D(30) |
556				AD7160_HAPTIC_SLOT_D_LVL_LOW,
557};
558#endif
559
560#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
561static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
562
563static struct resource bfin_twi0_resource[] = {
564	[0] = {
565		.start = TWI0_REGBASE,
566		.end   = TWI0_REGBASE,
567		.flags = IORESOURCE_MEM,
568	},
569	[1] = {
570		.start = IRQ_TWI,
571		.end   = IRQ_TWI,
572		.flags = IORESOURCE_IRQ,
573	},
574};
575
576static struct platform_device i2c_bfin_twi_device = {
577	.name = "i2c-bfin-twi",
578	.id = 0,
579	.num_resources = ARRAY_SIZE(bfin_twi0_resource),
580	.resource = bfin_twi0_resource,
581	.dev = {
582		.platform_data = &bfin_twi0_pins,
583	},
584};
585#endif
586
587static struct i2c_board_info __initdata bfin_i2c_board_info[] = {
588#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7160)
589	{
590		I2C_BOARD_INFO("ad7160", 0x33),
591		.irq = IRQ_PH1,
592		.platform_data = (void *)&bfin_ad7160_ts_info,
593	},
594#endif
595};
596
597#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
598#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
599static struct resource bfin_sport0_uart_resources[] = {
600	{
601		.start = SPORT0_TCR1,
602		.end = SPORT0_MRCS3+4,
603		.flags = IORESOURCE_MEM,
604	},
605	{
606		.start = IRQ_SPORT0_RX,
607		.end = IRQ_SPORT0_RX+1,
608		.flags = IORESOURCE_IRQ,
609	},
610	{
611		.start = IRQ_SPORT0_ERROR,
612		.end = IRQ_SPORT0_ERROR,
613		.flags = IORESOURCE_IRQ,
614	},
615};
616
617static unsigned short bfin_sport0_peripherals[] = {
618	P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
619	P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
620};
621
622static struct platform_device bfin_sport0_uart_device = {
623	.name = "bfin-sport-uart",
624	.id = 0,
625	.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
626	.resource = bfin_sport0_uart_resources,
627	.dev = {
628		.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
629	},
630};
631#endif
632#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
633static struct resource bfin_sport1_uart_resources[] = {
634	{
635		.start = SPORT1_TCR1,
636		.end = SPORT1_MRCS3+4,
637		.flags = IORESOURCE_MEM,
638	},
639	{
640		.start = IRQ_SPORT1_RX,
641		.end = IRQ_SPORT1_RX+1,
642		.flags = IORESOURCE_IRQ,
643	},
644	{
645		.start = IRQ_SPORT1_ERROR,
646		.end = IRQ_SPORT1_ERROR,
647		.flags = IORESOURCE_IRQ,
648	},
649};
650
651static unsigned short bfin_sport1_peripherals[] = {
652	P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
653	P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
654};
655
656static struct platform_device bfin_sport1_uart_device = {
657	.name = "bfin-sport-uart",
658	.id = 1,
659	.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
660	.resource = bfin_sport1_uart_resources,
661	.dev = {
662		.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
663	},
664};
665#endif
666#endif
667
668#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
669#include <linux/platform_data/bfin_rotary.h>
670
671static const u16 per_cnt[] = {
672	P_CNT_CUD,
673	P_CNT_CDG,
674	P_CNT_CZM,
675	0
676};
677
678static struct bfin_rotary_platform_data bfin_rotary_data = {
679	/*.rotary_up_key     = KEY_UP,*/
680	/*.rotary_down_key   = KEY_DOWN,*/
681	.rotary_rel_code   = REL_WHEEL,
682	.rotary_button_key = KEY_ENTER,
683	.debounce	   = 10,	/* 0..17 */
684	.mode		   = ROT_QUAD_ENC | ROT_DEBE,
685	.pm_wakeup	   = 1,
686	.pin_list	   = per_cnt,
687};
688
689static struct resource bfin_rotary_resources[] = {
690	{
691		.start = CNT_CONFIG,
692		.end   = CNT_CONFIG + 0xff,
693		.flags = IORESOURCE_MEM,
694	},
695	{
696		.start = IRQ_CNT,
697		.end = IRQ_CNT,
698		.flags = IORESOURCE_IRQ,
699	},
700};
701
702static struct platform_device bfin_rotary_device = {
703	.name		= "bfin-rotary",
704	.id		= -1,
705	.num_resources	= ARRAY_SIZE(bfin_rotary_resources),
706	.resource	= bfin_rotary_resources,
707	.dev		= {
708		.platform_data = &bfin_rotary_data,
709	},
710};
711#endif
712
713static const unsigned int cclk_vlev_datasheet[] = {
714	VRPAIR(VLEV_100, 400000000),
715	VRPAIR(VLEV_105, 426000000),
716	VRPAIR(VLEV_110, 500000000),
717	VRPAIR(VLEV_115, 533000000),
718	VRPAIR(VLEV_120, 600000000),
719};
720
721static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
722	.tuple_tab = cclk_vlev_datasheet,
723	.tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
724	.vr_settling_time = 25 /* us */,
725};
726
727static struct platform_device bfin_dpmc = {
728	.name = "bfin dpmc",
729	.dev = {
730		.platform_data = &bfin_dmpc_vreg_data,
731	},
732};
733
734static struct platform_device *stamp_devices[] __initdata = {
735
736	&bfin_dpmc,
737
738#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX)
739	&bf5xx_nand_device,
740#endif
741
742#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
743	&rtc_device,
744#endif
745
746#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
747	&musb_device,
748#endif
749
750#if IS_ENABLED(CONFIG_BFIN_MAC)
751	&bfin_mii_bus,
752	&bfin_mac_device,
753#endif
754
755#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
756	&bfin_spi0_device,
757#endif
758
759#if IS_ENABLED(CONFIG_SERIAL_BFIN)
760#ifdef CONFIG_SERIAL_BFIN_UART0
761	&bfin_uart0_device,
762#endif
763#ifdef CONFIG_SERIAL_BFIN_UART1
764	&bfin_uart1_device,
765#endif
766#endif
767
768#if IS_ENABLED(CONFIG_FB_BFIN_RA158Z)
769	&bf52x_ra158z_device,
770#endif
771
772#if IS_ENABLED(CONFIG_BFIN_SIR)
773#ifdef CONFIG_BFIN_SIR0
774	&bfin_sir0_device,
775#endif
776#ifdef CONFIG_BFIN_SIR1
777	&bfin_sir1_device,
778#endif
779#endif
780
781#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
782	&i2c_bfin_twi_device,
783#endif
784
785#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
786#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
787	&bfin_sport0_uart_device,
788#endif
789#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
790	&bfin_sport1_uart_device,
791#endif
792#endif
793
794#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY)
795	&bfin_rotary_device,
796#endif
797
798#if IS_ENABLED(CONFIG_MTD_PHYSMAP)
799	&ad7160eval_flash_device,
800#endif
801
802#if IS_ENABLED(CONFIG_SND_BF5XX_I2S)
803	&bfin_i2s,
804#endif
805};
806
807static int __init ad7160eval_init(void)
808{
809	printk(KERN_INFO "%s(): registering device resources\n", __func__);
810	i2c_register_board_info(0, bfin_i2c_board_info,
811				ARRAY_SIZE(bfin_i2c_board_info));
812	platform_add_devices(stamp_devices, ARRAY_SIZE(stamp_devices));
813	spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
814	return 0;
815}
816
817arch_initcall(ad7160eval_init);
818
819static struct platform_device *ad7160eval_early_devices[] __initdata = {
820#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
821#ifdef CONFIG_SERIAL_BFIN_UART0
822	&bfin_uart0_device,
823#endif
824#ifdef CONFIG_SERIAL_BFIN_UART1
825	&bfin_uart1_device,
826#endif
827#endif
828
829#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
830#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
831	&bfin_sport0_uart_device,
832#endif
833#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
834	&bfin_sport1_uart_device,
835#endif
836#endif
837};
838
839void __init native_machine_early_platform_add_devices(void)
840{
841	printk(KERN_INFO "register early platform devices\n");
842	early_platform_add_devices(ad7160eval_early_devices,
843		ARRAY_SIZE(ad7160eval_early_devices));
844}
845
846void native_machine_restart(char *cmd)
847{
848	/* workaround reboot hang when booting from SPI */
849	if ((bfin_read_SYSCR() & 0x7) == 0x3)
850		bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
851}
852
853int bfin_get_ether_addr(char *addr)
854{
855	/* the MAC is stored in OTP memory page 0xDF */
856	u32 ret;
857	u64 otp_mac;
858	u32 (*otp_read)(u32 page, u32 flags, u64 *page_content) = (void *)0xEF00001A;
859
860	ret = otp_read(0xDF, 0x00, &otp_mac);
861	if (!(ret & 0x1)) {
862		char *otp_mac_p = (char *)&otp_mac;
863		for (ret = 0; ret < 6; ++ret)
864			addr[ret] = otp_mac_p[5 - ret];
865	}
866	return 0;
867}
868EXPORT_SYMBOL(bfin_get_ether_addr);
869