1/*
2 * Copyright 2004-2009 Analog Devices Inc.
3 *           2008-2009 Cambridge Signal Processing
4 *                2005 National ICT Australia (NICTA)
5 *                      Aidan Williams <aidan@nicta.com.au>
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/mtd/mtd.h>
13#include <linux/mtd/partitions.h>
14#include <linux/spi/spi.h>
15#include <linux/spi/flash.h>
16#if IS_ENABLED(CONFIG_USB_ISP1362_HCD)
17#include <linux/usb/isp1362.h>
18#endif
19#include <linux/ata_platform.h>
20#include <linux/irq.h>
21#include <linux/interrupt.h>
22#include <linux/usb/sl811.h>
23#include <asm/dma.h>
24#include <asm/bfin5xx_spi.h>
25#include <asm/reboot.h>
26#include <asm/portmux.h>
27#include <linux/spi/ad7877.h>
28
29/*
30 * Name the Board for the /proc/cpuinfo
31 */
32const char bfin_board_name[] = "CamSig Minotaur BF537";
33
34#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
35static struct resource bfin_pcmcia_cf_resources[] = {
36	{
37		.start = 0x20310000, /* IO PORT */
38		.end = 0x20312000,
39		.flags = IORESOURCE_MEM,
40	}, {
41		.start = 0x20311000, /* Attribute Memory */
42		.end = 0x20311FFF,
43		.flags = IORESOURCE_MEM,
44	}, {
45		.start = IRQ_PF4,
46		.end = IRQ_PF4,
47		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
48	}, {
49		.start = IRQ_PF6, /* Card Detect PF6 */
50		.end = IRQ_PF6,
51		.flags = IORESOURCE_IRQ,
52	},
53};
54
55static struct platform_device bfin_pcmcia_cf_device = {
56	.name = "bfin_cf_pcmcia",
57	.id = -1,
58	.num_resources = ARRAY_SIZE(bfin_pcmcia_cf_resources),
59	.resource = bfin_pcmcia_cf_resources,
60};
61#endif
62
63#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
64static struct platform_device rtc_device = {
65	.name = "rtc-bfin",
66	.id   = -1,
67};
68#endif
69
70#if IS_ENABLED(CONFIG_BFIN_MAC)
71#include <linux/bfin_mac.h>
72static const unsigned short bfin_mac_peripherals[] = P_MII0;
73
74static struct bfin_phydev_platform_data bfin_phydev_data[] = {
75	{
76		.addr = 1,
77		.irq = IRQ_MAC_PHYINT,
78	},
79};
80
81static struct bfin_mii_bus_platform_data bfin_mii_bus_data = {
82	.phydev_number = 1,
83	.phydev_data = bfin_phydev_data,
84	.phy_mode = PHY_INTERFACE_MODE_MII,
85	.mac_peripherals = bfin_mac_peripherals,
86};
87
88static struct platform_device bfin_mii_bus = {
89	.name = "bfin_mii_bus",
90	.dev = {
91		.platform_data = &bfin_mii_bus_data,
92	}
93};
94
95static struct platform_device bfin_mac_device = {
96	.name = "bfin_mac",
97	.dev = {
98		.platform_data = &bfin_mii_bus,
99	}
100};
101#endif
102
103#if IS_ENABLED(CONFIG_USB_NET2272)
104static struct resource net2272_bfin_resources[] = {
105	{
106		.start = 0x20300000,
107		.end = 0x20300000 + 0x100,
108		.flags = IORESOURCE_MEM,
109	}, {
110		.start = IRQ_PF7,
111		.end = IRQ_PF7,
112		.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
113	},
114};
115
116static struct platform_device net2272_bfin_device = {
117	.name = "net2272",
118	.id = -1,
119	.num_resources = ARRAY_SIZE(net2272_bfin_resources),
120	.resource = net2272_bfin_resources,
121};
122#endif
123
124#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
125/* all SPI peripherals info goes here */
126
127#if IS_ENABLED(CONFIG_MTD_M25P80)
128
129/* Partition sizes */
130#define FLASH_SIZE       0x00400000
131#define PSIZE_UBOOT      0x00030000
132#define PSIZE_INITRAMFS  0x00240000
133
134static struct mtd_partition bfin_spi_flash_partitions[] = {
135	{
136		.name       = "bootloader(spi)",
137		.size       = PSIZE_UBOOT,
138		.offset     = 0x000000,
139		.mask_flags = MTD_CAP_ROM
140	}, {
141		.name       = "initramfs(spi)",
142		.size       = PSIZE_INITRAMFS,
143		.offset     = PSIZE_UBOOT
144	}, {
145		.name       = "opt(spi)",
146		.size       = FLASH_SIZE - (PSIZE_UBOOT + PSIZE_INITRAMFS),
147		.offset     = PSIZE_UBOOT + PSIZE_INITRAMFS,
148	}
149};
150
151static struct flash_platform_data bfin_spi_flash_data = {
152	.name = "m25p80",
153	.parts = bfin_spi_flash_partitions,
154	.nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions),
155	.type = "m25p64",
156};
157
158/* SPI flash chip (m25p64) */
159static struct bfin5xx_spi_chip spi_flash_chip_info = {
160	.enable_dma = 0,         /* use dma transfer with this chip*/
161};
162#endif
163
164#if IS_ENABLED(CONFIG_MMC_SPI)
165static struct bfin5xx_spi_chip mmc_spi_chip_info = {
166	.enable_dma = 0,
167};
168#endif
169
170static struct spi_board_info bfin_spi_board_info[] __initdata = {
171#if IS_ENABLED(CONFIG_MTD_M25P80)
172	{
173		/* the modalias must be the same as spi device driver name */
174		.modalias = "m25p80", /* Name of spi_driver for this device */
175		.max_speed_hz = 25000000,     /* max spi clock (SCK) speed in HZ */
176		.bus_num = 0, /* Framework bus number */
177		.chip_select = 1, /* Framework chip select. On STAMP537 it is SPISSEL1*/
178		.platform_data = &bfin_spi_flash_data,
179		.controller_data = &spi_flash_chip_info,
180		.mode = SPI_MODE_3,
181	},
182#endif
183
184#if IS_ENABLED(CONFIG_MMC_SPI)
185	{
186		.modalias = "mmc_spi",
187		.max_speed_hz = 5000000,     /* max spi clock (SCK) speed in HZ */
188		.bus_num = 0,
189		.chip_select = 5,
190		.controller_data = &mmc_spi_chip_info,
191		.mode = SPI_MODE_3,
192	},
193#endif
194};
195
196/* SPI controller data */
197static struct bfin5xx_spi_master bfin_spi0_info = {
198	.num_chipselect = 8,
199	.enable_dma = 1,  /* master has the ability to do dma transfer */
200};
201
202/* SPI (0) */
203static struct resource bfin_spi0_resource[] = {
204	[0] = {
205		.start = SPI0_REGBASE,
206		.end   = SPI0_REGBASE + 0xFF,
207		.flags = IORESOURCE_MEM,
208		},
209	[1] = {
210		.start = CH_SPI,
211		.end   = CH_SPI,
212		.flags = IORESOURCE_DMA,
213	},
214	[2] = {
215		.start = IRQ_SPI,
216		.end   = IRQ_SPI,
217		.flags = IORESOURCE_IRQ,
218	},
219};
220
221static struct platform_device bfin_spi0_device = {
222	.name = "bfin-spi",
223	.id = 0, /* Bus number */
224	.num_resources = ARRAY_SIZE(bfin_spi0_resource),
225	.resource = bfin_spi0_resource,
226	.dev = {
227		.platform_data = &bfin_spi0_info, /* Passed to driver */
228	},
229};
230#endif  /* spi master and devices */
231
232#if IS_ENABLED(CONFIG_SERIAL_BFIN)
233#ifdef CONFIG_SERIAL_BFIN_UART0
234static struct resource bfin_uart0_resources[] = {
235	{
236		.start = UART0_THR,
237		.end = UART0_GCTL+2,
238		.flags = IORESOURCE_MEM,
239	},
240	{
241		.start = IRQ_UART0_TX,
242		.end = IRQ_UART0_TX,
243		.flags = IORESOURCE_IRQ,
244	},
245	{
246		.start = IRQ_UART0_RX,
247		.end = IRQ_UART0_RX,
248		.flags = IORESOURCE_IRQ,
249	},
250	{
251		.start = IRQ_UART0_ERROR,
252		.end = IRQ_UART0_ERROR,
253		.flags = IORESOURCE_IRQ,
254	},
255	{
256		.start = CH_UART0_TX,
257		.end = CH_UART0_TX,
258		.flags = IORESOURCE_DMA,
259	},
260	{
261		.start = CH_UART0_RX,
262		.end = CH_UART0_RX,
263		.flags = IORESOURCE_DMA,
264	},
265};
266
267static unsigned short bfin_uart0_peripherals[] = {
268	P_UART0_TX, P_UART0_RX, 0
269};
270
271static struct platform_device bfin_uart0_device = {
272	.name = "bfin-uart",
273	.id = 0,
274	.num_resources = ARRAY_SIZE(bfin_uart0_resources),
275	.resource = bfin_uart0_resources,
276	.dev = {
277		.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
278	},
279};
280#endif
281#ifdef CONFIG_SERIAL_BFIN_UART1
282static struct resource bfin_uart1_resources[] = {
283	{
284		.start = UART1_THR,
285		.end = UART1_GCTL+2,
286		.flags = IORESOURCE_MEM,
287	},
288	{
289		.start = IRQ_UART1_TX,
290		.end = IRQ_UART1_TX,
291		.flags = IORESOURCE_IRQ,
292	},
293	{
294		.start = IRQ_UART1_RX,
295		.end = IRQ_UART1_RX,
296		.flags = IORESOURCE_IRQ,
297	},
298	{
299		.start = IRQ_UART1_ERROR,
300		.end = IRQ_UART1_ERROR,
301		.flags = IORESOURCE_IRQ,
302	},
303	{
304		.start = CH_UART1_TX,
305		.end = CH_UART1_TX,
306		.flags = IORESOURCE_DMA,
307	},
308	{
309		.start = CH_UART1_RX,
310		.end = CH_UART1_RX,
311		.flags = IORESOURCE_DMA,
312	},
313};
314
315static unsigned short bfin_uart1_peripherals[] = {
316	P_UART1_TX, P_UART1_RX, 0
317};
318
319static struct platform_device bfin_uart1_device = {
320	.name = "bfin-uart",
321	.id = 1,
322	.num_resources = ARRAY_SIZE(bfin_uart1_resources),
323	.resource = bfin_uart1_resources,
324	.dev = {
325		.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
326	},
327};
328#endif
329#endif
330
331#if IS_ENABLED(CONFIG_BFIN_SIR)
332#ifdef CONFIG_BFIN_SIR0
333static struct resource bfin_sir0_resources[] = {
334	{
335		.start = 0xFFC00400,
336		.end = 0xFFC004FF,
337		.flags = IORESOURCE_MEM,
338	},
339	{
340		.start = IRQ_UART0_RX,
341		.end = IRQ_UART0_RX+1,
342		.flags = IORESOURCE_IRQ,
343	},
344	{
345		.start = CH_UART0_RX,
346		.end = CH_UART0_RX+1,
347		.flags = IORESOURCE_DMA,
348	},
349};
350
351static struct platform_device bfin_sir0_device = {
352	.name = "bfin_sir",
353	.id = 0,
354	.num_resources = ARRAY_SIZE(bfin_sir0_resources),
355	.resource = bfin_sir0_resources,
356};
357#endif
358#ifdef CONFIG_BFIN_SIR1
359static struct resource bfin_sir1_resources[] = {
360	{
361		.start = 0xFFC02000,
362		.end = 0xFFC020FF,
363		.flags = IORESOURCE_MEM,
364	},
365	{
366		.start = IRQ_UART1_RX,
367		.end = IRQ_UART1_RX+1,
368		.flags = IORESOURCE_IRQ,
369	},
370	{
371		.start = CH_UART1_RX,
372		.end = CH_UART1_RX+1,
373		.flags = IORESOURCE_DMA,
374	},
375};
376
377static struct platform_device bfin_sir1_device = {
378	.name = "bfin_sir",
379	.id = 1,
380	.num_resources = ARRAY_SIZE(bfin_sir1_resources),
381	.resource = bfin_sir1_resources,
382};
383#endif
384#endif
385
386#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
387static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0};
388
389static struct resource bfin_twi0_resource[] = {
390	[0] = {
391		.start = TWI0_REGBASE,
392		.end   = TWI0_REGBASE + 0xFF,
393		.flags = IORESOURCE_MEM,
394	},
395	[1] = {
396		.start = IRQ_TWI,
397		.end   = IRQ_TWI,
398		.flags = IORESOURCE_IRQ,
399	},
400};
401
402static struct platform_device i2c_bfin_twi_device = {
403	.name = "i2c-bfin-twi",
404	.id = 0,
405	.num_resources = ARRAY_SIZE(bfin_twi0_resource),
406	.resource = bfin_twi0_resource,
407	.dev = {
408		.platform_data = &bfin_twi0_pins,
409	},
410};
411#endif
412
413#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
414#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
415static struct resource bfin_sport0_uart_resources[] = {
416	{
417		.start = SPORT0_TCR1,
418		.end = SPORT0_MRCS3+4,
419		.flags = IORESOURCE_MEM,
420	},
421	{
422		.start = IRQ_SPORT0_RX,
423		.end = IRQ_SPORT0_RX+1,
424		.flags = IORESOURCE_IRQ,
425	},
426	{
427		.start = IRQ_SPORT0_ERROR,
428		.end = IRQ_SPORT0_ERROR,
429		.flags = IORESOURCE_IRQ,
430	},
431};
432
433static unsigned short bfin_sport0_peripherals[] = {
434	P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
435	P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
436};
437
438static struct platform_device bfin_sport0_uart_device = {
439	.name = "bfin-sport-uart",
440	.id = 0,
441	.num_resources = ARRAY_SIZE(bfin_sport0_uart_resources),
442	.resource = bfin_sport0_uart_resources,
443	.dev = {
444		.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
445	},
446};
447#endif
448#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
449static struct resource bfin_sport1_uart_resources[] = {
450	{
451		.start = SPORT1_TCR1,
452		.end = SPORT1_MRCS3+4,
453		.flags = IORESOURCE_MEM,
454	},
455	{
456		.start = IRQ_SPORT1_RX,
457		.end = IRQ_SPORT1_RX+1,
458		.flags = IORESOURCE_IRQ,
459	},
460	{
461		.start = IRQ_SPORT1_ERROR,
462		.end = IRQ_SPORT1_ERROR,
463		.flags = IORESOURCE_IRQ,
464	},
465};
466
467static unsigned short bfin_sport1_peripherals[] = {
468	P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
469	P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
470};
471
472static struct platform_device bfin_sport1_uart_device = {
473	.name = "bfin-sport-uart",
474	.id = 1,
475	.num_resources = ARRAY_SIZE(bfin_sport1_uart_resources),
476	.resource = bfin_sport1_uart_resources,
477	.dev = {
478		.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
479	},
480};
481#endif
482#endif
483
484static struct platform_device *minotaur_devices[] __initdata = {
485#if IS_ENABLED(CONFIG_BFIN_CFPCMCIA)
486	&bfin_pcmcia_cf_device,
487#endif
488
489#if IS_ENABLED(CONFIG_RTC_DRV_BFIN)
490	&rtc_device,
491#endif
492
493#if IS_ENABLED(CONFIG_BFIN_MAC)
494	&bfin_mii_bus,
495	&bfin_mac_device,
496#endif
497
498#if IS_ENABLED(CONFIG_USB_NET2272)
499	&net2272_bfin_device,
500#endif
501
502#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
503	&bfin_spi0_device,
504#endif
505
506#if IS_ENABLED(CONFIG_SERIAL_BFIN)
507#ifdef CONFIG_SERIAL_BFIN_UART0
508	&bfin_uart0_device,
509#endif
510#ifdef CONFIG_SERIAL_BFIN_UART1
511	&bfin_uart1_device,
512#endif
513#endif
514
515#if IS_ENABLED(CONFIG_BFIN_SIR)
516#ifdef CONFIG_BFIN_SIR0
517	&bfin_sir0_device,
518#endif
519#ifdef CONFIG_BFIN_SIR1
520	&bfin_sir1_device,
521#endif
522#endif
523
524#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI)
525	&i2c_bfin_twi_device,
526#endif
527
528#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT)
529#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
530	&bfin_sport0_uart_device,
531#endif
532#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
533	&bfin_sport1_uart_device,
534#endif
535#endif
536
537};
538
539static int __init minotaur_init(void)
540{
541	printk(KERN_INFO "%s(): registering device resources\n", __func__);
542	platform_add_devices(minotaur_devices, ARRAY_SIZE(minotaur_devices));
543#if IS_ENABLED(CONFIG_SPI_BFIN5XX)
544	spi_register_board_info(bfin_spi_board_info,
545				ARRAY_SIZE(bfin_spi_board_info));
546#endif
547
548	return 0;
549}
550
551arch_initcall(minotaur_init);
552
553static struct platform_device *minotaur_early_devices[] __initdata = {
554#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
555#ifdef CONFIG_SERIAL_BFIN_UART0
556	&bfin_uart0_device,
557#endif
558#ifdef CONFIG_SERIAL_BFIN_UART1
559	&bfin_uart1_device,
560#endif
561#endif
562
563#if defined(CONFIG_SERIAL_BFIN_SPORT_CONSOLE)
564#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
565	&bfin_sport0_uart_device,
566#endif
567#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
568	&bfin_sport1_uart_device,
569#endif
570#endif
571};
572
573void __init native_machine_early_platform_add_devices(void)
574{
575	printk(KERN_INFO "register early platform devices\n");
576	early_platform_add_devices(minotaur_early_devices,
577		ARRAY_SIZE(minotaur_early_devices));
578}
579
580void native_machine_restart(char *cmd)
581{
582	/* workaround reboot hang when booting from SPI */
583	if ((bfin_read_SYSCR() & 0x7) == 0x3)
584		bfin_reset_boot_spi_cs(P_DEFAULT_BOOT_SPI_CS);
585}
586