1/* 2 * Copyright 2004-2009 Analog Devices Inc. 3 * 2005 National ICT Australia (NICTA) 4 * Aidan Williams <aidan@nicta.com.au> 5 * 6 * Licensed under the GPL-2 or later. 7 */ 8 9#include <linux/device.h> 10#include <linux/platform_device.h> 11#include <linux/mtd/mtd.h> 12#include <linux/mtd/partitions.h> 13#include <linux/mtd/physmap.h> 14#include <linux/spi/spi.h> 15#include <linux/spi/flash.h> 16#include <linux/irq.h> 17#include <linux/i2c.h> 18#include <linux/interrupt.h> 19#include <linux/usb/musb.h> 20#include <linux/pinctrl/machine.h> 21#include <linux/pinctrl/pinconf-generic.h> 22#include <linux/platform_data/pinctrl-adi2.h> 23#include <asm/bfin5xx_spi.h> 24#include <asm/dma.h> 25#include <asm/gpio.h> 26#include <asm/nand.h> 27#include <asm/dpmc.h> 28#include <asm/bfin_sport.h> 29#include <asm/portmux.h> 30#include <asm/bfin_sdh.h> 31#include <mach/bf54x_keys.h> 32#include <linux/input.h> 33#include <linux/spi/ad7877.h> 34 35/* 36 * Name the Board for the /proc/cpuinfo 37 */ 38const char bfin_board_name[] = "ADI BF548-EZKIT"; 39 40/* 41 * Driver needs to know address, irq and flag pin. 42 */ 43 44#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) 45#include <linux/usb/isp1760.h> 46static struct resource bfin_isp1760_resources[] = { 47 [0] = { 48 .start = 0x2C0C0000, 49 .end = 0x2C0C0000 + 0xfffff, 50 .flags = IORESOURCE_MEM, 51 }, 52 [1] = { 53 .start = IRQ_PG7, 54 .end = IRQ_PG7, 55 .flags = IORESOURCE_IRQ, 56 }, 57}; 58 59static struct isp1760_platform_data isp1760_priv = { 60 .is_isp1761 = 0, 61 .bus_width_16 = 1, 62 .port1_otg = 0, 63 .analog_oc = 0, 64 .dack_polarity_high = 0, 65 .dreq_polarity_high = 0, 66}; 67 68static struct platform_device bfin_isp1760_device = { 69 .name = "isp1760", 70 .id = 0, 71 .dev = { 72 .platform_data = &isp1760_priv, 73 }, 74 .num_resources = ARRAY_SIZE(bfin_isp1760_resources), 75 .resource = bfin_isp1760_resources, 76}; 77#endif 78 79#if IS_ENABLED(CONFIG_FB_BF54X_LQ043) 80 81#include <mach/bf54x-lq043.h> 82 83static struct bfin_bf54xfb_mach_info bf54x_lq043_data = { 84 .width = 95, 85 .height = 54, 86 .xres = {480, 480, 480}, 87 .yres = {272, 272, 272}, 88 .bpp = {24, 24, 24}, 89 .disp = GPIO_PE3, 90}; 91 92static struct resource bf54x_lq043_resources[] = { 93 { 94 .start = IRQ_EPPI0_ERR, 95 .end = IRQ_EPPI0_ERR, 96 .flags = IORESOURCE_IRQ, 97 }, 98}; 99 100static struct platform_device bf54x_lq043_device = { 101 .name = "bf54x-lq043", 102 .id = -1, 103 .num_resources = ARRAY_SIZE(bf54x_lq043_resources), 104 .resource = bf54x_lq043_resources, 105 .dev = { 106 .platform_data = &bf54x_lq043_data, 107 }, 108}; 109#endif 110 111#if IS_ENABLED(CONFIG_KEYBOARD_BFIN) 112static const unsigned int bf548_keymap[] = { 113 KEYVAL(0, 0, KEY_ENTER), 114 KEYVAL(0, 1, KEY_HELP), 115 KEYVAL(0, 2, KEY_0), 116 KEYVAL(0, 3, KEY_BACKSPACE), 117 KEYVAL(1, 0, KEY_TAB), 118 KEYVAL(1, 1, KEY_9), 119 KEYVAL(1, 2, KEY_8), 120 KEYVAL(1, 3, KEY_7), 121 KEYVAL(2, 0, KEY_DOWN), 122 KEYVAL(2, 1, KEY_6), 123 KEYVAL(2, 2, KEY_5), 124 KEYVAL(2, 3, KEY_4), 125 KEYVAL(3, 0, KEY_UP), 126 KEYVAL(3, 1, KEY_3), 127 KEYVAL(3, 2, KEY_2), 128 KEYVAL(3, 3, KEY_1), 129}; 130 131static struct bfin_kpad_platform_data bf54x_kpad_data = { 132 .rows = 4, 133 .cols = 4, 134 .keymap = bf548_keymap, 135 .keymapsize = ARRAY_SIZE(bf548_keymap), 136 .repeat = 0, 137 .debounce_time = 5000, /* ns (5ms) */ 138 .coldrive_time = 1000, /* ns (1ms) */ 139 .keyup_test_interval = 50, /* ms (50ms) */ 140}; 141 142static struct resource bf54x_kpad_resources[] = { 143 { 144 .start = IRQ_KEY, 145 .end = IRQ_KEY, 146 .flags = IORESOURCE_IRQ, 147 }, 148}; 149 150static struct platform_device bf54x_kpad_device = { 151 .name = "bf54x-keys", 152 .id = -1, 153 .num_resources = ARRAY_SIZE(bf54x_kpad_resources), 154 .resource = bf54x_kpad_resources, 155 .dev = { 156 .platform_data = &bf54x_kpad_data, 157 }, 158}; 159#endif 160 161#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) 162#include <linux/platform_data/bfin_rotary.h> 163 164static struct bfin_rotary_platform_data bfin_rotary_data = { 165 /*.rotary_up_key = KEY_UP,*/ 166 /*.rotary_down_key = KEY_DOWN,*/ 167 .rotary_rel_code = REL_WHEEL, 168 .rotary_button_key = KEY_ENTER, 169 .debounce = 10, /* 0..17 */ 170 .mode = ROT_QUAD_ENC | ROT_DEBE, 171 .pm_wakeup = 1, 172}; 173 174static struct resource bfin_rotary_resources[] = { 175 { 176 .start = CNT_CONFIG, 177 .end = CNT_CONFIG + 0xff, 178 .flags = IORESOURCE_MEM, 179 }, 180 { 181 .start = IRQ_CNT, 182 .end = IRQ_CNT, 183 .flags = IORESOURCE_IRQ, 184 }, 185}; 186 187static struct platform_device bfin_rotary_device = { 188 .name = "bfin-rotary", 189 .id = -1, 190 .num_resources = ARRAY_SIZE(bfin_rotary_resources), 191 .resource = bfin_rotary_resources, 192 .dev = { 193 .platform_data = &bfin_rotary_data, 194 }, 195}; 196#endif 197 198#if IS_ENABLED(CONFIG_INPUT_ADXL34X) 199#include <linux/input/adxl34x.h> 200static const struct adxl34x_platform_data adxl34x_info = { 201 .x_axis_offset = 0, 202 .y_axis_offset = 0, 203 .z_axis_offset = 0, 204 .tap_threshold = 0x31, 205 .tap_duration = 0x10, 206 .tap_latency = 0x60, 207 .tap_window = 0xF0, 208 .tap_axis_control = ADXL_TAP_X_EN | ADXL_TAP_Y_EN | ADXL_TAP_Z_EN, 209 .act_axis_control = 0xFF, 210 .activity_threshold = 5, 211 .inactivity_threshold = 3, 212 .inactivity_time = 4, 213 .free_fall_threshold = 0x7, 214 .free_fall_time = 0x20, 215 .data_rate = 0x8, 216 .data_range = ADXL_FULL_RES, 217 218 .ev_type = EV_ABS, 219 .ev_code_x = ABS_X, /* EV_REL */ 220 .ev_code_y = ABS_Y, /* EV_REL */ 221 .ev_code_z = ABS_Z, /* EV_REL */ 222 223 .ev_code_tap = {BTN_TOUCH, BTN_TOUCH, BTN_TOUCH}, /* EV_KEY x,y,z */ 224 225/* .ev_code_ff = KEY_F,*/ /* EV_KEY */ 226/* .ev_code_act_inactivity = KEY_A,*/ /* EV_KEY */ 227 .power_mode = ADXL_AUTO_SLEEP | ADXL_LINK, 228 .fifo_mode = ADXL_FIFO_STREAM, 229 .orientation_enable = ADXL_EN_ORIENTATION_3D, 230 .deadzone_angle = ADXL_DEADZONE_ANGLE_10p8, 231 .divisor_length = ADXL_LP_FILTER_DIVISOR_16, 232 /* EV_KEY {+Z, +Y, +X, -X, -Y, -Z} */ 233 .ev_codes_orient_3d = {BTN_Z, BTN_Y, BTN_X, BTN_A, BTN_B, BTN_C}, 234}; 235#endif 236 237#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) 238static struct platform_device rtc_device = { 239 .name = "rtc-bfin", 240 .id = -1, 241}; 242#endif 243 244#if IS_ENABLED(CONFIG_SERIAL_BFIN) 245#ifdef CONFIG_SERIAL_BFIN_UART0 246static struct resource bfin_uart0_resources[] = { 247 { 248 .start = UART0_DLL, 249 .end = UART0_RBR+2, 250 .flags = IORESOURCE_MEM, 251 }, 252#ifdef CONFIG_EARLY_PRINTK 253 { 254 .start = PORTE_FER, 255 .end = PORTE_FER+2, 256 .flags = IORESOURCE_REG, 257 }, 258#endif 259 { 260 .start = IRQ_UART0_TX, 261 .end = IRQ_UART0_TX, 262 .flags = IORESOURCE_IRQ, 263 }, 264 { 265 .start = IRQ_UART0_RX, 266 .end = IRQ_UART0_RX, 267 .flags = IORESOURCE_IRQ, 268 }, 269 { 270 .start = IRQ_UART0_ERROR, 271 .end = IRQ_UART0_ERROR, 272 .flags = IORESOURCE_IRQ, 273 }, 274 { 275 .start = CH_UART0_TX, 276 .end = CH_UART0_TX, 277 .flags = IORESOURCE_DMA, 278 }, 279 { 280 .start = CH_UART0_RX, 281 .end = CH_UART0_RX, 282 .flags = IORESOURCE_DMA, 283 }, 284}; 285 286static unsigned short bfin_uart0_peripherals[] = { 287 P_UART0_TX, P_UART0_RX, 0 288}; 289 290static struct platform_device bfin_uart0_device = { 291 .name = "bfin-uart", 292 .id = 0, 293 .num_resources = ARRAY_SIZE(bfin_uart0_resources), 294 .resource = bfin_uart0_resources, 295 .dev = { 296 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */ 297 }, 298}; 299#endif 300#ifdef CONFIG_SERIAL_BFIN_UART1 301static struct resource bfin_uart1_resources[] = { 302 { 303 .start = UART1_DLL, 304 .end = UART1_RBR+2, 305 .flags = IORESOURCE_MEM, 306 }, 307#ifdef CONFIG_EARLY_PRINTK 308 { 309 .start = PORTH_FER, 310 .end = PORTH_FER+2, 311 .flags = IORESOURCE_REG, 312 }, 313#endif 314 { 315 .start = IRQ_UART1_TX, 316 .end = IRQ_UART1_TX, 317 .flags = IORESOURCE_IRQ, 318 }, 319 { 320 .start = IRQ_UART1_RX, 321 .end = IRQ_UART1_RX, 322 .flags = IORESOURCE_IRQ, 323 }, 324 { 325 .start = IRQ_UART1_ERROR, 326 .end = IRQ_UART1_ERROR, 327 .flags = IORESOURCE_IRQ, 328 }, 329 { 330 .start = CH_UART1_TX, 331 .end = CH_UART1_TX, 332 .flags = IORESOURCE_DMA, 333 }, 334 { 335 .start = CH_UART1_RX, 336 .end = CH_UART1_RX, 337 .flags = IORESOURCE_DMA, 338 }, 339#ifdef CONFIG_BFIN_UART1_CTSRTS 340 { /* CTS pin -- 0 means not supported */ 341 .start = GPIO_PE10, 342 .end = GPIO_PE10, 343 .flags = IORESOURCE_IO, 344 }, 345 { /* RTS pin -- 0 means not supported */ 346 .start = GPIO_PE9, 347 .end = GPIO_PE9, 348 .flags = IORESOURCE_IO, 349 }, 350#endif 351}; 352 353static unsigned short bfin_uart1_peripherals[] = { 354 P_UART1_TX, P_UART1_RX, 355#ifdef CONFIG_BFIN_UART1_CTSRTS 356 P_UART1_RTS, P_UART1_CTS, 357#endif 358 0 359}; 360 361static struct platform_device bfin_uart1_device = { 362 .name = "bfin-uart", 363 .id = 1, 364 .num_resources = ARRAY_SIZE(bfin_uart1_resources), 365 .resource = bfin_uart1_resources, 366 .dev = { 367 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */ 368 }, 369}; 370#endif 371#ifdef CONFIG_SERIAL_BFIN_UART2 372static struct resource bfin_uart2_resources[] = { 373 { 374 .start = UART2_DLL, 375 .end = UART2_RBR+2, 376 .flags = IORESOURCE_MEM, 377 }, 378#ifdef CONFIG_EARLY_PRINTK 379 { 380 .start = PORTB_FER, 381 .end = PORTB_FER+2, 382 .flags = IORESOURCE_REG, 383 }, 384#endif 385 { 386 .start = IRQ_UART2_TX, 387 .end = IRQ_UART2_TX, 388 .flags = IORESOURCE_IRQ, 389 }, 390 { 391 .start = IRQ_UART2_RX, 392 .end = IRQ_UART2_RX, 393 .flags = IORESOURCE_IRQ, 394 }, 395 { 396 .start = IRQ_UART2_ERROR, 397 .end = IRQ_UART2_ERROR, 398 .flags = IORESOURCE_IRQ, 399 }, 400 { 401 .start = CH_UART2_TX, 402 .end = CH_UART2_TX, 403 .flags = IORESOURCE_DMA, 404 }, 405 { 406 .start = CH_UART2_RX, 407 .end = CH_UART2_RX, 408 .flags = IORESOURCE_DMA, 409 }, 410}; 411 412static unsigned short bfin_uart2_peripherals[] = { 413 P_UART2_TX, P_UART2_RX, 0 414}; 415 416static struct platform_device bfin_uart2_device = { 417 .name = "bfin-uart", 418 .id = 2, 419 .num_resources = ARRAY_SIZE(bfin_uart2_resources), 420 .resource = bfin_uart2_resources, 421 .dev = { 422 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */ 423 }, 424}; 425#endif 426#ifdef CONFIG_SERIAL_BFIN_UART3 427static struct resource bfin_uart3_resources[] = { 428 { 429 .start = UART3_DLL, 430 .end = UART3_RBR+2, 431 .flags = IORESOURCE_MEM, 432 }, 433#ifdef CONFIG_EARLY_PRINTK 434 { 435 .start = PORTB_FER, 436 .end = PORTB_FER+2, 437 .flags = IORESOURCE_REG, 438 }, 439#endif 440 { 441 .start = IRQ_UART3_TX, 442 .end = IRQ_UART3_TX, 443 .flags = IORESOURCE_IRQ, 444 }, 445 { 446 .start = IRQ_UART3_RX, 447 .end = IRQ_UART3_RX, 448 .flags = IORESOURCE_IRQ, 449 }, 450 { 451 .start = IRQ_UART3_ERROR, 452 .end = IRQ_UART3_ERROR, 453 .flags = IORESOURCE_IRQ, 454 }, 455 { 456 .start = CH_UART3_TX, 457 .end = CH_UART3_TX, 458 .flags = IORESOURCE_DMA, 459 }, 460 { 461 .start = CH_UART3_RX, 462 .end = CH_UART3_RX, 463 .flags = IORESOURCE_DMA, 464 }, 465#ifdef CONFIG_BFIN_UART3_CTSRTS 466 { /* CTS pin -- 0 means not supported */ 467 .start = GPIO_PB3, 468 .end = GPIO_PB3, 469 .flags = IORESOURCE_IO, 470 }, 471 { /* RTS pin -- 0 means not supported */ 472 .start = GPIO_PB2, 473 .end = GPIO_PB2, 474 .flags = IORESOURCE_IO, 475 }, 476#endif 477}; 478 479static unsigned short bfin_uart3_peripherals[] = { 480 P_UART3_TX, P_UART3_RX, 481#ifdef CONFIG_BFIN_UART3_CTSRTS 482 P_UART3_RTS, P_UART3_CTS, 483#endif 484 0 485}; 486 487static struct platform_device bfin_uart3_device = { 488 .name = "bfin-uart", 489 .id = 3, 490 .num_resources = ARRAY_SIZE(bfin_uart3_resources), 491 .resource = bfin_uart3_resources, 492 .dev = { 493 .platform_data = &bfin_uart3_peripherals, /* Passed to driver */ 494 }, 495}; 496#endif 497#endif 498 499#if IS_ENABLED(CONFIG_BFIN_SIR) 500#ifdef CONFIG_BFIN_SIR0 501static struct resource bfin_sir0_resources[] = { 502 { 503 .start = 0xFFC00400, 504 .end = 0xFFC004FF, 505 .flags = IORESOURCE_MEM, 506 }, 507 { 508 .start = IRQ_UART0_RX, 509 .end = IRQ_UART0_RX+1, 510 .flags = IORESOURCE_IRQ, 511 }, 512 { 513 .start = CH_UART0_RX, 514 .end = CH_UART0_RX+1, 515 .flags = IORESOURCE_DMA, 516 }, 517}; 518static struct platform_device bfin_sir0_device = { 519 .name = "bfin_sir", 520 .id = 0, 521 .num_resources = ARRAY_SIZE(bfin_sir0_resources), 522 .resource = bfin_sir0_resources, 523}; 524#endif 525#ifdef CONFIG_BFIN_SIR1 526static struct resource bfin_sir1_resources[] = { 527 { 528 .start = 0xFFC02000, 529 .end = 0xFFC020FF, 530 .flags = IORESOURCE_MEM, 531 }, 532 { 533 .start = IRQ_UART1_RX, 534 .end = IRQ_UART1_RX+1, 535 .flags = IORESOURCE_IRQ, 536 }, 537 { 538 .start = CH_UART1_RX, 539 .end = CH_UART1_RX+1, 540 .flags = IORESOURCE_DMA, 541 }, 542}; 543static struct platform_device bfin_sir1_device = { 544 .name = "bfin_sir", 545 .id = 1, 546 .num_resources = ARRAY_SIZE(bfin_sir1_resources), 547 .resource = bfin_sir1_resources, 548}; 549#endif 550#ifdef CONFIG_BFIN_SIR2 551static struct resource bfin_sir2_resources[] = { 552 { 553 .start = 0xFFC02100, 554 .end = 0xFFC021FF, 555 .flags = IORESOURCE_MEM, 556 }, 557 { 558 .start = IRQ_UART2_RX, 559 .end = IRQ_UART2_RX+1, 560 .flags = IORESOURCE_IRQ, 561 }, 562 { 563 .start = CH_UART2_RX, 564 .end = CH_UART2_RX+1, 565 .flags = IORESOURCE_DMA, 566 }, 567}; 568static struct platform_device bfin_sir2_device = { 569 .name = "bfin_sir", 570 .id = 2, 571 .num_resources = ARRAY_SIZE(bfin_sir2_resources), 572 .resource = bfin_sir2_resources, 573}; 574#endif 575#ifdef CONFIG_BFIN_SIR3 576static struct resource bfin_sir3_resources[] = { 577 { 578 .start = 0xFFC03100, 579 .end = 0xFFC031FF, 580 .flags = IORESOURCE_MEM, 581 }, 582 { 583 .start = IRQ_UART3_RX, 584 .end = IRQ_UART3_RX+1, 585 .flags = IORESOURCE_IRQ, 586 }, 587 { 588 .start = CH_UART3_RX, 589 .end = CH_UART3_RX+1, 590 .flags = IORESOURCE_DMA, 591 }, 592}; 593static struct platform_device bfin_sir3_device = { 594 .name = "bfin_sir", 595 .id = 3, 596 .num_resources = ARRAY_SIZE(bfin_sir3_resources), 597 .resource = bfin_sir3_resources, 598}; 599#endif 600#endif 601 602#if IS_ENABLED(CONFIG_SMSC911X) 603#include <linux/smsc911x.h> 604 605static struct resource smsc911x_resources[] = { 606 { 607 .name = "smsc911x-memory", 608 .start = 0x24000000, 609 .end = 0x24000000 + 0xFF, 610 .flags = IORESOURCE_MEM, 611 }, 612 { 613 .start = IRQ_PE8, 614 .end = IRQ_PE8, 615 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, 616 }, 617}; 618 619static struct smsc911x_platform_config smsc911x_config = { 620 .flags = SMSC911X_USE_32BIT, 621 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 622 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, 623 .phy_interface = PHY_INTERFACE_MODE_MII, 624}; 625 626static struct platform_device smsc911x_device = { 627 .name = "smsc911x", 628 .id = 0, 629 .num_resources = ARRAY_SIZE(smsc911x_resources), 630 .resource = smsc911x_resources, 631 .dev = { 632 .platform_data = &smsc911x_config, 633 }, 634}; 635#endif 636 637#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) 638static struct resource musb_resources[] = { 639 [0] = { 640 .start = 0xFFC03C00, 641 .end = 0xFFC040FF, 642 .flags = IORESOURCE_MEM, 643 }, 644 [1] = { /* general IRQ */ 645 .start = IRQ_USB_INT0, 646 .end = IRQ_USB_INT0, 647 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 648 .name = "mc" 649 }, 650 [2] = { /* DMA IRQ */ 651 .start = IRQ_USB_DMA, 652 .end = IRQ_USB_DMA, 653 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL, 654 .name = "dma" 655 }, 656}; 657 658static struct musb_hdrc_config musb_config = { 659 .multipoint = 0, 660 .dyn_fifo = 0, 661 .soft_con = 1, 662 .dma = 1, 663 .num_eps = 8, 664 .dma_channels = 8, 665 .gpio_vrsel = GPIO_PE7, 666 /* Some custom boards need to be active low, just set it to "0" 667 * if it is the case. 668 */ 669 .gpio_vrsel_active = 1, 670 .clkin = 24, /* musb CLKIN in MHZ */ 671}; 672 673static struct musb_hdrc_platform_data musb_plat = { 674#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC) 675 .mode = MUSB_OTG, 676#elif defined(CONFIG_USB_MUSB_HDRC) 677 .mode = MUSB_HOST, 678#elif defined(CONFIG_USB_GADGET_MUSB_HDRC) 679 .mode = MUSB_PERIPHERAL, 680#endif 681 .config = &musb_config, 682}; 683 684static u64 musb_dmamask = ~(u32)0; 685 686static struct platform_device musb_device = { 687 .name = "musb-blackfin", 688 .id = 0, 689 .dev = { 690 .dma_mask = &musb_dmamask, 691 .coherent_dma_mask = 0xffffffff, 692 .platform_data = &musb_plat, 693 }, 694 .num_resources = ARRAY_SIZE(musb_resources), 695 .resource = musb_resources, 696}; 697#endif 698 699#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) 700#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 701static struct resource bfin_sport0_uart_resources[] = { 702 { 703 .start = SPORT0_TCR1, 704 .end = SPORT0_MRCS3+4, 705 .flags = IORESOURCE_MEM, 706 }, 707 { 708 .start = IRQ_SPORT0_RX, 709 .end = IRQ_SPORT0_RX+1, 710 .flags = IORESOURCE_IRQ, 711 }, 712 { 713 .start = IRQ_SPORT0_ERROR, 714 .end = IRQ_SPORT0_ERROR, 715 .flags = IORESOURCE_IRQ, 716 }, 717}; 718 719static unsigned short bfin_sport0_peripherals[] = { 720 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS, 721 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0 722}; 723 724static struct platform_device bfin_sport0_uart_device = { 725 .name = "bfin-sport-uart", 726 .id = 0, 727 .num_resources = ARRAY_SIZE(bfin_sport0_uart_resources), 728 .resource = bfin_sport0_uart_resources, 729 .dev = { 730 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */ 731 }, 732}; 733#endif 734#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 735static struct resource bfin_sport1_uart_resources[] = { 736 { 737 .start = SPORT1_TCR1, 738 .end = SPORT1_MRCS3+4, 739 .flags = IORESOURCE_MEM, 740 }, 741 { 742 .start = IRQ_SPORT1_RX, 743 .end = IRQ_SPORT1_RX+1, 744 .flags = IORESOURCE_IRQ, 745 }, 746 { 747 .start = IRQ_SPORT1_ERROR, 748 .end = IRQ_SPORT1_ERROR, 749 .flags = IORESOURCE_IRQ, 750 }, 751}; 752 753static unsigned short bfin_sport1_peripherals[] = { 754 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS, 755 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0 756}; 757 758static struct platform_device bfin_sport1_uart_device = { 759 .name = "bfin-sport-uart", 760 .id = 1, 761 .num_resources = ARRAY_SIZE(bfin_sport1_uart_resources), 762 .resource = bfin_sport1_uart_resources, 763 .dev = { 764 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */ 765 }, 766}; 767#endif 768#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART 769static struct resource bfin_sport2_uart_resources[] = { 770 { 771 .start = SPORT2_TCR1, 772 .end = SPORT2_MRCS3+4, 773 .flags = IORESOURCE_MEM, 774 }, 775 { 776 .start = IRQ_SPORT2_RX, 777 .end = IRQ_SPORT2_RX+1, 778 .flags = IORESOURCE_IRQ, 779 }, 780 { 781 .start = IRQ_SPORT2_ERROR, 782 .end = IRQ_SPORT2_ERROR, 783 .flags = IORESOURCE_IRQ, 784 }, 785}; 786 787static unsigned short bfin_sport2_peripherals[] = { 788 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS, 789 P_SPORT2_DRPRI, P_SPORT2_RSCLK, P_SPORT2_DRSEC, P_SPORT2_DTSEC, 0 790}; 791 792static struct platform_device bfin_sport2_uart_device = { 793 .name = "bfin-sport-uart", 794 .id = 2, 795 .num_resources = ARRAY_SIZE(bfin_sport2_uart_resources), 796 .resource = bfin_sport2_uart_resources, 797 .dev = { 798 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */ 799 }, 800}; 801#endif 802#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART 803static struct resource bfin_sport3_uart_resources[] = { 804 { 805 .start = SPORT3_TCR1, 806 .end = SPORT3_MRCS3+4, 807 .flags = IORESOURCE_MEM, 808 }, 809 { 810 .start = IRQ_SPORT3_RX, 811 .end = IRQ_SPORT3_RX+1, 812 .flags = IORESOURCE_IRQ, 813 }, 814 { 815 .start = IRQ_SPORT3_ERROR, 816 .end = IRQ_SPORT3_ERROR, 817 .flags = IORESOURCE_IRQ, 818 }, 819}; 820 821static unsigned short bfin_sport3_peripherals[] = { 822 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS, 823 P_SPORT3_DRPRI, P_SPORT3_RSCLK, P_SPORT3_DRSEC, P_SPORT3_DTSEC, 0 824}; 825 826static struct platform_device bfin_sport3_uart_device = { 827 .name = "bfin-sport-uart", 828 .id = 3, 829 .num_resources = ARRAY_SIZE(bfin_sport3_uart_resources), 830 .resource = bfin_sport3_uart_resources, 831 .dev = { 832 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */ 833 }, 834}; 835#endif 836#endif 837 838#if IS_ENABLED(CONFIG_CAN_BFIN) 839 840static unsigned short bfin_can0_peripherals[] = { 841 P_CAN0_RX, P_CAN0_TX, 0 842}; 843 844static struct resource bfin_can0_resources[] = { 845 { 846 .start = 0xFFC02A00, 847 .end = 0xFFC02FFF, 848 .flags = IORESOURCE_MEM, 849 }, 850 { 851 .start = IRQ_CAN0_RX, 852 .end = IRQ_CAN0_RX, 853 .flags = IORESOURCE_IRQ, 854 }, 855 { 856 .start = IRQ_CAN0_TX, 857 .end = IRQ_CAN0_TX, 858 .flags = IORESOURCE_IRQ, 859 }, 860 { 861 .start = IRQ_CAN0_ERROR, 862 .end = IRQ_CAN0_ERROR, 863 .flags = IORESOURCE_IRQ, 864 }, 865}; 866 867static struct platform_device bfin_can0_device = { 868 .name = "bfin_can", 869 .id = 0, 870 .num_resources = ARRAY_SIZE(bfin_can0_resources), 871 .resource = bfin_can0_resources, 872 .dev = { 873 .platform_data = &bfin_can0_peripherals, /* Passed to driver */ 874 }, 875}; 876 877static unsigned short bfin_can1_peripherals[] = { 878 P_CAN1_RX, P_CAN1_TX, 0 879}; 880 881static struct resource bfin_can1_resources[] = { 882 { 883 .start = 0xFFC03200, 884 .end = 0xFFC037FF, 885 .flags = IORESOURCE_MEM, 886 }, 887 { 888 .start = IRQ_CAN1_RX, 889 .end = IRQ_CAN1_RX, 890 .flags = IORESOURCE_IRQ, 891 }, 892 { 893 .start = IRQ_CAN1_TX, 894 .end = IRQ_CAN1_TX, 895 .flags = IORESOURCE_IRQ, 896 }, 897 { 898 .start = IRQ_CAN1_ERROR, 899 .end = IRQ_CAN1_ERROR, 900 .flags = IORESOURCE_IRQ, 901 }, 902}; 903 904static struct platform_device bfin_can1_device = { 905 .name = "bfin_can", 906 .id = 1, 907 .num_resources = ARRAY_SIZE(bfin_can1_resources), 908 .resource = bfin_can1_resources, 909 .dev = { 910 .platform_data = &bfin_can1_peripherals, /* Passed to driver */ 911 }, 912}; 913 914#endif 915 916#if IS_ENABLED(CONFIG_PATA_BF54X) 917static struct resource bfin_atapi_resources[] = { 918 { 919 .start = 0xFFC03800, 920 .end = 0xFFC0386F, 921 .flags = IORESOURCE_MEM, 922 }, 923 { 924 .start = IRQ_ATAPI_ERR, 925 .end = IRQ_ATAPI_ERR, 926 .flags = IORESOURCE_IRQ, 927 }, 928}; 929 930static struct platform_device bfin_atapi_device = { 931 .name = "pata-bf54x", 932 .id = -1, 933 .num_resources = ARRAY_SIZE(bfin_atapi_resources), 934 .resource = bfin_atapi_resources, 935}; 936#endif 937 938#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) 939static struct mtd_partition partition_info[] = { 940 { 941 .name = "bootloader(nand)", 942 .offset = 0, 943 .size = 0x80000, 944 }, { 945 .name = "linux kernel(nand)", 946 .offset = MTDPART_OFS_APPEND, 947 .size = 4 * 1024 * 1024, 948 }, 949 { 950 .name = "file system(nand)", 951 .offset = MTDPART_OFS_APPEND, 952 .size = MTDPART_SIZ_FULL, 953 }, 954}; 955 956static struct bf5xx_nand_platform bf5xx_nand_platform = { 957 .data_width = NFC_NWIDTH_8, 958 .partitions = partition_info, 959 .nr_partitions = ARRAY_SIZE(partition_info), 960 .rd_dly = 3, 961 .wr_dly = 3, 962}; 963 964static struct resource bf5xx_nand_resources[] = { 965 { 966 .start = 0xFFC03B00, 967 .end = 0xFFC03B4F, 968 .flags = IORESOURCE_MEM, 969 }, 970 { 971 .start = CH_NFC, 972 .end = CH_NFC, 973 .flags = IORESOURCE_IRQ, 974 }, 975}; 976 977static struct platform_device bf5xx_nand_device = { 978 .name = "bf5xx-nand", 979 .id = 0, 980 .num_resources = ARRAY_SIZE(bf5xx_nand_resources), 981 .resource = bf5xx_nand_resources, 982 .dev = { 983 .platform_data = &bf5xx_nand_platform, 984 }, 985}; 986#endif 987 988#if IS_ENABLED(CONFIG_SDH_BFIN) 989 990static struct bfin_sd_host bfin_sdh_data = { 991 .dma_chan = CH_SDH, 992 .irq_int0 = IRQ_SDH_MASK0, 993 .pin_req = {P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0}, 994}; 995 996static struct platform_device bf54x_sdh_device = { 997 .name = "bfin-sdh", 998 .id = 0, 999 .dev = { 1000 .platform_data = &bfin_sdh_data, 1001 }, 1002}; 1003#endif 1004 1005#if IS_ENABLED(CONFIG_MTD_PHYSMAP) 1006static struct mtd_partition ezkit_partitions[] = { 1007 { 1008 .name = "bootloader(nor)", 1009 .size = 0x80000, 1010 .offset = 0, 1011 }, { 1012 .name = "linux kernel(nor)", 1013 .size = 0x400000, 1014 .offset = MTDPART_OFS_APPEND, 1015 }, { 1016 .name = "file system(nor)", 1017 .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4, 1018 .offset = MTDPART_OFS_APPEND, 1019 }, { 1020 .name = "config(nor)", 1021 .size = 0x8000 * 3, 1022 .offset = MTDPART_OFS_APPEND, 1023 }, { 1024 .name = "u-boot env(nor)", 1025 .size = 0x8000, 1026 .offset = MTDPART_OFS_APPEND, 1027 } 1028}; 1029 1030static struct physmap_flash_data ezkit_flash_data = { 1031 .width = 2, 1032 .parts = ezkit_partitions, 1033 .nr_parts = ARRAY_SIZE(ezkit_partitions), 1034}; 1035 1036static struct resource ezkit_flash_resource = { 1037 .start = 0x20000000, 1038 .end = 0x21ffffff, 1039 .flags = IORESOURCE_MEM, 1040}; 1041 1042static struct platform_device ezkit_flash_device = { 1043 .name = "physmap-flash", 1044 .id = 0, 1045 .dev = { 1046 .platform_data = &ezkit_flash_data, 1047 }, 1048 .num_resources = 1, 1049 .resource = &ezkit_flash_resource, 1050}; 1051#endif 1052 1053#if IS_ENABLED(CONFIG_MTD_M25P80) 1054/* SPI flash chip (m25p16) */ 1055static struct mtd_partition bfin_spi_flash_partitions[] = { 1056 { 1057 .name = "bootloader(spi)", 1058 .size = 0x00080000, 1059 .offset = 0, 1060 .mask_flags = MTD_CAP_ROM 1061 }, { 1062 .name = "linux kernel(spi)", 1063 .size = MTDPART_SIZ_FULL, 1064 .offset = MTDPART_OFS_APPEND, 1065 } 1066}; 1067 1068static struct flash_platform_data bfin_spi_flash_data = { 1069 .name = "m25p80", 1070 .parts = bfin_spi_flash_partitions, 1071 .nr_parts = ARRAY_SIZE(bfin_spi_flash_partitions), 1072 .type = "m25p16", 1073}; 1074 1075static struct bfin5xx_spi_chip spi_flash_chip_info = { 1076 .enable_dma = 0, /* use dma transfer with this chip*/ 1077}; 1078#endif 1079 1080#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) 1081static const struct ad7877_platform_data bfin_ad7877_ts_info = { 1082 .model = 7877, 1083 .vref_delay_usecs = 50, /* internal, no capacitor */ 1084 .x_plate_ohms = 419, 1085 .y_plate_ohms = 486, 1086 .pressure_max = 1000, 1087 .pressure_min = 0, 1088 .stopacq_polarity = 1, 1089 .first_conversion_delay = 3, 1090 .acquisition_time = 1, 1091 .averaging = 1, 1092 .pen_down_acc_interval = 1, 1093}; 1094#endif 1095 1096#ifdef CONFIG_PINCTRL_ADI2 1097 1098# define ADI_PINT_DEVNAME "adi-gpio-pint" 1099# define ADI_GPIO_DEVNAME "adi-gpio" 1100# define ADI_PINCTRL_DEVNAME "pinctrl-adi2" 1101 1102static struct platform_device bfin_pinctrl_device = { 1103 .name = ADI_PINCTRL_DEVNAME, 1104 .id = 0, 1105}; 1106 1107static struct resource bfin_pint0_resources[] = { 1108 { 1109 .start = PINT0_MASK_SET, 1110 .end = PINT0_LATCH + 3, 1111 .flags = IORESOURCE_MEM, 1112 }, 1113 { 1114 .start = IRQ_PINT0, 1115 .end = IRQ_PINT0, 1116 .flags = IORESOURCE_IRQ, 1117 }, 1118}; 1119 1120static struct platform_device bfin_pint0_device = { 1121 .name = ADI_PINT_DEVNAME, 1122 .id = 0, 1123 .num_resources = ARRAY_SIZE(bfin_pint0_resources), 1124 .resource = bfin_pint0_resources, 1125}; 1126 1127static struct resource bfin_pint1_resources[] = { 1128 { 1129 .start = PINT1_MASK_SET, 1130 .end = PINT1_LATCH + 3, 1131 .flags = IORESOURCE_MEM, 1132 }, 1133 { 1134 .start = IRQ_PINT1, 1135 .end = IRQ_PINT1, 1136 .flags = IORESOURCE_IRQ, 1137 }, 1138}; 1139 1140static struct platform_device bfin_pint1_device = { 1141 .name = ADI_PINT_DEVNAME, 1142 .id = 1, 1143 .num_resources = ARRAY_SIZE(bfin_pint1_resources), 1144 .resource = bfin_pint1_resources, 1145}; 1146 1147static struct resource bfin_pint2_resources[] = { 1148 { 1149 .start = PINT2_MASK_SET, 1150 .end = PINT2_LATCH + 3, 1151 .flags = IORESOURCE_MEM, 1152 }, 1153 { 1154 .start = IRQ_PINT2, 1155 .end = IRQ_PINT2, 1156 .flags = IORESOURCE_IRQ, 1157 }, 1158}; 1159 1160static struct platform_device bfin_pint2_device = { 1161 .name = ADI_PINT_DEVNAME, 1162 .id = 2, 1163 .num_resources = ARRAY_SIZE(bfin_pint2_resources), 1164 .resource = bfin_pint2_resources, 1165}; 1166 1167static struct resource bfin_pint3_resources[] = { 1168 { 1169 .start = PINT3_MASK_SET, 1170 .end = PINT3_LATCH + 3, 1171 .flags = IORESOURCE_MEM, 1172 }, 1173 { 1174 .start = IRQ_PINT3, 1175 .end = IRQ_PINT3, 1176 .flags = IORESOURCE_IRQ, 1177 }, 1178}; 1179 1180static struct platform_device bfin_pint3_device = { 1181 .name = ADI_PINT_DEVNAME, 1182 .id = 3, 1183 .num_resources = ARRAY_SIZE(bfin_pint3_resources), 1184 .resource = bfin_pint3_resources, 1185}; 1186 1187static struct resource bfin_gpa_resources[] = { 1188 { 1189 .start = PORTA_FER, 1190 .end = PORTA_MUX + 3, 1191 .flags = IORESOURCE_MEM, 1192 }, 1193 { /* optional */ 1194 .start = IRQ_PA0, 1195 .end = IRQ_PA0, 1196 .flags = IORESOURCE_IRQ, 1197 }, 1198}; 1199 1200static struct adi_pinctrl_gpio_platform_data bfin_gpa_pdata = { 1201 .port_gpio_base = GPIO_PA0, /* Optional */ 1202 .port_pin_base = GPIO_PA0, 1203 .port_width = GPIO_BANKSIZE, 1204 .pint_id = 0, /* PINT0 */ 1205 .pint_assign = true, /* PINT upper 16 bit */ 1206 .pint_map = 0, /* mapping mask in PINT */ 1207}; 1208 1209static struct platform_device bfin_gpa_device = { 1210 .name = ADI_GPIO_DEVNAME, 1211 .id = 0, 1212 .num_resources = ARRAY_SIZE(bfin_gpa_resources), 1213 .resource = bfin_gpa_resources, 1214 .dev = { 1215 .platform_data = &bfin_gpa_pdata, /* Passed to driver */ 1216 }, 1217}; 1218 1219static struct resource bfin_gpb_resources[] = { 1220 { 1221 .start = PORTB_FER, 1222 .end = PORTB_MUX + 3, 1223 .flags = IORESOURCE_MEM, 1224 }, 1225 { 1226 .start = IRQ_PB0, 1227 .end = IRQ_PB0, 1228 .flags = IORESOURCE_IRQ, 1229 }, 1230}; 1231 1232static struct adi_pinctrl_gpio_platform_data bfin_gpb_pdata = { 1233 .port_gpio_base = GPIO_PB0, 1234 .port_pin_base = GPIO_PB0, 1235 .port_width = 15, 1236 .pint_id = 0, 1237 .pint_assign = true, 1238 .pint_map = 1, 1239}; 1240 1241static struct platform_device bfin_gpb_device = { 1242 .name = ADI_GPIO_DEVNAME, 1243 .id = 1, 1244 .num_resources = ARRAY_SIZE(bfin_gpb_resources), 1245 .resource = bfin_gpb_resources, 1246 .dev = { 1247 .platform_data = &bfin_gpb_pdata, /* Passed to driver */ 1248 }, 1249}; 1250 1251static struct resource bfin_gpc_resources[] = { 1252 { 1253 .start = PORTC_FER, 1254 .end = PORTC_MUX + 3, 1255 .flags = IORESOURCE_MEM, 1256 }, 1257 { 1258 .start = IRQ_PC0, 1259 .end = IRQ_PC0, 1260 .flags = IORESOURCE_IRQ, 1261 }, 1262}; 1263 1264static struct adi_pinctrl_gpio_platform_data bfin_gpc_pdata = { 1265 .port_gpio_base = GPIO_PC0, 1266 .port_pin_base = GPIO_PC0, 1267 .port_width = 14, 1268 .pint_id = 2, 1269 .pint_assign = true, 1270 .pint_map = 0, 1271}; 1272 1273static struct platform_device bfin_gpc_device = { 1274 .name = ADI_GPIO_DEVNAME, 1275 .id = 2, 1276 .num_resources = ARRAY_SIZE(bfin_gpc_resources), 1277 .resource = bfin_gpc_resources, 1278 .dev = { 1279 .platform_data = &bfin_gpc_pdata, /* Passed to driver */ 1280 }, 1281}; 1282 1283static struct resource bfin_gpd_resources[] = { 1284 { 1285 .start = PORTD_FER, 1286 .end = PORTD_MUX + 3, 1287 .flags = IORESOURCE_MEM, 1288 }, 1289 { 1290 .start = IRQ_PD0, 1291 .end = IRQ_PD0, 1292 .flags = IORESOURCE_IRQ, 1293 }, 1294}; 1295 1296static struct adi_pinctrl_gpio_platform_data bfin_gpd_pdata = { 1297 .port_gpio_base = GPIO_PD0, 1298 .port_pin_base = GPIO_PD0, 1299 .port_width = GPIO_BANKSIZE, 1300 .pint_id = 2, 1301 .pint_assign = false, 1302 .pint_map = 1, 1303}; 1304 1305static struct platform_device bfin_gpd_device = { 1306 .name = ADI_GPIO_DEVNAME, 1307 .id = 3, 1308 .num_resources = ARRAY_SIZE(bfin_gpd_resources), 1309 .resource = bfin_gpd_resources, 1310 .dev = { 1311 .platform_data = &bfin_gpd_pdata, /* Passed to driver */ 1312 }, 1313}; 1314 1315static struct resource bfin_gpe_resources[] = { 1316 { 1317 .start = PORTE_FER, 1318 .end = PORTE_MUX + 3, 1319 .flags = IORESOURCE_MEM, 1320 }, 1321 { 1322 .start = IRQ_PE0, 1323 .end = IRQ_PE0, 1324 .flags = IORESOURCE_IRQ, 1325 }, 1326}; 1327 1328static struct adi_pinctrl_gpio_platform_data bfin_gpe_pdata = { 1329 .port_gpio_base = GPIO_PE0, 1330 .port_pin_base = GPIO_PE0, 1331 .port_width = GPIO_BANKSIZE, 1332 .pint_id = 3, 1333 .pint_assign = true, 1334 .pint_map = 2, 1335}; 1336 1337static struct platform_device bfin_gpe_device = { 1338 .name = ADI_GPIO_DEVNAME, 1339 .id = 4, 1340 .num_resources = ARRAY_SIZE(bfin_gpe_resources), 1341 .resource = bfin_gpe_resources, 1342 .dev = { 1343 .platform_data = &bfin_gpe_pdata, /* Passed to driver */ 1344 }, 1345}; 1346 1347static struct resource bfin_gpf_resources[] = { 1348 { 1349 .start = PORTF_FER, 1350 .end = PORTF_MUX + 3, 1351 .flags = IORESOURCE_MEM, 1352 }, 1353 { 1354 .start = IRQ_PF0, 1355 .end = IRQ_PF0, 1356 .flags = IORESOURCE_IRQ, 1357 }, 1358}; 1359 1360static struct adi_pinctrl_gpio_platform_data bfin_gpf_pdata = { 1361 .port_gpio_base = GPIO_PF0, 1362 .port_pin_base = GPIO_PF0, 1363 .port_width = GPIO_BANKSIZE, 1364 .pint_id = 3, 1365 .pint_assign = false, 1366 .pint_map = 3, 1367}; 1368 1369static struct platform_device bfin_gpf_device = { 1370 .name = ADI_GPIO_DEVNAME, 1371 .id = 5, 1372 .num_resources = ARRAY_SIZE(bfin_gpf_resources), 1373 .resource = bfin_gpf_resources, 1374 .dev = { 1375 .platform_data = &bfin_gpf_pdata, /* Passed to driver */ 1376 }, 1377}; 1378 1379static struct resource bfin_gpg_resources[] = { 1380 { 1381 .start = PORTG_FER, 1382 .end = PORTG_MUX + 3, 1383 .flags = IORESOURCE_MEM, 1384 }, 1385 { 1386 .start = IRQ_PG0, 1387 .end = IRQ_PG0, 1388 .flags = IORESOURCE_IRQ, 1389 }, 1390}; 1391 1392static struct adi_pinctrl_gpio_platform_data bfin_gpg_pdata = { 1393 .port_gpio_base = GPIO_PG0, 1394 .port_pin_base = GPIO_PG0, 1395 .port_width = GPIO_BANKSIZE, 1396 .pint_id = -1, 1397}; 1398 1399static struct platform_device bfin_gpg_device = { 1400 .name = ADI_GPIO_DEVNAME, 1401 .id = 6, 1402 .num_resources = ARRAY_SIZE(bfin_gpg_resources), 1403 .resource = bfin_gpg_resources, 1404 .dev = { 1405 .platform_data = &bfin_gpg_pdata, /* Passed to driver */ 1406 }, 1407}; 1408 1409static struct resource bfin_gph_resources[] = { 1410 { 1411 .start = PORTH_FER, 1412 .end = PORTH_MUX + 3, 1413 .flags = IORESOURCE_MEM, 1414 }, 1415 { 1416 .start = IRQ_PH0, 1417 .end = IRQ_PH0, 1418 .flags = IORESOURCE_IRQ, 1419 }, 1420}; 1421 1422static struct adi_pinctrl_gpio_platform_data bfin_gph_pdata = { 1423 .port_gpio_base = GPIO_PH0, 1424 .port_pin_base = GPIO_PH0, 1425 .port_width = 14, 1426 .pint_id = -1, 1427}; 1428 1429static struct platform_device bfin_gph_device = { 1430 .name = ADI_GPIO_DEVNAME, 1431 .id = 7, 1432 .num_resources = ARRAY_SIZE(bfin_gph_resources), 1433 .resource = bfin_gph_resources, 1434 .dev = { 1435 .platform_data = &bfin_gph_pdata, /* Passed to driver */ 1436 }, 1437}; 1438 1439static struct resource bfin_gpi_resources[] = { 1440 { 1441 .start = PORTI_FER, 1442 .end = PORTI_MUX + 3, 1443 .flags = IORESOURCE_MEM, 1444 }, 1445 { 1446 .start = IRQ_PI0, 1447 .end = IRQ_PI0, 1448 .flags = IORESOURCE_IRQ, 1449 }, 1450}; 1451 1452static struct adi_pinctrl_gpio_platform_data bfin_gpi_pdata = { 1453 .port_gpio_base = GPIO_PI0, 1454 .port_pin_base = GPIO_PI0, 1455 .port_width = GPIO_BANKSIZE, 1456 .pint_id = -1, 1457}; 1458 1459static struct platform_device bfin_gpi_device = { 1460 .name = ADI_GPIO_DEVNAME, 1461 .id = 8, 1462 .num_resources = ARRAY_SIZE(bfin_gpi_resources), 1463 .resource = bfin_gpi_resources, 1464 .dev = { 1465 .platform_data = &bfin_gpi_pdata, /* Passed to driver */ 1466 }, 1467}; 1468 1469static struct resource bfin_gpj_resources[] = { 1470 { 1471 .start = PORTJ_FER, 1472 .end = PORTJ_MUX + 3, 1473 .flags = IORESOURCE_MEM, 1474 }, 1475 { 1476 .start = IRQ_PJ0, 1477 .end = IRQ_PJ0, 1478 .flags = IORESOURCE_IRQ, 1479 }, 1480}; 1481 1482static struct adi_pinctrl_gpio_platform_data bfin_gpj_pdata = { 1483 .port_gpio_base = GPIO_PJ0, 1484 .port_pin_base = GPIO_PJ0, 1485 .port_width = 14, 1486 .pint_id = -1, 1487}; 1488 1489static struct platform_device bfin_gpj_device = { 1490 .name = ADI_GPIO_DEVNAME, 1491 .id = 9, 1492 .num_resources = ARRAY_SIZE(bfin_gpj_resources), 1493 .resource = bfin_gpj_resources, 1494 .dev = { 1495 .platform_data = &bfin_gpj_pdata, /* Passed to driver */ 1496 }, 1497}; 1498 1499#endif 1500 1501static struct spi_board_info bfin_spi_board_info[] __initdata = { 1502#if IS_ENABLED(CONFIG_MTD_M25P80) 1503 { 1504 /* the modalias must be the same as spi device driver name */ 1505 .modalias = "m25p80", /* Name of spi_driver for this device */ 1506 .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ 1507 .bus_num = 0, /* Framework bus number */ 1508 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1*/ 1509 .platform_data = &bfin_spi_flash_data, 1510 .controller_data = &spi_flash_chip_info, 1511 .mode = SPI_MODE_3, 1512 }, 1513#endif 1514#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD183X) 1515 { 1516 .modalias = "ad183x", 1517 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1518 .bus_num = 1, 1519 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */ 1520 }, 1521#endif 1522#if IS_ENABLED(CONFIG_TOUCHSCREEN_AD7877) 1523 { 1524 .modalias = "ad7877", 1525 .platform_data = &bfin_ad7877_ts_info, 1526 .irq = IRQ_PB4, /* old boards (<=Rev 1.3) use IRQ_PJ11 */ 1527 .max_speed_hz = 12500000, /* max spi clock (SCK) speed in HZ */ 1528 .bus_num = 0, 1529 .chip_select = MAX_CTRL_CS + GPIO_PE5, /* SPI_SSEL2 */ 1530 }, 1531#endif 1532#if IS_ENABLED(CONFIG_SPI_SPIDEV) 1533 { 1534 .modalias = "spidev", 1535 .max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */ 1536 .bus_num = 0, 1537 .chip_select = MAX_CTRL_CS + GPIO_PE4, /* SPI_SSEL1 */ 1538 }, 1539#endif 1540#if IS_ENABLED(CONFIG_INPUT_ADXL34X_SPI) 1541 { 1542 .modalias = "adxl34x", 1543 .platform_data = &adxl34x_info, 1544 .irq = IRQ_PC5, 1545 .max_speed_hz = 5000000, /* max spi clock (SCK) speed in HZ */ 1546 .bus_num = 1, 1547 .chip_select = MAX_CTRL_CS + GPIO_PG6, /* SPI_SSEL2 */ 1548 .mode = SPI_MODE_3, 1549 }, 1550#endif 1551}; 1552#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 1553/* SPI (0) */ 1554static struct resource bfin_spi0_resource[] = { 1555 [0] = { 1556 .start = SPI0_REGBASE, 1557 .end = SPI0_REGBASE + 0xFF, 1558 .flags = IORESOURCE_MEM, 1559 }, 1560 [1] = { 1561 .start = CH_SPI0, 1562 .end = CH_SPI0, 1563 .flags = IORESOURCE_DMA, 1564 }, 1565 [2] = { 1566 .start = IRQ_SPI0, 1567 .end = IRQ_SPI0, 1568 .flags = IORESOURCE_IRQ, 1569 } 1570}; 1571 1572/* SPI (1) */ 1573static struct resource bfin_spi1_resource[] = { 1574 [0] = { 1575 .start = SPI1_REGBASE, 1576 .end = SPI1_REGBASE + 0xFF, 1577 .flags = IORESOURCE_MEM, 1578 }, 1579 [1] = { 1580 .start = CH_SPI1, 1581 .end = CH_SPI1, 1582 .flags = IORESOURCE_DMA, 1583 }, 1584 [2] = { 1585 .start = IRQ_SPI1, 1586 .end = IRQ_SPI1, 1587 .flags = IORESOURCE_IRQ, 1588 } 1589}; 1590 1591/* SPI controller data */ 1592static struct bfin5xx_spi_master bf54x_spi_master_info0 = { 1593 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, 1594 .enable_dma = 1, /* master has the ability to do dma transfer */ 1595 .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0}, 1596}; 1597 1598static struct platform_device bf54x_spi_master0 = { 1599 .name = "bfin-spi", 1600 .id = 0, /* Bus number */ 1601 .num_resources = ARRAY_SIZE(bfin_spi0_resource), 1602 .resource = bfin_spi0_resource, 1603 .dev = { 1604 .platform_data = &bf54x_spi_master_info0, /* Passed to driver */ 1605 }, 1606}; 1607 1608static struct bfin5xx_spi_master bf54x_spi_master_info1 = { 1609 .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS, 1610 .enable_dma = 1, /* master has the ability to do dma transfer */ 1611 .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0}, 1612}; 1613 1614static struct platform_device bf54x_spi_master1 = { 1615 .name = "bfin-spi", 1616 .id = 1, /* Bus number */ 1617 .num_resources = ARRAY_SIZE(bfin_spi1_resource), 1618 .resource = bfin_spi1_resource, 1619 .dev = { 1620 .platform_data = &bf54x_spi_master_info1, /* Passed to driver */ 1621 }, 1622}; 1623#endif /* spi master and devices */ 1624 1625#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) 1626#include <linux/videodev2.h> 1627#include <media/blackfin/bfin_capture.h> 1628#include <media/blackfin/ppi.h> 1629 1630static const unsigned short ppi_req[] = { 1631 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3, 1632 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7, 1633 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2, 1634 0, 1635}; 1636 1637static const struct ppi_info ppi_info = { 1638 .type = PPI_TYPE_EPPI, 1639 .dma_ch = CH_EPPI1, 1640 .irq_err = IRQ_EPPI1_ERROR, 1641 .base = (void __iomem *)EPPI1_STATUS, 1642 .pin_req = ppi_req, 1643}; 1644 1645#if IS_ENABLED(CONFIG_VIDEO_VS6624) 1646static struct v4l2_input vs6624_inputs[] = { 1647 { 1648 .index = 0, 1649 .name = "Camera", 1650 .type = V4L2_INPUT_TYPE_CAMERA, 1651 .std = V4L2_STD_UNKNOWN, 1652 }, 1653}; 1654 1655static struct bcap_route vs6624_routes[] = { 1656 { 1657 .input = 0, 1658 .output = 0, 1659 }, 1660}; 1661 1662static const unsigned vs6624_ce_pin = GPIO_PG6; 1663 1664static struct bfin_capture_config bfin_capture_data = { 1665 .card_name = "BF548", 1666 .inputs = vs6624_inputs, 1667 .num_inputs = ARRAY_SIZE(vs6624_inputs), 1668 .routes = vs6624_routes, 1669 .i2c_adapter_id = 0, 1670 .board_info = { 1671 .type = "vs6624", 1672 .addr = 0x10, 1673 .platform_data = (void *)&vs6624_ce_pin, 1674 }, 1675 .ppi_info = &ppi_info, 1676 .ppi_control = (POLC | PACKEN | DLEN_8 | XFR_TYPE | 0x20), 1677 .int_mask = 0xFFFFFFFF, /* disable error interrupt on eppi */ 1678 .blank_clocks = 8, /* 8 clocks as SAV and EAV */ 1679}; 1680#endif 1681 1682static struct platform_device bfin_capture_device = { 1683 .name = "bfin_capture", 1684 .dev = { 1685 .platform_data = &bfin_capture_data, 1686 }, 1687}; 1688#endif 1689 1690#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) 1691static const u16 bfin_twi0_pins[] = {P_TWI0_SCL, P_TWI0_SDA, 0}; 1692 1693static struct resource bfin_twi0_resource[] = { 1694 [0] = { 1695 .start = TWI0_REGBASE, 1696 .end = TWI0_REGBASE + 0xFF, 1697 .flags = IORESOURCE_MEM, 1698 }, 1699 [1] = { 1700 .start = IRQ_TWI0, 1701 .end = IRQ_TWI0, 1702 .flags = IORESOURCE_IRQ, 1703 }, 1704}; 1705 1706static struct platform_device i2c_bfin_twi0_device = { 1707 .name = "i2c-bfin-twi", 1708 .id = 0, 1709 .num_resources = ARRAY_SIZE(bfin_twi0_resource), 1710 .resource = bfin_twi0_resource, 1711 .dev = { 1712 .platform_data = &bfin_twi0_pins, 1713 }, 1714}; 1715 1716#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 1717static const u16 bfin_twi1_pins[] = {P_TWI1_SCL, P_TWI1_SDA, 0}; 1718 1719static struct resource bfin_twi1_resource[] = { 1720 [0] = { 1721 .start = TWI1_REGBASE, 1722 .end = TWI1_REGBASE + 0xFF, 1723 .flags = IORESOURCE_MEM, 1724 }, 1725 [1] = { 1726 .start = IRQ_TWI1, 1727 .end = IRQ_TWI1, 1728 .flags = IORESOURCE_IRQ, 1729 }, 1730}; 1731 1732static struct platform_device i2c_bfin_twi1_device = { 1733 .name = "i2c-bfin-twi", 1734 .id = 1, 1735 .num_resources = ARRAY_SIZE(bfin_twi1_resource), 1736 .resource = bfin_twi1_resource, 1737 .dev = { 1738 .platform_data = &bfin_twi1_pins, 1739 }, 1740}; 1741#endif 1742#endif 1743 1744static struct i2c_board_info __initdata bfin_i2c_board_info0[] = { 1745#if IS_ENABLED(CONFIG_SND_SOC_SSM2602) 1746 { 1747 I2C_BOARD_INFO("ssm2602", 0x1b), 1748 }, 1749#endif 1750}; 1751 1752#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 1753static struct i2c_board_info __initdata bfin_i2c_board_info1[] = { 1754#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) 1755 { 1756 I2C_BOARD_INFO("pcf8574_lcd", 0x22), 1757 }, 1758#endif 1759#if IS_ENABLED(CONFIG_INPUT_PCF8574) 1760 { 1761 I2C_BOARD_INFO("pcf8574_keypad", 0x27), 1762 .irq = 212, 1763 }, 1764#endif 1765#if IS_ENABLED(CONFIG_INPUT_ADXL34X_I2C) 1766 { 1767 I2C_BOARD_INFO("adxl34x", 0x53), 1768 .irq = IRQ_PC5, 1769 .platform_data = (void *)&adxl34x_info, 1770 }, 1771#endif 1772#if IS_ENABLED(CONFIG_BFIN_TWI_LCD) 1773 { 1774 I2C_BOARD_INFO("ad5252", 0x2f), 1775 }, 1776#endif 1777}; 1778#endif 1779 1780#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) 1781#include <linux/gpio_keys.h> 1782 1783static struct gpio_keys_button bfin_gpio_keys_table[] = { 1784 {BTN_0, GPIO_PB8, 1, "gpio-keys: BTN0"}, 1785 {BTN_1, GPIO_PB9, 1, "gpio-keys: BTN1"}, 1786 {BTN_2, GPIO_PB10, 1, "gpio-keys: BTN2"}, 1787 {BTN_3, GPIO_PB11, 1, "gpio-keys: BTN3"}, 1788}; 1789 1790static struct gpio_keys_platform_data bfin_gpio_keys_data = { 1791 .buttons = bfin_gpio_keys_table, 1792 .nbuttons = ARRAY_SIZE(bfin_gpio_keys_table), 1793}; 1794 1795static struct platform_device bfin_device_gpiokeys = { 1796 .name = "gpio-keys", 1797 .dev = { 1798 .platform_data = &bfin_gpio_keys_data, 1799 }, 1800}; 1801#endif 1802 1803static const unsigned int cclk_vlev_datasheet[] = 1804{ 1805/* 1806 * Internal VLEV BF54XSBBC1533 1807 ****temporarily using these values until data sheet is updated 1808 */ 1809 VRPAIR(VLEV_085, 150000000), 1810 VRPAIR(VLEV_090, 250000000), 1811 VRPAIR(VLEV_110, 276000000), 1812 VRPAIR(VLEV_115, 301000000), 1813 VRPAIR(VLEV_120, 525000000), 1814 VRPAIR(VLEV_125, 550000000), 1815 VRPAIR(VLEV_130, 600000000), 1816}; 1817 1818static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = { 1819 .tuple_tab = cclk_vlev_datasheet, 1820 .tabsize = ARRAY_SIZE(cclk_vlev_datasheet), 1821 .vr_settling_time = 25 /* us */, 1822}; 1823 1824static struct platform_device bfin_dpmc = { 1825 .name = "bfin dpmc", 1826 .dev = { 1827 .platform_data = &bfin_dmpc_vreg_data, 1828 }, 1829}; 1830 1831#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) || \ 1832 IS_ENABLED(CONFIG_SND_BF5XX_AC97) 1833 1834#define SPORT_REQ(x) \ 1835 [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \ 1836 P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0} 1837 1838static const u16 bfin_snd_pin[][7] = { 1839 SPORT_REQ(0), 1840 SPORT_REQ(1), 1841 SPORT_REQ(2), 1842 SPORT_REQ(3), 1843}; 1844 1845static struct bfin_snd_platform_data bfin_snd_data[] = { 1846 { 1847 .pin_req = &bfin_snd_pin[0][0], 1848 }, 1849 { 1850 .pin_req = &bfin_snd_pin[1][0], 1851 }, 1852 { 1853 .pin_req = &bfin_snd_pin[2][0], 1854 }, 1855 { 1856 .pin_req = &bfin_snd_pin[3][0], 1857 }, 1858}; 1859 1860#define BFIN_SND_RES(x) \ 1861 [x] = { \ 1862 { \ 1863 .start = SPORT##x##_TCR1, \ 1864 .end = SPORT##x##_TCR1, \ 1865 .flags = IORESOURCE_MEM \ 1866 }, \ 1867 { \ 1868 .start = CH_SPORT##x##_RX, \ 1869 .end = CH_SPORT##x##_RX, \ 1870 .flags = IORESOURCE_DMA, \ 1871 }, \ 1872 { \ 1873 .start = CH_SPORT##x##_TX, \ 1874 .end = CH_SPORT##x##_TX, \ 1875 .flags = IORESOURCE_DMA, \ 1876 }, \ 1877 { \ 1878 .start = IRQ_SPORT##x##_ERROR, \ 1879 .end = IRQ_SPORT##x##_ERROR, \ 1880 .flags = IORESOURCE_IRQ, \ 1881 } \ 1882 } 1883 1884static struct resource bfin_snd_resources[][4] = { 1885 BFIN_SND_RES(0), 1886 BFIN_SND_RES(1), 1887 BFIN_SND_RES(2), 1888 BFIN_SND_RES(3), 1889}; 1890#endif 1891 1892#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 1893static struct platform_device bfin_i2s_pcm = { 1894 .name = "bfin-i2s-pcm-audio", 1895 .id = -1, 1896}; 1897#endif 1898 1899#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) 1900static struct platform_device bfin_ac97_pcm = { 1901 .name = "bfin-ac97-pcm-audio", 1902 .id = -1, 1903}; 1904#endif 1905 1906#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD73311) 1907static struct platform_device bfin_ad73311_codec_device = { 1908 .name = "ad73311", 1909 .id = -1, 1910}; 1911#endif 1912 1913#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980) 1914static struct platform_device bfin_ad1980_codec_device = { 1915 .name = "ad1980", 1916 .id = -1, 1917}; 1918#endif 1919 1920#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_I2S) 1921static struct platform_device bfin_i2s = { 1922 .name = "bfin-i2s", 1923 .id = CONFIG_SND_BF5XX_SPORT_NUM, 1924 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), 1925 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], 1926 .dev = { 1927 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], 1928 }, 1929}; 1930#endif 1931 1932#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AC97) 1933static struct platform_device bfin_ac97 = { 1934 .name = "bfin-ac97", 1935 .id = CONFIG_SND_BF5XX_SPORT_NUM, 1936 .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]), 1937 .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM], 1938 .dev = { 1939 .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM], 1940 }, 1941}; 1942#endif 1943 1944static struct platform_device *ezkit_devices[] __initdata = { 1945 1946 &bfin_dpmc, 1947#if defined(CONFIG_PINCTRL_ADI2) 1948 &bfin_pinctrl_device, 1949 &bfin_pint0_device, 1950 &bfin_pint1_device, 1951 &bfin_pint2_device, 1952 &bfin_pint3_device, 1953 &bfin_gpa_device, 1954 &bfin_gpb_device, 1955 &bfin_gpc_device, 1956 &bfin_gpd_device, 1957 &bfin_gpe_device, 1958 &bfin_gpf_device, 1959 &bfin_gpg_device, 1960 &bfin_gph_device, 1961 &bfin_gpi_device, 1962 &bfin_gpj_device, 1963#endif 1964 1965#if IS_ENABLED(CONFIG_RTC_DRV_BFIN) 1966 &rtc_device, 1967#endif 1968 1969#if IS_ENABLED(CONFIG_SERIAL_BFIN) 1970#ifdef CONFIG_SERIAL_BFIN_UART0 1971 &bfin_uart0_device, 1972#endif 1973#ifdef CONFIG_SERIAL_BFIN_UART1 1974 &bfin_uart1_device, 1975#endif 1976#ifdef CONFIG_SERIAL_BFIN_UART2 1977 &bfin_uart2_device, 1978#endif 1979#ifdef CONFIG_SERIAL_BFIN_UART3 1980 &bfin_uart3_device, 1981#endif 1982#endif 1983 1984#if IS_ENABLED(CONFIG_BFIN_SIR) 1985#ifdef CONFIG_BFIN_SIR0 1986 &bfin_sir0_device, 1987#endif 1988#ifdef CONFIG_BFIN_SIR1 1989 &bfin_sir1_device, 1990#endif 1991#ifdef CONFIG_BFIN_SIR2 1992 &bfin_sir2_device, 1993#endif 1994#ifdef CONFIG_BFIN_SIR3 1995 &bfin_sir3_device, 1996#endif 1997#endif 1998 1999#if IS_ENABLED(CONFIG_FB_BF54X_LQ043) 2000 &bf54x_lq043_device, 2001#endif 2002 2003#if IS_ENABLED(CONFIG_SMSC911X) 2004 &smsc911x_device, 2005#endif 2006 2007#if IS_ENABLED(CONFIG_USB_MUSB_HDRC) 2008 &musb_device, 2009#endif 2010 2011#if IS_ENABLED(CONFIG_USB_ISP1760_HCD) 2012 &bfin_isp1760_device, 2013#endif 2014 2015#if IS_ENABLED(CONFIG_SERIAL_BFIN_SPORT) 2016#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 2017 &bfin_sport0_uart_device, 2018#endif 2019#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART 2020 &bfin_sport1_uart_device, 2021#endif 2022#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART 2023 &bfin_sport2_uart_device, 2024#endif 2025#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART 2026 &bfin_sport3_uart_device, 2027#endif 2028#endif 2029 2030#if IS_ENABLED(CONFIG_CAN_BFIN) 2031 &bfin_can0_device, 2032 &bfin_can1_device, 2033#endif 2034 2035#if IS_ENABLED(CONFIG_PATA_BF54X) 2036 &bfin_atapi_device, 2037#endif 2038 2039#if IS_ENABLED(CONFIG_MTD_NAND_BF5XX) 2040 &bf5xx_nand_device, 2041#endif 2042 2043#if IS_ENABLED(CONFIG_SDH_BFIN) 2044 &bf54x_sdh_device, 2045#endif 2046 2047#if IS_ENABLED(CONFIG_SPI_BFIN5XX) 2048 &bf54x_spi_master0, 2049 &bf54x_spi_master1, 2050#endif 2051#if IS_ENABLED(CONFIG_VIDEO_BLACKFIN_CAPTURE) 2052 &bfin_capture_device, 2053#endif 2054 2055#if IS_ENABLED(CONFIG_KEYBOARD_BFIN) 2056 &bf54x_kpad_device, 2057#endif 2058 2059#if IS_ENABLED(CONFIG_INPUT_BFIN_ROTARY) 2060 &bfin_rotary_device, 2061#endif 2062 2063#if IS_ENABLED(CONFIG_I2C_BLACKFIN_TWI) 2064 &i2c_bfin_twi0_device, 2065#if !defined(CONFIG_BF542) 2066 &i2c_bfin_twi1_device, 2067#endif 2068#endif 2069 2070#if IS_ENABLED(CONFIG_KEYBOARD_GPIO) 2071 &bfin_device_gpiokeys, 2072#endif 2073 2074#if IS_ENABLED(CONFIG_MTD_PHYSMAP) 2075 &ezkit_flash_device, 2076#endif 2077 2078#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 2079 &bfin_i2s_pcm, 2080#endif 2081 2082#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) 2083 &bfin_ac97_pcm, 2084#endif 2085 2086#if IS_ENABLED(CONFIG_SND_BF5XX_SOC_AD1980) 2087 &bfin_ad1980_codec_device, 2088#endif 2089 2090#if IS_ENABLED(CONFIG_SND_BF5XX_I2S) 2091 &bfin_i2s, 2092#endif 2093 2094#if IS_ENABLED(CONFIG_SND_BF5XX_AC97) 2095 &bfin_ac97, 2096#endif 2097}; 2098 2099/* Pin control settings */ 2100static struct pinctrl_map __initdata bfin_pinmux_map[] = { 2101 /* per-device maps */ 2102 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.0", "pinctrl-adi2.0", NULL, "uart0"), 2103 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1"), 2104#ifdef CONFIG_BFIN_UART1_CTSRTS 2105 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.1", "pinctrl-adi2.0", NULL, "uart1_ctsrts"), 2106#endif 2107 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.2", "pinctrl-adi2.0", NULL, "uart2"), 2108 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3"), 2109#ifdef CONFIG_BFIN_UART3_CTSRTS 2110 PIN_MAP_MUX_GROUP_DEFAULT("bfin-uart.3", "pinctrl-adi2.0", NULL, "uart3_ctsrts"), 2111#endif 2112 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.0", "pinctrl-adi2.0", NULL, "uart0"), 2113 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.1", "pinctrl-adi2.0", NULL, "uart1"), 2114 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.2", "pinctrl-adi2.0", NULL, "uart2"), 2115 PIN_MAP_MUX_GROUP_DEFAULT("bfin_sir.3", "pinctrl-adi2.0", NULL, "uart3"), 2116 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sdh.0", "pinctrl-adi2.0", NULL, "rsi0"), 2117 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.0", "pinctrl-adi2.0", NULL, "spi0"), 2118 PIN_MAP_MUX_GROUP_DEFAULT("bfin-spi.1", "pinctrl-adi2.0", NULL, "spi1"), 2119 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.0", "pinctrl-adi2.0", NULL, "twi0"), 2120#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 2121 PIN_MAP_MUX_GROUP_DEFAULT("i2c-bfin-twi.1", "pinctrl-adi2.0", NULL, "twi1"), 2122#endif 2123 PIN_MAP_MUX_GROUP_DEFAULT("bfin-rotary", "pinctrl-adi2.0", NULL, "rotary"), 2124 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.0", "pinctrl-adi2.0", NULL, "can0"), 2125 PIN_MAP_MUX_GROUP_DEFAULT("bfin_can.1", "pinctrl-adi2.0", NULL, "can1"), 2126 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-lq043", "pinctrl-adi2.0", "ppi0_24bgrp", "ppi0"), 2127 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.0", "pinctrl-adi2.0", NULL, "sport0"), 2128 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.0", "pinctrl-adi2.0", NULL, "sport0"), 2129 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.0", "pinctrl-adi2.0", NULL, "sport0"), 2130 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.1", "pinctrl-adi2.0", NULL, "sport1"), 2131 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.1", "pinctrl-adi2.0", NULL, "sport1"), 2132 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.1", "pinctrl-adi2.0", NULL, "sport1"), 2133 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.2", "pinctrl-adi2.0", NULL, "sport2"), 2134 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.2", "pinctrl-adi2.0", NULL, "sport2"), 2135 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.2", "pinctrl-adi2.0", NULL, "sport2"), 2136 PIN_MAP_MUX_GROUP_DEFAULT("bfin-i2s.3", "pinctrl-adi2.0", NULL, "sport3"), 2137 PIN_MAP_MUX_GROUP_DEFAULT("bfin-tdm.3", "pinctrl-adi2.0", NULL, "sport3"), 2138 PIN_MAP_MUX_GROUP_DEFAULT("bfin-ac97.3", "pinctrl-adi2.0", NULL, "sport3"), 2139 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.0", "pinctrl-adi2.0", NULL, "sport0"), 2140 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.1", "pinctrl-adi2.0", NULL, "sport1"), 2141 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.2", "pinctrl-adi2.0", NULL, "sport2"), 2142 PIN_MAP_MUX_GROUP_DEFAULT("bfin-sport-uart.3", "pinctrl-adi2.0", NULL, "sport3"), 2143 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi"), 2144#ifdef CONFIG_BF548_ATAPI_ALTERNATIVE_PORT 2145 PIN_MAP_MUX_GROUP_DEFAULT("pata-bf54x", "pinctrl-adi2.0", NULL, "atapi_alter"), 2146#endif 2147 PIN_MAP_MUX_GROUP_DEFAULT("bf5xx-nand.0", "pinctrl-adi2.0", NULL, "nfc0"), 2148 PIN_MAP_MUX_GROUP_DEFAULT("bf54x-keys", "pinctrl-adi2.0", "keys_4x4grp", "keys"), 2149 PIN_MAP_MUX_GROUP("bf54x-keys", "4bit", "pinctrl-adi2.0", "keys_4x4grp", "keys"), 2150 PIN_MAP_MUX_GROUP("bf54x-keys", "8bit", "pinctrl-adi2.0", "keys_8x8grp", "keys"), 2151}; 2152 2153static int __init ezkit_init(void) 2154{ 2155 printk(KERN_INFO "%s(): registering device resources\n", __func__); 2156 2157 /* Initialize pinmuxing */ 2158 pinctrl_register_mappings(bfin_pinmux_map, 2159 ARRAY_SIZE(bfin_pinmux_map)); 2160 2161 i2c_register_board_info(0, bfin_i2c_board_info0, 2162 ARRAY_SIZE(bfin_i2c_board_info0)); 2163#if !defined(CONFIG_BF542) /* The BF542 only has 1 TWI */ 2164 i2c_register_board_info(1, bfin_i2c_board_info1, 2165 ARRAY_SIZE(bfin_i2c_board_info1)); 2166#endif 2167 2168 platform_add_devices(ezkit_devices, ARRAY_SIZE(ezkit_devices)); 2169 2170 spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info)); 2171 2172 return 0; 2173} 2174 2175arch_initcall(ezkit_init); 2176 2177static struct platform_device *ezkit_early_devices[] __initdata = { 2178#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) 2179#ifdef CONFIG_SERIAL_BFIN_UART0 2180 &bfin_uart0_device, 2181#endif 2182#ifdef CONFIG_SERIAL_BFIN_UART1 2183 &bfin_uart1_device, 2184#endif 2185#ifdef CONFIG_SERIAL_BFIN_UART2 2186 &bfin_uart2_device, 2187#endif 2188#ifdef CONFIG_SERIAL_BFIN_UART3 2189 &bfin_uart3_device, 2190#endif 2191#endif 2192}; 2193 2194void __init native_machine_early_platform_add_devices(void) 2195{ 2196 printk(KERN_INFO "register early platform devices\n"); 2197 early_platform_add_devices(ezkit_early_devices, 2198 ARRAY_SIZE(ezkit_early_devices)); 2199} 2200