Searched refs:RT (Results 1 - 129 of 129) sorted by relevance

/linux-4.1.27/arch/mips/mm/
H A Duasm-mips.c52 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
53 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
54 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
55 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
56 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
57 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
59 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
64 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
66 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
68 { insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 },
70 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
71 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
72 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
73 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
74 { insn_divu, M(spec_op, 0, 0, 0, 0, divu_op), RS | RT },
75 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
76 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
77 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
78 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
79 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
80 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
81 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
82 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
83 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
84 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
86 { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
87 { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
97 { insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
98 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
99 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
100 { insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
105 { insn_lld, M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9 },
106 { insn_ll, M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9 },
108 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
109 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
110 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
111 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
112 { insn_mfhc0, M(cop0_op, mfhc0_op, 0, 0, 0, 0), RT | RD | SET},
115 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
116 { insn_mthc0, M(cop0_op, mthc0_op, 0, 0, 0, 0), RT | RD | SET},
117 { insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
118 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
119 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
121 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
123 { insn_pref, M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9 },
126 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
128 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
129 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
131 { insn_scd, M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9 },
132 { insn_sc, M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9 },
134 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
135 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
136 { insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD },
137 { insn_slt, M(spec_op, 0, 0, 0, 0, slt_op), RS | RT | RD },
138 { insn_sltiu, M(sltiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
139 { insn_sltu, M(spec_op, 0, 0, 0, 0, sltu_op), RS | RT | RD },
140 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
141 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
142 { insn_srlv, M(spec_op, 0, 0, 0, 0, srlv_op), RS | RT | RD },
143 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
144 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
152 { insn_wsbh, M(spec3_op, 0, 0, 0, wsbh_op, bshfl_op), RT | RD },
153 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
154 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
203 if (ip->fields & RT) build_insn()
H A Duasm-micromips.c44 { insn_addu, M(mm_pool32a_op, 0, 0, 0, 0, mm_addu32_op), RT | RS | RD },
45 { insn_addiu, M(mm_addiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
46 { insn_and, M(mm_pool32a_op, 0, 0, 0, 0, mm_and_op), RT | RS | RD },
47 { insn_andi, M(mm_andi32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
48 { insn_beq, M(mm_beq32_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
54 { insn_bne, M(mm_bne32_op, 0, 0, 0, 0, 0), RT | RS | BIMM },
55 { insn_cache, M(mm_pool32b_op, 0, 0, mm_cache_func, 0, 0), RT | RS | SIMM },
58 { insn_divu, M(mm_pool32a_op, 0, 0, 0, mm_divu_op, mm_pool32axf_op), RT | RS },
70 { insn_ins, M(mm_pool32a_op, 0, 0, 0, 0, mm_ins_op), RT | RS | RD | RE },
71 { insn_ext, M(mm_pool32a_op, 0, 0, 0, 0, mm_ext_op), RT | RS | RD | RE },
74 { insn_jalr, M(mm_pool32a_op, 0, 0, 0, mm_jalr_op, mm_pool32axf_op), RT | RS },
76 { insn_lb, M(mm_lb32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
79 { insn_ll, M(mm_pool32c_op, 0, 0, (mm_ll_func << 1), 0, 0), RS | RT | SIMM },
82 { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
83 { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
86 { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
87 { insn_mul, M(mm_pool32a_op, 0, 0, 0, 0, mm_mul_op), RT | RS | RD },
88 { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
89 { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
90 { insn_pref, M(mm_pool32c_op, 0, 0, (mm_pref_func << 1), 0, 0), RT | RS | SIMM },
92 { insn_sc, M(mm_pool32c_op, 0, 0, (mm_sc_func << 1), 0, 0), RT | RS | SIMM },
95 { insn_sll, M(mm_pool32a_op, 0, 0, 0, 0, mm_sll32_op), RT | RS | RD },
96 { insn_sllv, M(mm_pool32a_op, 0, 0, 0, 0, mm_sllv32_op), RT | RS | RD },
97 { insn_slt, M(mm_pool32a_op, 0, 0, 0, 0, mm_slt_op), RT | RS | RD },
98 { insn_sltiu, M(mm_sltiu32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
99 { insn_sltu, M(mm_pool32a_op, 0, 0, 0, 0, mm_sltu_op), RT | RS | RD },
100 { insn_sra, M(mm_pool32a_op, 0, 0, 0, 0, mm_sra_op), RT | RS | RD },
101 { insn_srl, M(mm_pool32a_op, 0, 0, 0, 0, mm_srl32_op), RT | RS | RD },
102 { insn_srlv, M(mm_pool32a_op, 0, 0, 0, 0, mm_srlv32_op), RT | RS | RD },
103 { insn_rotr, M(mm_pool32a_op, 0, 0, 0, 0, mm_rotr_op), RT | RS | RD },
104 { insn_subu, M(mm_pool32a_op, 0, 0, 0, 0, mm_subu32_op), RT | RS | RD },
105 { insn_sw, M(mm_sw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
112 { insn_wsbh, M(mm_pool32a_op, 0, 0, 0, mm_wsbh_op, mm_pool32axf_op), RT | RS },
113 { insn_xor, M(mm_pool32a_op, 0, 0, 0, 0, mm_xor32_op), RT | RS | RD },
114 { insn_xori, M(mm_xori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },
174 if (ip->fields & RT) { build_insn()
H A Duasm.c18 RT = 0x002, enumerator in enum:fields
/linux-4.1.27/arch/powerpc/xmon/
H A Dspu-insns.h26 RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT |
32 RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT |
38 RI16 | op | I16 | RT | RI18 | op | I18 | RT |
44 RR | op | RB | RA | RT | LBT | op |RO| I16 | RO |
64 ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4
65 ASM_RI7 mnemonic RT, RA, I7
68 ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10
69 ASM_RI10 mnemonic RT, RA, R10
70 ASM_RI10IDX mnemonic RT, I10(RA)
73 ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18
74 ASM_RI16 mnemonic RT, I16
75 ASM_RI16W mnemonic RT, I16W
78 ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg
79 ASM_MTSPR mnemonic SA, RT
83 ASM_RDCH mnemonic RT, CA
84 ASM_RR mnemonic RT, RA, RB
85 ASM_RT mnemonic RT
86 ASM_RTA mnemonic RT, RA
87 ASM_WRCH mnemonic CA, RT
89 Note that RRR instructions have the names for RC and RT reversed from
90 what's in the ISA, in order to put RT in the same position it appears
96 The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits.
102 used as sources and RT is the target.
133 /* 0[RC][RB][RA][RT] */
137 APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */
139 APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */
140 APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */
141 APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */
142 APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */
149 APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */
150 APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */
151 APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */
154 APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */
155 APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */
156 APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */
157 APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */
158 APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */
159 APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */
160 APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */
161 APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */
162 APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */
164 APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
167 APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
169 APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */
170 APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */
171 APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
172 APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
173 APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */
174 APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
175 APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
176 APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */
177 APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
178 APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
179 APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
180 APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */
181 APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */
182 APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */
183 APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */
184 APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */
185 APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */
186 APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */
187 APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */
188 APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
189 APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
190 APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
191 APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
192 APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
193 APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
194 APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
195 APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */
196 APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */
197 APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */
198 APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */
199 APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */
200 APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */
201 APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */
202 APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */
203 APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */
204 APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */
205 APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */
206 APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */
207 APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */
208 APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */
209 APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */
210 APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */
211 APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */
214 APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */
215 APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */
216 APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
217 APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */
218 APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */
219 APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
220 APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */
221 APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */
222 APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */
223 APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
224 APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */
225 APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
226 APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */
227 APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
228 APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */
229 APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */
230 APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
231 APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */
232 APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
233 APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
234 APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */
235 APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
236 APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
237 APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */
244 APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */
245 APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */
246 APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */
247 APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */
248 APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */
249 APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */
250 APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */
251 APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */
252 APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */
255 APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */
256 APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */
257 APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */
258 APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */
259 APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */
260 APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
261 APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
262 APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
263 APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */
264 APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */
265 APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */
266 APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */
267 APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */
268 APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
269 APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */
270 APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
271 APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */
272 APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
273 APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
274 APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */
275 APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
276 APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
277 APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */
278 APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
279 APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
280 APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */
287 APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */
288 APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */
289 APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */
290 APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */
291 APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */
292 APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */
293 APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */
294 APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */
295 APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */
296 APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */
297 APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */
298 APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */
299 APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */
300 APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */
301 APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */
302 APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */
303 APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */
304 APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */
305 APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */
306 APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */
307 APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */
308 APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */
309 APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */
310 APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */
311 APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */
312 APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */
313 APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */
314 APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */
315 APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
316 APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
317 APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
318 APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
319 APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */
320 APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */
321 APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */
322 APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */
323 APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */
324 APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */
325 APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */
326 APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */
327 APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */
328 APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */
329 APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */
330 APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */
331 APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */
332 APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */
333 APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */
353 APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
354 APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
355 APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
356 APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */
357 APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */
358 APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */
372 APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
373 APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */
378 APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
379 APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */
380 APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
381 APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
382 APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
383 APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
384 APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
385 APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
386 APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
387 APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
392 APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */
393 APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */
394 APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
395 APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */
396 APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
397 APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
398 APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */
399 APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
400 APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */
401 APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
402 APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */
403 APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
404 APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */
H A Dppc-opc.c391 equal the RT field. */
422 instruction or the RT field in a D, DS, X, XFX or XO form
425 #define RT RS
434 /* The RT field of the DQ form lq instruction, which has special
600 /* The L field in an X form with the RT field fixed instruction. */
1296 equal the RT field. */ insert_ral()
1380 /* The RT field of the DQ form lq instruction, which has special
1688 /* An X_MASK with the RT field fixed. */
1700 /* An X_MASK with the RT and RA fields fixed. */
1988 { "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1989 { "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1990 { "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1991 { "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1992 { "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1993 { "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1994 { "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1995 { "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1996 { "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1997 { "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1998 { "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
1999 { "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2000 { "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2001 { "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2002 { "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2003 { "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2004 { "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2005 { "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2006 { "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2007 { "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2008 { "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2009 { "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2010 { "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2011 { "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2012 { "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2013 { "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2014 { "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2015 { "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2016 { "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2017 { "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2018 { "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2019 { "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2020 { "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2021 { "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2022 { "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2023 { "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2024 { "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2025 { "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2026 { "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2027 { "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2028 { "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2029 { "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2030 { "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2031 { "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2032 { "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2033 { "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2034 { "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2035 { "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2036 { "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2037 { "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2038 { "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2039 { "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2040 { "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2041 { "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2042 { "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2043 { "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2044 { "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2045 { "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2046 { "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2047 { "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } },
2048 { "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2049 { "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2050 { "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2051 { "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2052 { "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2053 { "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2054 { "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2055 { "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2056 { "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2057 { "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2058 { "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2059 { "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2060 { "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2061 { "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2062 { "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2063 { "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2064 { "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2065 { "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2066 { "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2067 { "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2068 { "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2069 { "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2070 { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2071 { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } },
2513 { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } },
2514 { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } },
2516 { "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } },
2517 { "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } },
2519 { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } },
2536 { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
2537 { "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } },
2538 { "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } },
2540 { "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } },
2541 { "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } },
2542 { "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } },
2544 { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } },
2545 { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } },
2546 { "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } },
2547 { "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } },
2548 { "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } },
2549 { "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } },
2551 { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } },
2552 { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } },
2553 { "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } },
2554 { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } },
2555 { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } },
3361 { "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3362 { "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3363 { "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } },
3364 { "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3365 { "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3366 { "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } },
3367 { "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3368 { "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3369 { "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } },
3370 { "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3371 { "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3372 { "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } },
3374 { "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3375 { "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3377 { "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3378 { "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3379 { "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3380 { "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3381 { "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3382 { "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3383 { "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3384 { "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3386 { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } },
3387 { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } },
3389 { "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } },
3390 { "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } },
3391 { "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } },
3392 { "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } },
3394 { "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } },
3395 { "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } },
3396 { "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } },
3398 { "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } },
3400 { "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } },
3405 { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } },
3406 { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } },
3429 { "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } },
3436 { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
3437 { "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } },
3438 { "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } },
3439 { "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } },
3440 { "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } },
3441 { "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } },
3442 { "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } },
3443 { "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } },
3445 { "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } },
3449 { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } },
3450 { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } },
3454 { "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } },
3478 { "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3479 { "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3481 { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } },
3482 { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } },
3489 { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } },
3491 { "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } },
3496 { "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } },
3500 { "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } },
3502 { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } },
3503 { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } },
3504 { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } },
3505 { "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } },
3507 { "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } },
3508 { "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } },
3509 { "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } },
3510 { "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } },
3516 { "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
3525 { "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } },
3527 { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } },
3533 { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3534 { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3535 { "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3536 { "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3537 { "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3538 { "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3539 { "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3540 { "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3542 { "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3543 { "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3544 { "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3545 { "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3546 { "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3547 { "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3548 { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3549 { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3597 { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3598 { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3599 { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3600 { "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3601 { "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3602 { "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3603 { "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3604 { "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3606 { "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3607 { "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3608 { "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3609 { "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3610 { "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3611 { "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3612 { "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3613 { "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3631 { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3632 { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3633 { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3634 { "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3635 { "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3636 { "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3637 { "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3638 { "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3640 { "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } },
3641 { "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } },
3642 { "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } },
3643 { "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } },
3645 { "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } },
3646 { "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } },
3647 { "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } },
3648 { "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } },
3649 { "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } },
3650 { "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } },
3651 { "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } },
3652 { "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } },
3654 { "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3655 { "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3656 { "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3657 { "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3658 { "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3659 { "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3660 { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3661 { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3680 { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } },
3681 { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } },
3682 { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } },
3683 { "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } },
3685 { "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3686 { "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3687 { "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3688 { "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3689 { "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } },
3690 { "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } },
3691 { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } },
3692 { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } },
3696 { "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } },
3698 { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } },
3699 { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } },
3703 { "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } },
3710 { "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } },
3715 { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } },
3717 { "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } },
3722 { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } },
3724 { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } },
3725 { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } },
3726 { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } },
3727 { "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } },
3728 { "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } },
3729 { "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } },
3730 { "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } },
3731 { "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } },
3732 { "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } },
3733 { "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } },
3734 { "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } },
3735 { "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } },
3736 { "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } },
3737 { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } },
3738 { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } },
3739 { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } },
3740 { "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } },
3741 { "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } },
3742 { "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } },
3743 { "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } },
3744 { "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } },
3745 { "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } },
3746 { "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } },
3747 { "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } },
3748 { "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } },
3749 { "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } },
3750 { "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } },
3751 { "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } },
3752 { "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } },
3753 { "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } },
3754 { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } },
3755 { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } },
3756 { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } },
3757 { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } },
3758 { "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } },
3760 { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } },
3761 { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } },
3762 { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } },
3763 { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } },
3765 { "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }},
3767 { "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } },
3768 { "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } },
3769 { "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } },
3770 { "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } },
3771 { "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } },
3772 { "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } },
3773 { "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } },
3774 { "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } },
3775 { "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } },
3776 { "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } },
3777 { "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } },
3778 { "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } },
3779 { "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } },
3780 { "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } },
3781 { "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } },
3782 { "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } },
3783 { "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } },
3784 { "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } },
3785 { "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } },
3786 { "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } },
3787 { "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } },
3788 { "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } },
3789 { "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } },
3790 { "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } },
3791 { "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } },
3792 { "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } },
3793 { "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } },
3794 { "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } },
3795 { "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } },
3796 { "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } },
3797 { "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } },
3798 { "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } },
3799 { "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } },
3800 { "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } },
3801 { "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } },
3802 { "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } },
3803 { "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } },
3804 { "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } },
3805 { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } },
3806 { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } },
3807 { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } },
3808 { "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } },
3809 { "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } },
3810 { "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
3811 { "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3812 { "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
3813 { "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
3814 { "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
3815 { "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
3816 { "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } },
3817 { "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
3818 { "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
3819 { "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } },
3820 { "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } },
3821 { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } },
3822 { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } },
3823 { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } },
3824 { "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } },
3825 { "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } },
3826 { "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } },
3827 { "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } },
3828 { "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } },
3829 { "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } },
3830 { "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } },
3831 { "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } },
3832 { "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } },
3833 { "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } },
3834 { "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } },
3835 { "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } },
3836 { "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } },
3837 { "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } },
3838 { "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } },
3839 { "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } },
3840 { "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } },
3841 { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } },
3842 { "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } },
3843 { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } },
3844 { "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } },
3845 { "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } },
3846 { "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } },
3847 { "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } },
3848 { "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } },
3849 { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } },
3850 { "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } },
3851 { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } },
3852 { "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } },
3853 { "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } },
3854 { "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } },
3855 { "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } },
3856 { "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } },
3857 { "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } },
3858 { "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } },
3859 { "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } },
3860 { "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } },
3861 { "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } },
3862 { "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } },
3863 { "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } },
3864 { "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } },
3865 { "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } },
3866 { "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } },
3867 { "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } },
3868 { "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } },
3869 { "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } },
3870 { "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } },
3871 { "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } },
3872 { "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } },
3873 { "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } },
3874 { "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } },
3875 { "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } },
3876 { "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } },
3877 { "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } },
3878 { "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } },
3879 { "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3880 { "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3881 { "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3882 { "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } },
3883 { "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } },
3884 { "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } },
3885 { "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } },
3886 { "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } },
3887 { "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } },
3888 { "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } },
3889 { "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } },
3890 { "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } },
3891 { "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } },
3892 { "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } },
3893 { "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } },
3894 { "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } },
3895 { "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } },
3896 { "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } },
3897 { "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } },
3898 { "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } },
3899 { "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } },
3900 { "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } },
3901 { "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } },
3902 { "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } },
3903 { "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } },
3904 { "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } },
3905 { "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } },
3906 { "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } },
3907 { "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } },
3908 { "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } },
3909 { "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } },
3910 { "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } },
3911 { "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } },
3912 { "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } },
3913 { "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } },
3914 { "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } },
3915 { "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } },
3916 { "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } },
3917 { "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } },
3918 { "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } },
3919 { "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } },
3920 { "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } },
3921 { "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } },
3922 { "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } },
3923 { "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } },
3924 { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } },
3925 { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } },
3926 { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } },
3927 { "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } },
3928 { "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } },
3929 { "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } },
3930 { "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } },
3931 { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } },
3932 { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } },
3933 { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } },
3934 { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } },
3935 { "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } },
3936 { "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } },
3937 { "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } },
3938 { "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } },
3939 { "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } },
3940 { "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } },
3941 { "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } },
3942 { "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } },
3943 { "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } },
3944 { "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } },
3945 { "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } },
3946 { "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } },
3947 { "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } },
3948 { "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } },
3949 { "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } },
3950 { "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } },
3951 { "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } },
3952 { "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } },
3953 { "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } },
3954 { "mfspr", X(31,339), X_MASK, COM, { RT, SPR } },
3956 { "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } },
3961 { "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } },
3963 { "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } },
3970 { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } },
3971 { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } },
3972 { "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } },
3973 { "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } },
3975 { "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } },
3976 { "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } },
3977 { "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } },
3978 { "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } },
3982 { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } },
3984 { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } },
3986 { "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } },
3992 { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3993 { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3995 { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } },
3996 { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } },
4028 { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } },
4075 { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4076 { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4078 { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4079 { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4080 { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4081 { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4083 { "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4084 { "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4086 { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } },
4087 { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } },
4088 { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } },
4089 { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } },
4252 { "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }},
4258 { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } },
4259 { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4260 { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } },
4261 { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } },
4262 { "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4263 { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } },
4265 { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } },
4266 { "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } },
4267 { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } },
4268 { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } },
4270 { "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } },
4271 { "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } },
4273 { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } },
4274 { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } },
4275 { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } },
4276 { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } },
4282 { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } },
4291 { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } },
4293 { "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } },
4295 { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } },
4296 { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } },
4298 { "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } },
4299 { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } },
4317 { "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } },
4329 { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } },
4331 { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } },
4332 { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } },
4346 { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } },
4354 { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } },
4396 { "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } },
4412 { "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } },
4414 { "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } },
4424 { "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } },
4426 { "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } },
4427 { "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } },
4429 { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } },
4431 { "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } },
4441 { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } },
4443 { "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } },
4450 { "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } },
4457 { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } },
4478 { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } },
4479 { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } },
4494 { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } },
4495 { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } },
4546 { "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } },
4547 { "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } },
4549 { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } },
4550 { "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } },
4552 { "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } },
4554 { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } },
4566 { "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } },
4568 { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } },
4570 { "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } },
4572 { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } },
4578 { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } },
4579 { "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } },
4608 { "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4609 { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } },
4610 { "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4611 { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } },
4612 { "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4613 { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } },
4614 { "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } },
4615 { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } },
4623 { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } },
4625 { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } },
4627 { "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } },
4735 { "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } },
4736 { "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } },
423 #define RT global() macro
H A Dspu-opc.c32 QUAD WORD (0,RC,RB,RA,RT) latency
/linux-4.1.27/arch/powerpc/crypto/
H A Dsha1-powerpc-asm.S15 #define RT(t) ((((t)+5)%6)+7) define
31 rotlwi RT(t),RA(t),5; \
34 add RT(t),RT(t),r6; \
38 add RT(t),RT(t),r14
43 rotlwi RT(t),RA(t),5; \
48 add RT(t),RT(t),r6; \
52 add RT(t),RT(t),r0; \
57 rotlwi RT(t),RA(t),5; \
61 add RT(t),RT(t),r6; \
63 add RT(t),RT(t),r0
67 rotlwi RT(t),RA(t),5; \
72 add RT(t),RT(t),r6; \
76 add RT(t),RT(t),r0; \
82 rotlwi RT(t),RA(t),5; \
90 add RT(t),RT(t),r6; \
93 add RT(t),RT(t),r0; \
/linux-4.1.27/arch/arm/boot/dts/
H A Dst-pincfg.h19 #define RT (1 << 23) macro
50 #define SE_NICLK_IO (RT)
55 #define SE_ICLK_IO (RT | INVERTCLK)
60 #define DE_IO (RT | DOUBLE_EDGE)
65 #define ICLK (RT | CLKNOTDATA | INVERTCLK)
70 #define NICLK (RT | CLKNOTDATA)
/linux-4.1.27/arch/mips/bcm47xx/
H A Dboard.c46 {{BCM47XX_BOARD_ASUS_RTN10U, "Asus RT-N10U"}, "RTN10U"},
47 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RTN10D"},
48 {{BCM47XX_BOARD_ASUS_RTN12, "Asus RT-N12"}, "RT-N12"},
49 {{BCM47XX_BOARD_ASUS_RTN12B1, "Asus RT-N12B1"}, "RTN12B1"},
50 {{BCM47XX_BOARD_ASUS_RTN12C1, "Asus RT-N12C1"}, "RTN12C1"},
51 {{BCM47XX_BOARD_ASUS_RTN12D1, "Asus RT-N12D1"}, "RTN12D1"},
52 {{BCM47XX_BOARD_ASUS_RTN12HP, "Asus RT-N12HP"}, "RTN12HP"},
53 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16-"},
81 {{BCM47XX_BOARD_ASUS_RTAC66U, "Asus RT-AC66U"}, "RT-AC66U"},
82 {{BCM47XX_BOARD_ASUS_RTN10, "Asus RT-N10"}, "RT-N10"},
83 {{BCM47XX_BOARD_ASUS_RTN10D, "Asus RT-N10D"}, "RT-N10D"},
84 {{BCM47XX_BOARD_ASUS_RTN15U, "Asus RT-N15U"}, "RT-N15U"},
85 {{BCM47XX_BOARD_ASUS_RTN16, "Asus RT-N16"}, "RT-N16"},
86 {{BCM47XX_BOARD_ASUS_RTN53, "Asus RT-N53"}, "RT-N53"},
87 {{BCM47XX_BOARD_ASUS_RTN66U, "Asus RT-N66U"}, "RT-N66U"},
/linux-4.1.27/include/linux/sched/
H A Ddeadline.h6 * the fact that any of them has higher prio than RT and
H A Dprio.h9 * Priority of a process goes from 0..MAX_PRIO-1, valid RT
15 * RT priority to be separate from the value exported to
/linux-4.1.27/kernel/sched/
H A Dcpupri.h11 /* values 2-101 are RT priorities 0-99 */
H A Dauto_group.c34 /* We've redirected RT tasks to the root task group... */ autogroup_destroy()
86 * Autogroup RT tasks are redirected to the root task group autogroup_create()
H A Drt.c94 /* We start is dequeued state, because no RT tasks are queued */ init_rt_rq()
263 /* Try to pull RT tasks here if we lower this rq's prio */ need_pull_rt_task()
913 printk_deferred_once("sched: RT throttling activated\n"); sched_rt_runtime_exceeded()
1329 * If the current task on @p's runqueue is an RT task, then select_task_rq_rt()
1330 * try to see if we can wake this RT task up on another select_task_rq_rt()
1331 * runqueue. Otherwise simply start this RT task select_task_rq_rt()
1700 * If the current CPU has more than one RT task, see if the non
1788 /* push_rt_task will return true if it moved an RT */ push_rt_tasks()
1939 /* Try the next RT overloaded CPU */ try_to_push_tasks()
2004 * Do we have an RT task that preempts pull_rt_task()
2125 * that we might want to pull RT tasks from other runqueues.
2130 * If there are other RT tasks then we will reschedule switched_from_rt()
2131 * and the scheduling of the other RT tasks will handle switched_from_rt()
2132 * the balancing. But if we are the last RT task switched_from_rt()
2133 * we may need to handle the pulling of RT tasks switched_from_rt()
2155 * When switching a task to RT, we may overload the runqueue
2156 * with RT tasks. In this case we try to push them off to
2167 * If that current running task is also an RT task switched_to_rt()
H A Dsched.h121 * This is the priority-queue data structure of the RT scheduling class:
145 * one used for RT-throttling (rt_bandwidth), with the main difference
428 /* RT IPI pull logic requires IRQ_WORK */
530 * than one runnable -deadline task (as it is below for RT tasks).
538 * The "RT overload" flag: it gets set if a CPU has more than
539 * one runnable RT task.
H A Dcore.c25 * 2007-11-29 RT balancing improvements by Steven Rostedt, Gregory Haskins,
288 * period over which we average the RT time consumption, measured
929 * without taking RT-inheritance into account. Might be
950 * be boosted by RT tasks, or might be boosted by
951 * interactivity modifiers. Will be RT if the task got
952 * RT-boosted. If not then it returns p->normal_prio.
958 * If we are RT tasks or we were boosted to RT priority, effective_prio()
3096 * The RT priorities are set via sched_setscheduler(), but we still set_user_nice()
3183 * RT tasks are offset by -200. Normal tasks are centered
3460 * Allow unprivileged RT tasks to decrease priority: __sched_setscheduler()
3663 * sched_setscheduler - change the scheduling policy and/or RT priority of a thread.
3666 * @param: structure containing the new RT priority.
3686 * sched_setscheduler_nocheck - change the scheduling policy and/or RT priority of a thread from kernelspace.
3689 * @param: structure containing the new RT priority.
3798 * sys_sched_setscheduler - set/change the scheduler policy and RT priority
3801 * @param: structure containing the new RT priority.
3816 * sys_sched_setparam - set/change the RT priority of a thread
3818 * @param: structure containing the new RT priority.
3889 * sys_sched_getparam - get the RT priority of a thread
3891 * @param: structure containing the RT priority.
3893 * Return: On success, 0 and the RT priority is in @param. Otherwise, an error
4414 * sys_sched_get_priority_max - return maximum RT priority.
4441 * sys_sched_get_priority_min - return minimum RT priority.
7595 * Autogroups do not have RT tasks; see autogroup_create(). tg_has_rt_tasks()
7636 * Ensure we don't starve existing RT tasks. tg_rt_schedulable()
7693 * Disallowing the root group RT runtime is BAD, it would disallow the tg_set_rt_bandwidth()
7694 * kernel creating (and or operating) RT threads. tg_set_rt_bandwidth()
8020 /* We don't support RT-tasks being in separate groups */ cgroup_taskset_for_each()
H A Ddeadline.c704 * The solution we're working towards is having the RT groups scheduled update_curr_dl()
713 * We'll let actual RT tasks worry about the overflow here, we update_curr_dl()
714 * have our own CBS to keep us inline; only account when RT update_curr_dl()
H A Dfair.c7681 * significantly reduced because of RT tasks or IRQs.
/linux-4.1.27/include/uapi/linux/caif/
H A Dif_caif.h22 * When using RT Netlink to create, destroy or configure a CAIF IP interface,
/linux-4.1.27/kernel/locking/
H A Drtmutex-debug.h2 * RT-Mutexes: blocking mutual exclusion locks with PI support
H A Drtmutex.h2 * RT-Mutexes: blocking mutual exclusion locks with PI support
H A Drtmutex-debug.c2 * RT-Mutexes: blocking mutual exclusion locks with PI support
H A Drtmutex_common.h2 * RT Mutexes: blocking mutual exclusion locks with PI support
H A Drtmutex-tester.c2 * RT-Mutex-tester: scriptable tester for rt mutexes
415 printk("Initializing RT-Tester: %s\n", ret ? "Failed" : "OK" ); init_rttest()
H A Drwsem-xadd.c392 * we're an RT task that will live-lock because we won't let rwsem_optimistic_spin()
H A Dmutex.c368 * we're an RT task that will live-lock because we won't let mutex_optimistic_spin()
H A Drtmutex.c2 * RT-Mutexes: simple blocking mutual exclusion locks with PI support
/linux-4.1.27/arch/x86/crypto/
H A Dtwofish-avx-x86_64-asm_64.S73 #define RT %xmm14 define
158 vpaddd x, RK1, RT;\
160 vpxor RT, c, c; \
163 vpsrld $1, c, RT; \
165 vpor c, RT, c; \
170 vpaddd x, RK1, RT;\
172 vpxor RT, c, c; \
/linux-4.1.27/include/uapi/asm-generic/
H A Dresource.h47 #define RLIMIT_RTTIME 15 /* timeout for RT tasks in us */
/linux-4.1.27/arch/parisc/lib/
H A Ddelay.c44 /* Allow RT tasks to run */ __cr16_delay()
/linux-4.1.27/include/linux/
H A Dioprio.h21 * These are the io priority groups as implemented by CFQ. RT is the realtime
H A Drtmutex.h2 * RT Mutexes: blocking mutual exclusion locks with PI support
H A Dquota.h343 u64 d_rt_spc_softlimit; /* preferred limit on RT space */
345 s64 d_rt_spc_timer; /* similar to above; for RT space */
346 int d_rt_spc_warns; /* # warnings issued wrt RT space */
H A Dplist.h23 * O(K) and K is the number of RT priority levels used in the system.
/linux-4.1.27/drivers/iio/adc/
H A Dtwl4030-madc.c55 * @requests: Array of request struct corresponding to SW1, SW2 and RT
172 * Hardware or RT real time conversion request initiated by external host
173 * processor for RT Signal conversions.
174 * External host processors can also request for non RT conversions
342 * corresponding to RT, SW1, SW2 conversion requests.
373 * corresponding to RT, SW1, SW2 conversion requests.
499 * corresponding to RT SW1 or SW2 conversion methods.
613 /* With RT method we should not be here anymore */ twl4030_madc_conversion()
/linux-4.1.27/arch/mips/sgi-ip27/
H A Dip27-timer.c49 .name = "SN HUB RT timer",
156 .name = "HUB-RT",
/linux-4.1.27/net/ipv6/netfilter/
H A Dip6t_rt.c71 pr_debug("IPv6 RT LEN %u %u ", hdrlen, rh->hdrlen); rt_mt6()
75 pr_debug("IPv6 RT segsleft %02X ", rt_mt6()
/linux-4.1.27/arch/x86/lib/
H A Ddelay.c65 /* Allow RT tasks to run */ delay_tsc()
/linux-4.1.27/drivers/acpi/
H A Dacpi_pad.c195 * the mechanism only works when all CPUs have RT task running, power_saving_thread()
196 * as if one CPU hasn't RT task, RT task from other CPUs will power_saving_thread()
197 * borrow CPU time from this CPU and cause RT task use > 95% power_saving_thread()
H A Dpci_irq.c282 * entry in the chipset's IO-APIC is masked (as, e.g. the RT kernel does
/linux-4.1.27/arch/mips/include/asm/sn/sn0/
H A Dhubpi.h96 #define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */
97 #define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */
100 #define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */
101 #define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */
104 #define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */
/linux-4.1.27/include/uapi/linux/
H A Ddqblk_xfs.h69 __u64 d_rtb_softlimit;/* preferred limit on RT disk blks */
71 __s32 d_rtbtimer; /* similar to above; for RT disk blks */
72 __u16 d_rtbwarns; /* # warnings issued wrt RT disk blks */
/linux-4.1.27/drivers/misc/
H A Dioc4.c224 /* There are three variants of IOC4 cards: IO9, IO10, and PCI-RT.
230 * If neither is present, it's a PCI-RT.
267 /* PCI-RT: No SCSI/SATA controller will be present */ ioc4_variant()
347 idd->idd_variant == IOC4_VARIANT_PCI_RT ? "PCI-RT" : ioc4_probe()
/linux-4.1.27/arch/powerpc/perf/
H A Dcallchain.c195 * 64-bit user processes use the same stack frame for RT and non-RT signals.
348 * Layout for non-RT signal frames
358 * Layout for RT signal frames
/linux-4.1.27/arch/ia64/kernel/
H A Defi_stub.S64 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
H A Desi_stub.S81 andcm r16=loc3,r16 // get psr with IT, DT, and RT bits cleared
H A Dfsys.S437 * PSR_PRESERVED_BITS==PSR.{UP,MFL,MFH,PK,DT,PP,SP,RT,IC}, we
/linux-4.1.27/arch/m68k/68000/
H A Dm68VZ328.c126 /* Init RT-Control uCdimm hardware */
/linux-4.1.27/arch/arm/mach-sa1100/
H A Dsleep.S119 @ Step 1 clear RT field of all MSCx registers
/linux-4.1.27/include/linux/i2c/
H A Dtwl4030-madc.h40 * @method: RT, SW1, SW2
/linux-4.1.27/drivers/media/radio/wl128x/
H A Dfmdrv.h173 * @ text_type: is the text following PS or RT
174 * @ text: radio text string which could either be PS or RT
/linux-4.1.27/arch/ia64/include/asm/sn/
H A Dioc3.h191 #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
192 #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
/linux-4.1.27/drivers/net/wireless/rt2x00/
H A Drt2x00dump.h98 * @chip_rt: RT chipset
H A Drt2x00.h149 * The chipset on the device is composed of a RT and RF chip.
1096 rt2x00_info(rt2x00dev, "RT chipset %04x, rev %04x detected\n", rt2x00_set_rt()
H A Drt61pci.h29 * RT chip PCI IDs.
H A Drt2500usb.c1467 rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n"); rt2500usb_init_eeprom()
H A Drt73usb.c1875 rt2x00_err(rt2x00dev, "Invalid RT chipset detected\n"); rt73usb_init_eeprom()
H A Drt2800lib.c7738 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n", rt2800_probe_rt()
/linux-4.1.27/arch/x86/include/asm/
H A Defi.h14 * This is the main reason why we're doing stable VA mappings for RT
/linux-4.1.27/drivers/hid/
H A Dhid-icade.c28 * RT ON,OFF = d,c
H A Dhid-wiimote-modules.c1062 * 4 | LT <3:1> | RT <5:1> | wiimod_classic_in_ext()
1071 * LT is left trigger, RT is right trigger wiimod_classic_in_ext()
1078 * LSB of RX, RY, LT, and RT are not transmitted and always 0. wiimod_classic_in_ext()
1088 * 4 | LT <3:1> | RT <5:1> | wiimod_classic_in_ext()
/linux-4.1.27/include/net/caif/
H A Dcaif_hsi.h184 * When using RT Netlink to create, destroy or configure a CAIF HSI interface,
/linux-4.1.27/include/linux/mfd/
H A Drt5033-private.h92 /* RT5033 RT CTRL1 register */
/linux-4.1.27/drivers/media/i2c/
H A Dsaa711x_regs.h276 "RT signal control"},
278 "RT/X port output control"},
H A Dir-kbd-i2c.c13 * modified for DViCO Fusion HDTV 5 RT GOLD by
/linux-4.1.27/drivers/irqchip/
H A Dirq-renesas-irqc.c41 /* SYS-CPU vs. RT-CPU */
/linux-4.1.27/drivers/rapidio/switches/
H A Dtsi57x.c74 /* Use local RT of the ingress port to avoid possible tsi57x_route_get_entry()
/linux-4.1.27/drivers/gpu/drm/radeon/
H A Dsumod.h79 # define RT(x) ((x) << 0) macro
H A Dsumo_dpm.c215 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t); sumo_gfx_powergating_initialize()
H A Datombios.h3587 #define eDP_TO_LVDS_RT_ID 0x02 // RT tanslator which require AMD SW init
/linux-4.1.27/fs/xfs/
H A Dxfs_quota.h67 long qt_delrtb_delta; /* delayed RT blk count changes */
H A Dxfs_trans_dquot.c451 * Adjust the RT reservation. xfs_trans_apply_dquot_deltas()
582 * if the blk reservation is for RT or regular blocks.
H A Dxfs_mount.c744 xfs_warn(mp, "RT mount failed"); xfs_mountfs()
856 xfs_warn(mp, "failed to read RT inodes"); xfs_mountfs()
H A Dxfs_file.c222 * If we have an RT and/or log subvolume we need to make sure xfs_file_fsync()
H A Dxfs_bmap_util.c189 * Lock out other modifications to the RT bitmap inode. xfs_bmap_rtalloc()
/linux-4.1.27/drivers/net/wireless/iwlwifi/mvm/
H A Dfw.c675 IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret); iwl_mvm_up()
767 IWL_DEBUG_INFO(mvm, "RT uCode started.\n"); iwl_mvm_up()
H A Dutils.c471 ? "Init" : "RT"); iwl_mvm_dump_umac_error_log()
520 ? "Init" : "RT"); iwl_mvm_dump_nic_error_log_old()
606 ? "Init" : "RT"); iwl_mvm_dump_nic_error_log()
/linux-4.1.27/drivers/tty/
H A Dsysrq.c405 .help_msg = "nice-all-RT-tasks(n)",
406 .action_msg = "Nice All RT Tasks",
H A Dmips_ejtag_fdc.c982 * cannot be deferred and handled by a thread on RT kernels. For mips_ejtag_fdc_tty_probe()
/linux-4.1.27/arch/mips/include/asm/sn/
H A Dioc3.h423 #define SIO_IR_RT_INT 0x08000000 /* RT output pulse */
424 #define SIO_IR_GEN_INT1 0x10000000 /* RT input pulse */
/linux-4.1.27/drivers/mfd/
H A Ducb1x00-ts.c203 * This is a RT kernel thread that handles the ADC accesses
/linux-4.1.27/drivers/staging/comedi/drivers/
H A Dcomedi_test.c308 "commands at RT priority not supported in this driver\n"); waveform_ai_cmd()
H A Ddt3000.c42 making it nearly impossible to write an RT compatible driver.
H A Dni_labpc_common.c659 /* dma unsafe at RT priority, labpc_ai_cmd()
H A Dni_mio_common.c1162 * RT code, as RT code might purposely be running close to the
/linux-4.1.27/fs/xfs/libxfs/
H A Dxfs_format.h1060 * RT Summary and bit manipulation macros.
1112 __be64 d_rtb_softlimit;/* preferred limit on RT disk blks */
1114 __be32 d_rtbtimer; /* similar to above; for RT disk blocks */
1115 __be16 d_rtbwarns; /* warnings issued wrt RT disk blocks */
/linux-4.1.27/arch/parisc/include/asm/
H A Dpdc.h331 case OS_ID_HPRT: return "HP-RT"; os_id_to_string()
/linux-4.1.27/lib/mpi/
H A Dlonglong.h889 ************** RT/ROMP **************
891 #if defined(__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
944 #endif /* RT/ROMP */
/linux-4.1.27/drivers/rapidio/
H A Drio.c1180 * @route_destid: destID entry in the RT
1208 * @route_destid: destID entry in the RT
1364 * entry into a switch routing table. Otherwise uses standard RT update method
1417 * entry from a switch routing table. Otherwise uses standard RT read method
1467 * routing table. Otherwise uses standard RT write method as defined by RapidIO
/linux-4.1.27/block/
H A Dcfq-iosched.c270 * only for RT and BE class and slot for IDLE class remains unused.
276 * RT and BE classes. These trees are subdivided in subclasses
989 * get averaged number of queues of RT/BE priority.
2931 /* Choose next priority. RT > BE > IDLE */ choose_wl_class_and_type()
2946 * For RT and BE, we have to choose also the type choose_wl_class_and_type()
3803 * Don't allow a non-RT request to preempt an ongoing RT cfqq timeslice. cfq_should_preempt()
3836 * Allow an RT request to pre-empt an ongoing non-RT cfqq timeslice. cfq_should_preempt()
3935 * this new queue is RT and the current one is BE cfq_rq_enqueued()
/linux-4.1.27/drivers/ide/
H A Dsgiioc4.c606 * PCI-RT does not bring out IDE connection. ioc4_ide_attach_one()
/linux-4.1.27/arch/mips/kernel/
H A Dtraps.c489 #define RT 0x001f0000 macro
547 regs->regs[(opcode & RT) >> 16] = value; simulate_ll()
570 reg = (opcode & RT) >> 16; simulate_sc()
659 int rt = (opcode & RT) >> 16; simulate_rdhwr_normal()
/linux-4.1.27/arch/parisc/include/uapi/asm/
H A Dpdc.h317 #define OS_ID_HPRT 4 /* HP-RT OS */
/linux-4.1.27/drivers/staging/rtl8192u/ieee80211/
H A Drtl819x_HTProc.c1239 // Check whether RT to RT aggregation mode is enabled HTResetSelfAndSavePeerSetting()
/linux-4.1.27/drivers/pinctrl/
H A Dpinctrl-st.c159 #define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
160 #define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
/linux-4.1.27/arch/arm64/kvm/
H A Dsys_regs.c557 /* DBGDTR[RT]Xint */
559 /* DBGDTR[RT]Xext */
/linux-4.1.27/kernel/rcu/
H A Drcutorture.c692 VERBOSE_TOROUT_STRING("rcu_torture_boost RT prio failed!"); rcu_torture_boost()
734 * interval. Besides, we are running at RT priority, rcu_torture_boost()
/linux-4.1.27/drivers/staging/rtl8192u/
H A Dr8192U_dm.c2221 /* Keep past Tx/Rx packet count for RT-to-RT EDCA turbo. */ dm_check_edca_turbo()
2242 /* For RT-AP, we needs to turn it on when Rx>Tx */ dm_check_edca_turbo()
H A Dr8192U.h460 /* Add this to 9100 bytes to receive A-MSDU from RT-AP */
/linux-4.1.27/drivers/net/wireless/iwlwifi/dvm/
H A Dmain.c1534 ? "Init" : "RT"); iwl_dump_nic_error_log()
1739 ? "Init" : "RT"); iwl_dump_nic_event_log()
H A Dmac80211.c260 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
/linux-4.1.27/drivers/isdn/gigaset/
H A Dusb-gigaset.c60 * RT|RQ|VALUE|INDEX|LEN |DATA
/linux-4.1.27/drivers/input/joystick/
H A Dxpad.c841 xpad->odata[7] = 0x00; /* TODO: RT actuator */ xpad_play_effect()
/linux-4.1.27/tools/perf/
H A Dbuiltin-record.c862 "collect data with this RT SCHED_FIFO priority"),
H A Dbuiltin-top.c1092 "collect data with this RT SCHED_FIFO priority"), cmd_top()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8821ae/
H A Ddm.c2676 /*Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.*/ rtl8821ae_dm_check_edca_turbo()
H A Dhw.c3317 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
/linux-4.1.27/arch/mips/kvm/
H A Demulate.c2302 #define RT 0x001f0000 macro
2346 int rt = (inst & RT) >> 16; kvm_mips_handle_ri()
/linux-4.1.27/kernel/
H A Dfutex.c1804 * - or MAX_RT_PRIO for non-RT threads.
1805 * Thus, all RT-threads are woken first in priority order, and
H A Dcgroup.c2428 * trapped in a cpuset, or RT worker may be born in a cgroup __cgroup_procs_write()
/linux-4.1.27/drivers/net/wan/
H A Dz85230.c325 * other code - this is true in the RT case too.
/linux-4.1.27/drivers/net/fddi/skfp/
H A Dfplustm.c969 rtm_init(smc) ; /* RT-Monitor */ init_mac()
/linux-4.1.27/kernel/time/
H A Dposix-cpu-timers.c878 "RT Watchdog Timeout: %s[%d]\n", check_thread_timers()
/linux-4.1.27/tools/perf/ui/browsers/
H A Dhists.c404 "You may want to run 'perf' using a RT scheduler policy:\n\n" ui_browser__warn_lost_events()
/linux-4.1.27/drivers/isdn/hardware/eicon/
H A Ddebug.c1528 diva_mnt_internal_dprintf(pC->hDbg->id, DLI_STAT, "MDM RT = %lu mSec", diva_maint_state_change_notify()
/linux-4.1.27/drivers/net/ethernet/realtek/
H A D8139cp.c1009 * *after* the [RT]xEnable bits in CpCmd are set. And on some hardware cp_start_hw()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8188ee/
H A Dhw.c2003 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); _rtl88ee_hal_customized_behavior()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ce/
H A Dhw.c1804 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); _rtl92ce_hal_customized_behavior()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192cu/
H A Dhw.c441 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n", _rtl92cu_hal_customized_behavior()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8192ee/
H A Dhw.c2232 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); _rtl92ee_hal_customized_behavior()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723ae/
H A Dhw.c1857 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); _rtl8723e_hal_customized_behavior()
/linux-4.1.27/drivers/net/wireless/rtlwifi/rtl8723be/
H A Dhw.c2258 "RT Customized ID: 0x%02X\n", rtlhal->oem_id); _rtl8723be_hal_customized_behavior()
/linux-4.1.27/drivers/usb/serial/
H A Dftdi_sio_ids.h883 * RT Systems programming cables for various ham radios
/linux-4.1.27/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_type.h2083 #define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */
2084 #define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */
/linux-4.1.27/drivers/media/pci/cx88/
H A Dcx88-cards.c3782 * FusionHDTV5 RT Gold has an ir receiver at 0x6b cx88_core_create()
/linux-4.1.27/drivers/tty/serial/
H A Dioc4_serial.c2782 /* PCI-RT does not bring out serial connections. ioc4_serial_attach_one()
/linux-4.1.27/drivers/net/wireless/iwlegacy/
H A D4965-mac.c5115 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); il4965_dump_nic_error_log()
/linux-4.1.27/kernel/trace/
H A Dtrace.c7 * Originally taken from the RT patch by:
/linux-4.1.27/drivers/md/
H A Dmd.c6953 * the very same RT priority as kswapd, thus we will never get md_thread()

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