1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle 7 * Copyright (C) 1995, 1996 Paul M. Antoine 8 * Copyright (C) 1998 Ulf Carlsson 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 11 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki 12 * Copyright (C) 2000, 2001, 2012 MIPS Technologies, Inc. All rights reserved. 13 * Copyright (C) 2014, Imagination Technologies Ltd. 14 */ 15#include <linux/bitops.h> 16#include <linux/bug.h> 17#include <linux/compiler.h> 18#include <linux/context_tracking.h> 19#include <linux/cpu_pm.h> 20#include <linux/kexec.h> 21#include <linux/init.h> 22#include <linux/kernel.h> 23#include <linux/module.h> 24#include <linux/mm.h> 25#include <linux/sched.h> 26#include <linux/smp.h> 27#include <linux/spinlock.h> 28#include <linux/kallsyms.h> 29#include <linux/bootmem.h> 30#include <linux/interrupt.h> 31#include <linux/ptrace.h> 32#include <linux/kgdb.h> 33#include <linux/kdebug.h> 34#include <linux/kprobes.h> 35#include <linux/notifier.h> 36#include <linux/kdb.h> 37#include <linux/irq.h> 38#include <linux/perf_event.h> 39 40#include <asm/bootinfo.h> 41#include <asm/branch.h> 42#include <asm/break.h> 43#include <asm/cop2.h> 44#include <asm/cpu.h> 45#include <asm/cpu-type.h> 46#include <asm/dsp.h> 47#include <asm/fpu.h> 48#include <asm/fpu_emulator.h> 49#include <asm/idle.h> 50#include <asm/mips-r2-to-r6-emul.h> 51#include <asm/mipsregs.h> 52#include <asm/mipsmtregs.h> 53#include <asm/module.h> 54#include <asm/msa.h> 55#include <asm/pgtable.h> 56#include <asm/ptrace.h> 57#include <asm/sections.h> 58#include <asm/tlbdebug.h> 59#include <asm/traps.h> 60#include <asm/uaccess.h> 61#include <asm/watch.h> 62#include <asm/mmu_context.h> 63#include <asm/types.h> 64#include <asm/stacktrace.h> 65#include <asm/uasm.h> 66 67extern void check_wait(void); 68extern asmlinkage void rollback_handle_int(void); 69extern asmlinkage void handle_int(void); 70extern u32 handle_tlbl[]; 71extern u32 handle_tlbs[]; 72extern u32 handle_tlbm[]; 73extern asmlinkage void handle_adel(void); 74extern asmlinkage void handle_ades(void); 75extern asmlinkage void handle_ibe(void); 76extern asmlinkage void handle_dbe(void); 77extern asmlinkage void handle_sys(void); 78extern asmlinkage void handle_bp(void); 79extern asmlinkage void handle_ri(void); 80extern asmlinkage void handle_ri_rdhwr_vivt(void); 81extern asmlinkage void handle_ri_rdhwr(void); 82extern asmlinkage void handle_cpu(void); 83extern asmlinkage void handle_ov(void); 84extern asmlinkage void handle_tr(void); 85extern asmlinkage void handle_msa_fpe(void); 86extern asmlinkage void handle_fpe(void); 87extern asmlinkage void handle_ftlb(void); 88extern asmlinkage void handle_msa(void); 89extern asmlinkage void handle_mdmx(void); 90extern asmlinkage void handle_watch(void); 91extern asmlinkage void handle_mt(void); 92extern asmlinkage void handle_dsp(void); 93extern asmlinkage void handle_mcheck(void); 94extern asmlinkage void handle_reserved(void); 95extern void tlb_do_page_fault_0(void); 96 97void (*board_be_init)(void); 98int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 99void (*board_nmi_handler_setup)(void); 100void (*board_ejtag_handler_setup)(void); 101void (*board_bind_eic_interrupt)(int irq, int regset); 102void (*board_ebase_setup)(void); 103void(*board_cache_error_setup)(void); 104 105static void show_raw_backtrace(unsigned long reg29) 106{ 107 unsigned long *sp = (unsigned long *)(reg29 & ~3); 108 unsigned long addr; 109 110 printk("Call Trace:"); 111#ifdef CONFIG_KALLSYMS 112 printk("\n"); 113#endif 114 while (!kstack_end(sp)) { 115 unsigned long __user *p = 116 (unsigned long __user *)(unsigned long)sp++; 117 if (__get_user(addr, p)) { 118 printk(" (Bad stack address)"); 119 break; 120 } 121 if (__kernel_text_address(addr)) 122 print_ip_sym(addr); 123 } 124 printk("\n"); 125} 126 127#ifdef CONFIG_KALLSYMS 128int raw_show_trace; 129static int __init set_raw_show_trace(char *str) 130{ 131 raw_show_trace = 1; 132 return 1; 133} 134__setup("raw_show_trace", set_raw_show_trace); 135#endif 136 137static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) 138{ 139 unsigned long sp = regs->regs[29]; 140 unsigned long ra = regs->regs[31]; 141 unsigned long pc = regs->cp0_epc; 142 143 if (!task) 144 task = current; 145 146 if (raw_show_trace || user_mode(regs) || !__kernel_text_address(pc)) { 147 show_raw_backtrace(sp); 148 return; 149 } 150 printk("Call Trace:\n"); 151 do { 152 print_ip_sym(pc); 153 pc = unwind_stack(task, &sp, pc, &ra); 154 } while (pc); 155 printk("\n"); 156} 157 158/* 159 * This routine abuses get_user()/put_user() to reference pointers 160 * with at least a bit of error checking ... 161 */ 162static void show_stacktrace(struct task_struct *task, 163 const struct pt_regs *regs) 164{ 165 const int field = 2 * sizeof(unsigned long); 166 long stackdata; 167 int i; 168 unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; 169 170 printk("Stack :"); 171 i = 0; 172 while ((unsigned long) sp & (PAGE_SIZE - 1)) { 173 if (i && ((i % (64 / field)) == 0)) 174 printk("\n "); 175 if (i > 39) { 176 printk(" ..."); 177 break; 178 } 179 180 if (__get_user(stackdata, sp++)) { 181 printk(" (Bad stack address)"); 182 break; 183 } 184 185 printk(" %0*lx", field, stackdata); 186 i++; 187 } 188 printk("\n"); 189 show_backtrace(task, regs); 190} 191 192void show_stack(struct task_struct *task, unsigned long *sp) 193{ 194 struct pt_regs regs; 195 mm_segment_t old_fs = get_fs(); 196 if (sp) { 197 regs.regs[29] = (unsigned long)sp; 198 regs.regs[31] = 0; 199 regs.cp0_epc = 0; 200 } else { 201 if (task && task != current) { 202 regs.regs[29] = task->thread.reg29; 203 regs.regs[31] = 0; 204 regs.cp0_epc = task->thread.reg31; 205#ifdef CONFIG_KGDB_KDB 206 } else if (atomic_read(&kgdb_active) != -1 && 207 kdb_current_regs) { 208 memcpy(®s, kdb_current_regs, sizeof(regs)); 209#endif /* CONFIG_KGDB_KDB */ 210 } else { 211 prepare_frametrace(®s); 212 } 213 } 214 /* 215 * show_stack() deals exclusively with kernel mode, so be sure to access 216 * the stack in the kernel (not user) address space. 217 */ 218 set_fs(KERNEL_DS); 219 show_stacktrace(task, ®s); 220 set_fs(old_fs); 221} 222 223static void show_code(unsigned int __user *pc) 224{ 225 long i; 226 unsigned short __user *pc16 = NULL; 227 228 printk("\nCode:"); 229 230 if ((unsigned long)pc & 1) 231 pc16 = (unsigned short __user *)((unsigned long)pc & ~1); 232 for(i = -3 ; i < 6 ; i++) { 233 unsigned int insn; 234 if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { 235 printk(" (Bad address in epc)\n"); 236 break; 237 } 238 printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); 239 } 240} 241 242static void __show_regs(const struct pt_regs *regs) 243{ 244 const int field = 2 * sizeof(unsigned long); 245 unsigned int cause = regs->cp0_cause; 246 int i; 247 248 show_regs_print_info(KERN_DEFAULT); 249 250 /* 251 * Saved main processor registers 252 */ 253 for (i = 0; i < 32; ) { 254 if ((i % 4) == 0) 255 printk("$%2d :", i); 256 if (i == 0) 257 printk(" %0*lx", field, 0UL); 258 else if (i == 26 || i == 27) 259 printk(" %*s", field, ""); 260 else 261 printk(" %0*lx", field, regs->regs[i]); 262 263 i++; 264 if ((i % 4) == 0) 265 printk("\n"); 266 } 267 268#ifdef CONFIG_CPU_HAS_SMARTMIPS 269 printk("Acx : %0*lx\n", field, regs->acx); 270#endif 271 printk("Hi : %0*lx\n", field, regs->hi); 272 printk("Lo : %0*lx\n", field, regs->lo); 273 274 /* 275 * Saved cp0 registers 276 */ 277 printk("epc : %0*lx %pS\n", field, regs->cp0_epc, 278 (void *) regs->cp0_epc); 279 printk("ra : %0*lx %pS\n", field, regs->regs[31], 280 (void *) regs->regs[31]); 281 282 printk("Status: %08x ", (uint32_t) regs->cp0_status); 283 284 if (cpu_has_3kex) { 285 if (regs->cp0_status & ST0_KUO) 286 printk("KUo "); 287 if (regs->cp0_status & ST0_IEO) 288 printk("IEo "); 289 if (regs->cp0_status & ST0_KUP) 290 printk("KUp "); 291 if (regs->cp0_status & ST0_IEP) 292 printk("IEp "); 293 if (regs->cp0_status & ST0_KUC) 294 printk("KUc "); 295 if (regs->cp0_status & ST0_IEC) 296 printk("IEc "); 297 } else if (cpu_has_4kex) { 298 if (regs->cp0_status & ST0_KX) 299 printk("KX "); 300 if (regs->cp0_status & ST0_SX) 301 printk("SX "); 302 if (regs->cp0_status & ST0_UX) 303 printk("UX "); 304 switch (regs->cp0_status & ST0_KSU) { 305 case KSU_USER: 306 printk("USER "); 307 break; 308 case KSU_SUPERVISOR: 309 printk("SUPERVISOR "); 310 break; 311 case KSU_KERNEL: 312 printk("KERNEL "); 313 break; 314 default: 315 printk("BAD_MODE "); 316 break; 317 } 318 if (regs->cp0_status & ST0_ERL) 319 printk("ERL "); 320 if (regs->cp0_status & ST0_EXL) 321 printk("EXL "); 322 if (regs->cp0_status & ST0_IE) 323 printk("IE "); 324 } 325 printk("\n"); 326 327 printk("Cause : %08x\n", cause); 328 329 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; 330 if (1 <= cause && cause <= 5) 331 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); 332 333 printk("PrId : %08x (%s)\n", read_c0_prid(), 334 cpu_name_string()); 335} 336 337/* 338 * FIXME: really the generic show_regs should take a const pointer argument. 339 */ 340void show_regs(struct pt_regs *regs) 341{ 342 __show_regs((struct pt_regs *)regs); 343} 344 345void show_registers(struct pt_regs *regs) 346{ 347 const int field = 2 * sizeof(unsigned long); 348 mm_segment_t old_fs = get_fs(); 349 350 __show_regs(regs); 351 print_modules(); 352 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", 353 current->comm, current->pid, current_thread_info(), current, 354 field, current_thread_info()->tp_value); 355 if (cpu_has_userlocal) { 356 unsigned long tls; 357 358 tls = read_c0_userlocal(); 359 if (tls != current_thread_info()->tp_value) 360 printk("*HwTLS: %0*lx\n", field, tls); 361 } 362 363 if (!user_mode(regs)) 364 /* Necessary for getting the correct stack content */ 365 set_fs(KERNEL_DS); 366 show_stacktrace(current, regs); 367 show_code((unsigned int __user *) regs->cp0_epc); 368 printk("\n"); 369 set_fs(old_fs); 370} 371 372static int regs_to_trapnr(struct pt_regs *regs) 373{ 374 return (regs->cp0_cause >> 2) & 0x1f; 375} 376 377static DEFINE_RAW_SPINLOCK(die_lock); 378 379void __noreturn die(const char *str, struct pt_regs *regs) 380{ 381 static int die_counter; 382 int sig = SIGSEGV; 383 384 oops_enter(); 385 386 if (notify_die(DIE_OOPS, str, regs, 0, regs_to_trapnr(regs), 387 SIGSEGV) == NOTIFY_STOP) 388 sig = 0; 389 390 console_verbose(); 391 raw_spin_lock_irq(&die_lock); 392 bust_spinlocks(1); 393 394 printk("%s[#%d]:\n", str, ++die_counter); 395 show_registers(regs); 396 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE); 397 raw_spin_unlock_irq(&die_lock); 398 399 oops_exit(); 400 401 if (in_interrupt()) 402 panic("Fatal exception in interrupt"); 403 404 if (panic_on_oops) { 405 printk(KERN_EMERG "Fatal exception: panic in 5 seconds"); 406 ssleep(5); 407 panic("Fatal exception"); 408 } 409 410 if (regs && kexec_should_crash(current)) 411 crash_kexec(regs); 412 413 do_exit(sig); 414} 415 416extern struct exception_table_entry __start___dbe_table[]; 417extern struct exception_table_entry __stop___dbe_table[]; 418 419__asm__( 420" .section __dbe_table, \"a\"\n" 421" .previous \n"); 422 423/* Given an address, look for it in the exception tables. */ 424static const struct exception_table_entry *search_dbe_tables(unsigned long addr) 425{ 426 const struct exception_table_entry *e; 427 428 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); 429 if (!e) 430 e = search_module_dbetables(addr); 431 return e; 432} 433 434asmlinkage void do_be(struct pt_regs *regs) 435{ 436 const int field = 2 * sizeof(unsigned long); 437 const struct exception_table_entry *fixup = NULL; 438 int data = regs->cp0_cause & 4; 439 int action = MIPS_BE_FATAL; 440 enum ctx_state prev_state; 441 442 prev_state = exception_enter(); 443 /* XXX For now. Fixme, this searches the wrong table ... */ 444 if (data && !user_mode(regs)) 445 fixup = search_dbe_tables(exception_epc(regs)); 446 447 if (fixup) 448 action = MIPS_BE_FIXUP; 449 450 if (board_be_handler) 451 action = board_be_handler(regs, fixup != NULL); 452 453 switch (action) { 454 case MIPS_BE_DISCARD: 455 goto out; 456 case MIPS_BE_FIXUP: 457 if (fixup) { 458 regs->cp0_epc = fixup->nextinsn; 459 goto out; 460 } 461 break; 462 default: 463 break; 464 } 465 466 /* 467 * Assume it would be too dangerous to continue ... 468 */ 469 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", 470 data ? "Data" : "Instruction", 471 field, regs->cp0_epc, field, regs->regs[31]); 472 if (notify_die(DIE_OOPS, "bus error", regs, 0, regs_to_trapnr(regs), 473 SIGBUS) == NOTIFY_STOP) 474 goto out; 475 476 die_if_kernel("Oops", regs); 477 force_sig(SIGBUS, current); 478 479out: 480 exception_exit(prev_state); 481} 482 483/* 484 * ll/sc, rdhwr, sync emulation 485 */ 486 487#define OPCODE 0xfc000000 488#define BASE 0x03e00000 489#define RT 0x001f0000 490#define OFFSET 0x0000ffff 491#define LL 0xc0000000 492#define SC 0xe0000000 493#define SPEC0 0x00000000 494#define SPEC3 0x7c000000 495#define RD 0x0000f800 496#define FUNC 0x0000003f 497#define SYNC 0x0000000f 498#define RDHWR 0x0000003b 499 500/* microMIPS definitions */ 501#define MM_POOL32A_FUNC 0xfc00ffff 502#define MM_RDHWR 0x00006b3c 503#define MM_RS 0x001f0000 504#define MM_RT 0x03e00000 505 506/* 507 * The ll_bit is cleared by r*_switch.S 508 */ 509 510unsigned int ll_bit; 511struct task_struct *ll_task; 512 513static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) 514{ 515 unsigned long value, __user *vaddr; 516 long offset; 517 518 /* 519 * analyse the ll instruction that just caused a ri exception 520 * and put the referenced address to addr. 521 */ 522 523 /* sign extend offset */ 524 offset = opcode & OFFSET; 525 offset <<= 16; 526 offset >>= 16; 527 528 vaddr = (unsigned long __user *) 529 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 530 531 if ((unsigned long)vaddr & 3) 532 return SIGBUS; 533 if (get_user(value, vaddr)) 534 return SIGSEGV; 535 536 preempt_disable(); 537 538 if (ll_task == NULL || ll_task == current) { 539 ll_bit = 1; 540 } else { 541 ll_bit = 0; 542 } 543 ll_task = current; 544 545 preempt_enable(); 546 547 regs->regs[(opcode & RT) >> 16] = value; 548 549 return 0; 550} 551 552static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) 553{ 554 unsigned long __user *vaddr; 555 unsigned long reg; 556 long offset; 557 558 /* 559 * analyse the sc instruction that just caused a ri exception 560 * and put the referenced address to addr. 561 */ 562 563 /* sign extend offset */ 564 offset = opcode & OFFSET; 565 offset <<= 16; 566 offset >>= 16; 567 568 vaddr = (unsigned long __user *) 569 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); 570 reg = (opcode & RT) >> 16; 571 572 if ((unsigned long)vaddr & 3) 573 return SIGBUS; 574 575 preempt_disable(); 576 577 if (ll_bit == 0 || ll_task != current) { 578 regs->regs[reg] = 0; 579 preempt_enable(); 580 return 0; 581 } 582 583 preempt_enable(); 584 585 if (put_user(regs->regs[reg], vaddr)) 586 return SIGSEGV; 587 588 regs->regs[reg] = 1; 589 590 return 0; 591} 592 593/* 594 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both 595 * opcodes are supposed to result in coprocessor unusable exceptions if 596 * executed on ll/sc-less processors. That's the theory. In practice a 597 * few processors such as NEC's VR4100 throw reserved instruction exceptions 598 * instead, so we're doing the emulation thing in both exception handlers. 599 */ 600static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) 601{ 602 if ((opcode & OPCODE) == LL) { 603 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 604 1, regs, 0); 605 return simulate_ll(regs, opcode); 606 } 607 if ((opcode & OPCODE) == SC) { 608 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 609 1, regs, 0); 610 return simulate_sc(regs, opcode); 611 } 612 613 return -1; /* Must be something else ... */ 614} 615 616/* 617 * Simulate trapping 'rdhwr' instructions to provide user accessible 618 * registers not implemented in hardware. 619 */ 620static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt) 621{ 622 struct thread_info *ti = task_thread_info(current); 623 624 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 625 1, regs, 0); 626 switch (rd) { 627 case 0: /* CPU number */ 628 regs->regs[rt] = smp_processor_id(); 629 return 0; 630 case 1: /* SYNCI length */ 631 regs->regs[rt] = min(current_cpu_data.dcache.linesz, 632 current_cpu_data.icache.linesz); 633 return 0; 634 case 2: /* Read count register */ 635 regs->regs[rt] = read_c0_count(); 636 return 0; 637 case 3: /* Count register resolution */ 638 switch (current_cpu_type()) { 639 case CPU_20KC: 640 case CPU_25KF: 641 regs->regs[rt] = 1; 642 break; 643 default: 644 regs->regs[rt] = 2; 645 } 646 return 0; 647 case 29: 648 regs->regs[rt] = ti->tp_value; 649 return 0; 650 default: 651 return -1; 652 } 653} 654 655static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode) 656{ 657 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { 658 int rd = (opcode & RD) >> 11; 659 int rt = (opcode & RT) >> 16; 660 661 simulate_rdhwr(regs, rd, rt); 662 return 0; 663 } 664 665 /* Not ours. */ 666 return -1; 667} 668 669static int simulate_rdhwr_mm(struct pt_regs *regs, unsigned short opcode) 670{ 671 if ((opcode & MM_POOL32A_FUNC) == MM_RDHWR) { 672 int rd = (opcode & MM_RS) >> 16; 673 int rt = (opcode & MM_RT) >> 21; 674 simulate_rdhwr(regs, rd, rt); 675 return 0; 676 } 677 678 /* Not ours. */ 679 return -1; 680} 681 682static int simulate_sync(struct pt_regs *regs, unsigned int opcode) 683{ 684 if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) { 685 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 686 1, regs, 0); 687 return 0; 688 } 689 690 return -1; /* Must be something else ... */ 691} 692 693asmlinkage void do_ov(struct pt_regs *regs) 694{ 695 enum ctx_state prev_state; 696 siginfo_t info = { 697 .si_signo = SIGFPE, 698 .si_code = FPE_INTOVF, 699 .si_addr = (void __user *)regs->cp0_epc, 700 }; 701 702 prev_state = exception_enter(); 703 die_if_kernel("Integer overflow", regs); 704 705 force_sig_info(SIGFPE, &info, current); 706 exception_exit(prev_state); 707} 708 709int process_fpemu_return(int sig, void __user *fault_addr, unsigned long fcr31) 710{ 711 struct siginfo si = { 0 }; 712 713 switch (sig) { 714 case 0: 715 return 0; 716 717 case SIGFPE: 718 si.si_addr = fault_addr; 719 si.si_signo = sig; 720 /* 721 * Inexact can happen together with Overflow or Underflow. 722 * Respect the mask to deliver the correct exception. 723 */ 724 fcr31 &= (fcr31 & FPU_CSR_ALL_E) << 725 (ffs(FPU_CSR_ALL_X) - ffs(FPU_CSR_ALL_E)); 726 if (fcr31 & FPU_CSR_INV_X) 727 si.si_code = FPE_FLTINV; 728 else if (fcr31 & FPU_CSR_DIV_X) 729 si.si_code = FPE_FLTDIV; 730 else if (fcr31 & FPU_CSR_OVF_X) 731 si.si_code = FPE_FLTOVF; 732 else if (fcr31 & FPU_CSR_UDF_X) 733 si.si_code = FPE_FLTUND; 734 else if (fcr31 & FPU_CSR_INE_X) 735 si.si_code = FPE_FLTRES; 736 else 737 si.si_code = __SI_FAULT; 738 force_sig_info(sig, &si, current); 739 return 1; 740 741 case SIGBUS: 742 si.si_addr = fault_addr; 743 si.si_signo = sig; 744 si.si_code = BUS_ADRERR; 745 force_sig_info(sig, &si, current); 746 return 1; 747 748 case SIGSEGV: 749 si.si_addr = fault_addr; 750 si.si_signo = sig; 751 down_read(¤t->mm->mmap_sem); 752 if (find_vma(current->mm, (unsigned long)fault_addr)) 753 si.si_code = SEGV_ACCERR; 754 else 755 si.si_code = SEGV_MAPERR; 756 up_read(¤t->mm->mmap_sem); 757 force_sig_info(sig, &si, current); 758 return 1; 759 760 default: 761 force_sig(sig, current); 762 return 1; 763 } 764} 765 766static int simulate_fp(struct pt_regs *regs, unsigned int opcode, 767 unsigned long old_epc, unsigned long old_ra) 768{ 769 union mips_instruction inst = { .word = opcode }; 770 void __user *fault_addr; 771 unsigned long fcr31; 772 int sig; 773 774 /* If it's obviously not an FP instruction, skip it */ 775 switch (inst.i_format.opcode) { 776 case cop1_op: 777 case cop1x_op: 778 case lwc1_op: 779 case ldc1_op: 780 case swc1_op: 781 case sdc1_op: 782 break; 783 784 default: 785 return -1; 786 } 787 788 /* 789 * do_ri skipped over the instruction via compute_return_epc, undo 790 * that for the FPU emulator. 791 */ 792 regs->cp0_epc = old_epc; 793 regs->regs[31] = old_ra; 794 795 /* Save the FP context to struct thread_struct */ 796 lose_fpu(1); 797 798 /* Run the emulator */ 799 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 800 &fault_addr); 801 fcr31 = current->thread.fpu.fcr31; 802 803 /* 804 * We can't allow the emulated instruction to leave any of 805 * the cause bits set in $fcr31. 806 */ 807 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 808 809 /* Restore the hardware register state */ 810 own_fpu(1); 811 812 /* Send a signal if required. */ 813 process_fpemu_return(sig, fault_addr, fcr31); 814 815 return 0; 816} 817 818/* 819 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX 820 */ 821asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) 822{ 823 enum ctx_state prev_state; 824 void __user *fault_addr; 825 int sig; 826 827 prev_state = exception_enter(); 828 if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), 829 SIGFPE) == NOTIFY_STOP) 830 goto out; 831 832 /* Clear FCSR.Cause before enabling interrupts */ 833 write_32bit_cp1_register(CP1_STATUS, fcr31 & ~FPU_CSR_ALL_X); 834 local_irq_enable(); 835 836 die_if_kernel("FP exception in kernel code", regs); 837 838 if (fcr31 & FPU_CSR_UNI_X) { 839 /* 840 * Unimplemented operation exception. If we've got the full 841 * software emulator on-board, let's use it... 842 * 843 * Force FPU to dump state into task/thread context. We're 844 * moving a lot of data here for what is probably a single 845 * instruction, but the alternative is to pre-decode the FP 846 * register operands before invoking the emulator, which seems 847 * a bit extreme for what should be an infrequent event. 848 */ 849 /* Ensure 'resume' not overwrite saved fp context again. */ 850 lose_fpu(1); 851 852 /* Run the emulator */ 853 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, 854 &fault_addr); 855 fcr31 = current->thread.fpu.fcr31; 856 857 /* 858 * We can't allow the emulated instruction to leave any of 859 * the cause bits set in $fcr31. 860 */ 861 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 862 863 /* Restore the hardware register state */ 864 own_fpu(1); /* Using the FPU again. */ 865 } else { 866 sig = SIGFPE; 867 fault_addr = (void __user *) regs->cp0_epc; 868 } 869 870 /* Send a signal if required. */ 871 process_fpemu_return(sig, fault_addr, fcr31); 872 873out: 874 exception_exit(prev_state); 875} 876 877void do_trap_or_bp(struct pt_regs *regs, unsigned int code, 878 const char *str) 879{ 880 siginfo_t info = { 0 }; 881 char b[40]; 882 883#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 884 if (kgdb_ll_trap(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 885 return; 886#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 887 888 if (notify_die(DIE_TRAP, str, regs, code, regs_to_trapnr(regs), 889 SIGTRAP) == NOTIFY_STOP) 890 return; 891 892 /* 893 * A short test says that IRIX 5.3 sends SIGTRAP for all trap 894 * insns, even for trap and break codes that indicate arithmetic 895 * failures. Weird ... 896 * But should we continue the brokenness??? --macro 897 */ 898 switch (code) { 899 case BRK_OVERFLOW: 900 case BRK_DIVZERO: 901 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 902 die_if_kernel(b, regs); 903 if (code == BRK_DIVZERO) 904 info.si_code = FPE_INTDIV; 905 else 906 info.si_code = FPE_INTOVF; 907 info.si_signo = SIGFPE; 908 info.si_addr = (void __user *) regs->cp0_epc; 909 force_sig_info(SIGFPE, &info, current); 910 break; 911 case BRK_BUG: 912 die_if_kernel("Kernel bug detected", regs); 913 force_sig(SIGTRAP, current); 914 break; 915 case BRK_MEMU: 916 /* 917 * This breakpoint code is used by the FPU emulator to retake 918 * control of the CPU after executing the instruction from the 919 * delay slot of an emulated branch. 920 * 921 * Terminate if exception was recognized as a delay slot return 922 * otherwise handle as normal. 923 */ 924 if (do_dsemulret(regs)) 925 return; 926 927 die_if_kernel("Math emu break/trap", regs); 928 force_sig(SIGTRAP, current); 929 break; 930 default: 931 scnprintf(b, sizeof(b), "%s instruction in kernel code", str); 932 die_if_kernel(b, regs); 933 force_sig(SIGTRAP, current); 934 } 935} 936 937asmlinkage void do_bp(struct pt_regs *regs) 938{ 939 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 940 unsigned int opcode, bcode; 941 enum ctx_state prev_state; 942 mm_segment_t seg; 943 944 seg = get_fs(); 945 if (!user_mode(regs)) 946 set_fs(KERNEL_DS); 947 948 prev_state = exception_enter(); 949 if (get_isa16_mode(regs->cp0_epc)) { 950 u16 instr[2]; 951 952 if (__get_user(instr[0], (u16 __user *)epc)) 953 goto out_sigsegv; 954 955 if (!cpu_has_mmips) { 956 /* MIPS16e mode */ 957 bcode = (instr[0] >> 5) & 0x3f; 958 } else if (mm_insn_16bit(instr[0])) { 959 /* 16-bit microMIPS BREAK */ 960 bcode = instr[0] & 0xf; 961 } else { 962 /* 32-bit microMIPS BREAK */ 963 if (__get_user(instr[1], (u16 __user *)(epc + 2))) 964 goto out_sigsegv; 965 opcode = (instr[0] << 16) | instr[1]; 966 bcode = (opcode >> 6) & ((1 << 20) - 1); 967 } 968 } else { 969 if (__get_user(opcode, (unsigned int __user *)epc)) 970 goto out_sigsegv; 971 bcode = (opcode >> 6) & ((1 << 20) - 1); 972 } 973 974 /* 975 * There is the ancient bug in the MIPS assemblers that the break 976 * code starts left to bit 16 instead to bit 6 in the opcode. 977 * Gas is bug-compatible, but not always, grrr... 978 * We handle both cases with a simple heuristics. --macro 979 */ 980 if (bcode >= (1 << 10)) 981 bcode = ((bcode & ((1 << 10) - 1)) << 10) | (bcode >> 10); 982 983 /* 984 * notify the kprobe handlers, if instruction is likely to 985 * pertain to them. 986 */ 987 switch (bcode) { 988 case BRK_KPROBE_BP: 989 if (notify_die(DIE_BREAK, "debug", regs, bcode, 990 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 991 goto out; 992 else 993 break; 994 case BRK_KPROBE_SSTEPBP: 995 if (notify_die(DIE_SSTEPBP, "single_step", regs, bcode, 996 regs_to_trapnr(regs), SIGTRAP) == NOTIFY_STOP) 997 goto out; 998 else 999 break; 1000 default: 1001 break; 1002 } 1003 1004 do_trap_or_bp(regs, bcode, "Break"); 1005 1006out: 1007 set_fs(seg); 1008 exception_exit(prev_state); 1009 return; 1010 1011out_sigsegv: 1012 force_sig(SIGSEGV, current); 1013 goto out; 1014} 1015 1016asmlinkage void do_tr(struct pt_regs *regs) 1017{ 1018 u32 opcode, tcode = 0; 1019 enum ctx_state prev_state; 1020 u16 instr[2]; 1021 mm_segment_t seg; 1022 unsigned long epc = msk_isa16_mode(exception_epc(regs)); 1023 1024 seg = get_fs(); 1025 if (!user_mode(regs)) 1026 set_fs(get_ds()); 1027 1028 prev_state = exception_enter(); 1029 if (get_isa16_mode(regs->cp0_epc)) { 1030 if (__get_user(instr[0], (u16 __user *)(epc + 0)) || 1031 __get_user(instr[1], (u16 __user *)(epc + 2))) 1032 goto out_sigsegv; 1033 opcode = (instr[0] << 16) | instr[1]; 1034 /* Immediate versions don't provide a code. */ 1035 if (!(opcode & OPCODE)) 1036 tcode = (opcode >> 12) & ((1 << 4) - 1); 1037 } else { 1038 if (__get_user(opcode, (u32 __user *)epc)) 1039 goto out_sigsegv; 1040 /* Immediate versions don't provide a code. */ 1041 if (!(opcode & OPCODE)) 1042 tcode = (opcode >> 6) & ((1 << 10) - 1); 1043 } 1044 1045 do_trap_or_bp(regs, tcode, "Trap"); 1046 1047out: 1048 set_fs(seg); 1049 exception_exit(prev_state); 1050 return; 1051 1052out_sigsegv: 1053 force_sig(SIGSEGV, current); 1054 goto out; 1055} 1056 1057asmlinkage void do_ri(struct pt_regs *regs) 1058{ 1059 unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); 1060 unsigned long old_epc = regs->cp0_epc; 1061 unsigned long old31 = regs->regs[31]; 1062 enum ctx_state prev_state; 1063 unsigned int opcode = 0; 1064 int status = -1; 1065 1066 /* 1067 * Avoid any kernel code. Just emulate the R2 instruction 1068 * as quickly as possible. 1069 */ 1070 if (mipsr2_emulation && cpu_has_mips_r6 && 1071 likely(user_mode(regs)) && 1072 likely(get_user(opcode, epc) >= 0)) { 1073 unsigned long fcr31 = 0; 1074 1075 status = mipsr2_decoder(regs, opcode, &fcr31); 1076 switch (status) { 1077 case 0: 1078 case SIGEMT: 1079 task_thread_info(current)->r2_emul_return = 1; 1080 return; 1081 case SIGILL: 1082 goto no_r2_instr; 1083 default: 1084 process_fpemu_return(status, 1085 ¤t->thread.cp0_baduaddr, 1086 fcr31); 1087 task_thread_info(current)->r2_emul_return = 1; 1088 return; 1089 } 1090 } 1091 1092no_r2_instr: 1093 1094 prev_state = exception_enter(); 1095 1096 if (notify_die(DIE_RI, "RI Fault", regs, 0, regs_to_trapnr(regs), 1097 SIGILL) == NOTIFY_STOP) 1098 goto out; 1099 1100 die_if_kernel("Reserved instruction in kernel code", regs); 1101 1102 if (unlikely(compute_return_epc(regs) < 0)) 1103 goto out; 1104 1105 if (get_isa16_mode(regs->cp0_epc)) { 1106 unsigned short mmop[2] = { 0 }; 1107 1108 if (unlikely(get_user(mmop[0], epc) < 0)) 1109 status = SIGSEGV; 1110 if (unlikely(get_user(mmop[1], epc) < 0)) 1111 status = SIGSEGV; 1112 opcode = (mmop[0] << 16) | mmop[1]; 1113 1114 if (status < 0) 1115 status = simulate_rdhwr_mm(regs, opcode); 1116 } else { 1117 if (unlikely(get_user(opcode, epc) < 0)) 1118 status = SIGSEGV; 1119 1120 if (!cpu_has_llsc && status < 0) 1121 status = simulate_llsc(regs, opcode); 1122 1123 if (status < 0) 1124 status = simulate_rdhwr_normal(regs, opcode); 1125 1126 if (status < 0) 1127 status = simulate_sync(regs, opcode); 1128 1129 if (status < 0) 1130 status = simulate_fp(regs, opcode, old_epc, old31); 1131 } 1132 1133 if (status < 0) 1134 status = SIGILL; 1135 1136 if (unlikely(status > 0)) { 1137 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1138 regs->regs[31] = old31; 1139 force_sig(status, current); 1140 } 1141 1142out: 1143 exception_exit(prev_state); 1144} 1145 1146/* 1147 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've 1148 * emulated more than some threshold number of instructions, force migration to 1149 * a "CPU" that has FP support. 1150 */ 1151static void mt_ase_fp_affinity(void) 1152{ 1153#ifdef CONFIG_MIPS_MT_FPAFF 1154 if (mt_fpemul_threshold > 0 && 1155 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { 1156 /* 1157 * If there's no FPU present, or if the application has already 1158 * restricted the allowed set to exclude any CPUs with FPUs, 1159 * we'll skip the procedure. 1160 */ 1161 if (cpumask_intersects(¤t->cpus_allowed, &mt_fpu_cpumask)) { 1162 cpumask_t tmask; 1163 1164 current->thread.user_cpus_allowed 1165 = current->cpus_allowed; 1166 cpumask_and(&tmask, ¤t->cpus_allowed, 1167 &mt_fpu_cpumask); 1168 set_cpus_allowed_ptr(current, &tmask); 1169 set_thread_flag(TIF_FPUBOUND); 1170 } 1171 } 1172#endif /* CONFIG_MIPS_MT_FPAFF */ 1173} 1174 1175/* 1176 * No lock; only written during early bootup by CPU 0. 1177 */ 1178static RAW_NOTIFIER_HEAD(cu2_chain); 1179 1180int __ref register_cu2_notifier(struct notifier_block *nb) 1181{ 1182 return raw_notifier_chain_register(&cu2_chain, nb); 1183} 1184 1185int cu2_notifier_call_chain(unsigned long val, void *v) 1186{ 1187 return raw_notifier_call_chain(&cu2_chain, val, v); 1188} 1189 1190static int default_cu2_call(struct notifier_block *nfb, unsigned long action, 1191 void *data) 1192{ 1193 struct pt_regs *regs = data; 1194 1195 die_if_kernel("COP2: Unhandled kernel unaligned access or invalid " 1196 "instruction", regs); 1197 force_sig(SIGILL, current); 1198 1199 return NOTIFY_OK; 1200} 1201 1202static int wait_on_fp_mode_switch(atomic_t *p) 1203{ 1204 /* 1205 * The FP mode for this task is currently being switched. That may 1206 * involve modifications to the format of this tasks FP context which 1207 * make it unsafe to proceed with execution for the moment. Instead, 1208 * schedule some other task. 1209 */ 1210 schedule(); 1211 return 0; 1212} 1213 1214static int enable_restore_fp_context(int msa) 1215{ 1216 int err, was_fpu_owner, prior_msa; 1217 1218 /* 1219 * If an FP mode switch is currently underway, wait for it to 1220 * complete before proceeding. 1221 */ 1222 wait_on_atomic_t(¤t->mm->context.fp_mode_switching, 1223 wait_on_fp_mode_switch, TASK_KILLABLE); 1224 1225 if (!used_math()) { 1226 /* First time FP context user. */ 1227 preempt_disable(); 1228 err = init_fpu(); 1229 if (msa && !err) { 1230 enable_msa(); 1231 init_msa_upper(); 1232 set_thread_flag(TIF_USEDMSA); 1233 set_thread_flag(TIF_MSA_CTX_LIVE); 1234 } 1235 preempt_enable(); 1236 if (!err) 1237 set_used_math(); 1238 return err; 1239 } 1240 1241 /* 1242 * This task has formerly used the FP context. 1243 * 1244 * If this thread has no live MSA vector context then we can simply 1245 * restore the scalar FP context. If it has live MSA vector context 1246 * (that is, it has or may have used MSA since last performing a 1247 * function call) then we'll need to restore the vector context. This 1248 * applies even if we're currently only executing a scalar FP 1249 * instruction. This is because if we were to later execute an MSA 1250 * instruction then we'd either have to: 1251 * 1252 * - Restore the vector context & clobber any registers modified by 1253 * scalar FP instructions between now & then. 1254 * 1255 * or 1256 * 1257 * - Not restore the vector context & lose the most significant bits 1258 * of all vector registers. 1259 * 1260 * Neither of those options is acceptable. We cannot restore the least 1261 * significant bits of the registers now & only restore the most 1262 * significant bits later because the most significant bits of any 1263 * vector registers whose aliased FP register is modified now will have 1264 * been zeroed. We'd have no way to know that when restoring the vector 1265 * context & thus may load an outdated value for the most significant 1266 * bits of a vector register. 1267 */ 1268 if (!msa && !thread_msa_context_live()) 1269 return own_fpu(1); 1270 1271 /* 1272 * This task is using or has previously used MSA. Thus we require 1273 * that Status.FR == 1. 1274 */ 1275 preempt_disable(); 1276 was_fpu_owner = is_fpu_owner(); 1277 err = own_fpu_inatomic(0); 1278 if (err) 1279 goto out; 1280 1281 enable_msa(); 1282 write_msa_csr(current->thread.fpu.msacsr); 1283 set_thread_flag(TIF_USEDMSA); 1284 1285 /* 1286 * If this is the first time that the task is using MSA and it has 1287 * previously used scalar FP in this time slice then we already nave 1288 * FP context which we shouldn't clobber. We do however need to clear 1289 * the upper 64b of each vector register so that this task has no 1290 * opportunity to see data left behind by another. 1291 */ 1292 prior_msa = test_and_set_thread_flag(TIF_MSA_CTX_LIVE); 1293 if (!prior_msa && was_fpu_owner) { 1294 init_msa_upper(); 1295 1296 goto out; 1297 } 1298 1299 if (!prior_msa) { 1300 /* 1301 * Restore the least significant 64b of each vector register 1302 * from the existing scalar FP context. 1303 */ 1304 _restore_fp(current); 1305 1306 /* 1307 * The task has not formerly used MSA, so clear the upper 64b 1308 * of each vector register such that it cannot see data left 1309 * behind by another task. 1310 */ 1311 init_msa_upper(); 1312 } else { 1313 /* We need to restore the vector context. */ 1314 restore_msa(current); 1315 1316 /* Restore the scalar FP control & status register */ 1317 if (!was_fpu_owner) 1318 write_32bit_cp1_register(CP1_STATUS, 1319 current->thread.fpu.fcr31); 1320 } 1321 1322out: 1323 preempt_enable(); 1324 1325 return 0; 1326} 1327 1328asmlinkage void do_cpu(struct pt_regs *regs) 1329{ 1330 enum ctx_state prev_state; 1331 unsigned int __user *epc; 1332 unsigned long old_epc, old31; 1333 void __user *fault_addr; 1334 unsigned int opcode; 1335 unsigned long fcr31; 1336 unsigned int cpid; 1337 int status, err; 1338 unsigned long __maybe_unused flags; 1339 int sig; 1340 1341 prev_state = exception_enter(); 1342 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; 1343 1344 if (cpid != 2) 1345 die_if_kernel("do_cpu invoked from kernel context!", regs); 1346 1347 switch (cpid) { 1348 case 0: 1349 epc = (unsigned int __user *)exception_epc(regs); 1350 old_epc = regs->cp0_epc; 1351 old31 = regs->regs[31]; 1352 opcode = 0; 1353 status = -1; 1354 1355 if (unlikely(compute_return_epc(regs) < 0)) 1356 break; 1357 1358 if (get_isa16_mode(regs->cp0_epc)) { 1359 unsigned short mmop[2] = { 0 }; 1360 1361 if (unlikely(get_user(mmop[0], epc) < 0)) 1362 status = SIGSEGV; 1363 if (unlikely(get_user(mmop[1], epc) < 0)) 1364 status = SIGSEGV; 1365 opcode = (mmop[0] << 16) | mmop[1]; 1366 1367 if (status < 0) 1368 status = simulate_rdhwr_mm(regs, opcode); 1369 } else { 1370 if (unlikely(get_user(opcode, epc) < 0)) 1371 status = SIGSEGV; 1372 1373 if (!cpu_has_llsc && status < 0) 1374 status = simulate_llsc(regs, opcode); 1375 1376 if (status < 0) 1377 status = simulate_rdhwr_normal(regs, opcode); 1378 } 1379 1380 if (status < 0) 1381 status = SIGILL; 1382 1383 if (unlikely(status > 0)) { 1384 regs->cp0_epc = old_epc; /* Undo skip-over. */ 1385 regs->regs[31] = old31; 1386 force_sig(status, current); 1387 } 1388 1389 break; 1390 1391 case 3: 1392 /* 1393 * The COP3 opcode space and consequently the CP0.Status.CU3 1394 * bit and the CP0.Cause.CE=3 encoding have been removed as 1395 * of the MIPS III ISA. From the MIPS IV and MIPS32r2 ISAs 1396 * up the space has been reused for COP1X instructions, that 1397 * are enabled by the CP0.Status.CU1 bit and consequently 1398 * use the CP0.Cause.CE=1 encoding for Coprocessor Unusable 1399 * exceptions. Some FPU-less processors that implement one 1400 * of these ISAs however use this code erroneously for COP1X 1401 * instructions. Therefore we redirect this trap to the FP 1402 * emulator too. 1403 */ 1404 if (raw_cpu_has_fpu || !cpu_has_mips_4_5_64_r2_r6) { 1405 force_sig(SIGILL, current); 1406 break; 1407 } 1408 /* Fall through. */ 1409 1410 case 1: 1411 err = enable_restore_fp_context(0); 1412 1413 if (raw_cpu_has_fpu && !err) 1414 break; 1415 1416 sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 0, 1417 &fault_addr); 1418 fcr31 = current->thread.fpu.fcr31; 1419 1420 /* 1421 * We can't allow the emulated instruction to leave 1422 * any of the cause bits set in $fcr31. 1423 */ 1424 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 1425 1426 /* Send a signal if required. */ 1427 if (!process_fpemu_return(sig, fault_addr, fcr31) && !err) 1428 mt_ase_fp_affinity(); 1429 1430 break; 1431 1432 case 2: 1433 raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); 1434 break; 1435 } 1436 1437 exception_exit(prev_state); 1438} 1439 1440asmlinkage void do_msa_fpe(struct pt_regs *regs, unsigned int msacsr) 1441{ 1442 enum ctx_state prev_state; 1443 1444 prev_state = exception_enter(); 1445 if (notify_die(DIE_MSAFP, "MSA FP exception", regs, 0, 1446 regs_to_trapnr(regs), SIGFPE) == NOTIFY_STOP) 1447 goto out; 1448 1449 /* Clear MSACSR.Cause before enabling interrupts */ 1450 write_msa_csr(msacsr & ~MSA_CSR_CAUSEF); 1451 local_irq_enable(); 1452 1453 die_if_kernel("do_msa_fpe invoked from kernel context!", regs); 1454 force_sig(SIGFPE, current); 1455out: 1456 exception_exit(prev_state); 1457} 1458 1459asmlinkage void do_msa(struct pt_regs *regs) 1460{ 1461 enum ctx_state prev_state; 1462 int err; 1463 1464 prev_state = exception_enter(); 1465 1466 if (!cpu_has_msa || test_thread_flag(TIF_32BIT_FPREGS)) { 1467 force_sig(SIGILL, current); 1468 goto out; 1469 } 1470 1471 die_if_kernel("do_msa invoked from kernel context!", regs); 1472 1473 err = enable_restore_fp_context(1); 1474 if (err) 1475 force_sig(SIGILL, current); 1476out: 1477 exception_exit(prev_state); 1478} 1479 1480asmlinkage void do_mdmx(struct pt_regs *regs) 1481{ 1482 enum ctx_state prev_state; 1483 1484 prev_state = exception_enter(); 1485 force_sig(SIGILL, current); 1486 exception_exit(prev_state); 1487} 1488 1489/* 1490 * Called with interrupts disabled. 1491 */ 1492asmlinkage void do_watch(struct pt_regs *regs) 1493{ 1494 enum ctx_state prev_state; 1495 u32 cause; 1496 1497 prev_state = exception_enter(); 1498 /* 1499 * Clear WP (bit 22) bit of cause register so we don't loop 1500 * forever. 1501 */ 1502 cause = read_c0_cause(); 1503 cause &= ~(1 << 22); 1504 write_c0_cause(cause); 1505 1506 /* 1507 * If the current thread has the watch registers loaded, save 1508 * their values and send SIGTRAP. Otherwise another thread 1509 * left the registers set, clear them and continue. 1510 */ 1511 if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { 1512 mips_read_watch_registers(); 1513 local_irq_enable(); 1514 force_sig(SIGTRAP, current); 1515 } else { 1516 mips_clear_watch_registers(); 1517 local_irq_enable(); 1518 } 1519 exception_exit(prev_state); 1520} 1521 1522asmlinkage void do_mcheck(struct pt_regs *regs) 1523{ 1524 const int field = 2 * sizeof(unsigned long); 1525 int multi_match = regs->cp0_status & ST0_TS; 1526 enum ctx_state prev_state; 1527 mm_segment_t old_fs = get_fs(); 1528 1529 prev_state = exception_enter(); 1530 show_regs(regs); 1531 1532 if (multi_match) { 1533 pr_err("Index : %0x\n", read_c0_index()); 1534 pr_err("Pagemask: %0x\n", read_c0_pagemask()); 1535 pr_err("EntryHi : %0*lx\n", field, read_c0_entryhi()); 1536 pr_err("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); 1537 pr_err("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); 1538 pr_err("Wired : %0x\n", read_c0_wired()); 1539 pr_err("Pagegrain: %0x\n", read_c0_pagegrain()); 1540 if (cpu_has_htw) { 1541 pr_err("PWField : %0*lx\n", field, read_c0_pwfield()); 1542 pr_err("PWSize : %0*lx\n", field, read_c0_pwsize()); 1543 pr_err("PWCtl : %0x\n", read_c0_pwctl()); 1544 } 1545 pr_err("\n"); 1546 dump_tlb_all(); 1547 } 1548 1549 if (!user_mode(regs)) 1550 set_fs(KERNEL_DS); 1551 1552 show_code((unsigned int __user *) regs->cp0_epc); 1553 1554 set_fs(old_fs); 1555 1556 /* 1557 * Some chips may have other causes of machine check (e.g. SB1 1558 * graduation timer) 1559 */ 1560 panic("Caught Machine Check exception - %scaused by multiple " 1561 "matching entries in the TLB.", 1562 (multi_match) ? "" : "not "); 1563} 1564 1565asmlinkage void do_mt(struct pt_regs *regs) 1566{ 1567 int subcode; 1568 1569 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) 1570 >> VPECONTROL_EXCPT_SHIFT; 1571 switch (subcode) { 1572 case 0: 1573 printk(KERN_DEBUG "Thread Underflow\n"); 1574 break; 1575 case 1: 1576 printk(KERN_DEBUG "Thread Overflow\n"); 1577 break; 1578 case 2: 1579 printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); 1580 break; 1581 case 3: 1582 printk(KERN_DEBUG "Gating Storage Exception\n"); 1583 break; 1584 case 4: 1585 printk(KERN_DEBUG "YIELD Scheduler Exception\n"); 1586 break; 1587 case 5: 1588 printk(KERN_DEBUG "Gating Storage Scheduler Exception\n"); 1589 break; 1590 default: 1591 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", 1592 subcode); 1593 break; 1594 } 1595 die_if_kernel("MIPS MT Thread exception in kernel", regs); 1596 1597 force_sig(SIGILL, current); 1598} 1599 1600 1601asmlinkage void do_dsp(struct pt_regs *regs) 1602{ 1603 if (cpu_has_dsp) 1604 panic("Unexpected DSP exception"); 1605 1606 force_sig(SIGILL, current); 1607} 1608 1609asmlinkage void do_reserved(struct pt_regs *regs) 1610{ 1611 /* 1612 * Game over - no way to handle this if it ever occurs. Most probably 1613 * caused by a new unknown cpu type or after another deadly 1614 * hard/software error. 1615 */ 1616 show_regs(regs); 1617 panic("Caught reserved exception %ld - should not happen.", 1618 (regs->cp0_cause & 0x7f) >> 2); 1619} 1620 1621static int __initdata l1parity = 1; 1622static int __init nol1parity(char *s) 1623{ 1624 l1parity = 0; 1625 return 1; 1626} 1627__setup("nol1par", nol1parity); 1628static int __initdata l2parity = 1; 1629static int __init nol2parity(char *s) 1630{ 1631 l2parity = 0; 1632 return 1; 1633} 1634__setup("nol2par", nol2parity); 1635 1636/* 1637 * Some MIPS CPUs can enable/disable for cache parity detection, but do 1638 * it different ways. 1639 */ 1640static inline void parity_protection_init(void) 1641{ 1642 switch (current_cpu_type()) { 1643 case CPU_24K: 1644 case CPU_34K: 1645 case CPU_74K: 1646 case CPU_1004K: 1647 case CPU_1074K: 1648 case CPU_INTERAPTIV: 1649 case CPU_PROAPTIV: 1650 case CPU_P5600: 1651 case CPU_QEMU_GENERIC: 1652 { 1653#define ERRCTL_PE 0x80000000 1654#define ERRCTL_L2P 0x00800000 1655 unsigned long errctl; 1656 unsigned int l1parity_present, l2parity_present; 1657 1658 errctl = read_c0_ecc(); 1659 errctl &= ~(ERRCTL_PE|ERRCTL_L2P); 1660 1661 /* probe L1 parity support */ 1662 write_c0_ecc(errctl | ERRCTL_PE); 1663 back_to_back_c0_hazard(); 1664 l1parity_present = (read_c0_ecc() & ERRCTL_PE); 1665 1666 /* probe L2 parity support */ 1667 write_c0_ecc(errctl|ERRCTL_L2P); 1668 back_to_back_c0_hazard(); 1669 l2parity_present = (read_c0_ecc() & ERRCTL_L2P); 1670 1671 if (l1parity_present && l2parity_present) { 1672 if (l1parity) 1673 errctl |= ERRCTL_PE; 1674 if (l1parity ^ l2parity) 1675 errctl |= ERRCTL_L2P; 1676 } else if (l1parity_present) { 1677 if (l1parity) 1678 errctl |= ERRCTL_PE; 1679 } else if (l2parity_present) { 1680 if (l2parity) 1681 errctl |= ERRCTL_L2P; 1682 } else { 1683 /* No parity available */ 1684 } 1685 1686 printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); 1687 1688 write_c0_ecc(errctl); 1689 back_to_back_c0_hazard(); 1690 errctl = read_c0_ecc(); 1691 printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); 1692 1693 if (l1parity_present) 1694 printk(KERN_INFO "Cache parity protection %sabled\n", 1695 (errctl & ERRCTL_PE) ? "en" : "dis"); 1696 1697 if (l2parity_present) { 1698 if (l1parity_present && l1parity) 1699 errctl ^= ERRCTL_L2P; 1700 printk(KERN_INFO "L2 cache parity protection %sabled\n", 1701 (errctl & ERRCTL_L2P) ? "en" : "dis"); 1702 } 1703 } 1704 break; 1705 1706 case CPU_5KC: 1707 case CPU_5KE: 1708 case CPU_LOONGSON1: 1709 write_c0_ecc(0x80000000); 1710 back_to_back_c0_hazard(); 1711 /* Set the PE bit (bit 31) in the c0_errctl register. */ 1712 printk(KERN_INFO "Cache parity protection %sabled\n", 1713 (read_c0_ecc() & 0x80000000) ? "en" : "dis"); 1714 break; 1715 case CPU_20KC: 1716 case CPU_25KF: 1717 /* Clear the DE bit (bit 16) in the c0_status register. */ 1718 printk(KERN_INFO "Enable cache parity protection for " 1719 "MIPS 20KC/25KF CPUs.\n"); 1720 clear_c0_status(ST0_DE); 1721 break; 1722 default: 1723 break; 1724 } 1725} 1726 1727asmlinkage void cache_parity_error(void) 1728{ 1729 const int field = 2 * sizeof(unsigned long); 1730 unsigned int reg_val; 1731 1732 /* For the moment, report the problem and hang. */ 1733 printk("Cache error exception:\n"); 1734 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1735 reg_val = read_c0_cacheerr(); 1736 printk("c0_cacheerr == %08x\n", reg_val); 1737 1738 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1739 reg_val & (1<<30) ? "secondary" : "primary", 1740 reg_val & (1<<31) ? "data" : "insn"); 1741 if ((cpu_has_mips_r2_r6) && 1742 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1743 pr_err("Error bits: %s%s%s%s%s%s%s%s\n", 1744 reg_val & (1<<29) ? "ED " : "", 1745 reg_val & (1<<28) ? "ET " : "", 1746 reg_val & (1<<27) ? "ES " : "", 1747 reg_val & (1<<26) ? "EE " : "", 1748 reg_val & (1<<25) ? "EB " : "", 1749 reg_val & (1<<24) ? "EI " : "", 1750 reg_val & (1<<23) ? "E1 " : "", 1751 reg_val & (1<<22) ? "E0 " : ""); 1752 } else { 1753 pr_err("Error bits: %s%s%s%s%s%s%s\n", 1754 reg_val & (1<<29) ? "ED " : "", 1755 reg_val & (1<<28) ? "ET " : "", 1756 reg_val & (1<<26) ? "EE " : "", 1757 reg_val & (1<<25) ? "EB " : "", 1758 reg_val & (1<<24) ? "EI " : "", 1759 reg_val & (1<<23) ? "E1 " : "", 1760 reg_val & (1<<22) ? "E0 " : ""); 1761 } 1762 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); 1763 1764#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) 1765 if (reg_val & (1<<22)) 1766 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); 1767 1768 if (reg_val & (1<<23)) 1769 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); 1770#endif 1771 1772 panic("Can't handle the cache error!"); 1773} 1774 1775asmlinkage void do_ftlb(void) 1776{ 1777 const int field = 2 * sizeof(unsigned long); 1778 unsigned int reg_val; 1779 1780 /* For the moment, report the problem and hang. */ 1781 if ((cpu_has_mips_r2_r6) && 1782 ((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_MIPS)) { 1783 pr_err("FTLB error exception, cp0_ecc=0x%08x:\n", 1784 read_c0_ecc()); 1785 pr_err("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); 1786 reg_val = read_c0_cacheerr(); 1787 pr_err("c0_cacheerr == %08x\n", reg_val); 1788 1789 if ((reg_val & 0xc0000000) == 0xc0000000) { 1790 pr_err("Decoded c0_cacheerr: FTLB parity error\n"); 1791 } else { 1792 pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n", 1793 reg_val & (1<<30) ? "secondary" : "primary", 1794 reg_val & (1<<31) ? "data" : "insn"); 1795 } 1796 } else { 1797 pr_err("FTLB error exception\n"); 1798 } 1799 /* Just print the cacheerr bits for now */ 1800 cache_parity_error(); 1801} 1802 1803/* 1804 * SDBBP EJTAG debug exception handler. 1805 * We skip the instruction and return to the next instruction. 1806 */ 1807void ejtag_exception_handler(struct pt_regs *regs) 1808{ 1809 const int field = 2 * sizeof(unsigned long); 1810 unsigned long depc, old_epc, old_ra; 1811 unsigned int debug; 1812 1813 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); 1814 depc = read_c0_depc(); 1815 debug = read_c0_debug(); 1816 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); 1817 if (debug & 0x80000000) { 1818 /* 1819 * In branch delay slot. 1820 * We cheat a little bit here and use EPC to calculate the 1821 * debug return address (DEPC). EPC is restored after the 1822 * calculation. 1823 */ 1824 old_epc = regs->cp0_epc; 1825 old_ra = regs->regs[31]; 1826 regs->cp0_epc = depc; 1827 compute_return_epc(regs); 1828 depc = regs->cp0_epc; 1829 regs->cp0_epc = old_epc; 1830 regs->regs[31] = old_ra; 1831 } else 1832 depc += 4; 1833 write_c0_depc(depc); 1834 1835#if 0 1836 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); 1837 write_c0_debug(debug | 0x100); 1838#endif 1839} 1840 1841/* 1842 * NMI exception handler. 1843 * No lock; only written during early bootup by CPU 0. 1844 */ 1845static RAW_NOTIFIER_HEAD(nmi_chain); 1846 1847int register_nmi_notifier(struct notifier_block *nb) 1848{ 1849 return raw_notifier_chain_register(&nmi_chain, nb); 1850} 1851 1852void __noreturn nmi_exception_handler(struct pt_regs *regs) 1853{ 1854 char str[100]; 1855 1856 raw_notifier_call_chain(&nmi_chain, 0, regs); 1857 bust_spinlocks(1); 1858 snprintf(str, 100, "CPU%d NMI taken, CP0_EPC=%lx\n", 1859 smp_processor_id(), regs->cp0_epc); 1860 regs->cp0_epc = read_c0_errorepc(); 1861 die(str, regs); 1862} 1863 1864#define VECTORSPACING 0x100 /* for EI/VI mode */ 1865 1866unsigned long ebase; 1867unsigned long exception_handlers[32]; 1868unsigned long vi_handlers[64]; 1869 1870void __init *set_except_vector(int n, void *addr) 1871{ 1872 unsigned long handler = (unsigned long) addr; 1873 unsigned long old_handler; 1874 1875#ifdef CONFIG_CPU_MICROMIPS 1876 /* 1877 * Only the TLB handlers are cache aligned with an even 1878 * address. All other handlers are on an odd address and 1879 * require no modification. Otherwise, MIPS32 mode will 1880 * be entered when handling any TLB exceptions. That 1881 * would be bad...since we must stay in microMIPS mode. 1882 */ 1883 if (!(handler & 0x1)) 1884 handler |= 1; 1885#endif 1886 old_handler = xchg(&exception_handlers[n], handler); 1887 1888 if (n == 0 && cpu_has_divec) { 1889#ifdef CONFIG_CPU_MICROMIPS 1890 unsigned long jump_mask = ~((1 << 27) - 1); 1891#else 1892 unsigned long jump_mask = ~((1 << 28) - 1); 1893#endif 1894 u32 *buf = (u32 *)(ebase + 0x200); 1895 unsigned int k0 = 26; 1896 if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { 1897 uasm_i_j(&buf, handler & ~jump_mask); 1898 uasm_i_nop(&buf); 1899 } else { 1900 UASM_i_LA(&buf, k0, handler); 1901 uasm_i_jr(&buf, k0); 1902 uasm_i_nop(&buf); 1903 } 1904 local_flush_icache_range(ebase + 0x200, (unsigned long)buf); 1905 } 1906 return (void *)old_handler; 1907} 1908 1909static void do_default_vi(void) 1910{ 1911 show_regs(get_irq_regs()); 1912 panic("Caught unexpected vectored interrupt."); 1913} 1914 1915static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) 1916{ 1917 unsigned long handler; 1918 unsigned long old_handler = vi_handlers[n]; 1919 int srssets = current_cpu_data.srsets; 1920 u16 *h; 1921 unsigned char *b; 1922 1923 BUG_ON(!cpu_has_veic && !cpu_has_vint); 1924 1925 if (addr == NULL) { 1926 handler = (unsigned long) do_default_vi; 1927 srs = 0; 1928 } else 1929 handler = (unsigned long) addr; 1930 vi_handlers[n] = handler; 1931 1932 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); 1933 1934 if (srs >= srssets) 1935 panic("Shadow register set %d not supported", srs); 1936 1937 if (cpu_has_veic) { 1938 if (board_bind_eic_interrupt) 1939 board_bind_eic_interrupt(n, srs); 1940 } else if (cpu_has_vint) { 1941 /* SRSMap is only defined if shadow sets are implemented */ 1942 if (srssets > 1) 1943 change_c0_srsmap(0xf << n*4, srs << n*4); 1944 } 1945 1946 if (srs == 0) { 1947 /* 1948 * If no shadow set is selected then use the default handler 1949 * that does normal register saving and standard interrupt exit 1950 */ 1951 extern char except_vec_vi, except_vec_vi_lui; 1952 extern char except_vec_vi_ori, except_vec_vi_end; 1953 extern char rollback_except_vec_vi; 1954 char *vec_start = using_rollback_handler() ? 1955 &rollback_except_vec_vi : &except_vec_vi; 1956#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) 1957 const int lui_offset = &except_vec_vi_lui - vec_start + 2; 1958 const int ori_offset = &except_vec_vi_ori - vec_start + 2; 1959#else 1960 const int lui_offset = &except_vec_vi_lui - vec_start; 1961 const int ori_offset = &except_vec_vi_ori - vec_start; 1962#endif 1963 const int handler_len = &except_vec_vi_end - vec_start; 1964 1965 if (handler_len > VECTORSPACING) { 1966 /* 1967 * Sigh... panicing won't help as the console 1968 * is probably not configured :( 1969 */ 1970 panic("VECTORSPACING too small"); 1971 } 1972 1973 set_handler(((unsigned long)b - ebase), vec_start, 1974#ifdef CONFIG_CPU_MICROMIPS 1975 (handler_len - 1)); 1976#else 1977 handler_len); 1978#endif 1979 h = (u16 *)(b + lui_offset); 1980 *h = (handler >> 16) & 0xffff; 1981 h = (u16 *)(b + ori_offset); 1982 *h = (handler & 0xffff); 1983 local_flush_icache_range((unsigned long)b, 1984 (unsigned long)(b+handler_len)); 1985 } 1986 else { 1987 /* 1988 * In other cases jump directly to the interrupt handler. It 1989 * is the handler's responsibility to save registers if required 1990 * (eg hi/lo) and return from the exception using "eret". 1991 */ 1992 u32 insn; 1993 1994 h = (u16 *)b; 1995 /* j handler */ 1996#ifdef CONFIG_CPU_MICROMIPS 1997 insn = 0xd4000000 | (((u32)handler & 0x07ffffff) >> 1); 1998#else 1999 insn = 0x08000000 | (((u32)handler & 0x0fffffff) >> 2); 2000#endif 2001 h[0] = (insn >> 16) & 0xffff; 2002 h[1] = insn & 0xffff; 2003 h[2] = 0; 2004 h[3] = 0; 2005 local_flush_icache_range((unsigned long)b, 2006 (unsigned long)(b+8)); 2007 } 2008 2009 return (void *)old_handler; 2010} 2011 2012void *set_vi_handler(int n, vi_handler_t addr) 2013{ 2014 return set_vi_srs_handler(n, addr, 0); 2015} 2016 2017extern void tlb_init(void); 2018 2019/* 2020 * Timer interrupt 2021 */ 2022int cp0_compare_irq; 2023EXPORT_SYMBOL_GPL(cp0_compare_irq); 2024int cp0_compare_irq_shift; 2025 2026/* 2027 * Performance counter IRQ or -1 if shared with timer 2028 */ 2029int cp0_perfcount_irq; 2030EXPORT_SYMBOL_GPL(cp0_perfcount_irq); 2031 2032/* 2033 * Fast debug channel IRQ or -1 if not present 2034 */ 2035int cp0_fdc_irq; 2036EXPORT_SYMBOL_GPL(cp0_fdc_irq); 2037 2038static int noulri; 2039 2040static int __init ulri_disable(char *s) 2041{ 2042 pr_info("Disabling ulri\n"); 2043 noulri = 1; 2044 2045 return 1; 2046} 2047__setup("noulri", ulri_disable); 2048 2049/* configure STATUS register */ 2050static void configure_status(void) 2051{ 2052 /* 2053 * Disable coprocessors and select 32-bit or 64-bit addressing 2054 * and the 16/32 or 32/32 FPR register model. Reset the BEV 2055 * flag that some firmware may have left set and the TS bit (for 2056 * IP27). Set XX for ISA IV code to work. 2057 */ 2058 unsigned int status_set = ST0_CU0; 2059#ifdef CONFIG_64BIT 2060 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; 2061#endif 2062 if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV) 2063 status_set |= ST0_XX; 2064 if (cpu_has_dsp) 2065 status_set |= ST0_MX; 2066 2067 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, 2068 status_set); 2069} 2070 2071/* configure HWRENA register */ 2072static void configure_hwrena(void) 2073{ 2074 unsigned int hwrena = cpu_hwrena_impl_bits; 2075 2076 if (cpu_has_mips_r2_r6) 2077 hwrena |= 0x0000000f; 2078 2079 if (!noulri && cpu_has_userlocal) 2080 hwrena |= (1 << 29); 2081 2082 if (hwrena) 2083 write_c0_hwrena(hwrena); 2084} 2085 2086static void configure_exception_vector(void) 2087{ 2088 if (cpu_has_veic || cpu_has_vint) { 2089 unsigned long sr = set_c0_status(ST0_BEV); 2090 write_c0_ebase(ebase); 2091 write_c0_status(sr); 2092 /* Setting vector spacing enables EI/VI mode */ 2093 change_c0_intctl(0x3e0, VECTORSPACING); 2094 } 2095 if (cpu_has_divec) { 2096 if (cpu_has_mipsmt) { 2097 unsigned int vpflags = dvpe(); 2098 set_c0_cause(CAUSEF_IV); 2099 evpe(vpflags); 2100 } else 2101 set_c0_cause(CAUSEF_IV); 2102 } 2103} 2104 2105void per_cpu_trap_init(bool is_boot_cpu) 2106{ 2107 unsigned int cpu = smp_processor_id(); 2108 2109 configure_status(); 2110 configure_hwrena(); 2111 2112 configure_exception_vector(); 2113 2114 /* 2115 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: 2116 * 2117 * o read IntCtl.IPTI to determine the timer interrupt 2118 * o read IntCtl.IPPCI to determine the performance counter interrupt 2119 * o read IntCtl.IPFDC to determine the fast debug channel interrupt 2120 */ 2121 if (cpu_has_mips_r2_r6) { 2122 cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; 2123 cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; 2124 cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; 2125 cp0_fdc_irq = (read_c0_intctl() >> INTCTLB_IPFDC) & 7; 2126 if (!cp0_fdc_irq) 2127 cp0_fdc_irq = -1; 2128 2129 } else { 2130 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; 2131 cp0_compare_irq_shift = CP0_LEGACY_PERFCNT_IRQ; 2132 cp0_perfcount_irq = -1; 2133 cp0_fdc_irq = -1; 2134 } 2135 2136 if (!cpu_data[cpu].asid_cache) 2137 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; 2138 2139 atomic_inc(&init_mm.mm_count); 2140 current->active_mm = &init_mm; 2141 BUG_ON(current->mm); 2142 enter_lazy_tlb(&init_mm, current); 2143 2144 /* Boot CPU's cache setup in setup_arch(). */ 2145 if (!is_boot_cpu) 2146 cpu_cache_init(); 2147 tlb_init(); 2148 TLBMISS_HANDLER_SETUP(); 2149} 2150 2151/* Install CPU exception handler */ 2152void set_handler(unsigned long offset, void *addr, unsigned long size) 2153{ 2154#ifdef CONFIG_CPU_MICROMIPS 2155 memcpy((void *)(ebase + offset), ((unsigned char *)addr - 1), size); 2156#else 2157 memcpy((void *)(ebase + offset), addr, size); 2158#endif 2159 local_flush_icache_range(ebase + offset, ebase + offset + size); 2160} 2161 2162static char panic_null_cerr[] = 2163 "Trying to set NULL cache error exception handler"; 2164 2165/* 2166 * Install uncached CPU exception handler. 2167 * This is suitable only for the cache error exception which is the only 2168 * exception handler that is being run uncached. 2169 */ 2170void set_uncached_handler(unsigned long offset, void *addr, 2171 unsigned long size) 2172{ 2173 unsigned long uncached_ebase = CKSEG1ADDR(ebase); 2174 2175 if (!addr) 2176 panic(panic_null_cerr); 2177 2178 memcpy((void *)(uncached_ebase + offset), addr, size); 2179} 2180 2181static int __initdata rdhwr_noopt; 2182static int __init set_rdhwr_noopt(char *str) 2183{ 2184 rdhwr_noopt = 1; 2185 return 1; 2186} 2187 2188__setup("rdhwr_noopt", set_rdhwr_noopt); 2189 2190void __init trap_init(void) 2191{ 2192 extern char except_vec3_generic; 2193 extern char except_vec4; 2194 extern char except_vec3_r4000; 2195 unsigned long i; 2196 2197 check_wait(); 2198 2199#if defined(CONFIG_KGDB) 2200 if (kgdb_early_setup) 2201 return; /* Already done */ 2202#endif 2203 2204 if (cpu_has_veic || cpu_has_vint) { 2205 unsigned long size = 0x200 + VECTORSPACING*64; 2206 ebase = (unsigned long) 2207 __alloc_bootmem(size, 1 << fls(size), 0); 2208 } else { 2209#ifdef CONFIG_KVM_GUEST 2210#define KVM_GUEST_KSEG0 0x40000000 2211 ebase = KVM_GUEST_KSEG0; 2212#else 2213 ebase = CKSEG0; 2214#endif 2215 if (cpu_has_mips_r2_r6) 2216 ebase += (read_c0_ebase() & 0x3ffff000); 2217 } 2218 2219 if (cpu_has_mmips) { 2220 unsigned int config3 = read_c0_config3(); 2221 2222 if (IS_ENABLED(CONFIG_CPU_MICROMIPS)) 2223 write_c0_config3(config3 | MIPS_CONF3_ISA_OE); 2224 else 2225 write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE); 2226 } 2227 2228 if (board_ebase_setup) 2229 board_ebase_setup(); 2230 per_cpu_trap_init(true); 2231 2232 /* 2233 * Copy the generic exception handlers to their final destination. 2234 * This will be overriden later as suitable for a particular 2235 * configuration. 2236 */ 2237 set_handler(0x180, &except_vec3_generic, 0x80); 2238 2239 /* 2240 * Setup default vectors 2241 */ 2242 for (i = 0; i <= 31; i++) 2243 set_except_vector(i, handle_reserved); 2244 2245 /* 2246 * Copy the EJTAG debug exception vector handler code to it's final 2247 * destination. 2248 */ 2249 if (cpu_has_ejtag && board_ejtag_handler_setup) 2250 board_ejtag_handler_setup(); 2251 2252 /* 2253 * Only some CPUs have the watch exceptions. 2254 */ 2255 if (cpu_has_watch) 2256 set_except_vector(23, handle_watch); 2257 2258 /* 2259 * Initialise interrupt handlers 2260 */ 2261 if (cpu_has_veic || cpu_has_vint) { 2262 int nvec = cpu_has_veic ? 64 : 8; 2263 for (i = 0; i < nvec; i++) 2264 set_vi_handler(i, NULL); 2265 } 2266 else if (cpu_has_divec) 2267 set_handler(0x200, &except_vec4, 0x8); 2268 2269 /* 2270 * Some CPUs can enable/disable for cache parity detection, but does 2271 * it different ways. 2272 */ 2273 parity_protection_init(); 2274 2275 /* 2276 * The Data Bus Errors / Instruction Bus Errors are signaled 2277 * by external hardware. Therefore these two exceptions 2278 * may have board specific handlers. 2279 */ 2280 if (board_be_init) 2281 board_be_init(); 2282 2283 set_except_vector(0, using_rollback_handler() ? rollback_handle_int 2284 : handle_int); 2285 set_except_vector(1, handle_tlbm); 2286 set_except_vector(2, handle_tlbl); 2287 set_except_vector(3, handle_tlbs); 2288 2289 set_except_vector(4, handle_adel); 2290 set_except_vector(5, handle_ades); 2291 2292 set_except_vector(6, handle_ibe); 2293 set_except_vector(7, handle_dbe); 2294 2295 set_except_vector(8, handle_sys); 2296 set_except_vector(9, handle_bp); 2297 set_except_vector(10, rdhwr_noopt ? handle_ri : 2298 (cpu_has_vtag_icache ? 2299 handle_ri_rdhwr_vivt : handle_ri_rdhwr)); 2300 set_except_vector(11, handle_cpu); 2301 set_except_vector(12, handle_ov); 2302 set_except_vector(13, handle_tr); 2303 set_except_vector(14, handle_msa_fpe); 2304 2305 if (current_cpu_type() == CPU_R6000 || 2306 current_cpu_type() == CPU_R6000A) { 2307 /* 2308 * The R6000 is the only R-series CPU that features a machine 2309 * check exception (similar to the R4000 cache error) and 2310 * unaligned ldc1/sdc1 exception. The handlers have not been 2311 * written yet. Well, anyway there is no R6000 machine on the 2312 * current list of targets for Linux/MIPS. 2313 * (Duh, crap, there is someone with a triple R6k machine) 2314 */ 2315 //set_except_vector(14, handle_mc); 2316 //set_except_vector(15, handle_ndc); 2317 } 2318 2319 2320 if (board_nmi_handler_setup) 2321 board_nmi_handler_setup(); 2322 2323 if (cpu_has_fpu && !cpu_has_nofpuex) 2324 set_except_vector(15, handle_fpe); 2325 2326 set_except_vector(16, handle_ftlb); 2327 2328 if (cpu_has_rixiex) { 2329 set_except_vector(19, tlb_do_page_fault_0); 2330 set_except_vector(20, tlb_do_page_fault_0); 2331 } 2332 2333 set_except_vector(21, handle_msa); 2334 set_except_vector(22, handle_mdmx); 2335 2336 if (cpu_has_mcheck) 2337 set_except_vector(24, handle_mcheck); 2338 2339 if (cpu_has_mipsmt) 2340 set_except_vector(25, handle_mt); 2341 2342 set_except_vector(26, handle_dsp); 2343 2344 if (board_cache_error_setup) 2345 board_cache_error_setup(); 2346 2347 if (cpu_has_vce) 2348 /* Special exception: R4[04]00 uses also the divec space. */ 2349 set_handler(0x180, &except_vec3_r4000, 0x100); 2350 else if (cpu_has_4kex) 2351 set_handler(0x180, &except_vec3_generic, 0x80); 2352 else 2353 set_handler(0x080, &except_vec3_generic, 0x80); 2354 2355 local_flush_icache_range(ebase, ebase + 0x400); 2356 2357 sort_extable(__start___dbe_table, __stop___dbe_table); 2358 2359 cu2_notifier(default_cu2_call, 0x80000000); /* Run last */ 2360} 2361 2362static int trap_pm_notifier(struct notifier_block *self, unsigned long cmd, 2363 void *v) 2364{ 2365 switch (cmd) { 2366 case CPU_PM_ENTER_FAILED: 2367 case CPU_PM_EXIT: 2368 configure_status(); 2369 configure_hwrena(); 2370 configure_exception_vector(); 2371 2372 /* Restore register with CPU number for TLB handlers */ 2373 TLBMISS_HANDLER_RESTORE(); 2374 2375 break; 2376 } 2377 2378 return NOTIFY_OK; 2379} 2380 2381static struct notifier_block trap_pm_notifier_block = { 2382 .notifier_call = trap_pm_notifier, 2383}; 2384 2385static int __init trap_pm_init(void) 2386{ 2387 return cpu_pm_register_notifier(&trap_pm_notifier_block); 2388} 2389arch_initcall(trap_pm_init); 2390