Searched refs:REG_READ (Results 1 - 131 of 131) sorted by relevance

/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/
H A Dreg_rdwr.h8 #ifndef REG_READ
9 #define REG_READ(type, addr) (*((volatile type *) (addr))) macro
H A Dirq_nmi_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dstrcop_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Drt_trace_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Data_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_slave_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_bp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
278 REG_READ( reg_##scope##_##reg, \
290 REG_READ( reg_##scope##_##reg, \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_core_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Deth_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dextmem_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dser_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dsser_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_dma_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Ddma_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/drivers/gpu/drm/gma500/
H A Dcdv_device.c47 REG_READ(vga_reg); cdv_disable_vga()
62 if (REG_READ(SDVOB) & SDVO_DETECTED) { cdv_output_init()
64 if (REG_READ(DP_B) & DP_DETECTED) cdv_output_init()
68 if (REG_READ(SDVOC) & SDVO_DETECTED) { cdv_output_init()
70 if (REG_READ(DP_C) & DP_DETECTED) cdv_output_init()
86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; cdv_backlight_combination_mode()
91 u32 max = REG_READ(BLC_PWM_CTL); cdv_get_max_backlight()
109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; cdv_get_brightness()
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; cdv_set_brightness()
274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D); cdv_save_display_registers()
275 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D); cdv_save_display_registers()
277 regs->cdv.saveDSPARB = REG_READ(DSPARB); cdv_save_display_registers()
278 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1); cdv_save_display_registers()
279 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2); cdv_save_display_registers()
280 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3); cdv_save_display_registers()
281 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4); cdv_save_display_registers()
282 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5); cdv_save_display_registers()
283 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6); cdv_save_display_registers()
285 regs->cdv.saveADPA = REG_READ(ADPA); cdv_save_display_registers()
287 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL); cdv_save_display_registers()
288 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); cdv_save_display_registers()
289 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); cdv_save_display_registers()
290 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); cdv_save_display_registers()
291 regs->cdv.saveLVDS = REG_READ(LVDS); cdv_save_display_registers()
293 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL); cdv_save_display_registers()
295 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS); cdv_save_display_registers()
296 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS); cdv_save_display_registers()
297 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE); cdv_save_display_registers()
299 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL); cdv_save_display_registers()
301 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R); cdv_save_display_registers()
302 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R); cdv_save_display_registers()
334 temp = REG_READ(DPLL_A); cdv_restore_display_registers()
337 REG_READ(DPLL_A); cdv_restore_display_registers()
340 temp = REG_READ(DPLL_B); cdv_restore_display_registers()
343 REG_READ(DPLL_B); cdv_restore_display_registers()
447 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); cdv_hotplug_event()
454 u32 hotplug = REG_READ(PORT_HOTPLUG_EN); cdv_hotplug_enable()
460 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); cdv_hotplug_enable()
H A Dgma_display.c88 dspcntr = REG_READ(map->cntr); gma_pipe_set_base()
120 REG_READ(map->base); gma_pipe_set_base()
123 REG_READ(map->base); gma_pipe_set_base()
125 REG_READ(map->surf); gma_pipe_set_base()
226 temp = REG_READ(map->dpll); gma_crtc_dpms()
229 REG_READ(map->dpll); gma_crtc_dpms()
233 REG_READ(map->dpll); gma_crtc_dpms()
237 REG_READ(map->dpll); gma_crtc_dpms()
243 temp = REG_READ(map->cntr); gma_crtc_dpms()
248 REG_WRITE(map->base, REG_READ(map->base)); gma_crtc_dpms()
254 temp = REG_READ(map->conf); gma_crtc_dpms()
258 temp = REG_READ(map->status); gma_crtc_dpms()
262 REG_READ(map->status); gma_crtc_dpms()
290 temp = REG_READ(map->cntr); gma_crtc_dpms()
295 REG_WRITE(map->base, REG_READ(map->base)); gma_crtc_dpms()
296 REG_READ(map->base); gma_crtc_dpms()
300 temp = REG_READ(map->conf); gma_crtc_dpms()
303 REG_READ(map->conf); gma_crtc_dpms()
312 temp = REG_READ(map->dpll); gma_crtc_dpms()
315 REG_READ(map->dpll); gma_crtc_dpms()
570 crtc_state->saveDSPCNTR = REG_READ(map->cntr); gma_crtc_save()
571 crtc_state->savePIPECONF = REG_READ(map->conf); gma_crtc_save()
572 crtc_state->savePIPESRC = REG_READ(map->src); gma_crtc_save()
573 crtc_state->saveFP0 = REG_READ(map->fp0); gma_crtc_save()
574 crtc_state->saveFP1 = REG_READ(map->fp1); gma_crtc_save()
575 crtc_state->saveDPLL = REG_READ(map->dpll); gma_crtc_save()
576 crtc_state->saveHTOTAL = REG_READ(map->htotal); gma_crtc_save()
577 crtc_state->saveHBLANK = REG_READ(map->hblank); gma_crtc_save()
578 crtc_state->saveHSYNC = REG_READ(map->hsync); gma_crtc_save()
579 crtc_state->saveVTOTAL = REG_READ(map->vtotal); gma_crtc_save()
580 crtc_state->saveVBLANK = REG_READ(map->vblank); gma_crtc_save()
581 crtc_state->saveVSYNC = REG_READ(map->vsync); gma_crtc_save()
582 crtc_state->saveDSPSTRIDE = REG_READ(map->stride); gma_crtc_save()
585 crtc_state->saveDSPSIZE = REG_READ(map->size); gma_crtc_save()
586 crtc_state->saveDSPPOS = REG_READ(map->pos); gma_crtc_save()
588 crtc_state->saveDSPBASE = REG_READ(map->base); gma_crtc_save()
592 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2)); gma_crtc_save()
616 REG_READ(map->dpll); gma_crtc_restore()
621 REG_READ(map->fp0); gma_crtc_restore()
624 REG_READ(map->fp1); gma_crtc_restore()
627 REG_READ(map->dpll); gma_crtc_restore()
741 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) { gma_find_best_pll()
748 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) == gma_find_best_pll()
H A Dpsb_lid.c40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); psb_lid_timer_func()
42 pp_status = REG_READ(PP_STATUS); psb_lid_timer_func()
46 if (REG_READ(PP_STATUS) & PP_ON) { psb_lid_timer_func()
56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON); psb_lid_timer_func()
58 pp_status = REG_READ(PP_STATUS); psb_lid_timer_func()
H A Dmdfld_intel_display.c73 temp = REG_READ(map->conf); mdfldWaitForPipeDisable()
101 temp = REG_READ(map->conf); mdfldWaitForPipeEnable()
115 pfit_control = REG_READ(PFIT_CONTROL); psb_intel_panel_fitter_pipe()
133 dspcntr = REG_READ(dspcntr_reg); mdfld__intel_plane_set_alpha()
202 dspcntr = REG_READ(map->cntr); mdfld__intel_pipe_set_base()
225 REG_READ(map->linoff); mdfld__intel_pipe_set_base()
227 REG_READ(map->surf); mdfld__intel_pipe_set_base()
252 temp = REG_READ(map->cntr); mdfld_disable_crtc()
257 REG_WRITE(map->base, REG_READ(map->base)); mdfld_disable_crtc()
258 REG_READ(map->base); mdfld_disable_crtc()
264 temp = REG_READ(map->conf); mdfld_disable_crtc()
269 REG_READ(map->conf); mdfld_disable_crtc()
275 temp = REG_READ(map->dpll); mdfld_disable_crtc()
278 !((REG_READ(PIPEACONF) | REG_READ(PIPECCONF)) mdfld_disable_crtc()
282 REG_READ(map->dpll); mdfld_disable_crtc()
331 temp = REG_READ(map->dpll); mdfld_crtc_dpms()
344 REG_READ(map->dpll); mdfld_crtc_dpms()
349 REG_READ(map->dpll); mdfld_crtc_dpms()
357 !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) { mdfld_crtc_dpms()
364 temp = REG_READ(map->cntr); mdfld_crtc_dpms()
369 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
373 temp = REG_READ(map->conf); mdfld_crtc_dpms()
384 REG_WRITE(map->status, REG_READ(map->status)); mdfld_crtc_dpms()
386 if (PIPE_VBLANK_STATUS & REG_READ(map->status)) mdfld_crtc_dpms()
391 temp = REG_READ(map->cntr); mdfld_crtc_dpms()
394 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
398 temp = REG_READ(map->conf); mdfld_crtc_dpms()
404 REG_WRITE(0xb004, REG_READ(0xb004)); mdfld_crtc_dpms()
407 temp = REG_READ(map->cntr); mdfld_crtc_dpms()
410 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
414 temp = REG_READ(map->conf); mdfld_crtc_dpms()
440 temp = REG_READ(map->cntr); mdfld_crtc_dpms()
445 REG_WRITE(map->base, REG_READ(map->base)); mdfld_crtc_dpms()
446 REG_READ(map->base); mdfld_crtc_dpms()
450 temp = REG_READ(map->conf); mdfld_crtc_dpms()
455 REG_READ(map->conf); mdfld_crtc_dpms()
461 temp = REG_READ(map->dpll); mdfld_crtc_dpms()
463 if ((pipe != 1 && !((REG_READ(PIPEACONF) mdfld_crtc_dpms()
464 | REG_READ(PIPECCONF)) & PIPEACONF_ENABLE)) mdfld_crtc_dpms()
468 REG_READ(map->dpll); mdfld_crtc_dpms()
858 dev_priv->pipeconf[pipe] = PIPEACONF_ENABLE; /* FIXME_JLIU7 REG_READ(pipeconf_reg); */ mdfld_crtc_mode_set()
861 dev_priv->dspcntr[pipe] = REG_READ(map->cntr); mdfld_crtc_mode_set()
928 dpll = REG_READ(map->dpll); mdfld_crtc_mode_set()
933 REG_READ(map->dpll); mdfld_crtc_mode_set()
999 REG_READ(map->dpll); mdfld_crtc_mode_set()
1003 !(REG_READ(map->conf) & PIPECONF_DSIPLL_LOCK)) { mdfld_crtc_mode_set()
1014 REG_READ(map->conf); mdfld_crtc_mode_set()
H A Doaktrail_hdmi.c291 dpll = REG_READ(DPLL_CTRL); oaktrail_crtc_hdmi_mode_set()
307 dpll = REG_READ(DPLL_CTRL); oaktrail_crtc_hdmi_mode_set()
355 dspcntr = REG_READ(dspcntr_reg); oaktrail_crtc_hdmi_mode_set()
361 pipeconf = REG_READ(pipeconf_reg); oaktrail_crtc_hdmi_mode_set()
365 REG_READ(pipeconf_reg); oaktrail_crtc_hdmi_mode_set()
368 REG_READ(PCH_PIPEBCONF); oaktrail_crtc_hdmi_mode_set()
391 temp = REG_READ(DSPBCNTR); oaktrail_crtc_hdmi_dpms()
394 REG_READ(DSPBCNTR); oaktrail_crtc_hdmi_dpms()
396 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); oaktrail_crtc_hdmi_dpms()
397 REG_READ(DSPBSURF); oaktrail_crtc_hdmi_dpms()
401 temp = REG_READ(PIPEBCONF); oaktrail_crtc_hdmi_dpms()
404 REG_READ(PIPEBCONF); oaktrail_crtc_hdmi_dpms()
408 temp = REG_READ(PCH_PIPEBCONF); oaktrail_crtc_hdmi_dpms()
411 REG_READ(PCH_PIPEBCONF); oaktrail_crtc_hdmi_dpms()
418 temp = REG_READ(DPLL_CTRL); oaktrail_crtc_hdmi_dpms()
432 temp = REG_READ(DPLL_CTRL); oaktrail_crtc_hdmi_dpms()
435 temp = REG_READ(DPLL_CLK_ENABLE); oaktrail_crtc_hdmi_dpms()
437 REG_READ(DPLL_CLK_ENABLE); oaktrail_crtc_hdmi_dpms()
443 temp = REG_READ(PIPEBCONF); oaktrail_crtc_hdmi_dpms()
446 REG_READ(PIPEBCONF); oaktrail_crtc_hdmi_dpms()
450 temp = REG_READ(PCH_PIPEBCONF); oaktrail_crtc_hdmi_dpms()
453 REG_READ(PCH_PIPEBCONF); oaktrail_crtc_hdmi_dpms()
459 temp = REG_READ(DSPBCNTR); oaktrail_crtc_hdmi_dpms()
463 REG_WRITE(DSPBSURF, REG_READ(DSPBSURF)); oaktrail_crtc_hdmi_dpms()
464 REG_READ(DSPBSURF); oaktrail_crtc_hdmi_dpms()
H A Dpsb_intel_display.c93 pfit_control = REG_READ(PFIT_CONTROL); psb_intel_panel_fitter_pipe()
202 pipeconf = REG_READ(map->conf); psb_intel_crtc_mode_set()
226 REG_READ(map->dpll); psb_intel_crtc_mode_set()
235 u32 lvds = REG_READ(LVDS); psb_intel_crtc_mode_set()
256 REG_READ(LVDS); psb_intel_crtc_mode_set()
261 REG_READ(map->dpll); psb_intel_crtc_mode_set()
268 REG_READ(map->dpll); psb_intel_crtc_mode_set()
293 REG_READ(map->conf); psb_intel_crtc_mode_set()
322 dpll = REG_READ(map->dpll); psb_intel_crtc_clock_get()
324 fp = REG_READ(map->fp0); psb_intel_crtc_clock_get()
326 fp = REG_READ(map->fp1); psb_intel_crtc_clock_get()
327 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); psb_intel_crtc_clock_get()
399 htot = REG_READ(map->htotal); psb_intel_crtc_mode_get()
400 hsync = REG_READ(map->hsync); psb_intel_crtc_mode_get()
401 vtot = REG_READ(map->vtotal); psb_intel_crtc_mode_get()
402 vsync = REG_READ(map->vsync); psb_intel_crtc_mode_get()
H A Dpsb_intel_lvds.c77 ret = REG_READ(BLC_PWM_CTL); psb_intel_lvds_get_max_backlight()
89 REG_READ(BLC_PWM_CTL), dev_priv->regs.saveBLC_PWM_CTL); psb_intel_lvds_get_max_backlight()
201 blc_pwm_ctl = REG_READ(BLC_PWM_CTL); psb_intel_lvds_set_backlight()
232 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | psb_intel_lvds_set_power()
235 pp_status = REG_READ(PP_STATUS); psb_intel_lvds_set_power()
243 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & psb_intel_lvds_set_power()
246 pp_status = REG_READ(PP_STATUS); psb_intel_lvds_set_power()
274 lvds_priv->savePP_ON = REG_READ(LVDSPP_ON); psb_intel_lvds_save()
275 lvds_priv->savePP_OFF = REG_READ(LVDSPP_OFF); psb_intel_lvds_save()
276 lvds_priv->saveLVDS = REG_READ(LVDS); psb_intel_lvds_save()
277 lvds_priv->savePP_CONTROL = REG_READ(PP_CONTROL); psb_intel_lvds_save()
278 lvds_priv->savePP_CYCLE = REG_READ(PP_CYCLE); psb_intel_lvds_save()
279 /*lvds_priv->savePP_DIVISOR = REG_READ(PP_DIVISOR);*/ psb_intel_lvds_save()
280 lvds_priv->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); psb_intel_lvds_save()
281 lvds_priv->savePFIT_CONTROL = REG_READ(PFIT_CONTROL); psb_intel_lvds_save()
282 lvds_priv->savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS); psb_intel_lvds_save()
332 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | psb_intel_lvds_restore()
335 pp_status = REG_READ(PP_STATUS); psb_intel_lvds_restore()
338 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & psb_intel_lvds_restore()
341 pp_status = REG_READ(PP_STATUS); psb_intel_lvds_restore()
447 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); psb_intel_lvds_prepare()
806 lvds = REG_READ(LVDS); psb_intel_lvds_init()
H A Dcdv_intel_display.c143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_read()
155 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_read()
161 *val = REG_READ(SB_DATA); cdv_sb_read()
178 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_write()
191 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); cdv_sb_write()
212 REG_READ(DPIO_CFG); cdv_sb_reset()
479 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) { cdv_disable_sr()
482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); cdv_disable_sr()
483 REG_READ(FW_BLC_SELF); cdv_disable_sr()
491 REG_READ(OV_OVADD); cdv_disable_sr()
507 fw = REG_READ(DSPFW1); cdv_update_wm()
514 fw = REG_READ(DSPFW2); cdv_update_wm()
543 REG_READ(FW_BLC_SELF); cdv_update_wm()
570 pfit_control = REG_READ(PFIT_CONTROL); cdv_intel_panel_fitter_pipe()
698 pipeconf = REG_READ(map->conf); cdv_intel_crtc_mode_set()
718 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP) cdv_intel_crtc_mode_set()
737 REG_READ(map->dpll); cdv_intel_crtc_mode_set()
749 u32 lvds = REG_READ(LVDS); cdv_intel_crtc_mode_set()
769 REG_READ(LVDS); cdv_intel_crtc_mode_set()
782 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); cdv_intel_crtc_mode_set()
783 REG_READ(map->dpll); cdv_intel_crtc_mode_set()
787 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { cdv_intel_crtc_mode_set()
818 REG_READ(map->conf); cdv_intel_crtc_mode_set()
863 dpll = REG_READ(map->dpll); cdv_intel_crtc_clock_get()
865 fp = REG_READ(map->fp0); cdv_intel_crtc_clock_get()
867 fp = REG_READ(map->fp1); cdv_intel_crtc_clock_get()
868 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN); cdv_intel_crtc_clock_get()
943 htot = REG_READ(map->htotal); cdv_intel_crtc_mode_get()
944 hsync = REG_READ(map->hsync); cdv_intel_crtc_mode_get()
945 vtot = REG_READ(map->vtotal); cdv_intel_crtc_mode_get()
946 vsync = REG_READ(map->vsync); cdv_intel_crtc_mode_get()
H A Dintel_i2c.c39 val = REG_READ(chan->reg); get_clock()
49 val = REG_READ(chan->reg); get_data()
61 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | set_clock()
81 REG_READ(chan->reg) & (GPIO_DATA_PULLUP_DISABLE | set_data()
H A Dcdv_intel_dp.c391 pp = REG_READ(PP_CONTROL); cdv_intel_edp_panel_vdd_on()
395 REG_READ(PP_CONTROL); cdv_intel_edp_panel_vdd_on()
405 pp = REG_READ(PP_CONTROL); cdv_intel_edp_panel_vdd_off()
409 REG_READ(PP_CONTROL); cdv_intel_edp_panel_vdd_off()
424 pp = REG_READ(PP_CONTROL); cdv_intel_edp_panel_on()
429 REG_READ(PP_CONTROL); cdv_intel_edp_panel_on()
431 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { cdv_intel_edp_panel_on()
432 DRM_DEBUG_KMS("Error in Powering up eDP panel, status %x\n", REG_READ(PP_STATUS)); cdv_intel_edp_panel_on()
449 pp = REG_READ(PP_CONTROL); cdv_intel_edp_panel_off()
462 REG_READ(PP_CONTROL); cdv_intel_edp_panel_off()
463 DRM_DEBUG_KMS("PP_STATUS %x\n", REG_READ(PP_STATUS)); cdv_intel_edp_panel_off()
465 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { cdv_intel_edp_panel_off()
486 pp = REG_READ(PP_CONTROL); cdv_intel_edp_backlight_on()
502 pp = REG_READ(PP_CONTROL); cdv_intel_edp_backlight_off()
596 if (REG_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) { cdv_intel_dp_aux_ch()
598 REG_READ(ch_ctl)); cdv_intel_dp_aux_ch()
620 status = REG_READ(ch_ctl); cdv_intel_dp_aux_ch()
663 unpack_aux(REG_READ(ch_data + i), cdv_intel_dp_aux_ch()
1175 uint32_t dp_reg = REG_READ(intel_dp->output_reg); cdv_intel_dp_dpms()
1395 REG_READ(intel_dp->output_reg); cdv_intel_dp_set_link_train()
1517 REG_READ(intel_dp->output_reg); cdv_intel_dp_start_link_train()
1673 REG_READ(intel_dp->output_reg); cdv_intel_dp_complete_link_train()
1685 if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0) cdv_intel_dp_link_down()
1695 REG_READ(intel_dp->output_reg); cdv_intel_dp_link_down()
1700 REG_READ(intel_dp->output_reg); cdv_intel_dp_link_down()
1982 reg_value = REG_READ(DSPCLK_GATE_D); cdv_disable_intel_clock_gating()
2071 pp_on = REG_READ(PP_CONTROL); cdv_intel_dp_init()
2077 pwm_ctrl = REG_READ(BLC_PWM_CTL2); cdv_intel_dp_init()
2081 pp_on = REG_READ(PP_ON_DELAYS); cdv_intel_dp_init()
2082 pp_off = REG_READ(PP_OFF_DELAYS); cdv_intel_dp_init()
2083 pp_div = REG_READ(PP_DIVISOR); cdv_intel_dp_init()
H A Doaktrail_lvds.c56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | oaktrail_lvds_set_power()
59 pp_status = REG_READ(PP_STATUS); oaktrail_lvds_set_power()
67 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & oaktrail_lvds_set_power()
70 pp_status = REG_READ(PP_STATUS); oaktrail_lvds_set_power()
112 lvds_port = (REG_READ(LVDS) & oaktrail_lvds_mode_set()
174 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); oaktrail_lvds_prepare()
187 ret = ((REG_READ(BLC_PWM_CTL) & oaktrail_lvds_get_max_backlight()
H A Dcdv_intel_crt.c45 temp = REG_READ(reg); cdv_intel_crt_dpms()
108 dpll_md = REG_READ(dpll_md_reg); cdv_intel_crt_mode_set()
148 orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN); cdv_intel_crt_detect_hotplug()
162 if (!(REG_READ(PORT_HOTPLUG_EN) & cdv_intel_crt_detect_hotplug()
169 if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) != cdv_intel_crt_detect_hotplug()
H A Dcdv_intel_hdmi.c89 REG_READ(hdmi_priv->hdmi_reg); cdv_hdmi_mode_set()
99 hdmib = REG_READ(hdmi_priv->hdmi_reg); cdv_hdmi_dpms()
105 REG_READ(hdmi_priv->hdmi_reg); cdv_hdmi_dpms()
114 hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg); cdv_hdmi_save()
124 REG_READ(hdmi_priv->hdmi_reg); cdv_hdmi_restore()
H A Dmdfld_dsi_dpi.c46 (REG_READ(gen_fifo_stat_reg) & DSI_FIFO_GEN_HS_DATA_FULL)) { mdfld_wait_for_HS_DATA_FIFO()
63 while ((timeout < 20000) && (REG_READ(gen_fifo_stat_reg) mdfld_wait_for_HS_CTRL_FIFO()
80 while ((timeout < 20000) && ((REG_READ(gen_fifo_stat_reg) & mdfld_wait_for_DPI_CTRL_FIFO()
98 while ((timeout < 20000) && (!(REG_READ(intr_stat_reg) mdfld_wait_for_SPL_PKG_SENT()
147 REG_READ(MIPI_DEVICE_READY_REG(pipe)); /* posted write? */ dsi_set_pipe_plane_enable_state()
151 REG_READ(MIPI_PORT_CONTROL(pipe)); /* posted write? */ dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); dsi_set_pipe_plane_enable_state()
158 REG_READ(dspbase_reg); dsi_set_pipe_plane_enable_state()
573 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) mdfld_dsi_dpi_turn_on()
583 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) mdfld_dsi_dpi_turn_on()
612 if (REG_READ(MIPI_INTR_STAT_REG(pipe)) & DSI_INTR_STATE_SPL_PKG_SENT) mdfld_dsi_dpi_shut_down()
616 if (REG_READ(MIPI_DPI_CONTROL_REG(pipe)) == DSI_DPI_CTRL_HS_SHUTDOWN) mdfld_dsi_dpi_shut_down()
656 REG_READ(MIPI_PORT_CONTROL(pipe)) | BIT(31)); mdfld_dsi_dpi_set_power()
657 REG_READ(MIPI_PORT_CONTROL(pipe)); mdfld_dsi_dpi_set_power()
673 REG_READ(MIPI_PORT_CONTROL(pipe)) & ~BIT(31)); mdfld_dsi_dpi_set_power()
674 REG_READ(MIPI_PORT_CONTROL(pipe)); mdfld_dsi_dpi_set_power()
886 REG_READ(MIPI_PORT_CONTROL(pipe)); mdfld_dsi_dpi_mode_set()
904 REG_READ(pipeconf_reg); mdfld_dsi_dpi_mode_set()
908 REG_READ(dspcntr_reg); mdfld_dsi_dpi_mode_set()
H A Dmdfld_dsi_pkg_sender.c88 if ((mask & REG_READ(gen_fifo_stat_reg)) == mask) wait_for_gen_fifo_empty()
92 DRM_ERROR("fifo is NOT empty 0x%08x\n", REG_READ(gen_fifo_stat_reg)); wait_for_gen_fifo_empty()
186 if (mask & REG_READ(intr_stat_reg)) handle_dsi_error()
201 intr_stat = REG_READ(intr_stat_reg); dsi_error_handler()
543 if ((REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) __read_panel_data()
550 while (retry && !(REG_READ(sender->mipi_intr_stat_reg) & BIT(29))) { __read_panel_data()
569 *(data_out + i) = REG_READ(gen_data_reg); __read_panel_data()
657 REG_READ(MIPI_PORT_CONTROL(pipe)); mdfld_dsi_pkg_sender_init()
H A Doaktrail_crtc.c308 REG_READ(map->base), i); oaktrail_crtc_dpms()
343 REG_WRITE(DSPCHICKENBIT, REG_READ(DSPCHICKENBIT) | 0xc040); oaktrail_crtc_dpms()
356 pfit_control = REG_READ(PFIT_CONTROL); oaktrail_panel_fitter_pipe()
492 pipeconf = REG_READ(map->conf); oaktrail_crtc_mode_set()
495 dspcntr = REG_READ(map->cntr); oaktrail_crtc_mode_set()
624 dspcntr = REG_READ(map->cntr); oaktrail_pipe_set_base()
649 REG_READ(map->base); oaktrail_pipe_set_base()
651 REG_READ(map->surf); oaktrail_pipe_set_base()
H A Dpsb_irq.c299 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT)); psb_irq_handler()
526 reg_val = REG_READ(pipeconf_reg); psb_enable_vblank()
585 reg_val = REG_READ(pipeconf_reg); mdfld_enable_te()
654 reg_val = REG_READ(pipeconf_reg); psb_get_vblank_counter()
668 high1 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> psb_get_vblank_counter()
670 low = ((REG_READ(low_frame) & PIPE_FRAME_LOW_MASK) >> psb_get_vblank_counter()
672 high2 = ((REG_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >> psb_get_vblank_counter()
H A Dcdv_intel_lvds.c75 retval = ((REG_READ(BLC_PWM_CTL) & cdv_intel_lvds_get_max_backlight()
183 REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; cdv_intel_lvds_set_backlight()
209 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | cdv_intel_lvds_set_power()
212 pp_status = REG_READ(PP_STATUS); cdv_intel_lvds_set_power()
220 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & cdv_intel_lvds_set_power()
223 pp_status = REG_READ(PP_STATUS); cdv_intel_lvds_set_power()
331 mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL); cdv_intel_lvds_prepare()
741 lvds = REG_READ(LVDS); cdv_intel_lvds_init()
766 pwm = REG_READ(BLC_PWM_CTL2); cdv_intel_lvds_init()
H A Dmdfld_device.c383 temp = REG_READ(mipi_reg); mdfld_restore_display_registers()
390 temp = REG_READ(device_ready_reg); mdfld_restore_display_registers()
397 temp = REG_READ(device_ready_reg); mdfld_restore_display_registers()
H A Doaktrail_device.c78 max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16; oaktrail_set_brightness()
94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); oaktrail_set_brightness()
135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); device_backlight_init()
H A Dmdfld_dsi_output.h51 REG_WRITE(reg, FLD_MOD(REG_READ(reg), val, start, end))
58 while (FLD_GET(REG_READ(reg), start, end) != val) { REGISTER_FLD_WAIT()
H A Dpsb_drv.h835 #define REG_READ(reg) REGISTER_READ(dev, (reg)) macro
847 val = REG_READ(reg); REGISTER_READ_WITH_AUX()
H A Dintel_gmbus.c91 val = REG_READ(DSPCLK_GATE_D); intel_i2c_quirk_set()
H A Dmdfld_dsi_output.c75 if ((REG_READ(gen_fifo_stat_reg) & fifo_stat) == fifo_stat) mdfld_dsi_gen_fifo_ready()
H A Dpsb_intel_sdvo.c1069 sdvox = REG_READ(psb_intel_sdvo->sdvo_reg); psb_intel_sdvo_mode_set()
1123 temp = REG_READ(psb_intel_sdvo->sdvo_reg); psb_intel_sdvo_dpms()
1136 temp = REG_READ(psb_intel_sdvo->sdvo_reg); psb_intel_sdvo_dpms()
1811 sdvo->saveSDVO = REG_READ(sdvo->sdvo_reg); psb_intel_sdvo_save()
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/
H A Diop_version_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_in_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_out_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_spu_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cfg_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cpu_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_mpu_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/drivers/net/wireless/ath/ath9k/
H A Dar9002_calib.c87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) & ar9002_hw_per_calibration()
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); ar9002_hw_iqcal_collect()
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); ar9002_hw_iqcal_collect()
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); ar9002_hw_iqcal_collect()
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); ar9002_hw_adc_gaincal_collect()
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); ar9002_hw_adc_gaincal_collect()
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); ar9002_hw_adc_gaincal_collect()
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); ar9002_hw_adc_gaincal_collect()
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); ar9002_hw_adc_dccal_collect()
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); ar9002_hw_adc_dccal_collect()
169 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); ar9002_hw_adc_dccal_collect()
171 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); ar9002_hw_adc_dccal_collect()
299 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); ar9002_hw_adc_gaincal_calibrate()
310 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | ar9002_hw_adc_gaincal_calibrate()
354 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i)); ar9002_hw_adc_dccal_calibrate()
364 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) | ar9002_hw_adc_dccal_calibrate()
373 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); ar9287_hw_olc_temp_compensation()
403 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4); ar9280_hw_olc_temp_compensation()
491 regVal = REG_READ(ah, AR9285_AN_RF2G6); ar9271_hw_pa_cal()
495 /* regVal = REG_READ(ah, 0x7834); */ ar9271_hw_pa_cal()
497 regVal |= (MS(REG_READ(ah, AR9285_AN_RF2G9), ar9271_hw_pa_cal()
556 regList[i][1] = REG_READ(ah, regList[i][0]); ar9285_hw_pa_cal()
558 regVal = REG_READ(ah, 0x7834); ar9285_hw_pa_cal()
561 regVal = REG_READ(ah, 0x9808); ar9285_hw_pa_cal()
577 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP); ar9285_hw_pa_cal()
586 regVal = REG_READ(ah, 0x7834); ar9285_hw_pa_cal()
590 regVal = REG_READ(ah, 0x7834); ar9285_hw_pa_cal()
592 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9); ar9285_hw_pa_cal()
599 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9); ar9285_hw_pa_cal()
601 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS); ar9285_hw_pa_cal()
602 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP); ar9285_hw_pa_cal()
623 regVal = REG_READ(ah, 0x7834); ar9285_hw_pa_cal()
626 regVal = REG_READ(ah, 0x9808); ar9285_hw_pa_cal()
666 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF); ar9002_hw_calibrate()
772 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7), ar9285_hw_clc()
776 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) & ar9285_hw_clc()
785 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) ar9285_hw_clc()
787 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2))) ar9285_hw_clc()
797 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5); ar9285_hw_clc()
834 REG_READ(ah, AR_PHY_AGC_CONTROL) | ar9002_hw_init_cal()
H A Dar9002_mac.c43 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) { ar9002_hw_get_isr()
44 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ar9002_hw_get_isr()
46 isr = REG_READ(ah, AR_ISR); ar9002_hw_get_isr()
50 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & ar9002_hw_get_isr()
59 isr = REG_READ(ah, AR_ISR); ar9002_hw_get_isr()
65 isr2 = REG_READ(ah, AR_ISR_S2); ar9002_hw_get_isr()
88 isr = REG_READ(ah, AR_ISR_RAC); ar9002_hw_get_isr()
109 s0_s = REG_READ(ah, AR_ISR_S0_S); ar9002_hw_get_isr()
110 s1_s = REG_READ(ah, AR_ISR_S1_S); ar9002_hw_get_isr()
112 s0_s = REG_READ(ah, AR_ISR_S0); ar9002_hw_get_isr()
114 s1_s = REG_READ(ah, AR_ISR_S1); ar9002_hw_get_isr()
141 s5_s = REG_READ(ah, AR_ISR_S5_S); ar9002_hw_get_isr()
143 s5_s = REG_READ(ah, AR_ISR_S5); ar9002_hw_get_isr()
167 REG_READ(ah, AR_ISR); ar9002_hw_get_isr()
205 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); ar9002_hw_get_isr()
H A Dar9003_calib.c84 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { ar9003_hw_per_calibration()
184 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); ar9003_hw_iqcal_collect()
186 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); ar9003_hw_iqcal_collect()
188 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); ar9003_hw_iqcal_collect()
272 REG_READ(ah, offset_array[i])); ar9003_hw_iqcalibrate()
289 REG_READ(ah, offset_array[i])); ar9003_hw_iqcalibrate()
294 REG_READ(ah, offset_array[i])); ar9003_hw_iqcalibrate()
307 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); ar9003_hw_iqcalibrate()
355 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); ar9003_hw_dynamic_osdac_selection()
385 osdac_ch0 = (REG_READ(ah, AR_PHY_65NM_CH0_BB1) >> 30) & 0x3; ar9003_hw_dynamic_osdac_selection()
386 osdac_ch1 = (REG_READ(ah, AR_PHY_65NM_CH1_BB1) >> 30) & 0x3; ar9003_hw_dynamic_osdac_selection()
387 osdac_ch2 = (REG_READ(ah, AR_PHY_65NM_CH2_BB1) >> 30) & 0x3; ar9003_hw_dynamic_osdac_selection()
392 REG_READ(ah, AR_PHY_AGC_CONTROL) | AR_PHY_AGC_CONTROL_CAL); ar9003_hw_dynamic_osdac_selection()
409 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (1 << 8))); ar9003_hw_dynamic_osdac_selection()
411 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (1 << 8))); ar9003_hw_dynamic_osdac_selection()
413 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (1 << 8))); ar9003_hw_dynamic_osdac_selection()
415 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); ar9003_hw_dynamic_osdac_selection()
419 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); ar9003_hw_dynamic_osdac_selection()
423 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); ar9003_hw_dynamic_osdac_selection()
431 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (2 << 8))); ar9003_hw_dynamic_osdac_selection()
433 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (2 << 8))); ar9003_hw_dynamic_osdac_selection()
435 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (2 << 8))); ar9003_hw_dynamic_osdac_selection()
437 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); ar9003_hw_dynamic_osdac_selection()
441 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); ar9003_hw_dynamic_osdac_selection()
445 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); ar9003_hw_dynamic_osdac_selection()
453 ((REG_READ(ah, AR_PHY_65NM_CH0_BB3) & 0xfffffcff) | (3 << 8))); ar9003_hw_dynamic_osdac_selection()
455 ((REG_READ(ah, AR_PHY_65NM_CH1_BB3) & 0xfffffcff) | (3 << 8))); ar9003_hw_dynamic_osdac_selection()
457 ((REG_READ(ah, AR_PHY_65NM_CH2_BB3) & 0xfffffcff) | (3 << 8))); ar9003_hw_dynamic_osdac_selection()
459 temp = REG_READ(ah, AR_PHY_65NM_CH0_BB3); ar9003_hw_dynamic_osdac_selection()
463 temp = REG_READ(ah, AR_PHY_65NM_CH1_BB3); ar9003_hw_dynamic_osdac_selection()
467 temp = REG_READ(ah, AR_PHY_65NM_CH2_BB3); ar9003_hw_dynamic_osdac_selection()
482 val = REG_READ(ah, AR_PHY_65NM_CH0_BB1) & 0x3fffffff; ar9003_hw_dynamic_osdac_selection()
503 val = REG_READ(ah, AR_PHY_65NM_CH1_BB1) & 0x3fffffff; ar9003_hw_dynamic_osdac_selection()
524 val = REG_READ(ah, AR_PHY_65NM_CH2_BB1) & 0x3fffffff; ar9003_hw_dynamic_osdac_selection()
1093 if (REG_READ(ah, txiqcal_status[i]) & ar9003_hw_tx_iq_cal_post_proc()
1109 iq_res[idx] = REG_READ(ah, ar9003_hw_tx_iq_cal_post_proc()
1119 iq_res[idx + 1] = 0xffff & REG_READ(ah, ar9003_hw_tx_iq_cal_post_proc()
1359 txclcal_done = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & ar9003_hw_cl_cal_post_proc()
1376 REG_READ(ah, CL_TAB_ENTRY(cl_idx[i])); ar9003_hw_cl_cal_post_proc()
1417 agc_ctrl = REG_READ(ah, AR_PHY_AGC_CONTROL); ar9003_hw_init_cal_pcoem()
1467 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { ar9003_hw_init_cal_pcoem()
1468 rx_delay = REG_READ(ah, AR_PHY_RX_DELAY); ar9003_hw_init_cal_pcoem()
1479 REG_READ(ah, AR_PHY_AGC_CONTROL) | ar9003_hw_init_cal_pcoem()
1490 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { ar9003_hw_init_cal_pcoem()
1566 REG_READ(ah, AR_PHY_AGC_CONTROL) | do_ar9003_agc_cal()
H A Dar9003_wow.c48 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW)); ath9k_hw_set_powermode_wow_sleep()
53 if (!REG_READ(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL)) ath9k_hw_set_powermode_wow_sleep()
56 if (!(REG_READ(ah, AR_NDP2_TIMER_MODE) & ath9k_hw_set_powermode_wow_sleep()
192 rval = REG_READ(ah, AR_WOW_PATTERN); ath9k_hw_wow_wakeup()
213 rval = REG_READ(ah, AR_MAC_PCU_WOW4); ath9k_hw_wow_wakeup()
236 AR_WOW_CLEAR_EVENTS(REG_READ(ah, AR_WOW_PATTERN))); ath9k_hw_wow_wakeup()
238 AR_WOW_CLEAR_EVENTS2(REG_READ(ah, AR_MAC_PCU_WOW4))); ath9k_hw_wow_wakeup()
256 u32 dc = REG_READ(ah, AR_DIRECT_CONNECT); ath9k_hw_wow_wakeup()
281 wa_reg = REG_READ(ah, AR_WA); ath9k_hw_wow_set_arwr_reg()
364 keep_alive = REG_READ(ah, AR_WOW_KEEP_ALIVE); ath9k_hw_wow_enable()
395 magic_pattern = REG_READ(ah, AR_WOW_PATTERN); ath9k_hw_wow_enable()
417 host_pm_ctrl = REG_READ(ah, AR_PCIE_PM_CTRL); ath9k_hw_wow_enable()
H A Dar9002_phy.c76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); ar9002_hw_set_channel()
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); ar9002_hw_set_channel()
241 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); ar9002_hw_spur_mitigate()
442 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4), ar9002_olc_init()
480 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR); ar9002_hw_do_getnf()
483 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); ar9002_hw_do_getnf()
490 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); ar9002_hw_do_getnf()
493 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); ar9002_hw_do_getnf()
527 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ar9002_hw_antdiv_comb_conf_get()
544 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ar9002_hw_antdiv_comb_conf_set()
599 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ar9002_hw_set_bt_ant_diversity()
613 regval = REG_READ(ah, AR_PHY_CCK_DETECT); ar9002_hw_set_bt_ant_diversity()
H A Dar9003_mac.c195 async_cause = REG_READ(ah, AR_INTR_ASYNC_CAUSE); ar9003_hw_get_isr()
198 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ar9003_hw_get_isr()
200 isr = REG_READ(ah, AR_ISR); ar9003_hw_get_isr()
204 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT; ar9003_hw_get_isr()
214 isr2 = REG_READ(ah, AR_ISR_S2); ar9003_hw_get_isr()
240 isr = REG_READ(ah, AR_ISR_RAC); ar9003_hw_get_isr()
268 s0 = REG_READ(ah, AR_ISR_S0); ar9003_hw_get_isr()
270 s1 = REG_READ(ah, AR_ISR_S1); ar9003_hw_get_isr()
282 s5 = REG_READ(ah, AR_ISR_S5_S); ar9003_hw_get_isr()
284 s5 = REG_READ(ah, AR_ISR_S5); ar9003_hw_get_isr()
307 (void) REG_READ(ah, AR_ISR); ar9003_hw_get_isr()
348 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR); ar9003_hw_get_isr()
H A Dmac.c48 return REG_READ(ah, AR_QTXDP(q)); ath9k_hw_gettxbuf()
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT; ath9k_hw_numtxpending()
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q)) ath9k_hw_numtxpending()
114 txcfg = REG_READ(ah, AR_TXCFG); ath9k_hw_updatetxtriglevel()
652 reg = REG_READ(ah, AR_OBS_BUS_1); ath9k_hw_setrxabort()
709 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0) ath9k_hw_stopdmarecv()
713 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0; ath9k_hw_stopdmarecv()
729 REG_READ(ah, AR_CR), ath9k_hw_stopdmarecv()
730 REG_READ(ah, AR_DIAG_SW), ath9k_hw_stopdmarecv()
731 REG_READ(ah, AR_DMADBG_7)); ath9k_hw_stopdmarecv()
764 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE); ath9k_hw_intrpend()
771 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE); ath9k_hw_intrpend()
786 (void) REG_READ(ah, AR_IER); ath9k_hw_kill_interrupts()
789 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE); ath9k_hw_kill_interrupts()
792 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE); ath9k_hw_kill_interrupts()
842 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); ath9k_hw_enable_interrupts()
H A Dar9003_mci.c39 if (!(REG_READ(ah, address) & bit_position)) { ar9003_mci_wait_for_interrupt()
71 REG_READ(ah, AR_MCI_INTERRUPT_RAW), ar9003_mci_wait_for_interrupt()
72 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); ar9003_mci_wait_for_interrupt()
232 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); ar9003_mci_prep_interface()
236 REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW)); ar9003_mci_prep_interface()
238 REG_READ(ah, AR_MCI_INTERRUPT_RAW)); ar9003_mci_prep_interface()
351 intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); ar9003_mci_check_int()
375 rx_msg_intr = REG_READ(ah, AR_MCI_INTERRUPT_RX_MSG_RAW); ar9003_mci_get_isr()
376 raw_intr = REG_READ(ah, AR_MCI_INTERRUPT_RAW); ar9003_mci_get_isr()
387 mci->cont_status = REG_READ(ah, AR_MCI_CONT_STATUS); ar9003_mci_get_isr()
916 if (REG_READ(ah, AR_BTCOEX_CTRL) == 0xdeadbeef) { ar9003_mci_reset()
974 regval = REG_READ(ah, AR_MCI_COMMAND2); ar9003_mci_reset()
1166 saved_mci_int_en = REG_READ(ah, AR_MCI_INTERRUPT_EN); ar9003_mci_send_message()
1167 regval = REG_READ(ah, AR_BTCOEX_CTRL); ar9003_mci_send_message()
1288 value = REG_READ(ah, AR_BTCOEX_CTRL); ar9003_mci_state()
1296 value = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); ar9003_mci_state()
1304 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), ar9003_mci_state()
1310 value = MS(REG_READ(ah, AR_MCI_RX_STATUS), ar9003_mci_state()
1330 if ((REG_READ(ah, AR_GLB_GPIO_CONTROL) & ar9003_mci_state()
1419 btcoex_ctrl2 = REG_READ(ah, AR_BTCOEX_CTRL2); ar9003_mci_set_power_awake()
1427 diag_sw = REG_READ(ah, AR_DIAG_SW); ar9003_mci_set_power_awake()
1433 lna_ctrl = REG_READ(ah, AR_OBS_BUS_CTRL) & 0x3; ar9003_mci_set_power_awake()
1434 bt_sleep = MS(REG_READ(ah, AR_MCI_RX_STATUS), AR_MCI_RX_REMOTE_SLEEP); ar9003_mci_set_power_awake()
1455 offset = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); ar9003_mci_check_gpm_offset()
1482 gpm_ptr = MS(REG_READ(ah, AR_MCI_GPM_1), AR_MCI_GPM_WRITE_PTR); ar9003_mci_get_next_gpm_offset()
H A Dar9003_phy.c643 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO); ar9003_hw_set_channel_regs()
661 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL); ar9003_hw_set_channel_regs()
686 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; ar9003_hw_init_bb()
729 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE); ar9003_hw_override_ini()
747 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) ar9003_hw_override_ini()
1080 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; ar9003_hw_rfbus_done()
1374 nf = MS(REG_READ(ah, ah->nf_regs[i]), ar9003_hw_do_getnf()
1381 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), ar9003_hw_do_getnf()
1431 val = REG_READ(ah, AR_PHY_SFCORR); ar9003_hw_ani_cache_ini_regs()
1436 val = REG_READ(ah, AR_PHY_SFCORR_LOW); ar9003_hw_ani_cache_ini_regs()
1441 val = REG_READ(ah, AR_PHY_SFCORR_EXT); ar9003_hw_ani_cache_ini_regs()
1484 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); ar9003_hw_set_radar_params()
1525 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_antdiv_comb_conf_get()
1557 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_antdiv_comb_conf_set()
1605 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1614 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1625 regval = REG_READ(ah, AR_PHY_CCK_DETECT); ar9003_hw_set_bt_ant_diversity()
1634 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
1673 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_set_bt_ant_diversity()
2087 val = REG_READ(ah, AR_PHY_RADAR_0); ar9003_hw_bb_watchdog_check()
2092 val = REG_READ(ah, AR_PHY_RADAR_0); ar9003_hw_bb_watchdog_check()
2127 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & ar9003_hw_bb_watchdog_config()
2133 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) & ar9003_hw_bb_watchdog_config()
2142 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK; ar9003_hw_bb_watchdog_config()
2183 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); ar9003_hw_bb_watchdog_read()
2217 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1), ar9003_hw_bb_watchdog_dbg_info()
2218 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2)); ar9003_hw_bb_watchdog_dbg_info()
2220 REG_READ(ah, AR_PHY_GEN_CTRL)); ar9003_hw_bb_watchdog_dbg_info()
2246 val = REG_READ(ah, AR_PHY_RESTART); ar9003_hw_disable_phy_restart()
H A Dar5008_phy.c215 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL); ar5008_hw_set_channel()
312 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0)); ar5008_hw_spur_mitigate()
561 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; ar5008_hw_init_bb()
608 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001); ar5008_hw_init_chain_masks()
631 val = REG_READ(ah, AR_PCU_MISC_MODE2) & ar5008_hw_override_ini()
658 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS); ar5008_hw_override_ini()
671 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) & ar5008_hw_set_channel_regs()
872 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; ar5008_hw_rfbus_done()
1118 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR); ar5008_hw_do_getnf()
1121 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR); ar5008_hw_do_getnf()
1124 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR); ar5008_hw_do_getnf()
1130 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR); ar5008_hw_do_getnf()
1133 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR); ar5008_hw_do_getnf()
1136 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR); ar5008_hw_do_getnf()
1161 val = REG_READ(ah, AR_PHY_SFCORR); ar5008_hw_ani_cache_ini_regs()
1166 val = REG_READ(ah, AR_PHY_SFCORR_LOW); ar5008_hw_ani_cache_ini_regs()
1171 val = REG_READ(ah, AR_PHY_SFCORR_EXT); ar5008_hw_ani_cache_ini_regs()
1223 radar_1 = REG_READ(ah, AR_PHY_RADAR_1); ar5008_hw_set_radar_params()
H A Dhw.c84 if ((REG_READ(ah, reg) & mask) == val) ath9k_hw_wait()
92 timeout, reg, REG_READ(ah, reg), mask, val); ath9k_hw_wait()
267 val = REG_READ(ah, AR_SREV); ath9k_hw_read_revisions()
284 val = REG_READ(ah, AR_SREV) & AR_SREV_ID; ath9k_hw_read_revisions()
287 val = REG_READ(ah, AR_SREV); ath9k_hw_read_revisions()
351 regHold[i] = REG_READ(ah, addr); ath9k_hw_chip_test()
355 rdData = REG_READ(ah, addr); ath9k_hw_chip_test()
366 rdData = REG_READ(ah, addr); ath9k_hw_chip_test()
592 ah->WARegVal = REG_READ(ah, AR_WA); __ath9k_hw_init()
623 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); __ath9k_hw_init()
732 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) { ar9003_get_pll_sqsum_dvc()
744 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; ar9003_get_pll_sqsum_dvc()
854 regval = REG_READ(ah, AR_PHY_PLL_MODE); ath9k_hw_init_pll()
866 regval = REG_READ(ah, AR_PHY_PLL_MODE); ath9k_hw_init_pll()
892 REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); ath9k_hw_init_pll()
895 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff); ath9k_hw_init_pll()
1071 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/ ath9k_hw_init_global_settings()
1073 reg = REG_READ(ah, AR_USEC); ath9k_hw_init_global_settings()
1320 (void)REG_READ(ah, AR_RTC_DERIVED_CLK); ath9k_hw_set_reset()
1337 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE); ath9k_hw_set_reset()
1475 } else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) || ath9k_hw_chip_reset()
1476 (REG_READ(ah, AR_CR) & AR_CR_RXE)) ath9k_hw_chip_reset()
1583 val = REG_READ(ah, AR_NAV); ath9k_hw_check_nav()
1602 last_val = REG_READ(ah, AR_OBS_BUS_1); ath9k_hw_check_alive()
1604 reg = REG_READ(ah, AR_OBS_BUS_1); ath9k_hw_check_alive()
1701 mask = REG_READ(ah, AR_CFG); ath9k_hw_init_desc()
1709 REG_READ(ah, AR_CFG)); ath9k_hw_init_desc()
1859 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA); ath9k_hw_reset()
1863 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B; ath9k_hw_reset()
1869 saveLedState = REG_READ(ah, AR_CFG_LED) & ath9k_hw_reset()
2135 if ((REG_READ(ah, AR_RTC_STATUS) & ath9k_hw_set_power_awake()
2155 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M; ath9k_hw_set_power_awake()
2533 ah->ent_mode = REG_READ(ah, AR_ENT_OTP); ath9k_hw_fill_cap_info()
2623 tmp = REG_READ(ah, addr); ath9k_hw_gpio_cfg_output_mux()
2656 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y))) ath9k_hw_gpio_get()
2663 val = REG_READ(ah, AR7010_GPIO_IN); ath9k_hw_gpio_get()
2666 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) & ath9k_hw_gpio_get()
2744 u32 bits = REG_READ(ah, AR_RX_FILTER); ath9k_hw_getrxfilter()
2745 u32 phybits = REG_READ(ah, AR_PHY_ERR); ath9k_hw_getrxfilter()
2894 tsf_upper1 = REG_READ(ah, AR_TSF_U32); ath9k_hw_gettsf64()
2896 tsf_lower = REG_READ(ah, AR_TSF_L32); ath9k_hw_gettsf64()
2897 tsf_upper2 = REG_READ(ah, AR_TSF_U32); ath9k_hw_gettsf64()
2981 return REG_READ(ah, AR_TSF_L32); ath9k_hw_gettsf32()
H A Dar9003_aic.c248 (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) | ar9003_aic_cal_start()
251 aic->aic_cal_start_time = REG_READ(ah, AR_TSF_L32); ar9003_aic_cal_start()
442 (REG_READ(ah, ATH_AIC_BT_JUPITER_CTRL) & ar9003_aic_cal_done()
467 if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) & ar9003_aic_cal_continue()
479 if ((REG_READ(ah, AR_PHY_AIC_CTRL_0_B1) & ar9003_aic_cal_continue()
491 value = REG_READ(ah, AR_PHY_AIC_SRAM_DATA_B1); ar9003_aic_cal_continue()
H A Deeprom_9287.c375 tmpVal = REG_READ(ah, 0xa270); ar9287_eeprom_olpc_set_pdadcs()
382 tmpVal = REG_READ(ah, 0xb270); ar9287_eeprom_olpc_set_pdadcs()
390 tmpVal = REG_READ(ah, 0xa398); ar9287_eeprom_olpc_set_pdadcs()
400 tmpVal = REG_READ(ah, 0xb398); ar9287_eeprom_olpc_set_pdadcs()
430 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), ath9k_hw_set_ar9287_power_cal_table()
927 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) ath9k_hw_ar9287_set_board_values()
976 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0); ath9k_hw_ar9287_set_board_values()
992 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1); ath9k_hw_ar9287_set_board_values()
H A Dcalib.c284 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) & ath9k_hw_loadnf()
302 REG_READ(ah, AR_PHY_AGC_CONTROL)); ath9k_hw_loadnf()
369 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { ath9k_hw_getnf()
438 else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)) ath9k_hw_bstuck_nfcal()
H A Dar9002_hw.c256 val = REG_READ(ah, AR_WA); ar9002_hw_configpcipowersave()
339 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; ar9002_hw_get_radiorev()
446 val_orig = REG_READ(ah, reg); ar9002_hw_load_ani_reg()
H A Dar9003_rtt.c162 val = MS(REG_READ(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain)), ar9003_hw_rtt_fill_hist_entry()
H A Dar9003_hw.c1103 dma_dbg_chain = REG_READ(ah, AR_DMADBG_4); ath9k_hw_verify_hang()
1105 dma_dbg_chain = REG_READ(ah, AR_DMADBG_5); ath9k_hw_verify_hang()
1107 dma_dbg_complete = REG_READ(ah, AR_DMADBG_6); ath9k_hw_verify_hang()
1130 dma_dbg_4 = REG_READ(ah, AR_DMADBG_4); ar9003_hw_detect_mac_hang()
1131 dma_dbg_5 = REG_READ(ah, AR_DMADBG_5); ar9003_hw_detect_mac_hang()
1132 dma_dbg_6 = REG_READ(ah, AR_DMADBG_6); ar9003_hw_detect_mac_hang()
H A Deeprom_4k.c373 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), ath9k_hw_set_4k_power_cal_table()
854 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ath9k_hw_4k_set_board_values()
870 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ath9k_hw_4k_set_board_values()
871 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); ath9k_hw_4k_set_board_values()
877 regVal = REG_READ(ah, AR_PHY_CCK_DETECT); ath9k_hw_4k_set_board_values()
884 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); ath9k_hw_4k_set_board_values()
H A Dar9003_paprd.c299 entry[i] = REG_READ(ah, reg); ar9003_paprd_get_gain_table()
940 data_L[i] = REG_READ(ah, reg + (i << 2)); ar9003_paprd_create_curve()
946 data_U[i] = REG_READ(ah, reg + (i << 2)); ar9003_paprd_create_curve()
H A Dani.c405 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1); ath9k_hw_ani_read_counters()
406 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2); ath9k_hw_ani_read_counters()
H A Dar9003_eeprom.c3088 REG_READ(ah, AR9300_OTP_BASE + (4 * addr)); ar9300_otp_read_word()
3094 *data = REG_READ(ah, AR9300_OTP_READ_DATA); ar9300_otp_read_word()
3660 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_ant_ctrl_apply()
3696 regval = REG_READ(ah, AR_PHY_CCK_DETECT); ar9003_hw_ant_ctrl_apply()
3707 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL); ar9003_hw_ant_ctrl_apply()
3737 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1); ar9003_hw_drive_strength_apply()
3747 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2); ar9003_hw_drive_strength_apply()
3760 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4); ar9003_hw_drive_strength_apply()
3873 while (pmu_set != REG_READ(ah, pmu_reg)) { is_pmu_set()
3893 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM; ar9003_hw_internal_regulator_apply()
3921 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000) ar9003_hw_internal_regulator_apply()
3927 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000) ar9003_hw_internal_regulator_apply()
3943 REG_READ(ah, AR_RTC_REG_CONTROL1) & ar9003_hw_internal_regulator_apply()
3948 REG_READ(ah, ar9003_hw_internal_regulator_apply()
3970 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) | ar9003_hw_internal_regulator_apply()
5440 val = REG_READ(ah, AR_PHY_POWER_TX_SUB); ath9k_hw_ar9300_set_txpower()
H A Dbtcoex.c287 val = REG_READ(ah, 0x50040); ath9k_hw_btcoex_enable_3wire()
H A Dhtc_drv_init.c496 val = REG_READ(ah, reg_offset); ath9k_reg_rmw()
521 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); ath_usb_eeprom_read()
530 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), ath_usb_eeprom_read()
H A Deeprom_def.c542 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) & ath9k_hw_def_set_board_values()
837 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5), ath9k_hw_set_def_power_cal_table()
H A Dhw.h82 #define REG_READ(_ah, _reg) \ macro
126 (((REG_READ(_a, _r) & _f) >> _f##_S))
H A Ddebug.c930 "0x%06x 0x%08x\n", i << 2, REG_READ(sc->sc_ah, i << 2)); open_file_regdump()
H A Dchannel.c561 sc->sched.next_tbtt = REG_READ(ah, AR_NEXT_TBTT_TIMER); ath_chanctx_event()
H A Dreg.h931 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
/linux-4.1.27/arch/cris/include/arch-v32/arch/hwregs/iop/
H A Diop_version_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_in_extra_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_out_extra_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_scrc_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_scrc_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_trigger_grp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_crc_par_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_mpu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_timer_grp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_dmc_in_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_dmc_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_fifo_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sap_out_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_spu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_spu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cfg_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_cpu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Diop_sw_mpu_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/mach-a3/mach/hwregs/
H A Dstrmux_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dclkgen_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dl2cache_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_bar_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
300 REG_READ( reg_##scope##_##reg, \
312 REG_READ( reg_##scope##_##reg, \
326 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
336 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_foo_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
426 REG_READ( reg_##scope##_##reg, \
438 REG_READ( reg_##scope##_##reg, \
452 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
462 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dddr2_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dintr_vect_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dpinmux_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dpio_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dtimer_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dgio_defs.h16 REG_READ( reg_##scope##_##reg, \
28 REG_READ( reg_##scope##_##reg, \
42 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
52 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/arch/cris/include/arch-v32/mach-fs/mach/hwregs/
H A Dconfig_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dstrmux_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_slave_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dintr_vect_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_bp_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dmarb_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
278 REG_READ( reg_##scope##_##reg, \
290 REG_READ( reg_##scope##_##reg, \
304 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
314 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_core_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dgio_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dpinmux_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dtimer_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
H A Dbif_dma_defs.h19 REG_READ( reg_##scope##_##reg, \
31 REG_READ( reg_##scope##_##reg, \
45 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
55 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
/linux-4.1.27/drivers/input/keyboard/
H A Dgoldfish_events.c27 REG_READ = 0x00, enumerator in enum:__anon5087
49 type = __raw_readl(edev->addr + REG_READ); events_interrupt()
50 code = __raw_readl(edev->addr + REG_READ); events_interrupt()
51 value = __raw_readl(edev->addr + REG_READ); events_interrupt()
/linux-4.1.27/drivers/net/wireless/ath/
H A Dhw.c23 #define REG_READ (common->ops->read) macro
124 id1 = REG_READ(ah, AR_STA_ID1) & ~AR_STA_ID1_SADH_MASK; ath_hw_setbssidmask()
151 cycles = REG_READ(ah, AR_CCCNT); ath_hw_cycle_counters_update()
152 busy = REG_READ(ah, AR_RCCNT); ath_hw_cycle_counters_update()
153 rx = REG_READ(ah, AR_RFCNT); ath_hw_cycle_counters_update()
154 tx = REG_READ(ah, AR_TFCNT); ath_hw_cycle_counters_update()
H A Dkey.c25 #define REG_READ (common->ops->read) macro
53 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry)); ath_hw_keyreset()
/linux-4.1.27/drivers/media/usb/dvb-usb-v2/
H A Dce6230.h46 REG_READ = 0xde, /* rd e */ enumerator in enum:ce6230_cmd
H A Dce6230.c43 case REG_READ: ce6230_ctrl_msg()
/linux-4.1.27/arch/x86/mm/
H A Dpf_in.h28 REG_READ, /* read from addr to reg */ enumerator in enum:reason_type
H A Dmmio-mod.c181 case REG_READ: pre()
222 case REG_READ: post()
H A Dpf_in.c155 CHECK_OP_TYPE(opcode, reg_rop, REG_READ); get_ins_type()
/linux-4.1.27/drivers/net/dsa/
H A Dmv88e6060.c32 #define REG_READ(addr, reg) \ macro
91 ret = REG_READ(REG_PORT(i), 0x04); mv88e6060_switch_reset()
104 ret = REG_READ(REG_GLOBAL, 0x00); mv88e6060_switch_reset()
H A Dmv88e6xxx.c209 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC); mv88e6xxx_set_addr_indirect()
243 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); mv88e6xxx_ppu_disable()
249 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); mv88e6xxx_ppu_disable()
264 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL); mv88e6xxx_ppu_enable()
269 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); mv88e6xxx_ppu_enable()
456 ret = REG_READ(REG_GLOBAL, GLOBAL_STATS_OP); mv88e6xxx_stats_wait()
742 ret = REG_READ(reg, offset); mv88e6xxx_wait()
808 return REG_READ(REG_GLOBAL2, GLOBAL2_SMI_DATA); _mv88e6xxx_phy_read_indirect()
1292 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0; mv88e6xxx_setup_common()
1311 ret = REG_READ(REG_PORT(i), PORT_CONTROL); mv88e6xxx_switch_reset()
1330 ret = REG_READ(REG_GLOBAL, 0x00); mv88e6xxx_switch_reset()
H A Dmv88e6171.c65 if (REG_READ(REG_PORT(0), 0x03) == 0x1710) mv88e6171_setup_global()
141 val = REG_READ(addr, 0x01); mv88e6171_setup_port()
H A Dmv88e6xxx.h318 #define REG_READ(addr, reg) \ macro
/linux-4.1.27/drivers/net/wireless/cw1200/
H A Dfwio.c89 #define REG_READ(reg, val) \ cw1200_load_firmware_cw1200() macro
139 REG_READ(ST90TDS_CONFIG_REG_ID, val32); cw1200_load_firmware_cw1200()
264 #undef REG_READ cw1200_load_firmware_cw1200() macro

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