84 		if ((REG_READ(ah, reg) & mask) == val)  in ath9k_hw_wait()
92 		timeout, reg, REG_READ(ah, reg), mask, val);  in ath9k_hw_wait()
267 			val = REG_READ(ah, AR_SREV);  in ath9k_hw_read_revisions()
284 	val = REG_READ(ah, AR_SREV) & AR_SREV_ID;  in ath9k_hw_read_revisions()
287 		val = REG_READ(ah, AR_SREV);  in ath9k_hw_read_revisions()
351 		regHold[i] = REG_READ(ah, addr);  in ath9k_hw_chip_test()
355 			rdData = REG_READ(ah, addr);  in ath9k_hw_chip_test()
366 			rdData = REG_READ(ah, addr);  in ath9k_hw_chip_test()
592 		ah->WARegVal = REG_READ(ah, AR_WA);  in __ath9k_hw_init()
623 	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);  in __ath9k_hw_init()
732 	while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {  in ar9003_get_pll_sqsum_dvc()
744 	return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;  in ar9003_get_pll_sqsum_dvc()
854 		regval = REG_READ(ah, AR_PHY_PLL_MODE);  in ath9k_hw_init_pll()
866 		regval = REG_READ(ah, AR_PHY_PLL_MODE);  in ath9k_hw_init_pll()
892 				  REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);  in ath9k_hw_init_pll()
895 				  REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);  in ath9k_hw_init_pll()
1071 			eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/  in ath9k_hw_init_global_settings()
1073 			reg = REG_READ(ah, AR_USEC);  in ath9k_hw_init_global_settings()
1320 		(void)REG_READ(ah, AR_RTC_DERIVED_CLK);  in ath9k_hw_set_reset()
1337 		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);  in ath9k_hw_set_reset()
1475 	} else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||  in ath9k_hw_chip_reset()
1476 		   (REG_READ(ah, AR_CR) & AR_CR_RXE))  in ath9k_hw_chip_reset()
1583 	val = REG_READ(ah, AR_NAV);  in ath9k_hw_check_nav()
1602 	last_val = REG_READ(ah, AR_OBS_BUS_1);  in ath9k_hw_check_alive()
1604 		reg = REG_READ(ah, AR_OBS_BUS_1);  in ath9k_hw_check_alive()
1701 		mask = REG_READ(ah, AR_CFG);  in ath9k_hw_init_desc()
1709 				REG_READ(ah, AR_CFG));  in ath9k_hw_init_desc()
1859 	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);  in ath9k_hw_reset()
1863 	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;  in ath9k_hw_reset()
1869 	saveLedState = REG_READ(ah, AR_CFG_LED) &  in ath9k_hw_reset()
2135 	if ((REG_READ(ah, AR_RTC_STATUS) &  in ath9k_hw_set_power_awake()
2155 		val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;  in ath9k_hw_set_power_awake()
2533 		ah->ent_mode = REG_READ(ah, AR_ENT_OTP);  in ath9k_hw_fill_cap_info()
2623 		tmp = REG_READ(ah, addr);  in ath9k_hw_gpio_cfg_output_mux()
2656 	(MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))  in ath9k_hw_gpio_get()
2663 		val = REG_READ(ah, AR7010_GPIO_IN);  in ath9k_hw_gpio_get()
2666 		return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &  in ath9k_hw_gpio_get()
2744 	u32 bits = REG_READ(ah, AR_RX_FILTER);  in ath9k_hw_getrxfilter()
2745 	u32 phybits = REG_READ(ah, AR_PHY_ERR);  in ath9k_hw_getrxfilter()
2894 	tsf_upper1 = REG_READ(ah, AR_TSF_U32);  in ath9k_hw_gettsf64()
2896 		tsf_lower = REG_READ(ah, AR_TSF_L32);  in ath9k_hw_gettsf64()
2897 		tsf_upper2 = REG_READ(ah, AR_TSF_U32);  in ath9k_hw_gettsf64()
2981 	return REG_READ(ah, AR_TSF_L32);  in ath9k_hw_gettsf32()