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Searched refs:I915_READ (Results 1 – 42 of 42) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Di915_suspend.c38 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
42 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); in i915_save_display()
44 dev_priv->regfile.saveLVDS = I915_READ(LVDS); in i915_save_display()
48 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()
49 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); in i915_save_display()
50 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); in i915_save_display()
51 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); in i915_save_display()
53 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); in i915_save_display()
54 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); in i915_save_display()
55 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); in i915_save_display()
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Di915_drv.c1041 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
1042 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
1043 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
1044 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
1045 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
1048 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); in vlv_save_gunit_s0ix_state()
1050 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
1051 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
1053 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
1054 s->ecochk = I915_READ(GAM_ECOCHK); in vlv_save_gunit_s0ix_state()
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Di915_gpu_error.c781 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); in i915_gem_record_fences()
784 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + in i915_gem_record_fences()
835 ering->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(ring->mmio_base)); in gen6_record_semaphore_state()
836 ering->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(ring->mmio_base)); in gen6_record_semaphore_state()
842 I915_READ(RING_SYNC_2(ring->mmio_base)); in gen6_record_semaphore_state()
855 ering->rc_psmi = I915_READ(ring->mmio_base + 0x50); in i915_record_ring_state()
856 ering->fault_reg = I915_READ(RING_FAULT_REG(ring)); in i915_record_ring_state()
864 ering->faddr = I915_READ(RING_DMA_FADD(ring->mmio_base)); in i915_record_ring_state()
865 ering->ipeir = I915_READ(RING_IPEIR(ring->mmio_base)); in i915_record_ring_state()
866 ering->ipehr = I915_READ(RING_IPEHR(ring->mmio_base)); in i915_record_ring_state()
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Dintel_audio.c103 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
109 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
114 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) in intel_eld_uptodate()
127 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
134 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
151 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_enable()
163 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
173 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
188 tmp = I915_READ(HSW_AUD_CFG(pipe)); in hsw_audio_codec_disable()
198 tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); in hsw_audio_codec_disable()
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Di915_debugfs.c592 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane))); in i915_gem_pageflip_info()
594 addr = I915_READ(DSPADDR(crtc->plane)); in i915_gem_pageflip_info()
723 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
726 I915_READ(VLV_IER)); in i915_interrupt_info()
728 I915_READ(VLV_IIR)); in i915_interrupt_info()
730 I915_READ(VLV_IIR_RW)); in i915_interrupt_info()
732 I915_READ(VLV_IMR)); in i915_interrupt_info()
736 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
739 I915_READ(PORT_HOTPLUG_EN)); in i915_interrupt_info()
741 I915_READ(VLV_DPFLIPSTAT)); in i915_interrupt_info()
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Di915_irq.c116 u32 val = I915_READ(reg); \
291 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
293 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) | in gen6_enable_rps_interrupts()
332 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) & in gen6_disable_rps_interrupts()
350 uint32_t sdeimr = I915_READ(SDEIMR); in ibx_display_interrupt_update()
370 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_enable_pipestat()
397 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_disable_pipestat()
585 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
586 low = I915_READ(low_frame); in i915_get_vblank_counter()
587 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; in i915_get_vblank_counter()
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Dintel_ddi.c327 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
410 temp = I915_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
418 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
432 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
438 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
451 temp = I915_READ(_FDI_RXA_MISC); in hsw_fdi_link_train()
684 wrpll = I915_READ(reg); in intel_ddi_calc_wrpll_link()
721 cfgcr1_val = I915_READ(cfgcr1_reg); in skl_calc_wrpll_link()
722 cfgcr2_val = I915_READ(cfgcr2_reg); in skl_calc_wrpll_link()
781 dpll_ctl1 = I915_READ(DPLL_CTRL1); in skl_ddi_clock_get()
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Dintel_crt.c79 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_hw_state()
98 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
146 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); in hsw_crt_pre_enable()
218 val = I915_READ(SPLL_CTL); in hsw_crt_post_disable()
348 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
357 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in intel_ironlake_crt_detect_hotplug()
368 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
387 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
394 if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, in valleyview_crt_detect_hotplug()
401 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
[all …]
Dintel_display.c137 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; in intel_pch_rawclk()
145 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; in intel_fdi_link_freq()
998 line1 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1000 line2 = I915_READ(reg) & line_mask; in pipe_dsl_stopped()
1032 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, in intel_wait_for_pipe_off()
1084 return I915_READ(SDEISR) & bit; in ibx_digital_port_connected()
1101 val = I915_READ(reg); in assert_pll()
1167 val = I915_READ(reg); in assert_fdi_tx()
1171 val = I915_READ(reg); in assert_fdi_tx()
1189 val = I915_READ(reg); in assert_fdi_rx()
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Dintel_dsi.c58 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) in wait_for_dsi_fifo_empty()
83 u32 val = I915_READ(reg); in read_data()
124 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) in intel_dsi_host_transfer()
135 if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { in intel_dsi_host_transfer()
144 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) in intel_dsi_host_transfer()
228 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
234 if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) in dpi_send_cmd()
299 temp = I915_READ(VLV_CHICKEN_3); in intel_dsi_port_enable()
307 temp = I915_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_enable()
334 temp = I915_READ(MIPI_PORT_CTRL(port)); in intel_dsi_port_disable()
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Dintel_psr.c69 val = I915_READ(VLV_PSRSTAT(pipe)) & in vlv_is_psr_active_on_pipe()
114 val = I915_READ(VLV_VSCSDP(pipe)); in vlv_psr_setup_vsc()
181 val = I915_READ(aux_ctl_reg); in hsw_psr_enable_sink()
226 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
285 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & in intel_psr_match_conditions()
307 WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE); in intel_psr_activate()
407 if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) & in vlv_psr_disable()
411 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); in vlv_psr_disable()
431 I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE); in hsw_psr_disable()
434 if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) & in hsw_psr_disable()
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Dintel_sideband.c54 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { in vlv_sideband_rw()
65 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) { in vlv_sideband_rw()
72 *val = I915_READ(VLV_IOSF_DATA); in vlv_sideband_rw()
218 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_read()
232 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_read()
238 return I915_READ(SBI_DATA); in intel_sbi_read()
248 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0, in intel_sbi_write()
263 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0, in intel_sbi_write()
Dintel_pm.c60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | in gen9_init_clock_gating()
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in skl_init_clock_gating()
82 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | in skl_init_clock_gating()
87 I915_READ(FF_SLICE_CS_CHICKEN2) | in skl_init_clock_gating()
93 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | in skl_init_clock_gating()
102 tmp = I915_READ(CLKCFG); in i915_pineview_get_mem_freq()
132 tmp = I915_READ(CSHRDDR3CTL); in i915_pineview_get_mem_freq()
319 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; in intel_set_memory_cxsr()
367 dsparb = I915_READ(DSPARB); in vlv_get_fifo_size()
368 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
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Dintel_lvds.c83 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_hw_state()
109 tmp = I915_READ(lvds_reg); in intel_lvds_get_config()
123 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
155 temp = I915_READ(lvds_encoder->reg); in intel_pre_enable_lvds()
228 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); in intel_enable_lvds()
232 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) in intel_enable_lvds()
257 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); in intel_disable_lvds()
258 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) in intel_disable_lvds()
261 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds()
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Dintel_runtime_pm.c73 return I915_READ(HSW_PWR_WELL_DRIVER) == in hsw_power_well_enabled()
238 tmp = I915_READ(HSW_PWR_WELL_DRIVER); in hsw_set_power_well()
249 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & in hsw_set_power_well()
329 tmp = I915_READ(HSW_PWR_WELL_DRIVER); in skl_set_power_well()
330 fuse_status = I915_READ(SKL_FUSE_STATUS); in skl_set_power_well()
334 if (wait_for((I915_READ(SKL_FUSE_STATUS) & in skl_set_power_well()
369 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & in skl_set_power_well()
385 if (wait_for((I915_READ(SKL_FUSE_STATUS) & in skl_set_power_well()
389 if (wait_for((I915_READ(SKL_FUSE_STATUS) & in skl_set_power_well()
408 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) in hsw_power_well_sync_hw()
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Dintel_panel.c489 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in bdw_get_backlight()
497 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
507 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
528 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
563 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in bdw_set_backlight()
573 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
601 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
615 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
704 tmp = I915_READ(BLC_PWM_CPU_CTL2); in pch_disable_backlight()
707 tmp = I915_READ(BLC_PWM_PCH_CTL1); in pch_disable_backlight()
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Di915_vgpu.c191 mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); in intel_vgt_balloon()
192 mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); in intel_vgt_balloon()
193 unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); in intel_vgt_balloon()
194 unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); in intel_vgt_balloon()
Dintel_dvo.c121 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
137 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
154 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
174 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
178 I915_READ(dvo_reg); in intel_disable_dvo()
187 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
194 I915_READ(dvo_reg); in intel_enable_dvo()
319 dvo_val = I915_READ(dvo_reg) & in intel_dvo_pre_enable()
433 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_current_mode()
Dintel_fbc.c52 fbc_ctl = I915_READ(FBC_CONTROL); in i8xx_fbc_disable()
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { in i8xx_fbc_disable()
107 fbc_ctl = I915_READ(FBC_CONTROL); in i8xx_fbc_enable()
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN; in i8xx_fbc_enabled()
161 dpfc_ctl = I915_READ(DPFC_CONTROL); in g4x_fbc_disable()
174 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; in g4x_fbc_enabled()
238 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); in ilk_fbc_disable()
251 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; in ilk_fbc_enabled()
292 I915_READ(ILK_DISPLAY_CHICKEN1) | in gen7_fbc_enable()
297 I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | in gen7_fbc_enable()
Dintel_ringbuffer.h32 #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
35 #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
38 #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
41 #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
44 #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
47 #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base))
Dintel_fifo_underrun.c108 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_check_fifo_underruns()
127 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_set_fifo_underrun_reporting()
169 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivybridge_set_fifo_underrun_reporting()
222 if (old && I915_READ(SERR_INT) & in cpt_set_fifo_underrun_reporting()
Dintel_hdmi.c55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
140 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
175 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframe_enabled()
192 u32 val = I915_READ(reg); in ibx_write_infoframe()
227 u32 val = I915_READ(reg); in ibx_infoframe_enabled()
241 u32 val = I915_READ(reg); in cpt_write_infoframe()
279 u32 val = I915_READ(reg); in cpt_infoframe_enabled()
293 u32 val = I915_READ(reg); in vlv_write_infoframe()
328 u32 val = I915_READ(reg); in vlv_infoframe_enabled()
344 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
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Di915_gem_tiling.c106 if (I915_READ(DISP_ARB_CTL) & in i915_gem_detect_bit_6_swizzle()
116 dimm_c0 = I915_READ(MAD_DIMM_C0); in i915_gem_detect_bit_6_swizzle()
117 dimm_c1 = I915_READ(MAD_DIMM_C1); in i915_gem_detect_bit_6_swizzle()
156 dcc = I915_READ(DCC); in i915_gem_detect_bit_6_swizzle()
184 uint32_t ddc2 = I915_READ(DCC2); in i915_gem_detect_bit_6_swizzle()
Dintel_overlay.c279 tmp = I915_READ(DOVSTA); in intel_overlay_continue()
405 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { in intel_overlay_release_old_vid()
870 u32 pfit_control = I915_READ(PFIT_CONTROL); in update_pfit_vscale_ratio()
878 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; in update_pfit_vscale_ratio()
881 ratio = I915_READ(PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
883 ratio = I915_READ(PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1043 pfit_control = I915_READ(PFIT_CONTROL); in intel_panel_fitter_pipe()
1281 attrs->gamma0 = I915_READ(OGAMC0); in intel_overlay_attrs()
1282 attrs->gamma1 = I915_READ(OGAMC1); in intel_overlay_attrs()
1283 attrs->gamma2 = I915_READ(OGAMC2); in intel_overlay_attrs()
[all …]
Dintel_dp.c262 clkcfg = I915_READ(CLKCFG); in intel_hrawclk()
334 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
345 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
355 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
454 return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON; in vlv_pipe_has_pp_on()
460 return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD; in vlv_pipe_has_vdd_on()
477 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
600 pp_div = I915_READ(pp_div_reg); in edp_notify_handler()
625 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
639 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
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Dintel_tv.c842 u32 tmp = I915_READ(TV_CTL); in intel_tv_get_hw_state()
862 I915_WRITE(TV_CTL, I915_READ(TV_CTL) | TV_ENC_ENABLE); in intel_enable_tv()
871 I915_WRITE(TV_CTL, I915_READ(TV_CTL) & ~TV_ENC_ENABLE); in intel_disable_tv()
1040 tv_ctl = I915_READ(TV_CTL); in intel_tv_pre_enable()
1148 I915_WRITE(TV_DAC, I915_READ(TV_DAC) & TV_DAC_SAVE); in intel_tv_pre_enable()
1199 save_tv_dac = tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1200 save_tv_ctl = tv_ctl = I915_READ(TV_CTL); in intel_tv_detect_type()
1237 tv_dac = I915_READ(TV_DAC); in intel_tv_detect_type()
1585 if ((I915_READ(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) in intel_tv_init()
1600 save_tv_dac = I915_READ(TV_DAC); in intel_tv_init()
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Dintel_frontbuffer.c81 dpll = I915_READ(dpll_reg); in intel_increase_pllclock()
91 dpll = I915_READ(dpll_reg); in intel_increase_pllclock()
Di915_dma.c601 u32 fuse_strap = I915_READ(FUSE_STRAP); in intel_device_info_runtime_init()
602 u32 sfuse_strap = I915_READ(SFUSE_STRAP); in intel_device_info_runtime_init()
626 fuse = I915_READ(CHV_FUSE_GT); in intel_device_info_runtime_init()
665 fuse2 = I915_READ(GEN8_FUSE2); in intel_device_info_runtime_init()
671 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0); in intel_device_info_runtime_init()
672 eu_disable[1] = I915_READ(GEN8_EU_DISABLE1); in intel_device_info_runtime_init()
673 eu_disable[2] = I915_READ(GEN8_EU_DISABLE2); in intel_device_info_runtime_init()
Di915_gem_stolen.c87 gtt_start = I915_READ(PGTBL_CTL); in i915_stolen_to_physical()
317 tmp = I915_READ(GEN7_BIOS_RESERVED); in i915_gem_init_stolen()
322 tmp = I915_READ(GEN7_BIOS_RESERVED); in i915_gem_init_stolen()
Di915_sysfs.c59 czcount_30ns = I915_READ(clk_reg) >> CLK_CTL2_CZCOUNT_30NS_SHIFT; in calc_residency()
85 if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) in calc_residency()
91 raw_time = I915_READ(reg) * units; in calc_residency()
321 u32 rpstat = I915_READ(GEN6_RPSTAT1); in gt_act_freq_mhz_show()
Dintel_dp_mst.c199 temp = I915_READ(DP_TP_STATUS(port)); in intel_mst_pre_enable_dp()
217 if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT), in intel_mst_enable_dp()
249 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_dp_mst_enc_get_config()
Dintel_sdvo.c245 I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_write_sdvox()
250 cval = I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
252 bval = I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
262 I915_READ(GEN3_SDVOB); in intel_sdvo_write_sdvox()
264 I915_READ(GEN3_SDVOC); in intel_sdvo_write_sdvox()
1268 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_pre_enable()
1327 tmp = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_hw_state()
1354 sdvox = I915_READ(intel_sdvo->sdvo_reg); in intel_sdvo_get_config()
1439 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_disable_sdvo()
1480 temp = I915_READ(intel_sdvo->sdvo_reg); in intel_enable_sdvo()
Dintel_uncore.c1258 reg->val = I915_READ(offset); in i915_reg_read_ioctl()
1357 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1367 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); in g4x_do_reset()
1382 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & in ironlake_do_reset()
1389 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & in ironlake_do_reset()
Dintel_i2c.c78 val = I915_READ(DSPCLK_GATE_D); in intel_i2c_quirk_set()
294 val = I915_READ(GMBUS3 + reg_offset); in gmbus_xfer_read_chunk()
Di915_gem_context.c116 reg = I915_READ(CXT_SIZE); in get_context_size()
120 reg = I915_READ(GEN7_CXT_SIZE); in get_context_size()
Di915_gem_gtt.c1056 ecobits = I915_READ(GAC_ECO_BITS); in gen7_ppgtt_enable()
1059 ecochk = I915_READ(GAM_ECOCHK); in gen7_ppgtt_enable()
1080 ecobits = I915_READ(GAC_ECO_BITS); in gen6_ppgtt_enable()
1084 gab_ctl = I915_READ(GAB_CTL); in gen6_ppgtt_enable()
1087 ecochk = I915_READ(GAM_ECOCHK); in gen6_ppgtt_enable()
1608 fault_reg = I915_READ(RING_FAULT_REG(ring)); in i915_check_and_clear_faults()
Dintel_ringbuffer.c456 acthd = I915_READ(RING_ACTHD(ring->mmio_base)); in intel_ring_get_active_head()
458 acthd = I915_READ(ACTHD); in intel_ring_get_active_head()
529 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, in intel_ring_setup_status_page()
795 #define WA_SET_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) | (mask))
796 #define WA_CLR_BIT(addr, mask) WA_REG(addr, mask, I915_READ(addr) & ~(mask))
2317 if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & in gen6_bsd_ring_write_tail()
Dintel_sprite.c174 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); in intel_update_primary_plane()
176 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); in intel_update_primary_plane()
644 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE); in ivb_disable_plane()
Dintel_bios.c1324 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { in intel_setup_bios()
Dintel_lrc.c474 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); in intel_lrc_irq_handler()
485 status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + in intel_lrc_irq_handler()
487 status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + in intel_lrc_irq_handler()
Di915_gem.c4666 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in i915_gem_init_swizzling()
4672 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); in i915_gem_init_swizzling()
4793 I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); in i915_gem_init_hw()
4801 u32 temp = I915_READ(GEN7_MSG_CTL); in i915_gem_init_hw()
4805 u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); in i915_gem_init_hw()
4862 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & in i915_gem_init()
4989 I915_READ(vgtif_reg(avail_rs.fence_num)); in i915_gem_load()
Di915_drv.h3178 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) macro
3194 upper = I915_READ(upper_reg); \
3197 lower = I915_READ(lower_reg); \
3198 upper = I915_READ(upper_reg); \