1/* 2 * Copyright © 2010 Daniel Vetter 3 * Copyright © 2011-2014 Intel Corporation 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 * 24 */ 25 26#include <linux/seq_file.h> 27#include <drm/drmP.h> 28#include <drm/i915_drm.h> 29#include "i915_drv.h" 30#include "i915_vgpu.h" 31#include "i915_trace.h" 32#include "intel_drv.h" 33 34/** 35 * DOC: Global GTT views 36 * 37 * Background and previous state 38 * 39 * Historically objects could exists (be bound) in global GTT space only as 40 * singular instances with a view representing all of the object's backing pages 41 * in a linear fashion. This view will be called a normal view. 42 * 43 * To support multiple views of the same object, where the number of mapped 44 * pages is not equal to the backing store, or where the layout of the pages 45 * is not linear, concept of a GGTT view was added. 46 * 47 * One example of an alternative view is a stereo display driven by a single 48 * image. In this case we would have a framebuffer looking like this 49 * (2x2 pages): 50 * 51 * 12 52 * 34 53 * 54 * Above would represent a normal GGTT view as normally mapped for GPU or CPU 55 * rendering. In contrast, fed to the display engine would be an alternative 56 * view which could look something like this: 57 * 58 * 1212 59 * 3434 60 * 61 * In this example both the size and layout of pages in the alternative view is 62 * different from the normal view. 63 * 64 * Implementation and usage 65 * 66 * GGTT views are implemented using VMAs and are distinguished via enum 67 * i915_ggtt_view_type and struct i915_ggtt_view. 68 * 69 * A new flavour of core GEM functions which work with GGTT bound objects were 70 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid 71 * renaming in large amounts of code. They take the struct i915_ggtt_view 72 * parameter encapsulating all metadata required to implement a view. 73 * 74 * As a helper for callers which are only interested in the normal view, 75 * globally const i915_ggtt_view_normal singleton instance exists. All old core 76 * GEM API functions, the ones not taking the view parameter, are operating on, 77 * or with the normal GGTT view. 78 * 79 * Code wanting to add or use a new GGTT view needs to: 80 * 81 * 1. Add a new enum with a suitable name. 82 * 2. Extend the metadata in the i915_ggtt_view structure if required. 83 * 3. Add support to i915_get_vma_pages(). 84 * 85 * New views are required to build a scatter-gather table from within the 86 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and 87 * exists for the lifetime of an VMA. 88 * 89 * Core API is designed to have copy semantics which means that passed in 90 * struct i915_ggtt_view does not need to be persistent (left around after 91 * calling the core API functions). 92 * 93 */ 94 95const struct i915_ggtt_view i915_ggtt_view_normal; 96const struct i915_ggtt_view i915_ggtt_view_rotated = { 97 .type = I915_GGTT_VIEW_ROTATED 98}; 99 100static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv); 101static void chv_setup_private_ppat(struct drm_i915_private *dev_priv); 102 103static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) 104{ 105 bool has_aliasing_ppgtt; 106 bool has_full_ppgtt; 107 108 has_aliasing_ppgtt = INTEL_INFO(dev)->gen >= 6; 109 has_full_ppgtt = INTEL_INFO(dev)->gen >= 7; 110 111 if (intel_vgpu_active(dev)) 112 has_full_ppgtt = false; /* emulation is too hard */ 113 114 /* 115 * We don't allow disabling PPGTT for gen9+ as it's a requirement for 116 * execlists, the sole mechanism available to submit work. 117 */ 118 if (INTEL_INFO(dev)->gen < 9 && 119 (enable_ppgtt == 0 || !has_aliasing_ppgtt)) 120 return 0; 121 122 if (enable_ppgtt == 1) 123 return 1; 124 125 if (enable_ppgtt == 2 && has_full_ppgtt) 126 return 2; 127 128#ifdef CONFIG_INTEL_IOMMU 129 /* Disable ppgtt on SNB if VT-d is on. */ 130 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { 131 DRM_INFO("Disabling PPGTT because VT-d is on\n"); 132 return 0; 133 } 134#endif 135 136 /* Early VLV doesn't have this */ 137 if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && 138 dev->pdev->revision < 0xb) { 139 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n"); 140 return 0; 141 } 142 143 if (INTEL_INFO(dev)->gen >= 8 && i915.enable_execlists) 144 return 2; 145 else 146 return has_aliasing_ppgtt ? 1 : 0; 147} 148 149static void ppgtt_bind_vma(struct i915_vma *vma, 150 enum i915_cache_level cache_level, 151 u32 flags); 152static void ppgtt_unbind_vma(struct i915_vma *vma); 153 154static inline gen8_pte_t gen8_pte_encode(dma_addr_t addr, 155 enum i915_cache_level level, 156 bool valid) 157{ 158 gen8_pte_t pte = valid ? _PAGE_PRESENT | _PAGE_RW : 0; 159 pte |= addr; 160 161 switch (level) { 162 case I915_CACHE_NONE: 163 pte |= PPAT_UNCACHED_INDEX; 164 break; 165 case I915_CACHE_WT: 166 pte |= PPAT_DISPLAY_ELLC_INDEX; 167 break; 168 default: 169 pte |= PPAT_CACHED_INDEX; 170 break; 171 } 172 173 return pte; 174} 175 176static inline gen8_pde_t gen8_pde_encode(struct drm_device *dev, 177 dma_addr_t addr, 178 enum i915_cache_level level) 179{ 180 gen8_pde_t pde = _PAGE_PRESENT | _PAGE_RW; 181 pde |= addr; 182 if (level != I915_CACHE_NONE) 183 pde |= PPAT_CACHED_PDE_INDEX; 184 else 185 pde |= PPAT_UNCACHED_INDEX; 186 return pde; 187} 188 189static gen6_pte_t snb_pte_encode(dma_addr_t addr, 190 enum i915_cache_level level, 191 bool valid, u32 unused) 192{ 193 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 194 pte |= GEN6_PTE_ADDR_ENCODE(addr); 195 196 switch (level) { 197 case I915_CACHE_L3_LLC: 198 case I915_CACHE_LLC: 199 pte |= GEN6_PTE_CACHE_LLC; 200 break; 201 case I915_CACHE_NONE: 202 pte |= GEN6_PTE_UNCACHED; 203 break; 204 default: 205 MISSING_CASE(level); 206 } 207 208 return pte; 209} 210 211static gen6_pte_t ivb_pte_encode(dma_addr_t addr, 212 enum i915_cache_level level, 213 bool valid, u32 unused) 214{ 215 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 216 pte |= GEN6_PTE_ADDR_ENCODE(addr); 217 218 switch (level) { 219 case I915_CACHE_L3_LLC: 220 pte |= GEN7_PTE_CACHE_L3_LLC; 221 break; 222 case I915_CACHE_LLC: 223 pte |= GEN6_PTE_CACHE_LLC; 224 break; 225 case I915_CACHE_NONE: 226 pte |= GEN6_PTE_UNCACHED; 227 break; 228 default: 229 MISSING_CASE(level); 230 } 231 232 return pte; 233} 234 235static gen6_pte_t byt_pte_encode(dma_addr_t addr, 236 enum i915_cache_level level, 237 bool valid, u32 flags) 238{ 239 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 240 pte |= GEN6_PTE_ADDR_ENCODE(addr); 241 242 if (!(flags & PTE_READ_ONLY)) 243 pte |= BYT_PTE_WRITEABLE; 244 245 if (level != I915_CACHE_NONE) 246 pte |= BYT_PTE_SNOOPED_BY_CPU_CACHES; 247 248 return pte; 249} 250 251static gen6_pte_t hsw_pte_encode(dma_addr_t addr, 252 enum i915_cache_level level, 253 bool valid, u32 unused) 254{ 255 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 256 pte |= HSW_PTE_ADDR_ENCODE(addr); 257 258 if (level != I915_CACHE_NONE) 259 pte |= HSW_WB_LLC_AGE3; 260 261 return pte; 262} 263 264static gen6_pte_t iris_pte_encode(dma_addr_t addr, 265 enum i915_cache_level level, 266 bool valid, u32 unused) 267{ 268 gen6_pte_t pte = valid ? GEN6_PTE_VALID : 0; 269 pte |= HSW_PTE_ADDR_ENCODE(addr); 270 271 switch (level) { 272 case I915_CACHE_NONE: 273 break; 274 case I915_CACHE_WT: 275 pte |= HSW_WT_ELLC_LLC_AGE3; 276 break; 277 default: 278 pte |= HSW_WB_ELLC_LLC_AGE3; 279 break; 280 } 281 282 return pte; 283} 284 285#define i915_dma_unmap_single(px, dev) \ 286 __i915_dma_unmap_single((px)->daddr, dev) 287 288static inline void __i915_dma_unmap_single(dma_addr_t daddr, 289 struct drm_device *dev) 290{ 291 struct device *device = &dev->pdev->dev; 292 293 dma_unmap_page(device, daddr, 4096, PCI_DMA_BIDIRECTIONAL); 294} 295 296/** 297 * i915_dma_map_single() - Create a dma mapping for a page table/dir/etc. 298 * @px: Page table/dir/etc to get a DMA map for 299 * @dev: drm device 300 * 301 * Page table allocations are unified across all gens. They always require a 302 * single 4k allocation, as well as a DMA mapping. If we keep the structs 303 * symmetric here, the simple macro covers us for every page table type. 304 * 305 * Return: 0 if success. 306 */ 307#define i915_dma_map_single(px, dev) \ 308 i915_dma_map_page_single((px)->page, (dev), &(px)->daddr) 309 310static inline int i915_dma_map_page_single(struct page *page, 311 struct drm_device *dev, 312 dma_addr_t *daddr) 313{ 314 struct device *device = &dev->pdev->dev; 315 316 *daddr = dma_map_page(device, page, 0, 4096, PCI_DMA_BIDIRECTIONAL); 317 if (dma_mapping_error(device, *daddr)) 318 return -ENOMEM; 319 320 return 0; 321} 322 323static void unmap_and_free_pt(struct i915_page_table_entry *pt, 324 struct drm_device *dev) 325{ 326 if (WARN_ON(!pt->page)) 327 return; 328 329 i915_dma_unmap_single(pt, dev); 330 __free_page(pt->page); 331 kfree(pt->used_ptes); 332 kfree(pt); 333} 334 335static struct i915_page_table_entry *alloc_pt_single(struct drm_device *dev) 336{ 337 struct i915_page_table_entry *pt; 338 const size_t count = INTEL_INFO(dev)->gen >= 8 ? 339 GEN8_PTES : GEN6_PTES; 340 int ret = -ENOMEM; 341 342 pt = kzalloc(sizeof(*pt), GFP_KERNEL); 343 if (!pt) 344 return ERR_PTR(-ENOMEM); 345 346 pt->used_ptes = kcalloc(BITS_TO_LONGS(count), sizeof(*pt->used_ptes), 347 GFP_KERNEL); 348 349 if (!pt->used_ptes) 350 goto fail_bitmap; 351 352 pt->page = alloc_page(GFP_KERNEL); 353 if (!pt->page) 354 goto fail_page; 355 356 ret = i915_dma_map_single(pt, dev); 357 if (ret) 358 goto fail_dma; 359 360 return pt; 361 362fail_dma: 363 __free_page(pt->page); 364fail_page: 365 kfree(pt->used_ptes); 366fail_bitmap: 367 kfree(pt); 368 369 return ERR_PTR(ret); 370} 371 372/** 373 * alloc_pt_range() - Allocate a multiple page tables 374 * @pd: The page directory which will have at least @count entries 375 * available to point to the allocated page tables. 376 * @pde: First page directory entry for which we are allocating. 377 * @count: Number of pages to allocate. 378 * @dev: DRM device. 379 * 380 * Allocates multiple page table pages and sets the appropriate entries in the 381 * page table structure within the page directory. Function cleans up after 382 * itself on any failures. 383 * 384 * Return: 0 if allocation succeeded. 385 */ 386static int alloc_pt_range(struct i915_page_directory_entry *pd, uint16_t pde, size_t count, 387 struct drm_device *dev) 388{ 389 int i, ret; 390 391 /* 512 is the max page tables per page_directory on any platform. */ 392 if (WARN_ON(pde + count > I915_PDES)) 393 return -EINVAL; 394 395 for (i = pde; i < pde + count; i++) { 396 struct i915_page_table_entry *pt = alloc_pt_single(dev); 397 398 if (IS_ERR(pt)) { 399 ret = PTR_ERR(pt); 400 goto err_out; 401 } 402 WARN(pd->page_table[i], 403 "Leaking page directory entry %d (%p)\n", 404 i, pd->page_table[i]); 405 pd->page_table[i] = pt; 406 } 407 408 return 0; 409 410err_out: 411 while (i-- > pde) 412 unmap_and_free_pt(pd->page_table[i], dev); 413 return ret; 414} 415 416static void unmap_and_free_pd(struct i915_page_directory_entry *pd) 417{ 418 if (pd->page) { 419 __free_page(pd->page); 420 kfree(pd); 421 } 422} 423 424static struct i915_page_directory_entry *alloc_pd_single(void) 425{ 426 struct i915_page_directory_entry *pd; 427 428 pd = kzalloc(sizeof(*pd), GFP_KERNEL); 429 if (!pd) 430 return ERR_PTR(-ENOMEM); 431 432 pd->page = alloc_page(GFP_KERNEL | __GFP_ZERO); 433 if (!pd->page) { 434 kfree(pd); 435 return ERR_PTR(-ENOMEM); 436 } 437 438 return pd; 439} 440 441/* Broadwell Page Directory Pointer Descriptors */ 442static int gen8_write_pdp(struct intel_engine_cs *ring, unsigned entry, 443 uint64_t val) 444{ 445 int ret; 446 447 BUG_ON(entry >= 4); 448 449 ret = intel_ring_begin(ring, 6); 450 if (ret) 451 return ret; 452 453 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 454 intel_ring_emit(ring, GEN8_RING_PDP_UDW(ring, entry)); 455 intel_ring_emit(ring, (u32)(val >> 32)); 456 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 457 intel_ring_emit(ring, GEN8_RING_PDP_LDW(ring, entry)); 458 intel_ring_emit(ring, (u32)(val)); 459 intel_ring_advance(ring); 460 461 return 0; 462} 463 464static int gen8_mm_switch(struct i915_hw_ppgtt *ppgtt, 465 struct intel_engine_cs *ring) 466{ 467 int i, ret; 468 469 /* bit of a hack to find the actual last used pd */ 470 int used_pd = ppgtt->num_pd_entries / I915_PDES; 471 472 for (i = used_pd - 1; i >= 0; i--) { 473 dma_addr_t addr = ppgtt->pdp.page_directory[i]->daddr; 474 ret = gen8_write_pdp(ring, i, addr); 475 if (ret) 476 return ret; 477 } 478 479 return 0; 480} 481 482static void gen8_ppgtt_clear_range(struct i915_address_space *vm, 483 uint64_t start, 484 uint64_t length, 485 bool use_scratch) 486{ 487 struct i915_hw_ppgtt *ppgtt = 488 container_of(vm, struct i915_hw_ppgtt, base); 489 gen8_pte_t *pt_vaddr, scratch_pte; 490 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; 491 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; 492 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; 493 unsigned num_entries = length >> PAGE_SHIFT; 494 unsigned last_pte, i; 495 496 scratch_pte = gen8_pte_encode(ppgtt->base.scratch.addr, 497 I915_CACHE_LLC, use_scratch); 498 499 while (num_entries) { 500 struct i915_page_directory_entry *pd; 501 struct i915_page_table_entry *pt; 502 struct page *page_table; 503 504 if (WARN_ON(!ppgtt->pdp.page_directory[pdpe])) 505 break; 506 507 pd = ppgtt->pdp.page_directory[pdpe]; 508 509 if (WARN_ON(!pd->page_table[pde])) 510 break; 511 512 pt = pd->page_table[pde]; 513 514 if (WARN_ON(!pt->page)) 515 break; 516 517 page_table = pt->page; 518 519 last_pte = pte + num_entries; 520 if (last_pte > GEN8_PTES) 521 last_pte = GEN8_PTES; 522 523 pt_vaddr = kmap_atomic(page_table); 524 525 for (i = pte; i < last_pte; i++) { 526 pt_vaddr[i] = scratch_pte; 527 num_entries--; 528 } 529 530 if (!HAS_LLC(ppgtt->base.dev)) 531 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); 532 kunmap_atomic(pt_vaddr); 533 534 pte = 0; 535 if (++pde == I915_PDES) { 536 pdpe++; 537 pde = 0; 538 } 539 } 540} 541 542static void gen8_ppgtt_insert_entries(struct i915_address_space *vm, 543 struct sg_table *pages, 544 uint64_t start, 545 enum i915_cache_level cache_level, u32 unused) 546{ 547 struct i915_hw_ppgtt *ppgtt = 548 container_of(vm, struct i915_hw_ppgtt, base); 549 gen8_pte_t *pt_vaddr; 550 unsigned pdpe = start >> GEN8_PDPE_SHIFT & GEN8_PDPE_MASK; 551 unsigned pde = start >> GEN8_PDE_SHIFT & GEN8_PDE_MASK; 552 unsigned pte = start >> GEN8_PTE_SHIFT & GEN8_PTE_MASK; 553 struct sg_page_iter sg_iter; 554 555 pt_vaddr = NULL; 556 557 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { 558 if (WARN_ON(pdpe >= GEN8_LEGACY_PDPES)) 559 break; 560 561 if (pt_vaddr == NULL) { 562 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[pdpe]; 563 struct i915_page_table_entry *pt = pd->page_table[pde]; 564 struct page *page_table = pt->page; 565 566 pt_vaddr = kmap_atomic(page_table); 567 } 568 569 pt_vaddr[pte] = 570 gen8_pte_encode(sg_page_iter_dma_address(&sg_iter), 571 cache_level, true); 572 if (++pte == GEN8_PTES) { 573 if (!HAS_LLC(ppgtt->base.dev)) 574 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); 575 kunmap_atomic(pt_vaddr); 576 pt_vaddr = NULL; 577 if (++pde == I915_PDES) { 578 pdpe++; 579 pde = 0; 580 } 581 pte = 0; 582 } 583 } 584 if (pt_vaddr) { 585 if (!HAS_LLC(ppgtt->base.dev)) 586 drm_clflush_virt_range(pt_vaddr, PAGE_SIZE); 587 kunmap_atomic(pt_vaddr); 588 } 589} 590 591static void gen8_free_page_tables(struct i915_page_directory_entry *pd, struct drm_device *dev) 592{ 593 int i; 594 595 if (!pd->page) 596 return; 597 598 for (i = 0; i < I915_PDES; i++) { 599 if (WARN_ON(!pd->page_table[i])) 600 continue; 601 602 unmap_and_free_pt(pd->page_table[i], dev); 603 pd->page_table[i] = NULL; 604 } 605} 606 607static void gen8_ppgtt_free(struct i915_hw_ppgtt *ppgtt) 608{ 609 int i; 610 611 for (i = 0; i < ppgtt->num_pd_pages; i++) { 612 if (WARN_ON(!ppgtt->pdp.page_directory[i])) 613 continue; 614 615 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); 616 unmap_and_free_pd(ppgtt->pdp.page_directory[i]); 617 } 618} 619 620static void gen8_ppgtt_unmap_pages(struct i915_hw_ppgtt *ppgtt) 621{ 622 struct pci_dev *hwdev = ppgtt->base.dev->pdev; 623 int i, j; 624 625 for (i = 0; i < ppgtt->num_pd_pages; i++) { 626 /* TODO: In the future we'll support sparse mappings, so this 627 * will have to change. */ 628 if (!ppgtt->pdp.page_directory[i]->daddr) 629 continue; 630 631 pci_unmap_page(hwdev, ppgtt->pdp.page_directory[i]->daddr, PAGE_SIZE, 632 PCI_DMA_BIDIRECTIONAL); 633 634 for (j = 0; j < I915_PDES; j++) { 635 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; 636 struct i915_page_table_entry *pt; 637 dma_addr_t addr; 638 639 if (WARN_ON(!pd->page_table[j])) 640 continue; 641 642 pt = pd->page_table[j]; 643 addr = pt->daddr; 644 645 if (addr) 646 pci_unmap_page(hwdev, addr, PAGE_SIZE, 647 PCI_DMA_BIDIRECTIONAL); 648 } 649 } 650} 651 652static void gen8_ppgtt_cleanup(struct i915_address_space *vm) 653{ 654 struct i915_hw_ppgtt *ppgtt = 655 container_of(vm, struct i915_hw_ppgtt, base); 656 657 gen8_ppgtt_unmap_pages(ppgtt); 658 gen8_ppgtt_free(ppgtt); 659} 660 661static int gen8_ppgtt_allocate_page_tables(struct i915_hw_ppgtt *ppgtt) 662{ 663 int i, ret; 664 665 for (i = 0; i < ppgtt->num_pd_pages; i++) { 666 ret = alloc_pt_range(ppgtt->pdp.page_directory[i], 667 0, I915_PDES, ppgtt->base.dev); 668 if (ret) 669 goto unwind_out; 670 } 671 672 return 0; 673 674unwind_out: 675 while (i--) 676 gen8_free_page_tables(ppgtt->pdp.page_directory[i], ppgtt->base.dev); 677 678 return -ENOMEM; 679} 680 681static int gen8_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt, 682 const int max_pdp) 683{ 684 int i; 685 686 for (i = 0; i < max_pdp; i++) { 687 ppgtt->pdp.page_directory[i] = alloc_pd_single(); 688 if (IS_ERR(ppgtt->pdp.page_directory[i])) 689 goto unwind_out; 690 } 691 692 ppgtt->num_pd_pages = max_pdp; 693 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPES); 694 695 return 0; 696 697unwind_out: 698 while (i--) 699 unmap_and_free_pd(ppgtt->pdp.page_directory[i]); 700 701 return -ENOMEM; 702} 703 704static int gen8_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt, 705 const int max_pdp) 706{ 707 int ret; 708 709 ret = gen8_ppgtt_allocate_page_directories(ppgtt, max_pdp); 710 if (ret) 711 return ret; 712 713 ret = gen8_ppgtt_allocate_page_tables(ppgtt); 714 if (ret) 715 goto err_out; 716 717 ppgtt->num_pd_entries = max_pdp * I915_PDES; 718 719 return 0; 720 721err_out: 722 gen8_ppgtt_free(ppgtt); 723 return ret; 724} 725 726static int gen8_ppgtt_setup_page_directories(struct i915_hw_ppgtt *ppgtt, 727 const int pd) 728{ 729 dma_addr_t pd_addr; 730 int ret; 731 732 pd_addr = pci_map_page(ppgtt->base.dev->pdev, 733 ppgtt->pdp.page_directory[pd]->page, 0, 734 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 735 736 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pd_addr); 737 if (ret) 738 return ret; 739 740 ppgtt->pdp.page_directory[pd]->daddr = pd_addr; 741 742 return 0; 743} 744 745static int gen8_ppgtt_setup_page_tables(struct i915_hw_ppgtt *ppgtt, 746 const int pd, 747 const int pt) 748{ 749 dma_addr_t pt_addr; 750 struct i915_page_directory_entry *pdir = ppgtt->pdp.page_directory[pd]; 751 struct i915_page_table_entry *ptab = pdir->page_table[pt]; 752 struct page *p = ptab->page; 753 int ret; 754 755 pt_addr = pci_map_page(ppgtt->base.dev->pdev, 756 p, 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 757 ret = pci_dma_mapping_error(ppgtt->base.dev->pdev, pt_addr); 758 if (ret) 759 return ret; 760 761 ptab->daddr = pt_addr; 762 763 return 0; 764} 765 766/* 767 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers 768 * with a net effect resembling a 2-level page table in normal x86 terms. Each 769 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address 770 * space. 771 * 772 * FIXME: split allocation into smaller pieces. For now we only ever do this 773 * once, but with full PPGTT, the multiple contiguous allocations will be bad. 774 * TODO: Do something with the size parameter 775 */ 776static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size) 777{ 778 const int max_pdp = DIV_ROUND_UP(size, 1 << 30); 779 const int min_pt_pages = I915_PDES * max_pdp; 780 int i, j, ret; 781 782 if (size % (1<<30)) 783 DRM_INFO("Pages will be wasted unless GTT size (%llu) is divisible by 1GB\n", size); 784 785 /* 1. Do all our allocations for page directories and page tables. 786 * We allocate more than was asked so that we can point the unused parts 787 * to valid entries that point to scratch page. Dynamic page tables 788 * will fix this eventually. 789 */ 790 ret = gen8_ppgtt_alloc(ppgtt, GEN8_LEGACY_PDPES); 791 if (ret) 792 return ret; 793 794 /* 795 * 2. Create DMA mappings for the page directories and page tables. 796 */ 797 for (i = 0; i < GEN8_LEGACY_PDPES; i++) { 798 ret = gen8_ppgtt_setup_page_directories(ppgtt, i); 799 if (ret) 800 goto bail; 801 802 for (j = 0; j < I915_PDES; j++) { 803 ret = gen8_ppgtt_setup_page_tables(ppgtt, i, j); 804 if (ret) 805 goto bail; 806 } 807 } 808 809 /* 810 * 3. Map all the page directory entires to point to the page tables 811 * we've allocated. 812 * 813 * For now, the PPGTT helper functions all require that the PDEs are 814 * plugged in correctly. So we do that now/here. For aliasing PPGTT, we 815 * will never need to touch the PDEs again. 816 */ 817 for (i = 0; i < GEN8_LEGACY_PDPES; i++) { 818 struct i915_page_directory_entry *pd = ppgtt->pdp.page_directory[i]; 819 gen8_pde_t *pd_vaddr; 820 pd_vaddr = kmap_atomic(ppgtt->pdp.page_directory[i]->page); 821 for (j = 0; j < I915_PDES; j++) { 822 struct i915_page_table_entry *pt = pd->page_table[j]; 823 dma_addr_t addr = pt->daddr; 824 pd_vaddr[j] = gen8_pde_encode(ppgtt->base.dev, addr, 825 I915_CACHE_LLC); 826 } 827 if (!HAS_LLC(ppgtt->base.dev)) 828 drm_clflush_virt_range(pd_vaddr, PAGE_SIZE); 829 kunmap_atomic(pd_vaddr); 830 } 831 832 ppgtt->switch_mm = gen8_mm_switch; 833 ppgtt->base.clear_range = gen8_ppgtt_clear_range; 834 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; 835 ppgtt->base.cleanup = gen8_ppgtt_cleanup; 836 ppgtt->base.start = 0; 837 838 /* This is the area that we advertise as usable for the caller */ 839 ppgtt->base.total = max_pdp * I915_PDES * GEN8_PTES * PAGE_SIZE; 840 841 /* Set all ptes to a valid scratch page. Also above requested space */ 842 ppgtt->base.clear_range(&ppgtt->base, 0, 843 ppgtt->num_pd_pages * GEN8_PTES * PAGE_SIZE, 844 true); 845 846 DRM_DEBUG_DRIVER("Allocated %d pages for page directories (%d wasted)\n", 847 ppgtt->num_pd_pages, ppgtt->num_pd_pages - max_pdp); 848 DRM_DEBUG_DRIVER("Allocated %d pages for page tables (%lld wasted)\n", 849 ppgtt->num_pd_entries, 850 (ppgtt->num_pd_entries - min_pt_pages) + size % (1<<30)); 851 return 0; 852 853bail: 854 gen8_ppgtt_unmap_pages(ppgtt); 855 gen8_ppgtt_free(ppgtt); 856 return ret; 857} 858 859static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, struct seq_file *m) 860{ 861 struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private; 862 struct i915_address_space *vm = &ppgtt->base; 863 gen6_pte_t __iomem *pd_addr; 864 gen6_pte_t scratch_pte; 865 uint32_t pd_entry; 866 int pte, pde; 867 868 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); 869 870 pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + 871 ppgtt->pd.pd_offset / sizeof(gen6_pte_t); 872 873 seq_printf(m, " VM %p (pd_offset %x-%x):\n", vm, 874 ppgtt->pd.pd_offset, 875 ppgtt->pd.pd_offset + ppgtt->num_pd_entries); 876 for (pde = 0; pde < ppgtt->num_pd_entries; pde++) { 877 u32 expected; 878 gen6_pte_t *pt_vaddr; 879 dma_addr_t pt_addr = ppgtt->pd.page_table[pde]->daddr; 880 pd_entry = readl(pd_addr + pde); 881 expected = (GEN6_PDE_ADDR_ENCODE(pt_addr) | GEN6_PDE_VALID); 882 883 if (pd_entry != expected) 884 seq_printf(m, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n", 885 pde, 886 pd_entry, 887 expected); 888 seq_printf(m, "\tPDE: %x\n", pd_entry); 889 890 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[pde]->page); 891 for (pte = 0; pte < GEN6_PTES; pte+=4) { 892 unsigned long va = 893 (pde * PAGE_SIZE * GEN6_PTES) + 894 (pte * PAGE_SIZE); 895 int i; 896 bool found = false; 897 for (i = 0; i < 4; i++) 898 if (pt_vaddr[pte + i] != scratch_pte) 899 found = true; 900 if (!found) 901 continue; 902 903 seq_printf(m, "\t\t0x%lx [%03d,%04d]: =", va, pde, pte); 904 for (i = 0; i < 4; i++) { 905 if (pt_vaddr[pte + i] != scratch_pte) 906 seq_printf(m, " %08x", pt_vaddr[pte + i]); 907 else 908 seq_puts(m, " SCRATCH "); 909 } 910 seq_puts(m, "\n"); 911 } 912 kunmap_atomic(pt_vaddr); 913 } 914} 915 916/* Write pde (index) from the page directory @pd to the page table @pt */ 917static void gen6_write_pde(struct i915_page_directory_entry *pd, 918 const int pde, struct i915_page_table_entry *pt) 919{ 920 /* Caller needs to make sure the write completes if necessary */ 921 struct i915_hw_ppgtt *ppgtt = 922 container_of(pd, struct i915_hw_ppgtt, pd); 923 u32 pd_entry; 924 925 pd_entry = GEN6_PDE_ADDR_ENCODE(pt->daddr); 926 pd_entry |= GEN6_PDE_VALID; 927 928 writel(pd_entry, ppgtt->pd_addr + pde); 929} 930 931/* Write all the page tables found in the ppgtt structure to incrementing page 932 * directories. */ 933static void gen6_write_page_range(struct drm_i915_private *dev_priv, 934 struct i915_page_directory_entry *pd, 935 uint32_t start, uint32_t length) 936{ 937 struct i915_page_table_entry *pt; 938 uint32_t pde, temp; 939 940 gen6_for_each_pde(pt, pd, start, length, temp, pde) 941 gen6_write_pde(pd, pde, pt); 942 943 /* Make sure write is complete before other code can use this page 944 * table. Also require for WC mapped PTEs */ 945 readl(dev_priv->gtt.gsm); 946} 947 948static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt) 949{ 950 BUG_ON(ppgtt->pd.pd_offset & 0x3f); 951 952 return (ppgtt->pd.pd_offset / 64) << 16; 953} 954 955static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt, 956 struct intel_engine_cs *ring) 957{ 958 int ret; 959 960 /* NB: TLBs must be flushed and invalidated before a switch */ 961 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 962 if (ret) 963 return ret; 964 965 ret = intel_ring_begin(ring, 6); 966 if (ret) 967 return ret; 968 969 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); 970 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); 971 intel_ring_emit(ring, PP_DIR_DCLV_2G); 972 intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); 973 intel_ring_emit(ring, get_pd_offset(ppgtt)); 974 intel_ring_emit(ring, MI_NOOP); 975 intel_ring_advance(ring); 976 977 return 0; 978} 979 980static int vgpu_mm_switch(struct i915_hw_ppgtt *ppgtt, 981 struct intel_engine_cs *ring) 982{ 983 struct drm_i915_private *dev_priv = to_i915(ppgtt->base.dev); 984 985 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 986 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); 987 return 0; 988} 989 990static int gen7_mm_switch(struct i915_hw_ppgtt *ppgtt, 991 struct intel_engine_cs *ring) 992{ 993 int ret; 994 995 /* NB: TLBs must be flushed and invalidated before a switch */ 996 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 997 if (ret) 998 return ret; 999 1000 ret = intel_ring_begin(ring, 6); 1001 if (ret) 1002 return ret; 1003 1004 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(2)); 1005 intel_ring_emit(ring, RING_PP_DIR_DCLV(ring)); 1006 intel_ring_emit(ring, PP_DIR_DCLV_2G); 1007 intel_ring_emit(ring, RING_PP_DIR_BASE(ring)); 1008 intel_ring_emit(ring, get_pd_offset(ppgtt)); 1009 intel_ring_emit(ring, MI_NOOP); 1010 intel_ring_advance(ring); 1011 1012 /* XXX: RCS is the only one to auto invalidate the TLBs? */ 1013 if (ring->id != RCS) { 1014 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); 1015 if (ret) 1016 return ret; 1017 } 1018 1019 return 0; 1020} 1021 1022static int gen6_mm_switch(struct i915_hw_ppgtt *ppgtt, 1023 struct intel_engine_cs *ring) 1024{ 1025 struct drm_device *dev = ppgtt->base.dev; 1026 struct drm_i915_private *dev_priv = dev->dev_private; 1027 1028 1029 I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); 1030 I915_WRITE(RING_PP_DIR_BASE(ring), get_pd_offset(ppgtt)); 1031 1032 POSTING_READ(RING_PP_DIR_DCLV(ring)); 1033 1034 return 0; 1035} 1036 1037static void gen8_ppgtt_enable(struct drm_device *dev) 1038{ 1039 struct drm_i915_private *dev_priv = dev->dev_private; 1040 struct intel_engine_cs *ring; 1041 int j; 1042 1043 for_each_ring(ring, dev_priv, j) { 1044 I915_WRITE(RING_MODE_GEN7(ring), 1045 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 1046 } 1047} 1048 1049static void gen7_ppgtt_enable(struct drm_device *dev) 1050{ 1051 struct drm_i915_private *dev_priv = dev->dev_private; 1052 struct intel_engine_cs *ring; 1053 uint32_t ecochk, ecobits; 1054 int i; 1055 1056 ecobits = I915_READ(GAC_ECO_BITS); 1057 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); 1058 1059 ecochk = I915_READ(GAM_ECOCHK); 1060 if (IS_HASWELL(dev)) { 1061 ecochk |= ECOCHK_PPGTT_WB_HSW; 1062 } else { 1063 ecochk |= ECOCHK_PPGTT_LLC_IVB; 1064 ecochk &= ~ECOCHK_PPGTT_GFDT_IVB; 1065 } 1066 I915_WRITE(GAM_ECOCHK, ecochk); 1067 1068 for_each_ring(ring, dev_priv, i) { 1069 /* GFX_MODE is per-ring on gen7+ */ 1070 I915_WRITE(RING_MODE_GEN7(ring), 1071 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 1072 } 1073} 1074 1075static void gen6_ppgtt_enable(struct drm_device *dev) 1076{ 1077 struct drm_i915_private *dev_priv = dev->dev_private; 1078 uint32_t ecochk, gab_ctl, ecobits; 1079 1080 ecobits = I915_READ(GAC_ECO_BITS); 1081 I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_SNB_BIT | 1082 ECOBITS_PPGTT_CACHE64B); 1083 1084 gab_ctl = I915_READ(GAB_CTL); 1085 I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); 1086 1087 ecochk = I915_READ(GAM_ECOCHK); 1088 I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | ECOCHK_PPGTT_CACHE64B); 1089 1090 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); 1091} 1092 1093/* PPGTT support for Sandybdrige/Gen6 and later */ 1094static void gen6_ppgtt_clear_range(struct i915_address_space *vm, 1095 uint64_t start, 1096 uint64_t length, 1097 bool use_scratch) 1098{ 1099 struct i915_hw_ppgtt *ppgtt = 1100 container_of(vm, struct i915_hw_ppgtt, base); 1101 gen6_pte_t *pt_vaddr, scratch_pte; 1102 unsigned first_entry = start >> PAGE_SHIFT; 1103 unsigned num_entries = length >> PAGE_SHIFT; 1104 unsigned act_pt = first_entry / GEN6_PTES; 1105 unsigned first_pte = first_entry % GEN6_PTES; 1106 unsigned last_pte, i; 1107 1108 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true, 0); 1109 1110 while (num_entries) { 1111 last_pte = first_pte + num_entries; 1112 if (last_pte > GEN6_PTES) 1113 last_pte = GEN6_PTES; 1114 1115 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); 1116 1117 for (i = first_pte; i < last_pte; i++) 1118 pt_vaddr[i] = scratch_pte; 1119 1120 kunmap_atomic(pt_vaddr); 1121 1122 num_entries -= last_pte - first_pte; 1123 first_pte = 0; 1124 act_pt++; 1125 } 1126} 1127 1128static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, 1129 struct sg_table *pages, 1130 uint64_t start, 1131 enum i915_cache_level cache_level, u32 flags) 1132{ 1133 struct i915_hw_ppgtt *ppgtt = 1134 container_of(vm, struct i915_hw_ppgtt, base); 1135 gen6_pte_t *pt_vaddr; 1136 unsigned first_entry = start >> PAGE_SHIFT; 1137 unsigned act_pt = first_entry / GEN6_PTES; 1138 unsigned act_pte = first_entry % GEN6_PTES; 1139 struct sg_page_iter sg_iter; 1140 1141 pt_vaddr = NULL; 1142 for_each_sg_page(pages->sgl, &sg_iter, pages->nents, 0) { 1143 if (pt_vaddr == NULL) 1144 pt_vaddr = kmap_atomic(ppgtt->pd.page_table[act_pt]->page); 1145 1146 pt_vaddr[act_pte] = 1147 vm->pte_encode(sg_page_iter_dma_address(&sg_iter), 1148 cache_level, true, flags); 1149 1150 if (++act_pte == GEN6_PTES) { 1151 kunmap_atomic(pt_vaddr); 1152 pt_vaddr = NULL; 1153 act_pt++; 1154 act_pte = 0; 1155 } 1156 } 1157 if (pt_vaddr) 1158 kunmap_atomic(pt_vaddr); 1159} 1160 1161/* PDE TLBs are a pain invalidate pre GEN8. It requires a context reload. If we 1162 * are switching between contexts with the same LRCA, we also must do a force 1163 * restore. 1164 */ 1165static inline void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt) 1166{ 1167 /* If current vm != vm, */ 1168 ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.dev)->ring_mask; 1169} 1170 1171static void gen6_initialize_pt(struct i915_address_space *vm, 1172 struct i915_page_table_entry *pt) 1173{ 1174 gen6_pte_t *pt_vaddr, scratch_pte; 1175 int i; 1176 1177 WARN_ON(vm->scratch.addr == 0); 1178 1179 scratch_pte = vm->pte_encode(vm->scratch.addr, 1180 I915_CACHE_LLC, true, 0); 1181 1182 pt_vaddr = kmap_atomic(pt->page); 1183 1184 for (i = 0; i < GEN6_PTES; i++) 1185 pt_vaddr[i] = scratch_pte; 1186 1187 kunmap_atomic(pt_vaddr); 1188} 1189 1190static int gen6_alloc_va_range(struct i915_address_space *vm, 1191 uint64_t start, uint64_t length) 1192{ 1193 DECLARE_BITMAP(new_page_tables, I915_PDES); 1194 struct drm_device *dev = vm->dev; 1195 struct drm_i915_private *dev_priv = dev->dev_private; 1196 struct i915_hw_ppgtt *ppgtt = 1197 container_of(vm, struct i915_hw_ppgtt, base); 1198 struct i915_page_table_entry *pt; 1199 const uint32_t start_save = start, length_save = length; 1200 uint32_t pde, temp; 1201 int ret; 1202 1203 WARN_ON(upper_32_bits(start)); 1204 1205 bitmap_zero(new_page_tables, I915_PDES); 1206 1207 /* The allocation is done in two stages so that we can bail out with 1208 * minimal amount of pain. The first stage finds new page tables that 1209 * need allocation. The second stage marks use ptes within the page 1210 * tables. 1211 */ 1212 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { 1213 if (pt != ppgtt->scratch_pt) { 1214 WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES)); 1215 continue; 1216 } 1217 1218 /* We've already allocated a page table */ 1219 WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES)); 1220 1221 pt = alloc_pt_single(dev); 1222 if (IS_ERR(pt)) { 1223 ret = PTR_ERR(pt); 1224 goto unwind_out; 1225 } 1226 1227 gen6_initialize_pt(vm, pt); 1228 1229 ppgtt->pd.page_table[pde] = pt; 1230 set_bit(pde, new_page_tables); 1231 trace_i915_page_table_entry_alloc(vm, pde, start, GEN6_PDE_SHIFT); 1232 } 1233 1234 start = start_save; 1235 length = length_save; 1236 1237 gen6_for_each_pde(pt, &ppgtt->pd, start, length, temp, pde) { 1238 DECLARE_BITMAP(tmp_bitmap, GEN6_PTES); 1239 1240 bitmap_zero(tmp_bitmap, GEN6_PTES); 1241 bitmap_set(tmp_bitmap, gen6_pte_index(start), 1242 gen6_pte_count(start, length)); 1243 1244 if (test_and_clear_bit(pde, new_page_tables)) 1245 gen6_write_pde(&ppgtt->pd, pde, pt); 1246 1247 trace_i915_page_table_entry_map(vm, pde, pt, 1248 gen6_pte_index(start), 1249 gen6_pte_count(start, length), 1250 GEN6_PTES); 1251 bitmap_or(pt->used_ptes, tmp_bitmap, pt->used_ptes, 1252 GEN6_PTES); 1253 } 1254 1255 WARN_ON(!bitmap_empty(new_page_tables, I915_PDES)); 1256 1257 /* Make sure write is complete before other code can use this page 1258 * table. Also require for WC mapped PTEs */ 1259 readl(dev_priv->gtt.gsm); 1260 1261 mark_tlbs_dirty(ppgtt); 1262 return 0; 1263 1264unwind_out: 1265 for_each_set_bit(pde, new_page_tables, I915_PDES) { 1266 struct i915_page_table_entry *pt = ppgtt->pd.page_table[pde]; 1267 1268 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; 1269 unmap_and_free_pt(pt, vm->dev); 1270 } 1271 1272 mark_tlbs_dirty(ppgtt); 1273 return ret; 1274} 1275 1276static void gen6_ppgtt_free(struct i915_hw_ppgtt *ppgtt) 1277{ 1278 int i; 1279 1280 for (i = 0; i < ppgtt->num_pd_entries; i++) { 1281 struct i915_page_table_entry *pt = ppgtt->pd.page_table[i]; 1282 1283 if (pt != ppgtt->scratch_pt) 1284 unmap_and_free_pt(ppgtt->pd.page_table[i], ppgtt->base.dev); 1285 } 1286 1287 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); 1288 unmap_and_free_pd(&ppgtt->pd); 1289} 1290 1291static void gen6_ppgtt_cleanup(struct i915_address_space *vm) 1292{ 1293 struct i915_hw_ppgtt *ppgtt = 1294 container_of(vm, struct i915_hw_ppgtt, base); 1295 1296 drm_mm_remove_node(&ppgtt->node); 1297 1298 gen6_ppgtt_free(ppgtt); 1299} 1300 1301static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt *ppgtt) 1302{ 1303 struct drm_device *dev = ppgtt->base.dev; 1304 struct drm_i915_private *dev_priv = dev->dev_private; 1305 bool retried = false; 1306 int ret; 1307 1308 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The 1309 * allocator works in address space sizes, so it's multiplied by page 1310 * size. We allocate at the top of the GTT to avoid fragmentation. 1311 */ 1312 BUG_ON(!drm_mm_initialized(&dev_priv->gtt.base.mm)); 1313 ppgtt->scratch_pt = alloc_pt_single(ppgtt->base.dev); 1314 if (IS_ERR(ppgtt->scratch_pt)) 1315 return PTR_ERR(ppgtt->scratch_pt); 1316 1317 gen6_initialize_pt(&ppgtt->base, ppgtt->scratch_pt); 1318 1319alloc: 1320 ret = drm_mm_insert_node_in_range_generic(&dev_priv->gtt.base.mm, 1321 &ppgtt->node, GEN6_PD_SIZE, 1322 GEN6_PD_ALIGN, 0, 1323 0, dev_priv->gtt.base.total, 1324 DRM_MM_TOPDOWN); 1325 if (ret == -ENOSPC && !retried) { 1326 ret = i915_gem_evict_something(dev, &dev_priv->gtt.base, 1327 GEN6_PD_SIZE, GEN6_PD_ALIGN, 1328 I915_CACHE_NONE, 1329 0, dev_priv->gtt.base.total, 1330 0); 1331 if (ret) 1332 goto err_out; 1333 1334 retried = true; 1335 goto alloc; 1336 } 1337 1338 if (ret) 1339 goto err_out; 1340 1341 1342 if (ppgtt->node.start < dev_priv->gtt.mappable_end) 1343 DRM_DEBUG("Forced to use aperture for PDEs\n"); 1344 1345 ppgtt->num_pd_entries = I915_PDES; 1346 return 0; 1347 1348err_out: 1349 unmap_and_free_pt(ppgtt->scratch_pt, ppgtt->base.dev); 1350 return ret; 1351} 1352 1353static int gen6_ppgtt_alloc(struct i915_hw_ppgtt *ppgtt) 1354{ 1355 return gen6_ppgtt_allocate_page_directories(ppgtt); 1356} 1357 1358static void gen6_scratch_va_range(struct i915_hw_ppgtt *ppgtt, 1359 uint64_t start, uint64_t length) 1360{ 1361 struct i915_page_table_entry *unused; 1362 uint32_t pde, temp; 1363 1364 gen6_for_each_pde(unused, &ppgtt->pd, start, length, temp, pde) 1365 ppgtt->pd.page_table[pde] = ppgtt->scratch_pt; 1366} 1367 1368static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt, bool aliasing) 1369{ 1370 struct drm_device *dev = ppgtt->base.dev; 1371 struct drm_i915_private *dev_priv = dev->dev_private; 1372 int ret; 1373 1374 ppgtt->base.pte_encode = dev_priv->gtt.base.pte_encode; 1375 if (IS_GEN6(dev)) { 1376 ppgtt->switch_mm = gen6_mm_switch; 1377 } else if (IS_HASWELL(dev)) { 1378 ppgtt->switch_mm = hsw_mm_switch; 1379 } else if (IS_GEN7(dev)) { 1380 ppgtt->switch_mm = gen7_mm_switch; 1381 } else 1382 BUG(); 1383 1384 if (intel_vgpu_active(dev)) 1385 ppgtt->switch_mm = vgpu_mm_switch; 1386 1387 ret = gen6_ppgtt_alloc(ppgtt); 1388 if (ret) 1389 return ret; 1390 1391 if (aliasing) { 1392 /* preallocate all pts */ 1393 ret = alloc_pt_range(&ppgtt->pd, 0, ppgtt->num_pd_entries, 1394 ppgtt->base.dev); 1395 1396 if (ret) { 1397 gen6_ppgtt_cleanup(&ppgtt->base); 1398 return ret; 1399 } 1400 } 1401 1402 ppgtt->base.allocate_va_range = gen6_alloc_va_range; 1403 ppgtt->base.clear_range = gen6_ppgtt_clear_range; 1404 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; 1405 ppgtt->base.cleanup = gen6_ppgtt_cleanup; 1406 ppgtt->base.start = 0; 1407 ppgtt->base.total = ppgtt->num_pd_entries * GEN6_PTES * PAGE_SIZE; 1408 ppgtt->debug_dump = gen6_dump_ppgtt; 1409 1410 ppgtt->pd.pd_offset = 1411 ppgtt->node.start / PAGE_SIZE * sizeof(gen6_pte_t); 1412 1413 ppgtt->pd_addr = (gen6_pte_t __iomem *)dev_priv->gtt.gsm + 1414 ppgtt->pd.pd_offset / sizeof(gen6_pte_t); 1415 1416 if (aliasing) 1417 ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true); 1418 else 1419 gen6_scratch_va_range(ppgtt, 0, ppgtt->base.total); 1420 1421 gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total); 1422 1423 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n", 1424 ppgtt->node.size >> 20, 1425 ppgtt->node.start / PAGE_SIZE); 1426 1427 DRM_DEBUG("Adding PPGTT at offset %x\n", 1428 ppgtt->pd.pd_offset << 10); 1429 1430 return 0; 1431} 1432 1433static int __hw_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt, 1434 bool aliasing) 1435{ 1436 struct drm_i915_private *dev_priv = dev->dev_private; 1437 1438 ppgtt->base.dev = dev; 1439 ppgtt->base.scratch = dev_priv->gtt.base.scratch; 1440 1441 if (INTEL_INFO(dev)->gen < 8) 1442 return gen6_ppgtt_init(ppgtt, aliasing); 1443 else 1444 return gen8_ppgtt_init(ppgtt, dev_priv->gtt.base.total); 1445} 1446int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt) 1447{ 1448 struct drm_i915_private *dev_priv = dev->dev_private; 1449 int ret = 0; 1450 1451 ret = __hw_ppgtt_init(dev, ppgtt, false); 1452 if (ret == 0) { 1453 kref_init(&ppgtt->ref); 1454 drm_mm_init(&ppgtt->base.mm, ppgtt->base.start, 1455 ppgtt->base.total); 1456 i915_init_vm(dev_priv, &ppgtt->base); 1457 } 1458 1459 return ret; 1460} 1461 1462int i915_ppgtt_init_hw(struct drm_device *dev) 1463{ 1464 struct drm_i915_private *dev_priv = dev->dev_private; 1465 struct intel_engine_cs *ring; 1466 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 1467 int i, ret = 0; 1468 1469 /* In the case of execlists, PPGTT is enabled by the context descriptor 1470 * and the PDPs are contained within the context itself. We don't 1471 * need to do anything here. */ 1472 if (i915.enable_execlists) 1473 return 0; 1474 1475 if (!USES_PPGTT(dev)) 1476 return 0; 1477 1478 if (IS_GEN6(dev)) 1479 gen6_ppgtt_enable(dev); 1480 else if (IS_GEN7(dev)) 1481 gen7_ppgtt_enable(dev); 1482 else if (INTEL_INFO(dev)->gen >= 8) 1483 gen8_ppgtt_enable(dev); 1484 else 1485 MISSING_CASE(INTEL_INFO(dev)->gen); 1486 1487 if (ppgtt) { 1488 for_each_ring(ring, dev_priv, i) { 1489 ret = ppgtt->switch_mm(ppgtt, ring); 1490 if (ret != 0) 1491 return ret; 1492 } 1493 } 1494 1495 return ret; 1496} 1497struct i915_hw_ppgtt * 1498i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) 1499{ 1500 struct i915_hw_ppgtt *ppgtt; 1501 int ret; 1502 1503 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); 1504 if (!ppgtt) 1505 return ERR_PTR(-ENOMEM); 1506 1507 ret = i915_ppgtt_init(dev, ppgtt); 1508 if (ret) { 1509 kfree(ppgtt); 1510 return ERR_PTR(ret); 1511 } 1512 1513 ppgtt->file_priv = fpriv; 1514 1515 trace_i915_ppgtt_create(&ppgtt->base); 1516 1517 return ppgtt; 1518} 1519 1520void i915_ppgtt_release(struct kref *kref) 1521{ 1522 struct i915_hw_ppgtt *ppgtt = 1523 container_of(kref, struct i915_hw_ppgtt, ref); 1524 1525 trace_i915_ppgtt_release(&ppgtt->base); 1526 1527 /* vmas should already be unbound */ 1528 WARN_ON(!list_empty(&ppgtt->base.active_list)); 1529 WARN_ON(!list_empty(&ppgtt->base.inactive_list)); 1530 1531 list_del(&ppgtt->base.global_link); 1532 drm_mm_takedown(&ppgtt->base.mm); 1533 1534 ppgtt->base.cleanup(&ppgtt->base); 1535 kfree(ppgtt); 1536} 1537 1538static void 1539ppgtt_bind_vma(struct i915_vma *vma, 1540 enum i915_cache_level cache_level, 1541 u32 flags) 1542{ 1543 /* Currently applicable only to VLV */ 1544 if (vma->obj->gt_ro) 1545 flags |= PTE_READ_ONLY; 1546 1547 vma->vm->insert_entries(vma->vm, vma->obj->pages, vma->node.start, 1548 cache_level, flags); 1549} 1550 1551static void ppgtt_unbind_vma(struct i915_vma *vma) 1552{ 1553 vma->vm->clear_range(vma->vm, 1554 vma->node.start, 1555 vma->obj->base.size, 1556 true); 1557} 1558 1559extern int intel_iommu_gfx_mapped; 1560/* Certain Gen5 chipsets require require idling the GPU before 1561 * unmapping anything from the GTT when VT-d is enabled. 1562 */ 1563static inline bool needs_idle_maps(struct drm_device *dev) 1564{ 1565#ifdef CONFIG_INTEL_IOMMU 1566 /* Query intel_iommu to see if we need the workaround. Presumably that 1567 * was loaded first. 1568 */ 1569 if (IS_GEN5(dev) && IS_MOBILE(dev) && intel_iommu_gfx_mapped) 1570 return true; 1571#endif 1572 return false; 1573} 1574 1575static bool do_idling(struct drm_i915_private *dev_priv) 1576{ 1577 bool ret = dev_priv->mm.interruptible; 1578 1579 if (unlikely(dev_priv->gtt.do_idle_maps)) { 1580 dev_priv->mm.interruptible = false; 1581 if (i915_gpu_idle(dev_priv->dev)) { 1582 DRM_ERROR("Couldn't idle GPU\n"); 1583 /* Wait a bit, in hopes it avoids the hang */ 1584 udelay(10); 1585 } 1586 } 1587 1588 return ret; 1589} 1590 1591static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible) 1592{ 1593 if (unlikely(dev_priv->gtt.do_idle_maps)) 1594 dev_priv->mm.interruptible = interruptible; 1595} 1596 1597void i915_check_and_clear_faults(struct drm_device *dev) 1598{ 1599 struct drm_i915_private *dev_priv = dev->dev_private; 1600 struct intel_engine_cs *ring; 1601 int i; 1602 1603 if (INTEL_INFO(dev)->gen < 6) 1604 return; 1605 1606 for_each_ring(ring, dev_priv, i) { 1607 u32 fault_reg; 1608 fault_reg = I915_READ(RING_FAULT_REG(ring)); 1609 if (fault_reg & RING_FAULT_VALID) { 1610 DRM_DEBUG_DRIVER("Unexpected fault\n" 1611 "\tAddr: 0x%08lx\n" 1612 "\tAddress space: %s\n" 1613 "\tSource ID: %d\n" 1614 "\tType: %d\n", 1615 fault_reg & PAGE_MASK, 1616 fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT", 1617 RING_FAULT_SRCID(fault_reg), 1618 RING_FAULT_FAULT_TYPE(fault_reg)); 1619 I915_WRITE(RING_FAULT_REG(ring), 1620 fault_reg & ~RING_FAULT_VALID); 1621 } 1622 } 1623 POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS])); 1624} 1625 1626static void i915_ggtt_flush(struct drm_i915_private *dev_priv) 1627{ 1628 if (INTEL_INFO(dev_priv->dev)->gen < 6) { 1629 intel_gtt_chipset_flush(); 1630 } else { 1631 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 1632 POSTING_READ(GFX_FLSH_CNTL_GEN6); 1633 } 1634} 1635 1636void i915_gem_suspend_gtt_mappings(struct drm_device *dev) 1637{ 1638 struct drm_i915_private *dev_priv = dev->dev_private; 1639 1640 /* Don't bother messing with faults pre GEN6 as we have little 1641 * documentation supporting that it's a good idea. 1642 */ 1643 if (INTEL_INFO(dev)->gen < 6) 1644 return; 1645 1646 i915_check_and_clear_faults(dev); 1647 1648 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 1649 dev_priv->gtt.base.start, 1650 dev_priv->gtt.base.total, 1651 true); 1652 1653 i915_ggtt_flush(dev_priv); 1654} 1655 1656void i915_gem_restore_gtt_mappings(struct drm_device *dev) 1657{ 1658 struct drm_i915_private *dev_priv = dev->dev_private; 1659 struct drm_i915_gem_object *obj; 1660 struct i915_address_space *vm; 1661 1662 i915_check_and_clear_faults(dev); 1663 1664 /* First fill our portion of the GTT with scratch pages */ 1665 dev_priv->gtt.base.clear_range(&dev_priv->gtt.base, 1666 dev_priv->gtt.base.start, 1667 dev_priv->gtt.base.total, 1668 true); 1669 1670 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 1671 struct i915_vma *vma = i915_gem_obj_to_vma(obj, 1672 &dev_priv->gtt.base); 1673 if (!vma) 1674 continue; 1675 1676 i915_gem_clflush_object(obj, obj->pin_display); 1677 /* The bind_vma code tries to be smart about tracking mappings. 1678 * Unfortunately above, we've just wiped out the mappings 1679 * without telling our object about it. So we need to fake it. 1680 * 1681 * Bind is not expected to fail since this is only called on 1682 * resume and assumption is all requirements exist already. 1683 */ 1684 vma->bound &= ~GLOBAL_BIND; 1685 WARN_ON(i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND)); 1686 } 1687 1688 1689 if (INTEL_INFO(dev)->gen >= 8) { 1690 if (IS_CHERRYVIEW(dev)) 1691 chv_setup_private_ppat(dev_priv); 1692 else 1693 bdw_setup_private_ppat(dev_priv); 1694 1695 return; 1696 } 1697 1698 if (USES_PPGTT(dev)) { 1699 list_for_each_entry(vm, &dev_priv->vm_list, global_link) { 1700 /* TODO: Perhaps it shouldn't be gen6 specific */ 1701 1702 struct i915_hw_ppgtt *ppgtt = 1703 container_of(vm, struct i915_hw_ppgtt, 1704 base); 1705 1706 if (i915_is_ggtt(vm)) 1707 ppgtt = dev_priv->mm.aliasing_ppgtt; 1708 1709 gen6_write_page_range(dev_priv, &ppgtt->pd, 1710 0, ppgtt->base.total); 1711 } 1712 } 1713 1714 i915_ggtt_flush(dev_priv); 1715} 1716 1717int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj) 1718{ 1719 if (obj->has_dma_mapping) 1720 return 0; 1721 1722 if (!dma_map_sg(&obj->base.dev->pdev->dev, 1723 obj->pages->sgl, obj->pages->nents, 1724 PCI_DMA_BIDIRECTIONAL)) 1725 return -ENOSPC; 1726 1727 return 0; 1728} 1729 1730static inline void gen8_set_pte(void __iomem *addr, gen8_pte_t pte) 1731{ 1732#ifdef writeq 1733 writeq(pte, addr); 1734#else 1735 iowrite32((u32)pte, addr); 1736 iowrite32(pte >> 32, addr + 4); 1737#endif 1738} 1739 1740static void gen8_ggtt_insert_entries(struct i915_address_space *vm, 1741 struct sg_table *st, 1742 uint64_t start, 1743 enum i915_cache_level level, u32 unused) 1744{ 1745 struct drm_i915_private *dev_priv = vm->dev->dev_private; 1746 unsigned first_entry = start >> PAGE_SHIFT; 1747 gen8_pte_t __iomem *gtt_entries = 1748 (gen8_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; 1749 int i = 0; 1750 struct sg_page_iter sg_iter; 1751 dma_addr_t addr = 0; /* shut up gcc */ 1752 1753 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 1754 addr = sg_dma_address(sg_iter.sg) + 1755 (sg_iter.sg_pgoffset << PAGE_SHIFT); 1756 gen8_set_pte(>t_entries[i], 1757 gen8_pte_encode(addr, level, true)); 1758 i++; 1759 } 1760 1761 /* 1762 * XXX: This serves as a posting read to make sure that the PTE has 1763 * actually been updated. There is some concern that even though 1764 * registers and PTEs are within the same BAR that they are potentially 1765 * of NUMA access patterns. Therefore, even with the way we assume 1766 * hardware should work, we must keep this posting read for paranoia. 1767 */ 1768 if (i != 0) 1769 WARN_ON(readq(>t_entries[i-1]) 1770 != gen8_pte_encode(addr, level, true)); 1771 1772 /* This next bit makes the above posting read even more important. We 1773 * want to flush the TLBs only after we're certain all the PTE updates 1774 * have finished. 1775 */ 1776 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 1777 POSTING_READ(GFX_FLSH_CNTL_GEN6); 1778} 1779 1780/* 1781 * Binds an object into the global gtt with the specified cache level. The object 1782 * will be accessible to the GPU via commands whose operands reference offsets 1783 * within the global GTT as well as accessible by the GPU through the GMADR 1784 * mapped BAR (dev_priv->mm.gtt->gtt). 1785 */ 1786static void gen6_ggtt_insert_entries(struct i915_address_space *vm, 1787 struct sg_table *st, 1788 uint64_t start, 1789 enum i915_cache_level level, u32 flags) 1790{ 1791 struct drm_i915_private *dev_priv = vm->dev->dev_private; 1792 unsigned first_entry = start >> PAGE_SHIFT; 1793 gen6_pte_t __iomem *gtt_entries = 1794 (gen6_pte_t __iomem *)dev_priv->gtt.gsm + first_entry; 1795 int i = 0; 1796 struct sg_page_iter sg_iter; 1797 dma_addr_t addr = 0; 1798 1799 for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) { 1800 addr = sg_page_iter_dma_address(&sg_iter); 1801 iowrite32(vm->pte_encode(addr, level, true, flags), >t_entries[i]); 1802 i++; 1803 } 1804 1805 /* XXX: This serves as a posting read to make sure that the PTE has 1806 * actually been updated. There is some concern that even though 1807 * registers and PTEs are within the same BAR that they are potentially 1808 * of NUMA access patterns. Therefore, even with the way we assume 1809 * hardware should work, we must keep this posting read for paranoia. 1810 */ 1811 if (i != 0) { 1812 unsigned long gtt = readl(>t_entries[i-1]); 1813 WARN_ON(gtt != vm->pte_encode(addr, level, true, flags)); 1814 } 1815 1816 /* This next bit makes the above posting read even more important. We 1817 * want to flush the TLBs only after we're certain all the PTE updates 1818 * have finished. 1819 */ 1820 I915_WRITE(GFX_FLSH_CNTL_GEN6, GFX_FLSH_CNTL_EN); 1821 POSTING_READ(GFX_FLSH_CNTL_GEN6); 1822} 1823 1824static void gen8_ggtt_clear_range(struct i915_address_space *vm, 1825 uint64_t start, 1826 uint64_t length, 1827 bool use_scratch) 1828{ 1829 struct drm_i915_private *dev_priv = vm->dev->dev_private; 1830 unsigned first_entry = start >> PAGE_SHIFT; 1831 unsigned num_entries = length >> PAGE_SHIFT; 1832 gen8_pte_t scratch_pte, __iomem *gtt_base = 1833 (gen8_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; 1834 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; 1835 int i; 1836 1837 if (WARN(num_entries > max_entries, 1838 "First entry = %d; Num entries = %d (max=%d)\n", 1839 first_entry, num_entries, max_entries)) 1840 num_entries = max_entries; 1841 1842 scratch_pte = gen8_pte_encode(vm->scratch.addr, 1843 I915_CACHE_LLC, 1844 use_scratch); 1845 for (i = 0; i < num_entries; i++) 1846 gen8_set_pte(>t_base[i], scratch_pte); 1847 readl(gtt_base); 1848} 1849 1850static void gen6_ggtt_clear_range(struct i915_address_space *vm, 1851 uint64_t start, 1852 uint64_t length, 1853 bool use_scratch) 1854{ 1855 struct drm_i915_private *dev_priv = vm->dev->dev_private; 1856 unsigned first_entry = start >> PAGE_SHIFT; 1857 unsigned num_entries = length >> PAGE_SHIFT; 1858 gen6_pte_t scratch_pte, __iomem *gtt_base = 1859 (gen6_pte_t __iomem *) dev_priv->gtt.gsm + first_entry; 1860 const int max_entries = gtt_total_entries(dev_priv->gtt) - first_entry; 1861 int i; 1862 1863 if (WARN(num_entries > max_entries, 1864 "First entry = %d; Num entries = %d (max=%d)\n", 1865 first_entry, num_entries, max_entries)) 1866 num_entries = max_entries; 1867 1868 scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch, 0); 1869 1870 for (i = 0; i < num_entries; i++) 1871 iowrite32(scratch_pte, >t_base[i]); 1872 readl(gtt_base); 1873} 1874 1875 1876static void i915_ggtt_bind_vma(struct i915_vma *vma, 1877 enum i915_cache_level cache_level, 1878 u32 unused) 1879{ 1880 const unsigned long entry = vma->node.start >> PAGE_SHIFT; 1881 unsigned int flags = (cache_level == I915_CACHE_NONE) ? 1882 AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY; 1883 1884 BUG_ON(!i915_is_ggtt(vma->vm)); 1885 intel_gtt_insert_sg_entries(vma->ggtt_view.pages, entry, flags); 1886 vma->bound = GLOBAL_BIND; 1887} 1888 1889static void i915_ggtt_clear_range(struct i915_address_space *vm, 1890 uint64_t start, 1891 uint64_t length, 1892 bool unused) 1893{ 1894 unsigned first_entry = start >> PAGE_SHIFT; 1895 unsigned num_entries = length >> PAGE_SHIFT; 1896 intel_gtt_clear_range(first_entry, num_entries); 1897} 1898 1899static void i915_ggtt_unbind_vma(struct i915_vma *vma) 1900{ 1901 const unsigned int first = vma->node.start >> PAGE_SHIFT; 1902 const unsigned int size = vma->obj->base.size >> PAGE_SHIFT; 1903 1904 BUG_ON(!i915_is_ggtt(vma->vm)); 1905 vma->bound = 0; 1906 intel_gtt_clear_range(first, size); 1907} 1908 1909static void ggtt_bind_vma(struct i915_vma *vma, 1910 enum i915_cache_level cache_level, 1911 u32 flags) 1912{ 1913 struct drm_device *dev = vma->vm->dev; 1914 struct drm_i915_private *dev_priv = dev->dev_private; 1915 struct drm_i915_gem_object *obj = vma->obj; 1916 struct sg_table *pages = obj->pages; 1917 1918 /* Currently applicable only to VLV */ 1919 if (obj->gt_ro) 1920 flags |= PTE_READ_ONLY; 1921 1922 if (i915_is_ggtt(vma->vm)) 1923 pages = vma->ggtt_view.pages; 1924 1925 /* If there is no aliasing PPGTT, or the caller needs a global mapping, 1926 * or we have a global mapping already but the cacheability flags have 1927 * changed, set the global PTEs. 1928 * 1929 * If there is an aliasing PPGTT it is anecdotally faster, so use that 1930 * instead if none of the above hold true. 1931 * 1932 * NB: A global mapping should only be needed for special regions like 1933 * "gtt mappable", SNB errata, or if specified via special execbuf 1934 * flags. At all other times, the GPU will use the aliasing PPGTT. 1935 */ 1936 if (!dev_priv->mm.aliasing_ppgtt || flags & GLOBAL_BIND) { 1937 if (!(vma->bound & GLOBAL_BIND) || 1938 (cache_level != obj->cache_level)) { 1939 vma->vm->insert_entries(vma->vm, pages, 1940 vma->node.start, 1941 cache_level, flags); 1942 vma->bound |= GLOBAL_BIND; 1943 } 1944 } 1945 1946 if (dev_priv->mm.aliasing_ppgtt && 1947 (!(vma->bound & LOCAL_BIND) || 1948 (cache_level != obj->cache_level))) { 1949 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; 1950 appgtt->base.insert_entries(&appgtt->base, pages, 1951 vma->node.start, 1952 cache_level, flags); 1953 vma->bound |= LOCAL_BIND; 1954 } 1955} 1956 1957static void ggtt_unbind_vma(struct i915_vma *vma) 1958{ 1959 struct drm_device *dev = vma->vm->dev; 1960 struct drm_i915_private *dev_priv = dev->dev_private; 1961 struct drm_i915_gem_object *obj = vma->obj; 1962 1963 if (vma->bound & GLOBAL_BIND) { 1964 vma->vm->clear_range(vma->vm, 1965 vma->node.start, 1966 obj->base.size, 1967 true); 1968 vma->bound &= ~GLOBAL_BIND; 1969 } 1970 1971 if (vma->bound & LOCAL_BIND) { 1972 struct i915_hw_ppgtt *appgtt = dev_priv->mm.aliasing_ppgtt; 1973 appgtt->base.clear_range(&appgtt->base, 1974 vma->node.start, 1975 obj->base.size, 1976 true); 1977 vma->bound &= ~LOCAL_BIND; 1978 } 1979} 1980 1981void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj) 1982{ 1983 struct drm_device *dev = obj->base.dev; 1984 struct drm_i915_private *dev_priv = dev->dev_private; 1985 bool interruptible; 1986 1987 interruptible = do_idling(dev_priv); 1988 1989 if (!obj->has_dma_mapping) 1990 dma_unmap_sg(&dev->pdev->dev, 1991 obj->pages->sgl, obj->pages->nents, 1992 PCI_DMA_BIDIRECTIONAL); 1993 1994 undo_idling(dev_priv, interruptible); 1995} 1996 1997static void i915_gtt_color_adjust(struct drm_mm_node *node, 1998 unsigned long color, 1999 u64 *start, 2000 u64 *end) 2001{ 2002 if (node->color != color) 2003 *start += 4096; 2004 2005 if (!list_empty(&node->node_list)) { 2006 node = list_entry(node->node_list.next, 2007 struct drm_mm_node, 2008 node_list); 2009 if (node->allocated && node->color != color) 2010 *end -= 4096; 2011 } 2012} 2013 2014static int i915_gem_setup_global_gtt(struct drm_device *dev, 2015 unsigned long start, 2016 unsigned long mappable_end, 2017 unsigned long end) 2018{ 2019 /* Let GEM Manage all of the aperture. 2020 * 2021 * However, leave one page at the end still bound to the scratch page. 2022 * There are a number of places where the hardware apparently prefetches 2023 * past the end of the object, and we've seen multiple hangs with the 2024 * GPU head pointer stuck in a batchbuffer bound at the last page of the 2025 * aperture. One page should be enough to keep any prefetching inside 2026 * of the aperture. 2027 */ 2028 struct drm_i915_private *dev_priv = dev->dev_private; 2029 struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; 2030 struct drm_mm_node *entry; 2031 struct drm_i915_gem_object *obj; 2032 unsigned long hole_start, hole_end; 2033 int ret; 2034 2035 BUG_ON(mappable_end > end); 2036 2037 /* Subtract the guard page ... */ 2038 drm_mm_init(&ggtt_vm->mm, start, end - start - PAGE_SIZE); 2039 2040 dev_priv->gtt.base.start = start; 2041 dev_priv->gtt.base.total = end - start; 2042 2043 if (intel_vgpu_active(dev)) { 2044 ret = intel_vgt_balloon(dev); 2045 if (ret) 2046 return ret; 2047 } 2048 2049 if (!HAS_LLC(dev)) 2050 dev_priv->gtt.base.mm.color_adjust = i915_gtt_color_adjust; 2051 2052 /* Mark any preallocated objects as occupied */ 2053 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { 2054 struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); 2055 2056 DRM_DEBUG_KMS("reserving preallocated space: %lx + %zx\n", 2057 i915_gem_obj_ggtt_offset(obj), obj->base.size); 2058 2059 WARN_ON(i915_gem_obj_ggtt_bound(obj)); 2060 ret = drm_mm_reserve_node(&ggtt_vm->mm, &vma->node); 2061 if (ret) { 2062 DRM_DEBUG_KMS("Reservation failed: %i\n", ret); 2063 return ret; 2064 } 2065 vma->bound |= GLOBAL_BIND; 2066 } 2067 2068 /* Clear any non-preallocated blocks */ 2069 drm_mm_for_each_hole(entry, &ggtt_vm->mm, hole_start, hole_end) { 2070 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n", 2071 hole_start, hole_end); 2072 ggtt_vm->clear_range(ggtt_vm, hole_start, 2073 hole_end - hole_start, true); 2074 } 2075 2076 /* And finally clear the reserved guard page */ 2077 ggtt_vm->clear_range(ggtt_vm, end - PAGE_SIZE, PAGE_SIZE, true); 2078 2079 if (USES_PPGTT(dev) && !USES_FULL_PPGTT(dev)) { 2080 struct i915_hw_ppgtt *ppgtt; 2081 2082 ppgtt = kzalloc(sizeof(*ppgtt), GFP_KERNEL); 2083 if (!ppgtt) 2084 return -ENOMEM; 2085 2086 ret = __hw_ppgtt_init(dev, ppgtt, true); 2087 if (ret) { 2088 kfree(ppgtt); 2089 return ret; 2090 } 2091 2092 dev_priv->mm.aliasing_ppgtt = ppgtt; 2093 } 2094 2095 return 0; 2096} 2097 2098void i915_gem_init_global_gtt(struct drm_device *dev) 2099{ 2100 struct drm_i915_private *dev_priv = dev->dev_private; 2101 unsigned long gtt_size, mappable_size; 2102 2103 gtt_size = dev_priv->gtt.base.total; 2104 mappable_size = dev_priv->gtt.mappable_end; 2105 2106 i915_gem_setup_global_gtt(dev, 0, mappable_size, gtt_size); 2107} 2108 2109void i915_global_gtt_cleanup(struct drm_device *dev) 2110{ 2111 struct drm_i915_private *dev_priv = dev->dev_private; 2112 struct i915_address_space *vm = &dev_priv->gtt.base; 2113 2114 if (dev_priv->mm.aliasing_ppgtt) { 2115 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; 2116 2117 ppgtt->base.cleanup(&ppgtt->base); 2118 } 2119 2120 if (drm_mm_initialized(&vm->mm)) { 2121 if (intel_vgpu_active(dev)) 2122 intel_vgt_deballoon(); 2123 2124 drm_mm_takedown(&vm->mm); 2125 list_del(&vm->global_link); 2126 } 2127 2128 vm->cleanup(vm); 2129} 2130 2131static int setup_scratch_page(struct drm_device *dev) 2132{ 2133 struct drm_i915_private *dev_priv = dev->dev_private; 2134 struct page *page; 2135 dma_addr_t dma_addr; 2136 2137 page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); 2138 if (page == NULL) 2139 return -ENOMEM; 2140 set_pages_uc(page, 1); 2141 2142#ifdef CONFIG_INTEL_IOMMU 2143 dma_addr = pci_map_page(dev->pdev, page, 0, PAGE_SIZE, 2144 PCI_DMA_BIDIRECTIONAL); 2145 if (pci_dma_mapping_error(dev->pdev, dma_addr)) 2146 return -EINVAL; 2147#else 2148 dma_addr = page_to_phys(page); 2149#endif 2150 dev_priv->gtt.base.scratch.page = page; 2151 dev_priv->gtt.base.scratch.addr = dma_addr; 2152 2153 return 0; 2154} 2155 2156static void teardown_scratch_page(struct drm_device *dev) 2157{ 2158 struct drm_i915_private *dev_priv = dev->dev_private; 2159 struct page *page = dev_priv->gtt.base.scratch.page; 2160 2161 set_pages_wb(page, 1); 2162 pci_unmap_page(dev->pdev, dev_priv->gtt.base.scratch.addr, 2163 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 2164 __free_page(page); 2165} 2166 2167static inline unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl) 2168{ 2169 snb_gmch_ctl >>= SNB_GMCH_GGMS_SHIFT; 2170 snb_gmch_ctl &= SNB_GMCH_GGMS_MASK; 2171 return snb_gmch_ctl << 20; 2172} 2173 2174static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl) 2175{ 2176 bdw_gmch_ctl >>= BDW_GMCH_GGMS_SHIFT; 2177 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; 2178 if (bdw_gmch_ctl) 2179 bdw_gmch_ctl = 1 << bdw_gmch_ctl; 2180 2181#ifdef CONFIG_X86_32 2182 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */ 2183 if (bdw_gmch_ctl > 4) 2184 bdw_gmch_ctl = 4; 2185#endif 2186 2187 return bdw_gmch_ctl << 20; 2188} 2189 2190static inline unsigned int chv_get_total_gtt_size(u16 gmch_ctrl) 2191{ 2192 gmch_ctrl >>= SNB_GMCH_GGMS_SHIFT; 2193 gmch_ctrl &= SNB_GMCH_GGMS_MASK; 2194 2195 if (gmch_ctrl) 2196 return 1 << (20 + gmch_ctrl); 2197 2198 return 0; 2199} 2200 2201static inline size_t gen6_get_stolen_size(u16 snb_gmch_ctl) 2202{ 2203 snb_gmch_ctl >>= SNB_GMCH_GMS_SHIFT; 2204 snb_gmch_ctl &= SNB_GMCH_GMS_MASK; 2205 return snb_gmch_ctl << 25; /* 32 MB units */ 2206} 2207 2208static inline size_t gen8_get_stolen_size(u16 bdw_gmch_ctl) 2209{ 2210 bdw_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; 2211 bdw_gmch_ctl &= BDW_GMCH_GMS_MASK; 2212 return bdw_gmch_ctl << 25; /* 32 MB units */ 2213} 2214 2215static size_t chv_get_stolen_size(u16 gmch_ctrl) 2216{ 2217 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT; 2218 gmch_ctrl &= SNB_GMCH_GMS_MASK; 2219 2220 /* 2221 * 0x0 to 0x10: 32MB increments starting at 0MB 2222 * 0x11 to 0x16: 4MB increments starting at 8MB 2223 * 0x17 to 0x1d: 4MB increments start at 36MB 2224 */ 2225 if (gmch_ctrl < 0x11) 2226 return gmch_ctrl << 25; 2227 else if (gmch_ctrl < 0x17) 2228 return (gmch_ctrl - 0x11 + 2) << 22; 2229 else 2230 return (gmch_ctrl - 0x17 + 9) << 22; 2231} 2232 2233static size_t gen9_get_stolen_size(u16 gen9_gmch_ctl) 2234{ 2235 gen9_gmch_ctl >>= BDW_GMCH_GMS_SHIFT; 2236 gen9_gmch_ctl &= BDW_GMCH_GMS_MASK; 2237 2238 if (gen9_gmch_ctl < 0xf0) 2239 return gen9_gmch_ctl << 25; /* 32 MB units */ 2240 else 2241 /* 4MB increments starting at 0xf0 for 4MB */ 2242 return (gen9_gmch_ctl - 0xf0 + 1) << 22; 2243} 2244 2245static int ggtt_probe_common(struct drm_device *dev, 2246 size_t gtt_size) 2247{ 2248 struct drm_i915_private *dev_priv = dev->dev_private; 2249 phys_addr_t gtt_phys_addr; 2250 int ret; 2251 2252 /* For Modern GENs the PTEs and register space are split in the BAR */ 2253 gtt_phys_addr = pci_resource_start(dev->pdev, 0) + 2254 (pci_resource_len(dev->pdev, 0) / 2); 2255 2256 dev_priv->gtt.gsm = ioremap_wc(gtt_phys_addr, gtt_size); 2257 if (!dev_priv->gtt.gsm) { 2258 DRM_ERROR("Failed to map the gtt page table\n"); 2259 return -ENOMEM; 2260 } 2261 2262 ret = setup_scratch_page(dev); 2263 if (ret) { 2264 DRM_ERROR("Scratch setup failed\n"); 2265 /* iounmap will also get called at remove, but meh */ 2266 iounmap(dev_priv->gtt.gsm); 2267 } 2268 2269 return ret; 2270} 2271 2272/* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability 2273 * bits. When using advanced contexts each context stores its own PAT, but 2274 * writing this data shouldn't be harmful even in those cases. */ 2275static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv) 2276{ 2277 uint64_t pat; 2278 2279 pat = GEN8_PPAT(0, GEN8_PPAT_WB | GEN8_PPAT_LLC) | /* for normal objects, no eLLC */ 2280 GEN8_PPAT(1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC) | /* for something pointing to ptes? */ 2281 GEN8_PPAT(2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC) | /* for scanout with eLLC */ 2282 GEN8_PPAT(3, GEN8_PPAT_UC) | /* Uncached objects, mostly for scanout */ 2283 GEN8_PPAT(4, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0)) | 2284 GEN8_PPAT(5, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1)) | 2285 GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) | 2286 GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); 2287 2288 if (!USES_PPGTT(dev_priv->dev)) 2289 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, 2290 * so RTL will always use the value corresponding to 2291 * pat_sel = 000". 2292 * So let's disable cache for GGTT to avoid screen corruptions. 2293 * MOCS still can be used though. 2294 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work 2295 * before this patch, i.e. the same uncached + snooping access 2296 * like on gen6/7 seems to be in effect. 2297 * - So this just fixes blitter/render access. Again it looks 2298 * like it's not just uncached access, but uncached + snooping. 2299 * So we can still hold onto all our assumptions wrt cpu 2300 * clflushing on LLC machines. 2301 */ 2302 pat = GEN8_PPAT(0, GEN8_PPAT_UC); 2303 2304 /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b 2305 * write would work. */ 2306 I915_WRITE(GEN8_PRIVATE_PAT, pat); 2307 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); 2308} 2309 2310static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) 2311{ 2312 uint64_t pat; 2313 2314 /* 2315 * Map WB on BDW to snooped on CHV. 2316 * 2317 * Only the snoop bit has meaning for CHV, the rest is 2318 * ignored. 2319 * 2320 * The hardware will never snoop for certain types of accesses: 2321 * - CPU GTT (GMADR->GGTT->no snoop->memory) 2322 * - PPGTT page tables 2323 * - some other special cycles 2324 * 2325 * As with BDW, we also need to consider the following for GT accesses: 2326 * "For GGTT, there is NO pat_sel[2:0] from the entry, 2327 * so RTL will always use the value corresponding to 2328 * pat_sel = 000". 2329 * Which means we must set the snoop bit in PAT entry 0 2330 * in order to keep the global status page working. 2331 */ 2332 pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | 2333 GEN8_PPAT(1, 0) | 2334 GEN8_PPAT(2, 0) | 2335 GEN8_PPAT(3, 0) | 2336 GEN8_PPAT(4, CHV_PPAT_SNOOP) | 2337 GEN8_PPAT(5, CHV_PPAT_SNOOP) | 2338 GEN8_PPAT(6, CHV_PPAT_SNOOP) | 2339 GEN8_PPAT(7, CHV_PPAT_SNOOP); 2340 2341 I915_WRITE(GEN8_PRIVATE_PAT, pat); 2342 I915_WRITE(GEN8_PRIVATE_PAT + 4, pat >> 32); 2343} 2344 2345static int gen8_gmch_probe(struct drm_device *dev, 2346 size_t *gtt_total, 2347 size_t *stolen, 2348 phys_addr_t *mappable_base, 2349 unsigned long *mappable_end) 2350{ 2351 struct drm_i915_private *dev_priv = dev->dev_private; 2352 unsigned int gtt_size; 2353 u16 snb_gmch_ctl; 2354 int ret; 2355 2356 /* TODO: We're not aware of mappable constraints on gen8 yet */ 2357 *mappable_base = pci_resource_start(dev->pdev, 2); 2358 *mappable_end = pci_resource_len(dev->pdev, 2); 2359 2360 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(39))) 2361 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(39)); 2362 2363 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); 2364 2365 if (INTEL_INFO(dev)->gen >= 9) { 2366 *stolen = gen9_get_stolen_size(snb_gmch_ctl); 2367 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); 2368 } else if (IS_CHERRYVIEW(dev)) { 2369 *stolen = chv_get_stolen_size(snb_gmch_ctl); 2370 gtt_size = chv_get_total_gtt_size(snb_gmch_ctl); 2371 } else { 2372 *stolen = gen8_get_stolen_size(snb_gmch_ctl); 2373 gtt_size = gen8_get_total_gtt_size(snb_gmch_ctl); 2374 } 2375 2376 *gtt_total = (gtt_size / sizeof(gen8_pte_t)) << PAGE_SHIFT; 2377 2378 if (IS_CHERRYVIEW(dev)) 2379 chv_setup_private_ppat(dev_priv); 2380 else 2381 bdw_setup_private_ppat(dev_priv); 2382 2383 ret = ggtt_probe_common(dev, gtt_size); 2384 2385 dev_priv->gtt.base.clear_range = gen8_ggtt_clear_range; 2386 dev_priv->gtt.base.insert_entries = gen8_ggtt_insert_entries; 2387 2388 return ret; 2389} 2390 2391static int gen6_gmch_probe(struct drm_device *dev, 2392 size_t *gtt_total, 2393 size_t *stolen, 2394 phys_addr_t *mappable_base, 2395 unsigned long *mappable_end) 2396{ 2397 struct drm_i915_private *dev_priv = dev->dev_private; 2398 unsigned int gtt_size; 2399 u16 snb_gmch_ctl; 2400 int ret; 2401 2402 *mappable_base = pci_resource_start(dev->pdev, 2); 2403 *mappable_end = pci_resource_len(dev->pdev, 2); 2404 2405 /* 64/512MB is the current min/max we actually know of, but this is just 2406 * a coarse sanity check. 2407 */ 2408 if ((*mappable_end < (64<<20) || (*mappable_end > (512<<20)))) { 2409 DRM_ERROR("Unknown GMADR size (%lx)\n", 2410 dev_priv->gtt.mappable_end); 2411 return -ENXIO; 2412 } 2413 2414 if (!pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(40))) 2415 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(40)); 2416 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &snb_gmch_ctl); 2417 2418 *stolen = gen6_get_stolen_size(snb_gmch_ctl); 2419 2420 gtt_size = gen6_get_total_gtt_size(snb_gmch_ctl); 2421 *gtt_total = (gtt_size / sizeof(gen6_pte_t)) << PAGE_SHIFT; 2422 2423 ret = ggtt_probe_common(dev, gtt_size); 2424 2425 dev_priv->gtt.base.clear_range = gen6_ggtt_clear_range; 2426 dev_priv->gtt.base.insert_entries = gen6_ggtt_insert_entries; 2427 2428 return ret; 2429} 2430 2431static void gen6_gmch_remove(struct i915_address_space *vm) 2432{ 2433 2434 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); 2435 2436 iounmap(gtt->gsm); 2437 teardown_scratch_page(vm->dev); 2438} 2439 2440static int i915_gmch_probe(struct drm_device *dev, 2441 size_t *gtt_total, 2442 size_t *stolen, 2443 phys_addr_t *mappable_base, 2444 unsigned long *mappable_end) 2445{ 2446 struct drm_i915_private *dev_priv = dev->dev_private; 2447 int ret; 2448 2449 ret = intel_gmch_probe(dev_priv->bridge_dev, dev_priv->dev->pdev, NULL); 2450 if (!ret) { 2451 DRM_ERROR("failed to set up gmch\n"); 2452 return -EIO; 2453 } 2454 2455 intel_gtt_get(gtt_total, stolen, mappable_base, mappable_end); 2456 2457 dev_priv->gtt.do_idle_maps = needs_idle_maps(dev_priv->dev); 2458 dev_priv->gtt.base.clear_range = i915_ggtt_clear_range; 2459 2460 if (unlikely(dev_priv->gtt.do_idle_maps)) 2461 DRM_INFO("applying Ironlake quirks for intel_iommu\n"); 2462 2463 return 0; 2464} 2465 2466static void i915_gmch_remove(struct i915_address_space *vm) 2467{ 2468 intel_gmch_remove(); 2469} 2470 2471int i915_gem_gtt_init(struct drm_device *dev) 2472{ 2473 struct drm_i915_private *dev_priv = dev->dev_private; 2474 struct i915_gtt *gtt = &dev_priv->gtt; 2475 int ret; 2476 2477 if (INTEL_INFO(dev)->gen <= 5) { 2478 gtt->gtt_probe = i915_gmch_probe; 2479 gtt->base.cleanup = i915_gmch_remove; 2480 } else if (INTEL_INFO(dev)->gen < 8) { 2481 gtt->gtt_probe = gen6_gmch_probe; 2482 gtt->base.cleanup = gen6_gmch_remove; 2483 if (IS_HASWELL(dev) && dev_priv->ellc_size) 2484 gtt->base.pte_encode = iris_pte_encode; 2485 else if (IS_HASWELL(dev)) 2486 gtt->base.pte_encode = hsw_pte_encode; 2487 else if (IS_VALLEYVIEW(dev)) 2488 gtt->base.pte_encode = byt_pte_encode; 2489 else if (INTEL_INFO(dev)->gen >= 7) 2490 gtt->base.pte_encode = ivb_pte_encode; 2491 else 2492 gtt->base.pte_encode = snb_pte_encode; 2493 } else { 2494 dev_priv->gtt.gtt_probe = gen8_gmch_probe; 2495 dev_priv->gtt.base.cleanup = gen6_gmch_remove; 2496 } 2497 2498 ret = gtt->gtt_probe(dev, >t->base.total, >t->stolen_size, 2499 >t->mappable_base, >t->mappable_end); 2500 if (ret) 2501 return ret; 2502 2503 gtt->base.dev = dev; 2504 2505 /* GMADR is the PCI mmio aperture into the global GTT. */ 2506 DRM_INFO("Memory usable by graphics device = %zdM\n", 2507 gtt->base.total >> 20); 2508 DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); 2509 DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); 2510#ifdef CONFIG_INTEL_IOMMU 2511 if (intel_iommu_gfx_mapped) 2512 DRM_INFO("VT-d active for gfx access\n"); 2513#endif 2514 /* 2515 * i915.enable_ppgtt is read-only, so do an early pass to validate the 2516 * user's requested state against the hardware/driver capabilities. We 2517 * do this now so that we can print out any log messages once rather 2518 * than every time we check intel_enable_ppgtt(). 2519 */ 2520 i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); 2521 DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); 2522 2523 return 0; 2524} 2525 2526static struct i915_vma * 2527__i915_gem_vma_create(struct drm_i915_gem_object *obj, 2528 struct i915_address_space *vm, 2529 const struct i915_ggtt_view *ggtt_view) 2530{ 2531 struct i915_vma *vma; 2532 2533 if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) 2534 return ERR_PTR(-EINVAL); 2535 vma = kzalloc(sizeof(*vma), GFP_KERNEL); 2536 if (vma == NULL) 2537 return ERR_PTR(-ENOMEM); 2538 2539 INIT_LIST_HEAD(&vma->vma_link); 2540 INIT_LIST_HEAD(&vma->mm_list); 2541 INIT_LIST_HEAD(&vma->exec_list); 2542 vma->vm = vm; 2543 vma->obj = obj; 2544 2545 if (INTEL_INFO(vm->dev)->gen >= 6) { 2546 if (i915_is_ggtt(vm)) { 2547 vma->ggtt_view = *ggtt_view; 2548 2549 vma->unbind_vma = ggtt_unbind_vma; 2550 vma->bind_vma = ggtt_bind_vma; 2551 } else { 2552 vma->unbind_vma = ppgtt_unbind_vma; 2553 vma->bind_vma = ppgtt_bind_vma; 2554 } 2555 } else { 2556 BUG_ON(!i915_is_ggtt(vm)); 2557 vma->ggtt_view = *ggtt_view; 2558 vma->unbind_vma = i915_ggtt_unbind_vma; 2559 vma->bind_vma = i915_ggtt_bind_vma; 2560 } 2561 2562 list_add_tail(&vma->vma_link, &obj->vma_list); 2563 if (!i915_is_ggtt(vm)) 2564 i915_ppgtt_get(i915_vm_to_ppgtt(vm)); 2565 2566 return vma; 2567} 2568 2569struct i915_vma * 2570i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, 2571 struct i915_address_space *vm) 2572{ 2573 struct i915_vma *vma; 2574 2575 vma = i915_gem_obj_to_vma(obj, vm); 2576 if (!vma) 2577 vma = __i915_gem_vma_create(obj, vm, 2578 i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL); 2579 2580 return vma; 2581} 2582 2583struct i915_vma * 2584i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, 2585 const struct i915_ggtt_view *view) 2586{ 2587 struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); 2588 struct i915_vma *vma; 2589 2590 if (WARN_ON(!view)) 2591 return ERR_PTR(-EINVAL); 2592 2593 vma = i915_gem_obj_to_ggtt_view(obj, view); 2594 2595 if (IS_ERR(vma)) 2596 return vma; 2597 2598 if (!vma) 2599 vma = __i915_gem_vma_create(obj, ggtt, view); 2600 2601 return vma; 2602 2603} 2604 2605static void 2606rotate_pages(dma_addr_t *in, unsigned int width, unsigned int height, 2607 struct sg_table *st) 2608{ 2609 unsigned int column, row; 2610 unsigned int src_idx; 2611 struct scatterlist *sg = st->sgl; 2612 2613 st->nents = 0; 2614 2615 for (column = 0; column < width; column++) { 2616 src_idx = width * (height - 1) + column; 2617 for (row = 0; row < height; row++) { 2618 st->nents++; 2619 /* We don't need the pages, but need to initialize 2620 * the entries so the sg list can be happily traversed. 2621 * The only thing we need are DMA addresses. 2622 */ 2623 sg_set_page(sg, NULL, PAGE_SIZE, 0); 2624 sg_dma_address(sg) = in[src_idx]; 2625 sg_dma_len(sg) = PAGE_SIZE; 2626 sg = sg_next(sg); 2627 src_idx -= width; 2628 } 2629 } 2630} 2631 2632static struct sg_table * 2633intel_rotate_fb_obj_pages(struct i915_ggtt_view *ggtt_view, 2634 struct drm_i915_gem_object *obj) 2635{ 2636 struct drm_device *dev = obj->base.dev; 2637 struct intel_rotation_info *rot_info = &ggtt_view->rotation_info; 2638 unsigned long size, pages, rot_pages; 2639 struct sg_page_iter sg_iter; 2640 unsigned long i; 2641 dma_addr_t *page_addr_list; 2642 struct sg_table *st; 2643 unsigned int tile_pitch, tile_height; 2644 unsigned int width_pages, height_pages; 2645 int ret = -ENOMEM; 2646 2647 pages = obj->base.size / PAGE_SIZE; 2648 2649 /* Calculate tiling geometry. */ 2650 tile_height = intel_tile_height(dev, rot_info->pixel_format, 2651 rot_info->fb_modifier); 2652 tile_pitch = PAGE_SIZE / tile_height; 2653 width_pages = DIV_ROUND_UP(rot_info->pitch, tile_pitch); 2654 height_pages = DIV_ROUND_UP(rot_info->height, tile_height); 2655 rot_pages = width_pages * height_pages; 2656 size = rot_pages * PAGE_SIZE; 2657 2658 /* Allocate a temporary list of source pages for random access. */ 2659 page_addr_list = drm_malloc_ab(pages, sizeof(dma_addr_t)); 2660 if (!page_addr_list) 2661 return ERR_PTR(ret); 2662 2663 /* Allocate target SG list. */ 2664 st = kmalloc(sizeof(*st), GFP_KERNEL); 2665 if (!st) 2666 goto err_st_alloc; 2667 2668 ret = sg_alloc_table(st, rot_pages, GFP_KERNEL); 2669 if (ret) 2670 goto err_sg_alloc; 2671 2672 /* Populate source page list from the object. */ 2673 i = 0; 2674 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { 2675 page_addr_list[i] = sg_page_iter_dma_address(&sg_iter); 2676 i++; 2677 } 2678 2679 /* Rotate the pages. */ 2680 rotate_pages(page_addr_list, width_pages, height_pages, st); 2681 2682 DRM_DEBUG_KMS( 2683 "Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages).\n", 2684 size, rot_info->pitch, rot_info->height, 2685 rot_info->pixel_format, width_pages, height_pages, 2686 rot_pages); 2687 2688 drm_free_large(page_addr_list); 2689 2690 return st; 2691 2692err_sg_alloc: 2693 kfree(st); 2694err_st_alloc: 2695 drm_free_large(page_addr_list); 2696 2697 DRM_DEBUG_KMS( 2698 "Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages)\n", 2699 size, ret, rot_info->pitch, rot_info->height, 2700 rot_info->pixel_format, width_pages, height_pages, 2701 rot_pages); 2702 return ERR_PTR(ret); 2703} 2704 2705static inline int 2706i915_get_ggtt_vma_pages(struct i915_vma *vma) 2707{ 2708 int ret = 0; 2709 2710 if (vma->ggtt_view.pages) 2711 return 0; 2712 2713 if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) 2714 vma->ggtt_view.pages = vma->obj->pages; 2715 else if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED) 2716 vma->ggtt_view.pages = 2717 intel_rotate_fb_obj_pages(&vma->ggtt_view, vma->obj); 2718 else 2719 WARN_ONCE(1, "GGTT view %u not implemented!\n", 2720 vma->ggtt_view.type); 2721 2722 if (!vma->ggtt_view.pages) { 2723 DRM_ERROR("Failed to get pages for GGTT view type %u!\n", 2724 vma->ggtt_view.type); 2725 ret = -EINVAL; 2726 } else if (IS_ERR(vma->ggtt_view.pages)) { 2727 ret = PTR_ERR(vma->ggtt_view.pages); 2728 vma->ggtt_view.pages = NULL; 2729 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n", 2730 vma->ggtt_view.type, ret); 2731 } 2732 2733 return ret; 2734} 2735 2736/** 2737 * i915_vma_bind - Sets up PTEs for an VMA in it's corresponding address space. 2738 * @vma: VMA to map 2739 * @cache_level: mapping cache level 2740 * @flags: flags like global or local mapping 2741 * 2742 * DMA addresses are taken from the scatter-gather table of this object (or of 2743 * this VMA in case of non-default GGTT views) and PTE entries set up. 2744 * Note that DMA addresses are also the only part of the SG table we care about. 2745 */ 2746int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, 2747 u32 flags) 2748{ 2749 if (i915_is_ggtt(vma->vm)) { 2750 int ret = i915_get_ggtt_vma_pages(vma); 2751 2752 if (ret) 2753 return ret; 2754 } 2755 2756 vma->bind_vma(vma, cache_level, flags); 2757 2758 return 0; 2759} 2760