Lines Matching refs:I915_READ
55 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
140 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
175 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframe_enabled()
192 u32 val = I915_READ(reg); in ibx_write_infoframe()
227 u32 val = I915_READ(reg); in ibx_infoframe_enabled()
241 u32 val = I915_READ(reg); in cpt_write_infoframe()
279 u32 val = I915_READ(reg); in cpt_infoframe_enabled()
293 u32 val = I915_READ(reg); in vlv_write_infoframe()
328 u32 val = I915_READ(reg); in vlv_infoframe_enabled()
344 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
376 u32 val = I915_READ(ctl_reg); in hsw_infoframe_enabled()
490 u32 val = I915_READ(reg); in g4x_set_infoframes()
545 u32 val = I915_READ(reg); in ibx_set_infoframes()
592 u32 val = I915_READ(reg); in cpt_set_infoframes()
630 u32 val = I915_READ(reg); in vlv_set_infoframes()
677 u32 val = I915_READ(reg); in hsw_set_infoframes()
747 tmp = I915_READ(intel_hdmi->hdmi_reg); in intel_hdmi_get_hw_state()
771 tmp = I915_READ(intel_hdmi->hdmi_reg); in intel_hdmi_get_config()
821 temp = I915_READ(intel_hdmi->hdmi_reg); in intel_enable_hdmi()
873 temp = I915_READ(intel_hdmi->hdmi_reg); in intel_disable_hdmi()
1738 u32 temp = I915_READ(PEG_BAND_GAP_DATA); in intel_hdmi_init_connector()