Lines Matching refs:I915_READ
1041 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
1042 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
1043 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
1044 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
1045 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
1048 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4); in vlv_save_gunit_s0ix_state()
1050 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
1051 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
1053 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
1054 s->ecochk = I915_READ(GAM_ECOCHK); in vlv_save_gunit_s0ix_state()
1055 s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
1056 s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
1058 s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR); in vlv_save_gunit_s0ix_state()
1061 s->g3dctl = I915_READ(VLV_G3DCTL); in vlv_save_gunit_s0ix_state()
1062 s->gsckgctl = I915_READ(VLV_GSCKGCTL); in vlv_save_gunit_s0ix_state()
1063 s->mbctl = I915_READ(GEN6_MBCTL); in vlv_save_gunit_s0ix_state()
1066 s->ucgctl1 = I915_READ(GEN6_UCGCTL1); in vlv_save_gunit_s0ix_state()
1067 s->ucgctl3 = I915_READ(GEN6_UCGCTL3); in vlv_save_gunit_s0ix_state()
1068 s->rcgctl1 = I915_READ(GEN6_RCGCTL1); in vlv_save_gunit_s0ix_state()
1069 s->rcgctl2 = I915_READ(GEN6_RCGCTL2); in vlv_save_gunit_s0ix_state()
1070 s->rstctl = I915_READ(GEN6_RSTCTL); in vlv_save_gunit_s0ix_state()
1071 s->misccpctl = I915_READ(GEN7_MISCCPCTL); in vlv_save_gunit_s0ix_state()
1074 s->gfxpause = I915_READ(GEN6_GFXPAUSE); in vlv_save_gunit_s0ix_state()
1075 s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC); in vlv_save_gunit_s0ix_state()
1076 s->rpdeuc = I915_READ(GEN6_RPDEUC); in vlv_save_gunit_s0ix_state()
1077 s->ecobus = I915_READ(ECOBUS); in vlv_save_gunit_s0ix_state()
1078 s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL); in vlv_save_gunit_s0ix_state()
1079 s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT); in vlv_save_gunit_s0ix_state()
1080 s->rp_deucsw = I915_READ(GEN6_RPDEUCSW); in vlv_save_gunit_s0ix_state()
1081 s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR); in vlv_save_gunit_s0ix_state()
1082 s->rcedata = I915_READ(VLV_RCEDATA); in vlv_save_gunit_s0ix_state()
1083 s->spare2gh = I915_READ(VLV_SPAREG2H); in vlv_save_gunit_s0ix_state()
1086 s->gt_imr = I915_READ(GTIMR); in vlv_save_gunit_s0ix_state()
1087 s->gt_ier = I915_READ(GTIER); in vlv_save_gunit_s0ix_state()
1088 s->pm_imr = I915_READ(GEN6_PMIMR); in vlv_save_gunit_s0ix_state()
1089 s->pm_ier = I915_READ(GEN6_PMIER); in vlv_save_gunit_s0ix_state()
1092 s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4); in vlv_save_gunit_s0ix_state()
1095 s->tilectl = I915_READ(TILECTL); in vlv_save_gunit_s0ix_state()
1096 s->gt_fifoctl = I915_READ(GTFIFOCTL); in vlv_save_gunit_s0ix_state()
1097 s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL); in vlv_save_gunit_s0ix_state()
1098 s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG); in vlv_save_gunit_s0ix_state()
1099 s->pmwgicz = I915_READ(VLV_PMWGICZ); in vlv_save_gunit_s0ix_state()
1102 s->gu_ctl0 = I915_READ(VLV_GU_CTL0); in vlv_save_gunit_s0ix_state()
1103 s->gu_ctl1 = I915_READ(VLV_GU_CTL1); in vlv_save_gunit_s0ix_state()
1104 s->pcbr = I915_READ(VLV_PCBR); in vlv_save_gunit_s0ix_state()
1105 s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2); in vlv_save_gunit_s0ix_state()
1184 val = I915_READ(VLV_GTLC_WAKE_CTRL); in vlv_restore_gunit_s0ix_state()
1189 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); in vlv_restore_gunit_s0ix_state()
1208 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT) in vlv_force_gfx_clock()
1210 val = I915_READ(VLV_GTLC_SURVIVABILITY_REG); in vlv_force_gfx_clock()
1222 I915_READ(VLV_GTLC_SURVIVABILITY_REG)); in vlv_force_gfx_clock()
1233 val = I915_READ(VLV_GTLC_WAKE_CTRL); in vlv_allow_gt_wake()
1240 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \ in vlv_allow_gt_wake()
1258 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val) in vlv_wait_for_gt_wells()
1264 I915_READ(VLV_GTLC_PW_STATUS)); in vlv_wait_for_gt_wells()
1281 if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR)) in vlv_check_no_gt_access()
1300 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask); in vlv_suspend_complete()