327 		if (I915_READ(reg) & DDI_BUF_IS_IDLE)  in intel_wait_ddi_buf_idle()
410 		temp = I915_READ(_FDI_RXA_MISC);  in hsw_fdi_link_train()
418 		temp = I915_READ(DP_TP_STATUS(PORT_E));  in hsw_fdi_link_train()
432 		temp = I915_READ(DDI_BUF_CTL(PORT_E));  in hsw_fdi_link_train()
438 		temp = I915_READ(DP_TP_CTL(PORT_E));  in hsw_fdi_link_train()
451 		temp = I915_READ(_FDI_RXA_MISC);  in hsw_fdi_link_train()
684 	wrpll = I915_READ(reg);  in intel_ddi_calc_wrpll_link()
721 	cfgcr1_val = I915_READ(cfgcr1_reg);  in skl_calc_wrpll_link()
722 	cfgcr2_val = I915_READ(cfgcr2_reg);  in skl_calc_wrpll_link()
781 	dpll_ctl1 = I915_READ(DPLL_CTRL1);  in skl_ddi_clock_get()
850 		pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;  in hsw_ddi_clock_get()
1274 	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_set_vc_payload_alloc()
1388 	uint32_t val = I915_READ(reg);  in intel_ddi_disable_transcoder_func()
1419 	tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_connector_get_hw_state()
1457 	tmp = I915_READ(DDI_BUF_CTL(port));  in intel_ddi_get_hw_state()
1463 		tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));  in intel_ddi_get_hw_state()
1481 			tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));  in intel_ddi_get_hw_state()
1547 			val = I915_READ(DPLL_CTRL1);  in intel_ddi_pre_enable()
1559 		val = I915_READ(DPLL_CTRL2);  in intel_ddi_pre_enable()
1602 	val = I915_READ(DDI_BUF_CTL(port));  in intel_ddi_post_disable()
1609 	val = I915_READ(DP_TP_CTL(port));  in intel_ddi_post_disable()
1625 		I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |  in intel_ddi_post_disable()
1694 	uint32_t lcpll1 = I915_READ(LCPLL1_CTL);  in skl_get_cdclk_freq()
1695 	uint32_t cdctl = I915_READ(CDCLK_CTL);  in skl_get_cdclk_freq()
1706 	linkrate = (I915_READ(DPLL_CTRL1) &  in skl_get_cdclk_freq()
1742 	uint32_t lcpll = I915_READ(LCPLL_CTL);  in bdw_get_cdclk_freq()
1747 	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)  in bdw_get_cdclk_freq()
1762 	uint32_t lcpll = I915_READ(LCPLL_CTL);  in hsw_get_cdclk_freq()
1767 	else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)  in hsw_get_cdclk_freq()
1804 	val = I915_READ(WRPLL_CTL(pll->id));  in hsw_ddi_pll_disable()
1818 	val = I915_READ(WRPLL_CTL(pll->id));  in hsw_ddi_pll_get_hw_state()
1887 	val = I915_READ(DPLL_CTRL1);  in skl_ddi_pll_enable()
1903 		   I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);  in skl_ddi_pll_enable()
1905 	if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))  in skl_ddi_pll_enable()
1916 		   I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);  in skl_ddi_pll_disable()
1934 	val = I915_READ(regs[pll->id].ctl);  in skl_ddi_pll_get_hw_state()
1938 	val = I915_READ(DPLL_CTRL1);  in skl_ddi_pll_get_hw_state()
1943 		hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);  in skl_ddi_pll_get_hw_state()
1944 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_get_hw_state()
1969 	uint32_t val = I915_READ(LCPLL_CTL);  in intel_ddi_pll_init()
1980 		if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))  in intel_ddi_pll_init()
2006 	if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {  in intel_ddi_prepare_link_retrain()
2007 		val = I915_READ(DDI_BUF_CTL(port));  in intel_ddi_prepare_link_retrain()
2014 		val = I915_READ(DP_TP_CTL(port));  in intel_ddi_prepare_link_retrain()
2051 	val = I915_READ(_FDI_RXA_CTL);  in intel_ddi_fdi_disable()
2055 	val = I915_READ(_FDI_RXA_MISC);  in intel_ddi_fdi_disable()
2060 	val = I915_READ(_FDI_RXA_CTL);  in intel_ddi_fdi_disable()
2064 	val = I915_READ(_FDI_RXA_CTL);  in intel_ddi_fdi_disable()
2092 	temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));  in intel_ddi_get_config()
2142 		temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);  in intel_ddi_get_config()
2265 	intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &  in intel_ddi_init()