| /linux-4.1.27/drivers/gpu/drm/exynos/ |
| D | exynos_dp_core.c | 270 int pre_emphasis, int lane) in exynos_dp_set_lane_lane_pre_emphasis()
293 int lane, lane_count, pll_tries, retval; in exynos_dp_link_start() local
352 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) in exynos_dp_get_lane_status()
362 int lane; in exynos_dp_clock_recovery_ok() local
376 int lane; in exynos_dp_channel_eq_ok() local
393 int lane) in exynos_dp_get_adjust_request_voltage()
403 int lane) in exynos_dp_get_adjust_request_pre_emphasis()
412 u8 training_lane_set, int lane) in exynos_dp_set_lane_link_training()
434 int lane) in exynos_dp_get_lane_link_training()
470 int lane, lane_count; in exynos_dp_get_adjust_training_lane() local
[all …]
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| /linux-4.1.27/drivers/gpu/drm/ |
| D | drm_dp_helper.c | 49 int lane) in dp_get_lane_status()
62 int lane; in drm_dp_channel_eq_ok() local
80 int lane; in drm_dp_clock_recovery_ok() local
93 int lane) in drm_dp_get_adjust_request_voltage()
106 int lane) in drm_dp_get_adjust_request_pre_emphasis()
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| /linux-4.1.27/arch/arm/mach-mv78xx0/ |
| D | pcie.c | 21 #define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4) argument
22 #define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane))) argument
23 #define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4) argument
24 #define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane))) argument
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| /linux-4.1.27/drivers/net/ethernet/ti/ |
| D | netcp_xgbepcsr.c | 155 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_config()
189 void __iomem *serdes_regs, int lane) in netcp_xgbe_serdes_lane_enable()
290 void __iomem *sig_detect_reg, int lane) in netcp_xgbe_serdes_reset_cdr()
437 int lane, int cm, int c1, int c2) in netcp_xgbe_serdes_setup_cm_c1_c2()
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| /linux-4.1.27/arch/mips/cavium-octeon/executive/ |
| D | cvmx-helper-errata.c | 51 int lane; in __cvmx_helper_errata_qlm_disable_2nd_order_cdr() local
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| /linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | dport.c | 128 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; in dp_link_train_commit() local
209 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in dp_link_train_cr() local
247 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; in dp_link_train_eq() local
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| D | sorgf110.c | 40 gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) in gf110_sor_dp_lane_map()
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| D | sorgm204.c | 54 gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) in gm204_sor_dp_lane_map()
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| D | sorg94.c | 43 g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane) in g94_sor_dp_lane_map()
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| D | outpdp.c | 66 u8 lane = (stat[i >> 1] >> ((i & 1) * 4)) & 0x0f; in nvkm_output_dp_train() local
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| /linux-4.1.27/drivers/ata/ |
| D | sata_highbank.c | 273 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_disable_overrides() local
284 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_tx_attenuation() local
303 u8 lane = port_data[sata_port].lane_mapping; in cphy_override_rx_mode() local
327 u8 lane = port_data[sata_port].lane_mapping; in highbank_cphy_override_lane() local
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| /linux-4.1.27/drivers/gpu/drm/tegra/ |
| D | sor.c | 137 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_dp_train_fast() local
158 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_dp_train_fast() local
173 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_dp_train_fast() local
1154 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_encoder_mode_set() local
1240 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING | in tegra_sor_encoder_mode_set() local
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| /linux-4.1.27/drivers/media/v4l2-core/ |
| D | v4l2-of.c | 33 const __be32 *lane = NULL; in v4l2_of_parse_csi_bus() local
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| /linux-4.1.27/arch/x86/crypto/sha-mb/ |
| D | sha1_mb_mgr_submit_avx2.S | 89 lane = %rbp define
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| /linux-4.1.27/include/video/ |
| D | sh_mipi_dsi.h | 49 int lane; member
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| /linux-4.1.27/drivers/video/fbdev/omap2/dss/ |
| D | hdmi_phy.c | 47 u8 lane, pol; in hdmi_phy_parse_lanes() local
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| D | dsi.c | 3789 u8 lane, pol; in dsi_configure_pins() local
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| /linux-4.1.27/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 1250 int lane) in cdv_intel_get_adjust_request_voltage()
1263 int lane) in cdv_intel_get_adjust_request_pre_emphasis()
1311 int lane; in cdv_intel_get_adjust_train() local
1336 int lane) in cdv_intel_get_lane_status()
1349 int lane; in cdv_intel_clock_recovery_ok() local
1370 int lane; in cdv_intel_channel_eq_ok() local
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| /linux-4.1.27/drivers/phy/ |
| D | phy-xgene.c | 669 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr()
684 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd()
695 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits()
705 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits()
955 int lane; in xgene_phy_sata_cfg_lanes() local
1354 static void xgene_phy_force_lat_summer_cal(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_force_lat_summer_cal()
1420 static void xgene_phy_reset_rxd(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_reset_rxd()
1434 static void xgene_phy_gen_avg_val(struct xgene_phy_ctx *ctx, int lane) in xgene_phy_gen_avg_val()
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| /linux-4.1.27/drivers/pinctrl/ |
| D | pinctrl-tegra-xusb.c | 294 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinmux_set() local
327 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_get() local
365 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_pinconf_group_set() local
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| /linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_link.c | 3228 u8 lane = 0; in bnx2x_get_warpcore_lane() local
3532 u8 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_ext_phy_update_adv_fc() local
3704 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_restart_AN_KR() local
3717 u16 lane, i, cl72_ctrl, an_adv = 0, val; in bnx2x_warpcore_enable_AN_KR() local
3871 u16 val16, i, lane; in bnx2x_warpcore_set_10G_KR() local
3939 u16 misc1_val, tap_val, tx_driver_val, lane, val; in bnx2x_warpcore_set_10G_XFI() local
4125 u16 lane) in bnx2x_warpcore_set_20G_DXGXS()
4279 u16 lane) in bnx2x_warpcore_clear_regs()
4373 u16 gp2_status_reg0, lane; in bnx2x_warpcore_get_sigdet() local
4398 u16 lane = bnx2x_get_warpcore_lane(phy, params); in bnx2x_warpcore_config_runtime() local
[all …]
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| /linux-4.1.27/arch/sh/drivers/pci/ |
| D | pcie-sh7786.c | 182 unsigned int lane, unsigned int data) in phy_write_reg()
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| /linux-4.1.27/drivers/gpu/drm/msm/edp/ |
| D | edp_ctrl.c | 433 u8 lane; in edp_fill_link_cfg() local
725 u8 rate, lane, max_lane; in edp_link_rate_down_shift() local
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| /linux-4.1.27/drivers/edac/ |
| D | ppc4xx_edac.h | 159 #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1) argument
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| D | ppc4xx_edac.c | 441 unsigned int lane, lanes; in ppc4xx_edac_generate_lane_message() local
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| /linux-4.1.27/drivers/net/ethernet/sfc/ |
| D | txc43128_phy.c | 211 int lane; in txc_bist_one() local
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| /linux-4.1.27/drivers/gpu/drm/radeon/ |
| D | atombios_dp.c | 263 int lane; in dp_get_adjust_train() local
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| /linux-4.1.27/drivers/video/fbdev/exynos/ |
| D | exynos_mipi_dsi_lowlevel.c | 253 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, in exynos_mipi_dsi_enable_lane()
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| /linux-4.1.27/drivers/media/platform/marvell-ccic/ |
| D | mcam-core.h | 128 int lane; /* lane number */ member
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| /linux-4.1.27/drivers/pci/host/ |
| D | pcie-rcar.c | 421 unsigned int lane, unsigned int data) in phy_write_reg()
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| D | pci-mvebu.c | 115 u32 lane; member
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| D | pci-tegra.c | 1598 unsigned int lane = 0; in tegra_pcie_parse_dt() local
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| /linux-4.1.27/drivers/gpu/drm/i915/ |
| D | i915_reg.h | 1104 #define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ argument
1107 #define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) argument
1108 #define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) argument
1109 #define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) argument
1110 #define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) argument
1111 #define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) argument
1112 #define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) argument
1113 #define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) argument
1114 #define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) argument
1115 #define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) argument
[all …]
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| D | intel_dp.c | 3248 int lane; in intel_get_adjust_train() local
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| D | intel_display.c | 5766 int lane, link_bw, fdi_dotclock; in ironlake_fdi_compute_config() local
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