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Searched refs:nvkm_wr32 (Results 1 – 160 of 160) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dgm204.c249 nvkm_wr32(device, 0x418880, 0x00001000 | (tmp & 0x00000fff)); in gm204_gr_init()
250 nvkm_wr32(device, 0x418890, 0x00000000); in gm204_gr_init()
251 nvkm_wr32(device, 0x418894, 0x00000000); in gm204_gr_init()
252 nvkm_wr32(device, 0x4188b4, nvkm_memory_addr(gr->unk4188b4) >> 8); in gm204_gr_init()
253 nvkm_wr32(device, 0x4188b8, nvkm_memory_addr(gr->unk4188b8) >> 8); in gm204_gr_init()
257 nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); in gm204_gr_init()
258 nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); in gm204_gr_init()
265 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); in gm204_gr_init()
278 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); in gm204_gr_init()
279 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); in gm204_gr_init()
[all …]
Dgk104.c190 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); in gk104_gr_init()
191 nvkm_wr32(device, GPC_BCAST(0x08a4), 0x00000000); in gk104_gr_init()
192 nvkm_wr32(device, GPC_BCAST(0x0888), 0x00000000); in gk104_gr_init()
193 nvkm_wr32(device, GPC_BCAST(0x088c), 0x00000000); in gk104_gr_init()
194 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); in gk104_gr_init()
195 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); in gk104_gr_init()
196 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); in gk104_gr_init()
197 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); in gk104_gr_init()
201 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); in gk104_gr_init()
214 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); in gk104_gr_init()
[all …]
Dgm107.c303 nvkm_wr32(device, regs[E].ctrl, infoE.data); in gm107_gr_init_bios()
305 nvkm_wr32(device, regs[E].data, infoX.data); in gm107_gr_init_bios()
320 nvkm_wr32(device, GPC_BCAST(0x0880), 0x00000000); in gm107_gr_init()
321 nvkm_wr32(device, GPC_BCAST(0x0890), 0x00000000); in gm107_gr_init()
322 nvkm_wr32(device, GPC_BCAST(0x0894), 0x00000000); in gm107_gr_init()
323 nvkm_wr32(device, GPC_BCAST(0x08b4), nvkm_memory_addr(gr->unk4188b4) >> 8); in gm107_gr_init()
324 nvkm_wr32(device, GPC_BCAST(0x08b8), nvkm_memory_addr(gr->unk4188b8) >> 8); in gm107_gr_init()
330 nvkm_wr32(device, GPC_UNIT(0, 0x3018), 0x00000001); in gm107_gr_init()
343 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); in gm107_gr_init()
344 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); in gm107_gr_init()
[all …]
Dnv40.c105 nvkm_wr32(device, 0x400720, 0x00000000); in nv40_gr_chan_fini()
106 nvkm_wr32(device, 0x400784, inst); in nv40_gr_chan_fini()
189 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv40_gr_tile()
190 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv40_gr_tile()
191 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv40_gr_tile()
192 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv40_gr_tile()
193 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv40_gr_tile()
194 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv40_gr_tile()
198 nvkm_wr32(device, NV20_PGRAPH_ZCOMP(i), tile->zcomp); in nv40_gr_tile()
199 nvkm_wr32(device, NV40_PGRAPH_ZCOMP1(i), tile->zcomp); in nv40_gr_tile()
[all …]
Dnv20.c41 nvkm_wr32(device, 0x400784, inst >> 4); in nv20_gr_chan_fini()
42 nvkm_wr32(device, 0x400788, 0x00000002); in nv20_gr_chan_fini()
47 nvkm_wr32(device, 0x400144, 0x10000000); in nv20_gr_chan_fini()
158 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv20_gr_tile()
159 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv20_gr_tile()
160 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv20_gr_tile()
162 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0030 + 4 * i); in nv20_gr_tile()
163 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->limit); in nv20_gr_tile()
164 nvkm_wr32(device, NV10_PGRAPH_RDI_INDEX, 0x00EA0050 + 4 * i); in nv20_gr_tile()
165 nvkm_wr32(device, NV10_PGRAPH_RDI_DATA, tile->pitch); in nv20_gr_tile()
[all …]
Dnv30.c108 nvkm_wr32(device, NV20_PGRAPH_CHANNEL_CTX_TABLE, in nv30_gr_init()
111 nvkm_wr32(device, NV03_PGRAPH_INTR , 0xFFFFFFFF); in nv30_gr_init()
112 nvkm_wr32(device, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); in nv30_gr_init()
114 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); in nv30_gr_init()
115 nvkm_wr32(device, NV04_PGRAPH_DEBUG_0, 0x00000000); in nv30_gr_init()
116 nvkm_wr32(device, NV04_PGRAPH_DEBUG_1, 0x401287c0); in nv30_gr_init()
117 nvkm_wr32(device, 0x400890, 0x01b463ff); in nv30_gr_init()
118 nvkm_wr32(device, NV04_PGRAPH_DEBUG_3, 0xf2de0475); in nv30_gr_init()
119 nvkm_wr32(device, NV10_PGRAPH_DEBUG_4, 0x00008000); in nv30_gr_init()
120 nvkm_wr32(device, NV04_PGRAPH_LIMIT_VIOL_PIX, 0xf04bdff6); in nv30_gr_init()
[all …]
Dgf100.c48 nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); in gf100_gr_zbc_clear_color()
49 nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); in gf100_gr_zbc_clear_color()
50 nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); in gf100_gr_zbc_clear_color()
51 nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); in gf100_gr_zbc_clear_color()
53 nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); in gf100_gr_zbc_clear_color()
54 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_color()
55 nvkm_wr32(device, 0x405824, 0x00000004); /* TRIGGER | WRITE | COLOR */ in gf100_gr_zbc_clear_color()
99 nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); in gf100_gr_zbc_clear_depth()
100 nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); in gf100_gr_zbc_clear_depth()
101 nvkm_wr32(device, 0x405820, zbc); in gf100_gr_zbc_clear_depth()
[all …]
Dnv50.c313 nvkm_wr32(device, addr + 0x10, mp10); in nv50_gr_mp_trap()
314 nvkm_wr32(device, addr + 0x14, 0); in nv50_gr_mp_trap()
385 nvkm_wr32(device, ustatus_addr, 0xc0000000); in nv50_gr_tp_trap()
416 nvkm_wr32(device, 0x400500, 0x00000000); in nv50_gr_trap_handler()
441 nvkm_wr32(device, 0x400808, 0); in nv50_gr_trap_handler()
442 nvkm_wr32(device, 0x4008e8, nvkm_rd32(device, 0x4008e8) & 3); in nv50_gr_trap_handler()
443 nvkm_wr32(device, 0x400848, 0); in nv50_gr_trap_handler()
466 nvkm_wr32(device, 0x40084c, 0); in nv50_gr_trap_handler()
475 nvkm_wr32(device, 0x400804, 0xc0000000); in nv50_gr_trap_handler()
476 nvkm_wr32(device, 0x400108, 0x001); in nv50_gr_trap_handler()
[all …]
Dnv44.c44 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
45 nvkm_wr32(device, NV20_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
46 nvkm_wr32(device, NV20_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
53 nvkm_wr32(device, NV47_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
54 nvkm_wr32(device, NV47_PGRAPH_TLIMIT(i), tile->limit); in nv44_gr_tile()
55 nvkm_wr32(device, NV47_PGRAPH_TILE(i), tile->addr); in nv44_gr_tile()
56 nvkm_wr32(device, NV40_PGRAPH_TSIZE1(i), tile->pitch); in nv44_gr_tile()
57 nvkm_wr32(device, NV40_PGRAPH_TLIMIT1(i), tile->limit); in nv44_gr_tile()
58 nvkm_wr32(device, NV40_PGRAPH_TILE1(i), tile->addr); in nv44_gr_tile()
61 nvkm_wr32(device, NV20_PGRAPH_TSIZE(i), tile->pitch); in nv44_gr_tile()
[all …]
Dnv10.c417 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
425 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, addr); \
427 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, state[__i]); \
464 nvkm_wr32(device, NV10_PGRAPH_XFMODE0, 0x10000000); in nv17_gr_mthd_lma_window()
465 nvkm_wr32(device, NV10_PGRAPH_XFMODE1, 0x00000000); in nv17_gr_mthd_lma_window()
466 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x000064c0); in nv17_gr_mthd_lma_window()
468 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
470 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x00000000); in nv17_gr_mthd_lma_window()
472 nvkm_wr32(device, NV10_PGRAPH_PIPE_ADDRESS, 0x00006ab0); in nv17_gr_mthd_lma_window()
474 nvkm_wr32(device, NV10_PGRAPH_PIPE_DATA, 0x3f800000); in nv17_gr_mthd_lma_window()
[all …]
Dgk20a.c178 nvkm_wr32(device, 0x419e44, 0x1ffffe); in gk20a_gr_set_hww_esr_report_mask()
179 nvkm_wr32(device, 0x419e4c, 0x7f); in gk20a_gr_set_hww_esr_report_mask()
193 nvkm_wr32(device, 0x40802c, 0x1); in gk20a_gr_init()
206 nvkm_wr32(device, 0x100cc8, nvkm_memory_addr(gr->unk4188b4) >> 8); in gk20a_gr_init()
207 nvkm_wr32(device, 0x100ccc, nvkm_memory_addr(gr->unk4188b8) >> 8); in gk20a_gr_init()
227 nvkm_wr32(device, GPC_BCAST(0x0980), data[0]); in gk20a_gr_init()
228 nvkm_wr32(device, GPC_BCAST(0x0984), data[1]); in gk20a_gr_init()
229 nvkm_wr32(device, GPC_BCAST(0x0988), data[2]); in gk20a_gr_init()
230 nvkm_wr32(device, GPC_BCAST(0x098c), data[3]); in gk20a_gr_init()
233 nvkm_wr32(device, GPC_UNIT(gpc, 0x0914), in gk20a_gr_init()
[all …]
Dgm20b.c37 nvkm_wr32(device, 0x100ce4, 0xffffffff); in gm20b_gr_init_gpc_mmu()
43 nvkm_wr32(device, 0x418880, val); in gm20b_gr_init_gpc_mmu()
44 nvkm_wr32(device, 0x418890, 0); in gm20b_gr_init_gpc_mmu()
45 nvkm_wr32(device, 0x418894, 0); in gm20b_gr_init_gpc_mmu()
47 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); in gm20b_gr_init_gpc_mmu()
48 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); in gm20b_gr_init_gpc_mmu()
49 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); in gm20b_gr_init_gpc_mmu()
51 nvkm_wr32(device, 0x4188ac, nvkm_rd32(device, 0x100800)); in gm20b_gr_init_gpc_mmu()
58 nvkm_wr32(device, 0x419e44, 0xdffffe); in gm20b_gr_set_hww_esr_report_mask()
59 nvkm_wr32(device, 0x419e4c, 0x5); in gm20b_gr_set_hww_esr_report_mask()
Dctxgf100.c1024 nvkm_wr32(device, addr, data); in gf100_grctx_mmio_item()
1094 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); in gf100_grctx_generate_tpcid()
1095 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x4e8), id); in gf100_grctx_generate_tpcid()
1096 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); in gf100_grctx_generate_tpcid()
1097 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); in gf100_grctx_generate_tpcid()
1101 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); in gf100_grctx_generate_tpcid()
1102 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); in gf100_grctx_generate_tpcid()
1115 nvkm_wr32(device, 0x406028 + (i * 4), tmp[i]); in gf100_grctx_generate_r406028()
1116 nvkm_wr32(device, 0x405870 + (i * 4), tmp[i]); in gf100_grctx_generate_r406028()
1140 nvkm_wr32(device, 0x4060a8 + (i * 4), ((u32 *)data)[i]); in gf100_grctx_generate_r4060a8()
[all …]
Dctxgm20b.c34 nvkm_wr32(device, 0x406028, tpc_per_gpc); in gm20b_grctx_generate_r406028()
35 nvkm_wr32(device, 0x405870, tpc_per_gpc); in gm20b_grctx_generate_r406028()
51 nvkm_wr32(device, 0x404154, 0x00000000); in gm20b_grctx_generate_main()
62 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); in gm20b_grctx_generate_main()
64 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm20b_grctx_generate_main()
67 nvkm_wr32(device, 0x408908, nvkm_rd32(device, 0x410108) | 0x80000000); in gm20b_grctx_generate_main()
71 nvkm_wr32(device, 0x4041c4, tmp); in gm20b_grctx_generate_main()
77 nvkm_wr32(device, 0x404154, idle_timeout_save); in gm20b_grctx_generate_main()
Dctxgm204.c930 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); in gm204_grctx_generate_tpcid()
931 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); in gm204_grctx_generate_tpcid()
932 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); in gm204_grctx_generate_tpcid()
975 nvkm_wr32(device, 0x405b60 + (i * 4), dist[i]); in gm204_grctx_generate_405b60()
977 nvkm_wr32(device, 0x405ba0 + (i * 4), gpcs[i]); in gm204_grctx_generate_405b60()
994 nvkm_wr32(device, 0x404154, 0x00000000); in gm204_grctx_generate_main()
1006 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); in gm204_grctx_generate_main()
1007 nvkm_wr32(device, 0x406500, 0x00000000); in gm204_grctx_generate_main()
1009 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm204_grctx_generate_main()
1015 nvkm_wr32(device, 0x4041c4, tmp); in gm204_grctx_generate_main()
[all …]
Dctxgk104.c926 nvkm_wr32(device, 0x418bb8, (gr->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
929 nvkm_wr32(device, 0x418b08 + (i * 4), data[i]); in gk104_grctx_generate_r418bb8()
932 nvkm_wr32(device, 0x41bfd0, (gr->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
934 nvkm_wr32(device, 0x41bfe4, data2[1]); in gk104_grctx_generate_r418bb8()
936 nvkm_wr32(device, 0x41bf00 + (i * 4), data[i]); in gk104_grctx_generate_r418bb8()
939 nvkm_wr32(device, 0x4078bc, (gr->tpc_total << 8) | in gk104_grctx_generate_r418bb8()
942 nvkm_wr32(device, 0x40780c + (i * 4), data[i]); in gk104_grctx_generate_r418bb8()
969 nvkm_wr32(device, 0x404154, 0x00000000); in gk104_grctx_generate_main()
982 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); in gk104_grctx_generate_main()
984 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk104_grctx_generate_main()
[all …]
Dctxgm107.c943 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x698), id); in gm107_grctx_generate_tpcid()
944 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c10 + tpc * 4), id); in gm107_grctx_generate_tpcid()
945 nvkm_wr32(device, TPC_UNIT(gpc, tpc, 0x088), id); in gm107_grctx_generate_tpcid()
949 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c08), gr->tpc_nr[gpc]); in gm107_grctx_generate_tpcid()
950 nvkm_wr32(device, GPC_UNIT(gpc, 0x0c8c), gr->tpc_nr[gpc]); in gm107_grctx_generate_tpcid()
968 nvkm_wr32(device, 0x404154, 0x00000000); in gm107_grctx_generate_main()
980 nvkm_wr32(device, 0x4064d0, 0x00000001); in gm107_grctx_generate_main()
982 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); in gm107_grctx_generate_main()
983 nvkm_wr32(device, 0x406500, 0x00000001); in gm107_grctx_generate_main()
985 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gm107_grctx_generate_main()
[all …]
Dnv04.c453 nvkm_wr32(device, 0x700000 + inst, tmp); in nv04_gr_set_ctx1()
455 nvkm_wr32(device, NV04_PGRAPH_CTX_SWITCH1, tmp); in nv04_gr_set_ctx1()
456 nvkm_wr32(device, NV04_PGRAPH_CTX_CACHE1 + (subc << 2), tmp); in nv04_gr_set_ctx1()
472 nvkm_wr32(device, 0x70000c + inst, tmp); in nv04_gr_set_ctx_val()
535 nvkm_wr32(device, 0x40053c, min); in nv04_gr_mthd_surf3d_clip_h()
536 nvkm_wr32(device, 0x400544, max); in nv04_gr_mthd_surf3d_clip_h()
553 nvkm_wr32(device, 0x400540, min); in nv04_gr_mthd_surf3d_clip_v()
554 nvkm_wr32(device, 0x400548, max); in nv04_gr_mthd_surf3d_clip_v()
1091 nvkm_wr32(device, nv04_gr_ctx_regs[i], chan->nv04[i]); in nv04_gr_load_context()
1093 nvkm_wr32(device, NV04_PGRAPH_CTX_CONTROL, 0x10010100); in nv04_gr_load_context()
[all …]
Dctxgk20a.c40 nvkm_wr32(device, 0x404154, 0x00000000); in gk20a_grctx_generate_main()
52 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); in gk20a_grctx_generate_main()
54 nvkm_wr32(device, 0x405b00, (gr->tpc_total << 8) | gr->gpc_nr); in gk20a_grctx_generate_main()
62 nvkm_wr32(device, 0x404154, idle_timeout_save); in gk20a_grctx_generate_main()
Dctxgf117.c236 nvkm_wr32(device, 0x404154, 0x00000000); in gf117_grctx_generate_main()
250 nvkm_wr32(device, 0x4064d0 + (i * 0x04), 0x00000000); in gf117_grctx_generate_main()
253 nvkm_wr32(device, 0x404154, 0x00000400); in gf117_grctx_generate_main()
Dg84.c165 nvkm_wr32(device, 0x100c80, 0x00000001); in g84_gr_tlb_flush()
Dctxnv40.c686 nvkm_wr32(device, 0x400324, 0); in nv40_grctx_init()
688 nvkm_wr32(device, 0x400328, ctxprog[i]); in nv40_grctx_init()
Dctxnv50.c279 nvkm_wr32(device, 0x400324, 0); in nv50_grctx_init()
281 nvkm_wr32(device, 0x400328, ctxprog[i]); in nv50_grctx_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv04.c58 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
78 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_pause()
80 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); in nv04_fifo_pause()
92 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); in nv04_fifo_start()
119 nvkm_wr32(device, 0x003280, (engine &= ~mask)); in nv04_fifo_swmthd()
170 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); in nv04_fifo_cache_error()
171 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_cache_error()
173 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
175 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_cache_error()
176 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
[all …]
Dnv40.c70 nvkm_wr32(device, 0x002040, 0x000000ff); in nv40_fifo_init()
71 nvkm_wr32(device, 0x002044, 0x2101ffff); in nv40_fifo_init()
72 nvkm_wr32(device, 0x002058, 0x00000001); in nv40_fifo_init()
74 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv40_fifo_init()
77 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv40_fifo_init()
83 nvkm_wr32(device, 0x002230, 0x00000001); in nv40_fifo_init()
90 nvkm_wr32(device, 0x002220, 0x00030002); in nv40_fifo_init()
93 nvkm_wr32(device, 0x002230, 0x00000000); in nv40_fifo_init()
94 nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 + in nv40_fifo_init()
100 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); in nv40_fifo_init()
[all …]
Dnv17.c60 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); in nv17_fifo_init()
61 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv17_fifo_init()
63 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv17_fifo_init()
66 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv17_fifo_init()
67 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | in nv17_fifo_init()
70 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); in nv17_fifo_init()
72 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); in nv17_fifo_init()
73 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv17_fifo_init()
75 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv17_fifo_init()
76 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv17_fifo_init()
[all …]
Dnv50.c46 nvkm_wr32(device, 0x0032f4, nvkm_memory_addr(cur) >> 12); in nv50_fifo_runlist_update_locked()
47 nvkm_wr32(device, 0x0032ec, p); in nv50_fifo_runlist_update_locked()
48 nvkm_wr32(device, 0x002500, 0x00000101); in nv50_fifo_runlist_update_locked()
84 nvkm_wr32(device, 0x00250c, 0x6f3cfc34); in nv50_fifo_init()
85 nvkm_wr32(device, 0x002044, 0x01003fff); in nv50_fifo_init()
87 nvkm_wr32(device, 0x002100, 0xffffffff); in nv50_fifo_init()
88 nvkm_wr32(device, 0x002140, 0xbfffffff); in nv50_fifo_init()
91 nvkm_wr32(device, 0x002600 + (i * 4), 0x00000000); in nv50_fifo_init()
94 nvkm_wr32(device, 0x003200, 0x00000001); in nv50_fifo_init()
95 nvkm_wr32(device, 0x003250, 0x00000001); in nv50_fifo_init()
[all …]
Dgf100.c70 nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12); in gf100_fifo_runlist_update()
71 nvkm_wr32(device, 0x002274, 0x01f00000 | nr); in gf100_fifo_runlist_update()
143 nvkm_wr32(device, 0x00262c, engm); in gf100_fifo_recover_work()
392 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); in gf100_fifo_intr_pbdma()
393 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); in gf100_fifo_intr_pbdma()
405 nvkm_wr32(device, 0x002a00, 0x10000000); in gf100_fifo_intr_runlist()
411 nvkm_wr32(device, 0x002a00, intr); in gf100_fifo_intr_runlist()
424 nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); in gf100_fifo_intr_engine_unit()
464 nvkm_wr32(device, 0x002100, 0x00000001); in gf100_fifo_intr()
470 nvkm_wr32(device, 0x002100, 0x00000100); in gf100_fifo_intr()
[all …]
Dgk104.c71 nvkm_wr32(device, 0x002270, nvkm_memory_addr(cur) >> 12); in gk104_fifo_runlist_update()
72 nvkm_wr32(device, 0x002274, (engine << 20) | nr); in gk104_fifo_runlist_update()
118 nvkm_wr32(device, 0x00262c, engm); in gk104_fifo_recover_work()
236 nvkm_wr32(device, 0x00256c, stat); in gk104_fifo_intr_chsw()
471 nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); in gk104_fifo_intr_pbdma_0()
485 nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); in gk104_fifo_intr_pbdma_0()
515 nvkm_wr32(device, 0x040148 + (unit * 0x2000), stat); in gk104_fifo_intr_pbdma_1()
526 nvkm_wr32(device, 0x002a00, 1 << engn); in gk104_fifo_intr_runlist()
548 nvkm_wr32(device, 0x002100, 0x00000001); in gk104_fifo_intr()
554 nvkm_wr32(device, 0x002100, 0x00000010); in gk104_fifo_intr()
[all …]
Ddmanv04.c84 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); in nv04_fifo_dma_fini()
90 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 0); in nv04_fifo_dma_fini()
104 nvkm_wr32(device, c->regp, 0x00000000); in nv04_fifo_dma_fini()
107 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, 0); in nv04_fifo_dma_fini()
108 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUT, 0); in nv04_fifo_dma_fini()
109 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, mask); in nv04_fifo_dma_fini()
110 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_fifo_dma_fini()
111 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_dma_fini()
116 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); in nv04_fifo_dma_fini()
Dchannv50.c75 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); in nv50_fifo_chan_engine_fini()
85 nvkm_wr32(device, 0x00b860, me); in nv50_fifo_chan_engine_fini()
189 nvkm_wr32(device, 0x002600 + (chid * 4), 0x00000000); in nv50_fifo_chan_fini()
201 nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | addr); in nv50_fifo_chan_init()
Dgpfifogf100.c62 nvkm_wr32(device, 0x002634, chan->base.chid); in gf100_fifo_gpfifo_engine_fini()
148 nvkm_wr32(device, 0x003000 + coff, 0x00000000); in gf100_fifo_gpfifo_fini()
160 nvkm_wr32(device, 0x003000 + coff, 0xc0000000 | addr); in gf100_fifo_gpfifo_init()
164 nvkm_wr32(device, 0x003004 + coff, 0x001f0001); in gf100_fifo_gpfifo_init()
Dchang84.c107 nvkm_wr32(device, 0x0032fc, chan->base.inst->addr >> 12); in g84_fifo_chan_engine_fini()
112 nvkm_wr32(device, 0x002520, save); in g84_fifo_chan_engine_fini()
213 nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | addr); in g84_fifo_chan_init()
Dgpfifogk104.c43 nvkm_wr32(device, 0x002634, chan->base.chid); in gk104_fifo_gpfifo_kick()
159 nvkm_wr32(device, 0x800000 + coff, 0x00000000); in gk104_fifo_gpfifo_fini()
172 nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr); in gk104_fifo_gpfifo_init()
Ddmanv40.c75 nvkm_wr32(device, reg, 0x00000000); in nv40_fifo_dma_engine_fini()
106 nvkm_wr32(device, reg, inst); in nv40_fifo_dma_engine_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dbase.c64 nvkm_wr32(device, 0x10a580, 0x00000001); in nvkm_pmu_send()
68 nvkm_wr32(device, 0x10a1c0, 0x01000000 | (((addr & 0x07) << 4) + in nvkm_pmu_send()
70 nvkm_wr32(device, 0x10a1c4, process); in nvkm_pmu_send()
71 nvkm_wr32(device, 0x10a1c4, message); in nvkm_pmu_send()
72 nvkm_wr32(device, 0x10a1c4, data0); in nvkm_pmu_send()
73 nvkm_wr32(device, 0x10a1c4, data1); in nvkm_pmu_send()
74 nvkm_wr32(device, 0x10a4a0, (addr + 1) & 0x0f); in nvkm_pmu_send()
77 nvkm_wr32(device, 0x10a580, 0x00000000); in nvkm_pmu_send()
105 nvkm_wr32(device, 0x10a580, 0x00000002); in nvkm_pmu_recv()
109 nvkm_wr32(device, 0x10a1c0, 0x02000000 | (((addr & 0x07) << 4) + in nvkm_pmu_recv()
[all …]
Dgk104.c36 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_()
37 nvkm_wr32(device, 0x00c808, 0x00000000); in magic_()
38 nvkm_wr32(device, 0x00c800, ctrl); in magic_()
42 nvkm_wr32(device, 0x00c804, 0x00000000); in magic_()
46 nvkm_wr32(device, 0x00c800, 0x00000000); in magic_()
Dmemx.c23 nvkm_wr32(device, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd); in memx_out()
25 nvkm_wr32(device, 0x10a1c4, memx->c.data[i]); in memx_out()
64 nvkm_wr32(device, 0x10a580, 0x00000003); in nvkm_memx_init()
66 nvkm_wr32(device, 0x10a1c0, 0x01000000 | memx->base); in nvkm_memx_init()
84 nvkm_wr32(device, 0x10a580, 0x00000000); in nvkm_memx_fini()
182 nvkm_wr32(device, 0x10a1c0, 0x02000000 | base); in nvkm_memx_train_result()
Dgk20a.c113 nvkm_wr32(device, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
114 nvkm_wr32(device, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000); in gk20a_pmu_dvfs_reset_dev_status()
190 nvkm_wr32(device, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001); in gk20a_pmu_init()
191 nvkm_wr32(device, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002); in gk20a_pmu_init()
192 nvkm_wr32(device, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003); in gk20a_pmu_init()
Dgk110.c69 nvkm_wr32(device, magic[i].addr, magic[i].data); in gk110_pmu_pgob()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c73 nvkm_wr32(device, 0x00b308, 0x00000100); in nv50_mpeg_intr()
83 nvkm_wr32(device, 0x00b100, stat); in nv50_mpeg_intr()
84 nvkm_wr32(device, 0x00b230, 0x00000001); in nv50_mpeg_intr()
93 nvkm_wr32(device, 0x00b32c, 0x00000000); in nv50_mpeg_init()
94 nvkm_wr32(device, 0x00b314, 0x00000100); in nv50_mpeg_init()
95 nvkm_wr32(device, 0x00b0e0, 0x0000001a); in nv50_mpeg_init()
97 nvkm_wr32(device, 0x00b220, 0x00000044); in nv50_mpeg_init()
98 nvkm_wr32(device, 0x00b300, 0x00801ec1); in nv50_mpeg_init()
99 nvkm_wr32(device, 0x00b390, 0x00000000); in nv50_mpeg_init()
100 nvkm_wr32(device, 0x00b394, 0x00000000); in nv50_mpeg_init()
[all …]
Dnv31.c119 nvkm_wr32(device, 0x00b008 + (i * 0x10), tile->pitch); in nv31_mpeg_tile()
120 nvkm_wr32(device, 0x00b004 + (i * 0x10), tile->limit); in nv31_mpeg_tile()
121 nvkm_wr32(device, 0x00b000 + (i * 0x10), tile->addr); in nv31_mpeg_tile()
142 nvkm_wr32(device, 0x00b334, base); in nv31_mpeg_mthd_dma()
143 nvkm_wr32(device, 0x00b324, size); in nv31_mpeg_mthd_dma()
149 nvkm_wr32(device, 0x00b360, base); in nv31_mpeg_mthd_dma()
150 nvkm_wr32(device, 0x00b364, size); in nv31_mpeg_mthd_dma()
156 nvkm_wr32(device, 0x00b370, base); in nv31_mpeg_mthd_dma()
157 nvkm_wr32(device, 0x00b374, size); in nv31_mpeg_mthd_dma()
206 nvkm_wr32(device, 0x00b100, stat); in nv31_mpeg_intr()
[all …]
Dnv40.c48 nvkm_wr32(device, 0x00b334, base); in nv40_mpeg_mthd_dma()
49 nvkm_wr32(device, 0x00b324, size); in nv40_mpeg_mthd_dma()
54 nvkm_wr32(device, 0x00b360, base); in nv40_mpeg_mthd_dma()
55 nvkm_wr32(device, 0x00b364, size); in nv40_mpeg_mthd_dma()
61 nvkm_wr32(device, 0x00b370, base); in nv40_mpeg_mthd_dma()
62 nvkm_wr32(device, 0x00b374, size); in nv40_mpeg_mthd_dma()
Dnv44.c180 nvkm_wr32(device, 0x00b100, stat); in nv44_mpeg_intr()
181 nvkm_wr32(device, 0x00b230, 0x00000001); in nv44_mpeg_intr()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/
Dfalcon.c75 nvkm_wr32(device, base + 0x004, 0x00000040); in nvkm_falcon_intr()
82 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_intr()
88 nvkm_wr32(device, base + 0x004, intr); in nvkm_falcon_intr()
111 nvkm_wr32(device, base + 0x014, 0xffffffff); in nvkm_falcon_fini()
180 nvkm_wr32(device, base + 0x004, 0x00000010); in nvkm_falcon_init()
184 nvkm_wr32(device, base + 0x014, 0xffffffff); in nvkm_falcon_init()
263 nvkm_wr32(device, base + 0x618, 0x04000000); in nvkm_falcon_init()
265 nvkm_wr32(device, base + 0x618, 0x00000114); in nvkm_falcon_init()
266 nvkm_wr32(device, base + 0x11c, 0); in nvkm_falcon_init()
267 nvkm_wr32(device, base + 0x110, addr >> 8); in nvkm_falcon_init()
[all …]
Dxtensa.c70 nvkm_wr32(device, base + 0xc20, intr); in nvkm_xtensa_intr()
85 nvkm_wr32(device, base + 0xd84, 0); /* INTR_EN */ in nvkm_xtensa_fini()
86 nvkm_wr32(device, base + 0xd94, 0); /* FIFO_CTRL */ in nvkm_xtensa_fini()
140 nvkm_wr32(device, base + 0xd10, 0x1fffffff); /* ?? */ in nvkm_xtensa_init()
141 nvkm_wr32(device, base + 0xd08, 0x0fffffff); /* ?? */ in nvkm_xtensa_init()
143 nvkm_wr32(device, base + 0xd28, xtensa->func->unkd28); /* ?? */ in nvkm_xtensa_init()
144 nvkm_wr32(device, base + 0xc20, 0x3f); /* INTR */ in nvkm_xtensa_init()
145 nvkm_wr32(device, base + 0xd84, 0x3f); /* INTR_EN */ in nvkm_xtensa_init()
147 nvkm_wr32(device, base + 0xcc0, addr >> 8); /* XT_REGION_BASE */ in nvkm_xtensa_init()
148 nvkm_wr32(device, base + 0xcc4, 0x1c); /* XT_REGION_SETUP */ in nvkm_xtensa_init()
[all …]
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.c159 nvkm_wr32(device, 0x001584, in setPLL_single()
166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff)); in setPLL_single()
169 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1); in setPLL_single()
178 nvkm_wr32(device, reg, pll); in setPLL_single()
181 nvkm_wr32(device, 0x001584, saved_powerctrl_1); in setPLL_single()
238 nvkm_wr32(device, 0x001584, in setPLL_double_highregs()
259 nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040)); in setPLL_double_highregs()
263 nvkm_wr32(device, 0x680580, ramdac580); in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
[all …]
Dgm204.c37 nvkm_wr32(device, 0x10a180, 0x01000000 | (sec ? 0x10000000 : 0) | pmu); in pmu_code()
40 nvkm_wr32(device, 0x10a188, (pmu + i) >> 8); in pmu_code()
41 nvkm_wr32(device, 0x10a184, nvbios_rd32(bios, img + i)); in pmu_code()
45 nvkm_wr32(device, 0x10a184, 0x00000000); in pmu_code()
57 nvkm_wr32(device, 0x10a1c0, 0x01000000 | pmu); in pmu_data()
59 nvkm_wr32(device, 0x10a1c4, nvbios_rd32(bios, img + i)); in pmu_data()
66 nvkm_wr32(device, 0x10a1c0, argp); in pmu_args()
67 nvkm_wr32(device, 0x10a1c0, nvkm_rd32(device, 0x10a1c4) + argi); in pmu_args()
75 nvkm_wr32(device, 0x10a104, init_addr); in pmu_exec()
76 nvkm_wr32(device, 0x10a10c, 0x00000000); in pmu_exec()
[all …]
Dnv50.c59 nvkm_wr32(device, info.reg + 0, 0x10000611); in nv50_devinit_pll_set()
69 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
73 nvkm_wr32(device, info.reg + 4, (N1 << 8) | M1); in nv50_devinit_pll_set()
Dgf100.c54 nvkm_wr32(device, info.reg + 0x04, (P << 16) | (N << 8) | M); in gf100_devinit_pll_set()
55 nvkm_wr32(device, info.reg + 0x10, fN << 16); in gf100_devinit_pll_set()
Dgt215.c51 nvkm_wr32(device, info.reg + 0, 0x50000610); in gt215_devinit_pll_set()
54 nvkm_wr32(device, info.reg + 8, fN); in gt215_devinit_pll_set()
Dnv20.c48 nvkm_wr32(device, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); in nv20_devinit_meminit()
Dnv10.c55 nvkm_wr32(device, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1); in nv10_devinit_meminit()
Dnv05.c84 nvkm_wr32(device, NV04_PFB_SCRAMBLE(i), scramble); in nv05_devinit_meminit()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgm107.c33 nvkm_wr32(device, 0x17e270, start); in gm107_ltc_cbc_clear()
34 nvkm_wr32(device, 0x17e274, limit); in gm107_ltc_cbc_clear()
35 nvkm_wr32(device, 0x17e26c, 0x00000004); in gm107_ltc_cbc_clear()
59 nvkm_wr32(device, 0x17e33c, color[0]); in gm107_ltc_zbc_clear_color()
60 nvkm_wr32(device, 0x17e340, color[1]); in gm107_ltc_zbc_clear_color()
61 nvkm_wr32(device, 0x17e344, color[2]); in gm107_ltc_zbc_clear_color()
62 nvkm_wr32(device, 0x17e348, color[3]); in gm107_ltc_zbc_clear_color()
70 nvkm_wr32(device, 0x17e34c, depth); in gm107_ltc_zbc_clear_depth()
83 nvkm_wr32(device, base + 0x00c, stat); in gm107_ltc_lts_isr()
126 nvkm_wr32(device, 0x17e27c, ltc->ltc_nr); in gm107_ltc_init()
[all …]
Dgf100.c34 nvkm_wr32(device, 0x17e8cc, start); in gf100_ltc_cbc_clear()
35 nvkm_wr32(device, 0x17e8d0, limit); in gf100_ltc_cbc_clear()
36 nvkm_wr32(device, 0x17e8c8, 0x00000004); in gf100_ltc_cbc_clear()
60 nvkm_wr32(device, 0x17ea48, color[0]); in gf100_ltc_zbc_clear_color()
61 nvkm_wr32(device, 0x17ea4c, color[1]); in gf100_ltc_zbc_clear_color()
62 nvkm_wr32(device, 0x17ea50, color[2]); in gf100_ltc_zbc_clear_color()
63 nvkm_wr32(device, 0x17ea54, color[3]); in gf100_ltc_zbc_clear_color()
71 nvkm_wr32(device, 0x17ea58, depth); in gf100_ltc_zbc_clear_depth()
107 nvkm_wr32(device, base + 0x020, intr); in gf100_ltc_lts_intr()
131 nvkm_wr32(device, 0x70004, 0x00000001); in gf100_ltc_invalidate()
[all …]
Dgk104.c32 nvkm_wr32(device, 0x17e8d8, ltc->ltc_nr); in gk104_ltc_init()
33 nvkm_wr32(device, 0x17e000, ltc->ltc_nr); in gk104_ltc_init()
34 nvkm_wr32(device, 0x17e8d4, ltc->tag_base); in gk104_ltc_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dg84.c64 nvkm_wr32(device, 0x20000, 0x000003ff); in g84_therm_program_alarms()
67 nvkm_wr32(device, 0x20484, sensor->thrs_shutdown.hysteresis); in g84_therm_program_alarms()
68 nvkm_wr32(device, 0x20480, sensor->thrs_shutdown.temp); in g84_therm_program_alarms()
71 nvkm_wr32(device, 0x204c4, sensor->thrs_fan_boost.temp); in g84_therm_program_alarms()
74 nvkm_wr32(device, 0x204c0, sensor->thrs_critical.temp); in g84_therm_program_alarms()
77 nvkm_wr32(device, 0x20414, sensor->thrs_down_clock.temp); in g84_therm_program_alarms()
110 nvkm_wr32(device, thrs_reg, thrs->temp - thrs->hysteresis); in g84_therm_threshold_hyst_emulation()
113 nvkm_wr32(device, thrs_reg, thrs->temp); in g84_therm_threshold_hyst_emulation()
187 nvkm_wr32(device, 0x20100, 0xffffffff); in g84_therm_intr()
188 nvkm_wr32(device, 0x1100, 0x10000); /* PBUS */ in g84_therm_intr()
[all …]
Dnv40.c61 nvkm_wr32(device, 0x15b0, 0x80003fff); in nv40_sensor_setup()
65 nvkm_wr32(device, 0x15b0, 0xff); in nv40_sensor_setup()
81 nvkm_wr32(device, 0x15b0, 0x80003fff); in nv40_temp_get()
84 nvkm_wr32(device, 0x15b0, 0xff); in nv40_temp_get()
157 nvkm_wr32(device, 0x0015f8, divs); in nv40_fan_pwm_set()
177 nvkm_wr32(device, 0x1100, 0x70000); in nv40_therm_intr()
Dgf119.c96 nvkm_wr32(device, 0x00e114 + (indx * 8), divs); in gf119_fan_pwm_set()
97 nvkm_wr32(device, 0x00e118 + (indx * 8), duty | 0x80000000); in gf119_fan_pwm_set()
100 nvkm_wr32(device, 0x0200dc, duty | 0x40000000); in gf119_fan_pwm_set()
129 nvkm_wr32(device, 0x00e724, device->crystal * 1000); in gf119_therm_init()
Dnv50.c90 nvkm_wr32(device, 0x00e114 + (id * 8), divs); in nv50_fan_pwm_set()
91 nvkm_wr32(device, 0x00e118 + (id * 8), duty | 0x80000000); in nv50_fan_pwm_set()
Dgm107.c47 nvkm_wr32(device, 0x10eb14, duty | 0x80000000); in gm107_fan_pwm_set()
Dgt215.c50 nvkm_wr32(device, 0x00e724, device->crystal * 1000); in gt215_therm_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dhdmig84.c66 nvkm_wr32(device, 0x616528 + hoff, 0x000d0282); in g84_hdmi_ctrl()
67 nvkm_wr32(device, 0x61652c + hoff, 0x0000006f); in g84_hdmi_ctrl()
68 nvkm_wr32(device, 0x616530 + hoff, 0x00000000); in g84_hdmi_ctrl()
69 nvkm_wr32(device, 0x616534 + hoff, 0x00000000); in g84_hdmi_ctrl()
70 nvkm_wr32(device, 0x616538 + hoff, 0x00000000); in g84_hdmi_ctrl()
75 nvkm_wr32(device, 0x616508 + hoff, 0x000a0184); in g84_hdmi_ctrl()
76 nvkm_wr32(device, 0x61650c + hoff, 0x00000071); in g84_hdmi_ctrl()
77 nvkm_wr32(device, 0x616510 + hoff, 0x00000000); in g84_hdmi_ctrl()
Dhdmigt215.c67 nvkm_wr32(device, 0x61c528 + soff, 0x000d0282); in gt215_hdmi_ctrl()
68 nvkm_wr32(device, 0x61c52c + soff, 0x0000006f); in gt215_hdmi_ctrl()
69 nvkm_wr32(device, 0x61c530 + soff, 0x00000000); in gt215_hdmi_ctrl()
70 nvkm_wr32(device, 0x61c534 + soff, 0x00000000); in gt215_hdmi_ctrl()
71 nvkm_wr32(device, 0x61c538 + soff, 0x00000000); in gt215_hdmi_ctrl()
76 nvkm_wr32(device, 0x61c508 + soff, 0x000a0184); in gt215_hdmi_ctrl()
77 nvkm_wr32(device, 0x61c50c + soff, 0x00000071); in gt215_hdmi_ctrl()
78 nvkm_wr32(device, 0x61c510 + soff, 0x00000000); in gt215_hdmi_ctrl()
Drootgf119.c73 nvkm_wr32(device, 0x6100b0, 0x00000000); in gf119_disp_root_fini()
92 nvkm_wr32(device, 0x6101b4 + (i * 0x800), tmp); in gf119_disp_root_init()
94 nvkm_wr32(device, 0x6101b8 + (i * 0x800), tmp); in gf119_disp_root_init()
96 nvkm_wr32(device, 0x6101bc + (i * 0x800), tmp); in gf119_disp_root_init()
102 nvkm_wr32(device, 0x6101c0 + (i * 0x800), tmp); in gf119_disp_root_init()
108 nvkm_wr32(device, 0x6301c4 + (i * 0x800), tmp); in gf119_disp_root_init()
113 nvkm_wr32(device, 0x6100ac, 0x00000100); in gf119_disp_root_init()
123 nvkm_wr32(device, 0x610010, (root->instmem->addr >> 8) | 9); in gf119_disp_root_init()
126 nvkm_wr32(device, 0x610090, 0x00000000); in gf119_disp_root_init()
127 nvkm_wr32(device, 0x6100a0, 0x00000000); in gf119_disp_root_init()
[all …]
Dhdmigk104.c66 nvkm_wr32(device, 0x690008 + hdmi, 0x000d0282); in gk104_hdmi_ctrl()
67 nvkm_wr32(device, 0x69000c + hdmi, 0x0000006f); in gk104_hdmi_ctrl()
68 nvkm_wr32(device, 0x690010 + hdmi, 0x00000000); in gk104_hdmi_ctrl()
69 nvkm_wr32(device, 0x690014 + hdmi, 0x00000000); in gk104_hdmi_ctrl()
70 nvkm_wr32(device, 0x690018 + hdmi, 0x00000000); in gk104_hdmi_ctrl()
75 nvkm_wr32(device, 0x6900cc + hdmi, 0x00000010); in gk104_hdmi_ctrl()
79 nvkm_wr32(device, 0x690080 + hdmi, 0x82000000); in gk104_hdmi_ctrl()
Dhdmigf119.c65 nvkm_wr32(device, 0x61671c + hoff, 0x000d0282); in gf119_hdmi_ctrl()
66 nvkm_wr32(device, 0x616720 + hoff, 0x0000006f); in gf119_hdmi_ctrl()
67 nvkm_wr32(device, 0x616724 + hoff, 0x00000000); in gf119_hdmi_ctrl()
68 nvkm_wr32(device, 0x616728 + hoff, 0x00000000); in gf119_hdmi_ctrl()
69 nvkm_wr32(device, 0x61672c + hoff, 0x00000000); in gf119_hdmi_ctrl()
74 nvkm_wr32(device, 0x6167ac + hoff, 0x00000010); in gf119_hdmi_ctrl()
Dnv04.c36 nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000001); in nv04_disp_vblank_init()
43 nvkm_wr32(device, 0x600140 + (head * 0x2000) , 0x00000000); in nv04_disp_vblank_fini()
57 nvkm_wr32(device, 0x600100, 0x00000001); in nv04_disp_intr()
62 nvkm_wr32(device, 0x602100, 0x00000001); in nv04_disp_intr()
69 nvkm_wr32(device, 0x8100, pvideo); in nv04_disp_intr()
Ddmacgf119.c75 nvkm_wr32(device, 0x610494 + (chid * 0x0010), chan->push); in gf119_disp_dmac_init()
76 nvkm_wr32(device, 0x610498 + (chid * 0x0010), 0x00010000); in gf119_disp_dmac_init()
77 nvkm_wr32(device, 0x61049c + (chid * 0x0010), 0x00000001); in gf119_disp_dmac_init()
79 nvkm_wr32(device, 0x640000 + (chid * 0x1000), 0x00000000); in gf119_disp_dmac_init()
80 nvkm_wr32(device, 0x610490 + (chid * 0x0010), 0x00000013); in gf119_disp_dmac_init()
Drootnv50.c301 nvkm_wr32(device, 0x610024, 0x00000000); in nv50_disp_root_fini()
302 nvkm_wr32(device, 0x610020, 0x00000000); in nv50_disp_root_fini()
318 nvkm_wr32(device, 0x610184, tmp); in nv50_disp_root_init()
323 nvkm_wr32(device, 0x610190 + (i * 0x10), tmp); in nv50_disp_root_init()
325 nvkm_wr32(device, 0x610194 + (i * 0x10), tmp); in nv50_disp_root_init()
327 nvkm_wr32(device, 0x610198 + (i * 0x10), tmp); in nv50_disp_root_init()
329 nvkm_wr32(device, 0x61019c + (i * 0x10), tmp); in nv50_disp_root_init()
335 nvkm_wr32(device, 0x6101d0 + (i * 0x04), tmp); in nv50_disp_root_init()
341 nvkm_wr32(device, 0x6101e0 + (i * 0x04), tmp); in nv50_disp_root_init()
347 nvkm_wr32(device, 0x6101f0 + (i * 0x04), tmp); in nv50_disp_root_init()
[all …]
Dcoregf119.c208 nvkm_wr32(device, 0x610494, chan->push); in gf119_disp_core_init()
209 nvkm_wr32(device, 0x610498, 0x00010000); in gf119_disp_core_init()
210 nvkm_wr32(device, 0x61049c, 0x00000001); in gf119_disp_core_init()
212 nvkm_wr32(device, 0x640000, 0x00000000); in gf119_disp_core_init()
213 nvkm_wr32(device, 0x610490, 0x01000013); in gf119_disp_core_init()
Dcorenv50.c206 nvkm_wr32(device, 0x610204, chan->push); in nv50_disp_core_init()
207 nvkm_wr32(device, 0x610208, 0x00010000); in nv50_disp_core_init()
208 nvkm_wr32(device, 0x61020c, 0x00000000); in nv50_disp_core_init()
210 nvkm_wr32(device, 0x640000, 0x00000000); in nv50_disp_core_init()
211 nvkm_wr32(device, 0x610200, 0x01000013); in nv50_disp_core_init()
Dsorgf119.c96 nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); in gf119_sor_dp_drv_ctl()
97 nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); in gf119_sor_dp_drv_ctl()
98 nvkm_wr32(device, 0x61c130 + loff, data[2]); in gf119_sor_dp_drv_ctl()
100 nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); in gf119_sor_dp_drv_ctl()
Dsorgm204.c122 nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); in gm204_sor_dp_drv_ctl()
123 nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); in gm204_sor_dp_drv_ctl()
124 nvkm_wr32(device, 0x61c130 + loff, data[2]); in gm204_sor_dp_drv_ctl()
126 nvkm_wr32(device, 0x61c13c + loff, data[3] | (ocfg.pc << shift)); in gm204_sor_dp_drv_ctl()
Ddmacnv50.c222 nvkm_wr32(device, 0x610204 + (chid * 0x0010), chan->push); in nv50_disp_dmac_init()
223 nvkm_wr32(device, 0x610208 + (chid * 0x0010), 0x00010000); in nv50_disp_dmac_init()
224 nvkm_wr32(device, 0x61020c + (chid * 0x0010), chid); in nv50_disp_dmac_init()
226 nvkm_wr32(device, 0x640000 + (chid * 0x1000), 0x00000000); in nv50_disp_dmac_init()
227 nvkm_wr32(device, 0x610200 + (chid * 0x0010), 0x00000013); in nv50_disp_dmac_init()
Dchangf119.c32 nvkm_wr32(device, 0x61008c, 0x00000001 << index); in gf119_disp_chan_uevent_fini()
40 nvkm_wr32(device, 0x61008c, 0x00000001 << index); in gf119_disp_chan_uevent_init()
Dgf119.c233 nvkm_wr32(device, 0x612200 + (head * 0x800), 0x00000000); in gf119_disp_intr_unk2_1()
295 nvkm_wr32(device, 0x616610 + hoff, value); in gf119_disp_intr_unk2_2_tu()
417 nvkm_wr32(device, 0x6101d4 + (head * 0x800), 0x00000000); in gf119_disp_intr_supervisor()
418 nvkm_wr32(device, 0x6101d0, 0x80000000); in gf119_disp_intr_supervisor()
443 nvkm_wr32(device, 0x61009c, (1 << chid)); in gf119_disp_intr_error()
444 nvkm_wr32(device, 0x6101f0 + (chid * 12), 0x90000000); in gf119_disp_intr_error()
460 nvkm_wr32(device, 0x61008c, 1 << chid); in gf119_disp_intr()
478 nvkm_wr32(device, 0x6100ac, disp->super); in gf119_disp_intr()
484 nvkm_wr32(device, 0x6100ac, stat); in gf119_disp_intr()
Dpiocnv50.c55 nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00002000); in nv50_disp_pioc_init()
65 nvkm_wr32(device, 0x610200 + (chid * 0x10), 0x00000001); in nv50_disp_pioc_init()
Dhdagt215.c62 nvkm_wr32(device, 0x61c440 + soff, (i << 8) | args->v0.data[0]); in gt215_hda_eld()
64 nvkm_wr32(device, 0x61c440 + soff, (i << 8)); in gt215_hda_eld()
Dhdagf119.c66 nvkm_wr32(device, 0x10ec00 + soff, (i << 8) | args->v0.data[i]); in gf119_hda_eld()
68 nvkm_wr32(device, 0x10ec00 + soff, (i << 8)); in gf119_hda_eld()
Dsorg94.c149 nvkm_wr32(device, 0x61c118 + loff, data[0] | (ocfg.dc << shift)); in g94_sor_dp_drv_ctl()
150 nvkm_wr32(device, 0x61c120 + loff, data[1] | (ocfg.pe << shift)); in g94_sor_dp_drv_ctl()
151 nvkm_wr32(device, 0x61c130 + loff, data[2]); in g94_sor_dp_drv_ctl()
Dchannv50.c108 nvkm_wr32(device, 0x610020, 0x00000001 << index); in nv50_disp_chan_uevent_fini()
116 nvkm_wr32(device, 0x610020, 0x00000001 << index); in nv50_disp_chan_uevent_init()
172 nvkm_wr32(device, 0x640000 + (chan->chid * 0x1000) + addr, data); in nv50_disp_chan_wr32()
Dpiocgf119.c63 nvkm_wr32(device, 0x610490 + (chid * 0x10), 0x00000001); in gf119_disp_pioc_init()
Dnv50.c222 nvkm_wr32(device, 0x610020, 0x00010000 << chid); in nv50_disp_intr_error()
223 nvkm_wr32(device, 0x610080 + (chid * 0x08), 0x90000000); in nv50_disp_intr_error()
776 nvkm_wr32(device, 0x610030, 0x80000000); in nv50_disp_intr_supervisor()
800 nvkm_wr32(device, 0x610024, 0x00000004); in nv50_disp_intr()
805 nvkm_wr32(device, 0x610024, 0x00000008); in nv50_disp_intr()
811 nvkm_wr32(device, 0x610024, disp->super); in nv50_disp_intr()
Ddacnv50.c97 nvkm_wr32(device, 0x61a00c + doff, 0x00100000 | loadval); in nv50_dac_sense()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
Dnv04.c38 nvkm_wr32(device, NV04_PTIMER_TIME_1, hi); in nv04_timer_time()
39 nvkm_wr32(device, NV04_PTIMER_TIME_0, lo); in nv04_timer_time()
60 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000000); in nv04_timer_alarm_fini()
67 nvkm_wr32(device, NV04_PTIMER_ALARM_0, time); in nv04_timer_alarm_init()
68 nvkm_wr32(device, NV04_PTIMER_INTR_EN_0, 0x00000001); in nv04_timer_alarm_init()
80 nvkm_wr32(device, NV04_PTIMER_INTR_0, 0x00000001); in nv04_timer_intr()
86 nvkm_wr32(device, NV04_PTIMER_INTR_0, stat); in nv04_timer_intr()
133 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); in nv04_timer_init()
134 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); in nv04_timer_init()
Dnv41.c66 nvkm_wr32(device, 0x009220, m - 1); in nv41_timer_init()
67 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); in nv41_timer_init()
68 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); in nv41_timer_init()
Dnv40.c70 nvkm_wr32(device, NV04_PTIMER_NUMERATOR, n); in nv40_timer_init()
71 nvkm_wr32(device, NV04_PTIMER_DENOMINATOR, d); in nv40_timer_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv50.c37 nvkm_wr32(device, 0x001304, 0x00000000); in nv50_bus_hwsq_exec()
39 nvkm_wr32(device, 0x001400 + (i * 4), data[i]); in nv50_bus_hwsq_exec()
41 nvkm_wr32(device, 0x00130c, 0x00000003); in nv50_bus_hwsq_exec()
68 nvkm_wr32(device, 0x001100, 0x00000008); in nv50_bus_intr()
76 nvkm_wr32(device, 0x001100, 0x00010000); in nv50_bus_intr()
89 nvkm_wr32(device, 0x001100, 0xffffffff); in nv50_bus_init()
90 nvkm_wr32(device, 0x001140, 0x00010008); in nv50_bus_init()
Dg94.c36 nvkm_wr32(device, 0x001304, 0x00000000); in g94_bus_hwsq_exec()
37 nvkm_wr32(device, 0x001318, 0x00000000); in g94_bus_hwsq_exec()
39 nvkm_wr32(device, 0x080000 + (i * 4), data[i]); in g94_bus_hwsq_exec()
41 nvkm_wr32(device, 0x00130c, 0x00000001); in g94_bus_hwsq_exec()
Dnv04.c41 nvkm_wr32(device, 0x001100, 0x00000001); in nv04_bus_intr()
49 nvkm_wr32(device, 0x001100, 0x00000110); in nv04_bus_intr()
62 nvkm_wr32(device, 0x001100, 0xffffffff); in nv04_bus_init()
63 nvkm_wr32(device, 0x001140, 0x00000111); in nv04_bus_init()
Dgf100.c46 nvkm_wr32(device, 0x009084, 0x00000000); in gf100_bus_intr()
47 nvkm_wr32(device, 0x001100, (stat & 0x0000000e)); in gf100_bus_intr()
61 nvkm_wr32(device, 0x001100, 0xffffffff); in gf100_bus_init()
62 nvkm_wr32(device, 0x001140, 0x0000000e); in gf100_bus_init()
Dnv31.c53 nvkm_wr32(device, 0x001100, 0x00000008); in nv31_bus_intr()
61 nvkm_wr32(device, 0x001100, 0x00070000); in nv31_bus_intr()
74 nvkm_wr32(device, 0x001100, 0xffffffff); in nv31_bus_init()
75 nvkm_wr32(device, 0x001140, 0x00070008); in nv31_bus_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mc/
Dnv44.c32 nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */ in nv44_mc_init()
34 nvkm_wr32(device, 0x001700, tmp); in nv44_mc_init()
35 nvkm_wr32(device, 0x001704, 0); in nv44_mc_init()
36 nvkm_wr32(device, 0x001708, 0); in nv44_mc_init()
37 nvkm_wr32(device, 0x00170c, tmp); in nv44_mc_init()
Dgf100.c55 nvkm_wr32(device, 0x000140, 0x00000000); in gf100_mc_intr_unarm()
56 nvkm_wr32(device, 0x000144, 0x00000000); in gf100_mc_intr_unarm()
64 nvkm_wr32(device, 0x000140, 0x00000001); in gf100_mc_intr_rearm()
65 nvkm_wr32(device, 0x000144, 0x00000001); in gf100_mc_intr_rearm()
80 nvkm_wr32(mc->subdev.device, 0x000260, data); in gf100_mc_unk260()
Dnv04.c45 nvkm_wr32(device, 0x000140, 0x00000000); in nv04_mc_intr_unarm()
53 nvkm_wr32(device, 0x000140, 0x00000001); in nv04_mc_intr_rearm()
66 nvkm_wr32(device, 0x000200, 0xffffffff); /* everything enabled */ in nv04_mc_init()
67 nvkm_wr32(device, 0x001850, 0x00000001); /* disable rom access */ in nv04_mc_init()
Dnv50.c48 nvkm_wr32(device, 0x000200, 0xffffffff); /* everything on */ in nv50_mc_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dnv41.c33 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv41_fb_tile_prog()
34 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv41_fb_tile_prog()
35 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv41_fb_tile_prog()
37 nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp); in nv41_fb_tile_prog()
43 nvkm_wr32(fb->subdev.device, 0x100800, 0x00000001); in nv41_fb_init()
Dramnv40.c116 nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */ in nv40_ram_prog()
117 nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */ in nv40_ram_prog()
118 nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */ in nv40_ram_prog()
120 nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */ in nv40_ram_prog()
132 nvkm_wr32(device, 0x004048, ram->coef); in nv40_ram_prog()
133 nvkm_wr32(device, 0x004030, ram->coef); in nv40_ram_prog()
138 nvkm_wr32(device, 0x00403c, ram->coef); in nv40_ram_prog()
141 nvkm_wr32(device, 0x004024, ram->coef); in nv40_ram_prog()
148 nvkm_wr32(device, 0x1002dc, 0x00000000); in nv40_ram_prog()
Dnv44.c43 nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit); in nv44_fb_tile_prog()
44 nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch); in nv44_fb_tile_prog()
45 nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr); in nv44_fb_tile_prog()
53 nvkm_wr32(device, 0x100850, 0x80000000); in nv44_fb_init()
54 nvkm_wr32(device, 0x100800, 0x00000001); in nv44_fb_init()
Dnv20.c73 nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit); in nv20_fb_tile_prog()
74 nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch); in nv20_fb_tile_prog()
75 nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr); in nv20_fb_tile_prog()
77 nvkm_wr32(device, 0x100300 + (i * 0x04), tile->zcomp); in nv20_fb_tile_prog()
Dnv10.c51 nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit); in nv10_fb_tile_prog()
52 nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch); in nv10_fb_tile_prog()
53 nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr); in nv10_fb_tile_prog()
Drammcp77.c44 nvkm_wr32(device, 0x100c18, dniso); in mcp77_ram_init()
46 nvkm_wr32(device, 0x100c1c, hostnb); in mcp77_ram_init()
48 nvkm_wr32(device, 0x100c24, flush); in mcp77_ram_init()
Dnv50.c172 nvkm_wr32(device, 0x100c90, idx | i << 24); in nv50_fb_intr()
175 nvkm_wr32(device, 0x100c90, idx | 0x80000000); in nv50_fb_intr()
223 nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8); in nv50_fb_init()
227 nvkm_wr32(device, 0x100c90, fb->func->trap); in nv50_fb_init()
Dramgf100.c533 nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8)); in gf100_ram_init()
534 nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8)); in gf100_ram_init()
535 nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]); in gf100_ram_init()
536 nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]); in gf100_ram_init()
537 nvkm_wr32(device, 0x10f918, train1[i % 12]); in gf100_ram_init()
538 nvkm_wr32(device, 0x10f91c, train1[i % 12]); in gf100_ram_init()
539 nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]); in gf100_ram_init()
540 nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]); in gf100_ram_init()
541 nvkm_wr32(device, 0x10f918, train1[i % 12]); in gf100_ram_init()
542 nvkm_wr32(device, 0x10f91c, train1[i % 12]); in gf100_ram_init()
Dramgt215.c198 nvkm_wr32(device, 0x111400, 0x00000000); in gt215_link_train()
203 nvkm_wr32(device, 0x100c04, 0x00000400); in gt215_link_train()
307 nvkm_wr32(device, 0x100538, 0x10000000 | (mem->offset >> 16)); in gt215_link_train_init()
308 nvkm_wr32(device, 0x1005a8, 0x0000ffff); in gt215_link_train_init()
312 nvkm_wr32(device, 0x10f8c0, (i << 8) | i); in gt215_link_train_init()
313 nvkm_wr32(device, 0x10f900, pattern[i % 16]); in gt215_link_train_init()
317 nvkm_wr32(device, 0x10f8e0, (i << 8) | i); in gt215_link_train_init()
318 nvkm_wr32(device, 0x10f920, pattern[i % 16]); in gt215_link_train_init()
323 nvkm_wr32(device, 0x1700, mem->offset >> 16); in gt215_link_train_init()
325 nvkm_wr32(device, 0x700000 + (i << 2), pattern[i]); in gt215_link_train_init()
[all …]
Dnv30.c107 nvkm_wr32(device, 0x10037c + 0xc * i + 0x4 * j, in nv30_fb_init()
111 nvkm_wr32(device, 0x1003ac + 0x8 * i + 0x4 * j, in nv30_fb_init()
Dnv04.c45 nvkm_wr32(device, NV04_PFB_CFG0, 0x1114); in nv04_fb_init()
Dgf100.c56 nvkm_wr32(device, 0x100c10, fb->r100c10 >> 8); in gf100_fb_init()
Dramgk104.c1339 nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8)); in gk104_ram_train_init_0()
1340 nvkm_wr32(device, 0x10f920 + j, 0x00000000 | in gk104_ram_train_init_0()
1343 nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]); in gk104_ram_train_init_0()
1344 nvkm_wr32(device, 0x10f920 + j, 0x00000100 | in gk104_ram_train_init_0()
1347 nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]); in gk104_ram_train_init_0()
1353 nvkm_wr32(device, 0x10f968 + j, i); in gk104_ram_train_init_0()
1354 nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]); in gk104_ram_train_init_0()
1431 nvkm_wr32(device, 0x10ecc0, 0xffffffff); in gk104_ram_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/ibus/
Dgk20a.c35 nvkm_wr32(device, 0x12004c, 0x4); in gk20a_ibus_init_ibus_ring()
36 nvkm_wr32(device, 0x122204, 0x2); in gk20a_ibus_init_ibus_ring()
43 nvkm_wr32(device, 0x122354, 0x800); in gk20a_ibus_init_ibus_ring()
44 nvkm_wr32(device, 0x128328, 0x800); in gk20a_ibus_init_ibus_ring()
45 nvkm_wr32(device, 0x124320, 0x800); in gk20a_ibus_init_ibus_ring()
Dgf100.c100 nvkm_wr32(device, 0x12232c, 0x00100064); in gf100_ibus_init()
101 nvkm_wr32(device, 0x122330, 0x00100064); in gf100_ibus_init()
102 nvkm_wr32(device, 0x122334, 0x00100064); in gf100_ibus_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/sw/
Dgf100.c47 nvkm_wr32(device, 0x001718, 0x80000000 | inst); in gf100_sw_chan_vblsem_release()
49 nvkm_wr32(device, 0x06000c, upper_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
50 nvkm_wr32(device, 0x060010, lower_32_bits(chan->vblank.offset)); in gf100_sw_chan_vblsem_release()
51 nvkm_wr32(device, 0x060014, chan->vblank.value); in gf100_sw_chan_vblsem_release()
81 nvkm_wr32(device, 0x419e00, data); in gf100_sw_chan_mthd()
85 nvkm_wr32(device, 0x419e44, data); in gf100_sw_chan_mthd()
90 nvkm_wr32(device, 0x419eac, data); in gf100_sw_chan_mthd()
Dnv50.c46 nvkm_wr32(device, 0x001704, chan->base.fifo->inst->addr >> 12); in nv50_sw_chan_vblsem_release()
47 nvkm_wr32(device, 0x001710, 0x80000000 | chan->vblank.ctxdma); in nv50_sw_chan_vblsem_release()
51 nvkm_wr32(device, 0x001570, chan->vblank.offset); in nv50_sw_chan_vblsem_release()
52 nvkm_wr32(device, 0x001574, chan->vblank.value); in nv50_sw_chan_vblsem_release()
54 nvkm_wr32(device, 0x060010, chan->vblank.offset); in nv50_sw_chan_vblsem_release()
55 nvkm_wr32(device, 0x060014, chan->vblank.value); in nv50_sw_chan_vblsem_release()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
Dnv44.c148 nvkm_wr32(device, 0x100814, mmu->base.limit - NV44_GART_PAGE); in nv44_vm_flush()
149 nvkm_wr32(device, 0x100808, 0x00000020); in nv44_vm_flush()
154 nvkm_wr32(device, 0x100808, 0x00000000); in nv44_vm_flush()
203 nvkm_wr32(device, 0x100850, 0x80000000); in nv44_mmu_init()
204 nvkm_wr32(device, 0x100818, mmu->null); in nv44_mmu_init()
205 nvkm_wr32(device, 0x100804, NV44_GART_SIZE); in nv44_mmu_init()
206 nvkm_wr32(device, 0x100850, 0x00008000); in nv44_mmu_init()
208 nvkm_wr32(device, 0x100820, 0x00000000); in nv44_mmu_init()
209 nvkm_wr32(device, 0x10082c, 0x00000001); in nv44_mmu_init()
210 nvkm_wr32(device, 0x100800, addr | 0x00000010); in nv44_mmu_init()
Dnv41.c75 nvkm_wr32(device, 0x100810, 0x00000022); in nv41_vm_flush()
80 nvkm_wr32(device, 0x100810, 0x00000000); in nv41_vm_flush()
113 nvkm_wr32(device, 0x100800, 0x00000002 | nvkm_memory_addr(dma)); in nv41_mmu_init()
115 nvkm_wr32(device, 0x100820, 0x00000000); in nv41_mmu_init()
Dgf100.c183 nvkm_wr32(device, 0x100cb8, vpgd->obj->addr >> 8); in gf100_vm_flush()
184 nvkm_wr32(device, 0x100cbc, 0x80000000 | type); in gf100_vm_flush()
Dnv50.c191 nvkm_wr32(device, 0x100c80, (vme << 16) | 1); in nv50_vm_flush()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/cipher/
Dg84.c104 nvkm_wr32(device, 0x102130, stat); in g84_cipher_intr()
105 nvkm_wr32(device, 0x10200c, 0x10); in g84_cipher_intr()
112 nvkm_wr32(device, 0x102130, 0xffffffff); in g84_cipher_init()
113 nvkm_wr32(device, 0x102140, 0xffffffbf); in g84_cipher_init()
114 nvkm_wr32(device, 0x10200c, 0x00000010); in g84_cipher_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dg94.c36 nvkm_wr32(device, 0x00e054, intr0); in g94_gpio_intr_stat()
37 nvkm_wr32(device, 0x00e074, intr1); in g94_gpio_intr_stat()
56 nvkm_wr32(device, 0x00e050, inte0); in g94_gpio_intr_mask()
57 nvkm_wr32(device, 0x00e070, inte1); in g94_gpio_intr_mask()
Dgk104.c36 nvkm_wr32(device, 0x00dc00, intr0); in gk104_gpio_intr_stat()
37 nvkm_wr32(device, 0x00dc80, intr1); in gk104_gpio_intr_stat()
56 nvkm_wr32(device, 0x00dc08, inte0); in gk104_gpio_intr_mask()
57 nvkm_wr32(device, 0x00dc88, inte1); in gk104_gpio_intr_mask()
Dnv10.c90 nvkm_wr32(device, 0x001104, intr); in nv10_gpio_intr_stat()
102 nvkm_wr32(device, 0x001144, inte); in nv10_gpio_intr_mask()
Dnv50.c103 nvkm_wr32(device, 0x00e054, intr); in nv50_gpio_intr_stat()
115 nvkm_wr32(device, 0x00e050, inte); in nv50_gpio_intr_mask()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Dgf100.c139 nvkm_wr32(device, dom->addr + 0x09c, 0x00040002 | (dom->mode << 3)); in gf100_perfctr_init()
140 nvkm_wr32(device, dom->addr + 0x100, 0x00000000); in gf100_perfctr_init()
141 nvkm_wr32(device, dom->addr + 0x040 + (ctr->slot * 0x08), src); in gf100_perfctr_init()
142 nvkm_wr32(device, dom->addr + 0x044 + (ctr->slot * 0x08), log); in gf100_perfctr_init()
164 nvkm_wr32(device, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27); in gf100_perfctr_next()
165 nvkm_wr32(device, dom->addr + 0x0ec, 0x00000011); in gf100_perfctr_next()
Dnv40.c38 nvkm_wr32(device, 0x00a7c0 + dom->addr, 0x00000001 | (dom->mode << 4)); in nv40_perfctr_init()
39 nvkm_wr32(device, 0x00a400 + dom->addr + (ctr->slot * 0x40), src); in nv40_perfctr_init()
40 nvkm_wr32(device, 0x00a420 + dom->addr + (ctr->slot * 0x40), log); in nv40_perfctr_init()
63 nvkm_wr32(device, 0x400084, 0x00000020); in nv40_perfctr_next()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dmcp77.c324 nvkm_wr32(device, 0x402c, clk->ccoef); in mcp77_clk_prog()
325 nvkm_wr32(device, 0x4028, 0x80000000 | clk->cctrl); in mcp77_clk_prog()
326 nvkm_wr32(device, 0x4040, clk->cpost); in mcp77_clk_prog()
345 nvkm_wr32(device, 0x4024, clk->scoef); in mcp77_clk_prog()
346 nvkm_wr32(device, 0x4020, 0x80000000 | clk->sctrl); in mcp77_clk_prog()
347 nvkm_wr32(device, 0x4070, clk->spost); in mcp77_clk_prog()
367 nvkm_wr32(device, 0x4600, clk->vdiv); in mcp77_clk_prog()
370 nvkm_wr32(device, 0xc054, mast); in mcp77_clk_prog()
375 nvkm_wr32(device, 0x4040, 0x00000000); in mcp77_clk_prog()
380 nvkm_wr32(device, 0x4070, 0x00000000); in mcp77_clk_prog()
Dgt215.c380 nvkm_wr32(device, coef, info->pll); in prog_pll()
421 nvkm_wr32(device, 0xc040, hsrc | 0x20000000); in prog_host()
428 nvkm_wr32(device, 0xc040, hsrc & ~0x30000000); in prog_host()
436 nvkm_wr32(device, 0xc044, 0x3e); in prog_host()
447 nvkm_wr32(device, 0x10002c, info->fb_delay); in prog_core()
452 nvkm_wr32(device, 0x10002c, info->fb_delay); in prog_core()
Dgk20a.c297 nvkm_wr32(device, GPCPLL_COEFF, val); in gk20a_pllg_slide()
303 nvkm_wr32(device, GPCPLL_NDIV_SLOWDOWN, val); in gk20a_pllg_slide()
380 nvkm_wr32(device, SEL_VCO, val); in _gk20a_pllg_program_mnp()
386 nvkm_wr32(device, GPCPLL_CFG, val); in _gk20a_pllg_program_mnp()
401 nvkm_wr32(device, GPCPLL_COEFF, val); in _gk20a_pllg_program_mnp()
408 nvkm_wr32(device, GPCPLL_CFG, val); in _gk20a_pllg_program_mnp()
424 nvkm_wr32(device, GPC2CLK_OUT, val); in _gk20a_pllg_program_mnp()
Dgf100.c342 nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc); in gf100_clk_prog_0()
367 nvkm_wr32(device, addr + 0x04, info->coef); in gf100_clk_prog_2()
Dgk104.c363 nvkm_wr32(device, 0x137160 + (idx * 0x04), info->dsrc); in gk104_clk_prog_0()
394 nvkm_wr32(device, addr + 0x04, info->coef); in gk104_clk_prog_2()
Dnv40.c191 nvkm_wr32(device, 0x004004, clk->npll_coef); in nv40_clk_prog()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bar/
Dnv50.c51 nvkm_wr32(device, 0x00330c, 0x00000001); in nv50_bar_flush()
156 nvkm_wr32(device, 0x100c80, 0x00060001); in nv50_bar_init()
163 nvkm_wr32(device, 0x001704, 0x00000000 | bar->mem->addr >> 12); in nv50_bar_init()
164 nvkm_wr32(device, 0x001704, 0x40000000 | bar->mem->addr >> 12); in nv50_bar_init()
165 nvkm_wr32(device, 0x001708, 0x80000000 | bar->bar1->node->offset >> 4); in nv50_bar_init()
166 nvkm_wr32(device, 0x00170c, 0x80000000 | bar->bar3->node->offset >> 4); in nv50_bar_init()
168 nvkm_wr32(device, 0x001900 + (i * 4), 0x00000000); in nv50_bar_init()
Dgf100.c128 nvkm_wr32(device, 0x001704, 0x80000000 | addr); in gf100_bar_init()
132 nvkm_wr32(device, 0x001714, 0xc0000000 | addr); in gf100_bar_init()
Dg84.c34 nvkm_wr32(device, 0x070000, 0x00000001); in g84_bar_flush()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
Dauxg94.c103 nvkm_wr32(device, 0x00e4c0 + base + i, xbuf[i / 4]); in g94_i2c_aux_xfer()
111 nvkm_wr32(device, 0x00e4e0 + base, addr); in g94_i2c_aux_xfer()
116 nvkm_wr32(device, 0x00e4e4 + base, 0x80000000 | ctrl); in g94_i2c_aux_xfer()
117 nvkm_wr32(device, 0x00e4e4 + base, 0x00000000 | ctrl); in g94_i2c_aux_xfer()
122 nvkm_wr32(device, 0x00e4e4 + base, 0x00010000 | ctrl); in g94_i2c_aux_xfer()
Dauxgm204.c103 nvkm_wr32(device, 0x00d930 + base + i, xbuf[i / 4]); in gm204_i2c_aux_xfer()
111 nvkm_wr32(device, 0x00d950 + base, addr); in gm204_i2c_aux_xfer()
116 nvkm_wr32(device, 0x00d954 + base, 0x80000000 | ctrl); in gm204_i2c_aux_xfer()
117 nvkm_wr32(device, 0x00d954 + base, 0x00000000 | ctrl); in gm204_i2c_aux_xfer()
122 nvkm_wr32(device, 0x00d954 + base, 0x00010000 | ctrl); in gm204_i2c_aux_xfer()
Dbusnv50.c42 nvkm_wr32(device, bus->addr, bus->data); in nv50_i2c_bus_drive_scl()
52 nvkm_wr32(device, bus->addr, bus->data); in nv50_i2c_bus_drive_sda()
76 nvkm_wr32(device, bus->addr, (bus->data = 0x00000007)); in nv50_i2c_bus_init()
Dgk104.c39 nvkm_wr32(device, 0x00dc60, intr); in gk104_aux_stat()
56 nvkm_wr32(device, 0x00dc68, temp); in gk104_aux_mask()
Dg94.c39 nvkm_wr32(device, 0x00e06c, intr); in g94_aux_stat()
56 nvkm_wr32(device, 0x00e068, temp); in g94_aux_mask()
Dbusgf119.c69 nvkm_wr32(device, bus->addr, 0x00000007); in gf119_i2c_bus_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/msvld/
Dg98.c32 nvkm_wr32(device, 0x084010, 0x0000ffd2); in g98_msvld_init()
33 nvkm_wr32(device, 0x08401c, 0x0000fff2); in g98_msvld_init()
Dgf100.c32 nvkm_wr32(device, 0x084010, 0x0000fff2); in gf100_msvld_init()
33 nvkm_wr32(device, 0x08401c, 0x0000fff2); in gf100_msvld_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/mspdec/
Dg98.c32 nvkm_wr32(device, 0x085010, 0x0000ffd2); in g98_mspdec_init()
33 nvkm_wr32(device, 0x08501c, 0x0000fff2); in g98_mspdec_init()
Dgf100.c32 nvkm_wr32(device, 0x085010, 0x0000fff2); in gf100_mspdec_init()
33 nvkm_wr32(device, 0x08501c, 0x0000fff2); in gf100_mspdec_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/msppp/
Dgf100.c32 nvkm_wr32(device, 0x086010, 0x0000fff2); in gf100_msppp_init()
33 nvkm_wr32(device, 0x08601c, 0x0000fff2); in gf100_msppp_init()
Dg98.c32 nvkm_wr32(device, 0x086010, 0x0000ffd2); in g98_msppp_init()
33 nvkm_wr32(device, 0x08601c, 0x0000fff2); in g98_msppp_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fuse/
Dgf100.c38 nvkm_wr32(device, 0x021000, unk); in gf100_fuse_read()
39 nvkm_wr32(device, 0x022400, fuse_enable); in gf100_fuse_read()
Dnv50.c37 nvkm_wr32(device, 0x001084, fuse_enable); in nv50_fuse_read()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowramin.c49 nvkm_wr32(device, 0x001700, priv->bar0); in pramin_fini()
106 nvkm_wr32(device, 0x001700, addr >> 16); in pramin_init()
Dinit.c195 nvkm_wr32(device, reg, val); in init_wr32()
205 nvkm_wr32(device, reg, (tmp & ~mask) | val); in init_mask()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/volt/
Dgk104.c61 nvkm_wr32(device, 0x20340, div); in gk104_volt_set()
62 nvkm_wr32(device, 0x20344, 0x80000000 | duty); in gk104_volt_set()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
Dnv50.c135 nvkm_wr32(device, 0x001700, base >> 16); in nv50_instobj_rd32()
152 nvkm_wr32(device, 0x001700, base >> 16); in nv50_instobj_wr32()
155 nvkm_wr32(device, 0x700000 + addr, data); in nv50_instobj_wr32()
Dnv04.c90 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
150 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/ce/
Dgk104.c37 nvkm_wr32(device, 0x104908 + base, stat); in gk104_ce_intr()
Dgf100.c34 nvkm_wr32(device, ce->addr + 0x084, index); in gf100_ce_init()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/pci/
Dnv04.c44 nvkm_wr32(device, 0x001800 + addr, data); in nv04_pci_wr32()
Dnv40.c44 nvkm_wr32(device, 0x088000 + addr, data); in nv40_pci_wr32()
/linux-4.4.14/drivers/gpu/drm/nouveau/include/nvkm/core/
Ddevice.h218 #define nvkm_wr32(d,a,v) iowrite32_native((v), (d)->pri + (a)) macro
222 nvkm_wr32(_device, _addr, (_temp & ~(m)) | (v)); \
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/device/
Duser.c198 nvkm_wr32(udev->device, addr, data); in nvkm_udevice_wr32()