1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv04.h"
25#include "channv04.h"
26#include "regsnv04.h"
27
28#include <core/ramht.h>
29#include <subdev/fb.h>
30#include <subdev/instmem.h>
31
32static const struct nv04_fifo_ramfc
33nv40_fifo_ramfc[] = {
34	{ 32,  0, 0x00,  0, NV04_PFIFO_CACHE1_DMA_PUT },
35	{ 32,  0, 0x04,  0, NV04_PFIFO_CACHE1_DMA_GET },
36	{ 32,  0, 0x08,  0, NV10_PFIFO_CACHE1_REF_CNT },
37	{ 32,  0, 0x0c,  0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
38	{ 32,  0, 0x10,  0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
39	{ 32,  0, 0x14,  0, NV04_PFIFO_CACHE1_DMA_STATE },
40	{ 28,  0, 0x18,  0, NV04_PFIFO_CACHE1_DMA_FETCH },
41	{  2, 28, 0x18, 28, 0x002058 },
42	{ 32,  0, 0x1c,  0, NV04_PFIFO_CACHE1_ENGINE },
43	{ 32,  0, 0x20,  0, NV04_PFIFO_CACHE1_PULL1 },
44	{ 32,  0, 0x24,  0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE },
45	{ 32,  0, 0x28,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP },
46	{ 32,  0, 0x2c,  0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT },
47	{ 32,  0, 0x30,  0, NV10_PFIFO_CACHE1_SEMAPHORE },
48	{ 32,  0, 0x34,  0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE },
49	{ 32,  0, 0x38,  0, NV40_PFIFO_GRCTX_INSTANCE },
50	{ 17,  0, 0x3c,  0, NV04_PFIFO_DMA_TIMESLICE },
51	{ 32,  0, 0x40,  0, 0x0032e4 },
52	{ 32,  0, 0x44,  0, 0x0032e8 },
53	{ 32,  0, 0x4c,  0, 0x002088 },
54	{ 32,  0, 0x50,  0, 0x003300 },
55	{ 32,  0, 0x54,  0, 0x00330c },
56	{}
57};
58
59static void
60nv40_fifo_init(struct nvkm_fifo *base)
61{
62	struct nv04_fifo *fifo = nv04_fifo(base);
63	struct nvkm_device *device = fifo->base.engine.subdev.device;
64	struct nvkm_fb *fb = device->fb;
65	struct nvkm_instmem *imem = device->imem;
66	struct nvkm_ramht *ramht = imem->ramht;
67	struct nvkm_memory *ramro = imem->ramro;
68	struct nvkm_memory *ramfc = imem->ramfc;
69
70	nvkm_wr32(device, 0x002040, 0x000000ff);
71	nvkm_wr32(device, 0x002044, 0x2101ffff);
72	nvkm_wr32(device, 0x002058, 0x00000001);
73
74	nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
75					    ((ramht->bits - 9) << 16) |
76					    (ramht->gpuobj->addr >> 8));
77	nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8);
78
79	switch (device->chipset) {
80	case 0x47:
81	case 0x49:
82	case 0x4b:
83		nvkm_wr32(device, 0x002230, 0x00000001);
84	case 0x40:
85	case 0x41:
86	case 0x42:
87	case 0x43:
88	case 0x45:
89	case 0x48:
90		nvkm_wr32(device, 0x002220, 0x00030002);
91		break;
92	default:
93		nvkm_wr32(device, 0x002230, 0x00000000);
94		nvkm_wr32(device, 0x002220, ((fb->ram->size - 512 * 1024 +
95					      nvkm_memory_addr(ramfc)) >> 16) |
96					    0x00030000);
97		break;
98	}
99
100	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1);
101
102	nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff);
103	nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff);
104
105	nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1);
106	nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1);
107	nvkm_wr32(device, NV03_PFIFO_CACHES, 1);
108}
109
110static const struct nvkm_fifo_func
111nv40_fifo = {
112	.init = nv40_fifo_init,
113	.intr = nv04_fifo_intr,
114	.pause = nv04_fifo_pause,
115	.start = nv04_fifo_start,
116	.chan = {
117		&nv40_fifo_dma_oclass,
118		NULL
119	},
120};
121
122int
123nv40_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo)
124{
125	return nv04_fifo_new_(&nv40_fifo, device, index, 32,
126			      nv40_fifo_ramfc, pfifo);
127}
128