1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "dmacnv50.h"
25#include "rootnv50.h"
26
27#include <core/client.h>
28#include <subdev/timer.h>
29
30#include <nvif/class.h>
31#include <nvif/unpack.h>
32
33int
34nv50_disp_core_new(const struct nv50_disp_dmac_func *func,
35		   const struct nv50_disp_chan_mthd *mthd,
36		   struct nv50_disp_root *root, int chid,
37		   const struct nvkm_oclass *oclass, void *data, u32 size,
38		   struct nvkm_object **pobject)
39{
40	union {
41		struct nv50_disp_core_channel_dma_v0 v0;
42	} *args = data;
43	struct nvkm_object *parent = oclass->parent;
44	u64 push;
45	int ret;
46
47	nvif_ioctl(parent, "create disp core channel dma size %d\n", size);
48	if (nvif_unpack(args->v0, 0, 0, false)) {
49		nvif_ioctl(parent, "create disp core channel dma vers %d "
50				   "pushbuf %016llx\n",
51			   args->v0.version, args->v0.pushbuf);
52		push = args->v0.pushbuf;
53	} else
54		return ret;
55
56	return nv50_disp_dmac_new_(func, mthd, root, chid, 0,
57				   push, oclass, pobject);
58}
59
60const struct nv50_disp_mthd_list
61nv50_disp_core_mthd_base = {
62	.mthd = 0x0000,
63	.addr = 0x000000,
64	.data = {
65		{ 0x0080, 0x000000 },
66		{ 0x0084, 0x610bb8 },
67		{ 0x0088, 0x610b9c },
68		{ 0x008c, 0x000000 },
69		{}
70	}
71};
72
73static const struct nv50_disp_mthd_list
74nv50_disp_core_mthd_dac = {
75	.mthd = 0x0080,
76	.addr = 0x000008,
77	.data = {
78		{ 0x0400, 0x610b58 },
79		{ 0x0404, 0x610bdc },
80		{ 0x0420, 0x610828 },
81		{}
82	}
83};
84
85const struct nv50_disp_mthd_list
86nv50_disp_core_mthd_sor = {
87	.mthd = 0x0040,
88	.addr = 0x000008,
89	.data = {
90		{ 0x0600, 0x610b70 },
91		{}
92	}
93};
94
95const struct nv50_disp_mthd_list
96nv50_disp_core_mthd_pior = {
97	.mthd = 0x0040,
98	.addr = 0x000008,
99	.data = {
100		{ 0x0700, 0x610b80 },
101		{}
102	}
103};
104
105static const struct nv50_disp_mthd_list
106nv50_disp_core_mthd_head = {
107	.mthd = 0x0400,
108	.addr = 0x000540,
109	.data = {
110		{ 0x0800, 0x610ad8 },
111		{ 0x0804, 0x610ad0 },
112		{ 0x0808, 0x610a48 },
113		{ 0x080c, 0x610a78 },
114		{ 0x0810, 0x610ac0 },
115		{ 0x0814, 0x610af8 },
116		{ 0x0818, 0x610b00 },
117		{ 0x081c, 0x610ae8 },
118		{ 0x0820, 0x610af0 },
119		{ 0x0824, 0x610b08 },
120		{ 0x0828, 0x610b10 },
121		{ 0x082c, 0x610a68 },
122		{ 0x0830, 0x610a60 },
123		{ 0x0834, 0x000000 },
124		{ 0x0838, 0x610a40 },
125		{ 0x0840, 0x610a24 },
126		{ 0x0844, 0x610a2c },
127		{ 0x0848, 0x610aa8 },
128		{ 0x084c, 0x610ab0 },
129		{ 0x0860, 0x610a84 },
130		{ 0x0864, 0x610a90 },
131		{ 0x0868, 0x610b18 },
132		{ 0x086c, 0x610b20 },
133		{ 0x0870, 0x610ac8 },
134		{ 0x0874, 0x610a38 },
135		{ 0x0880, 0x610a58 },
136		{ 0x0884, 0x610a9c },
137		{ 0x08a0, 0x610a70 },
138		{ 0x08a4, 0x610a50 },
139		{ 0x08a8, 0x610ae0 },
140		{ 0x08c0, 0x610b28 },
141		{ 0x08c4, 0x610b30 },
142		{ 0x08c8, 0x610b40 },
143		{ 0x08d4, 0x610b38 },
144		{ 0x08d8, 0x610b48 },
145		{ 0x08dc, 0x610b50 },
146		{ 0x0900, 0x610a18 },
147		{ 0x0904, 0x610ab8 },
148		{}
149	}
150};
151
152static const struct nv50_disp_chan_mthd
153nv50_disp_core_chan_mthd = {
154	.name = "Core",
155	.addr = 0x000000,
156	.prev = 0x000004,
157	.data = {
158		{ "Global", 1, &nv50_disp_core_mthd_base },
159		{    "DAC", 3, &nv50_disp_core_mthd_dac  },
160		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
161		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
162		{   "HEAD", 2, &nv50_disp_core_mthd_head },
163		{}
164	}
165};
166
167static void
168nv50_disp_core_fini(struct nv50_disp_dmac *chan)
169{
170	struct nv50_disp *disp = chan->base.root->disp;
171	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
172	struct nvkm_device *device = subdev->device;
173
174	/* deactivate channel */
175	nvkm_mask(device, 0x610200, 0x00000010, 0x00000000);
176	nvkm_mask(device, 0x610200, 0x00000003, 0x00000000);
177	if (nvkm_msec(device, 2000,
178		if (!(nvkm_rd32(device, 0x610200) & 0x001e0000))
179			break;
180	) < 0) {
181		nvkm_error(subdev, "core fini: %08x\n",
182			   nvkm_rd32(device, 0x610200));
183	}
184
185	/* disable error reporting and completion notifications */
186	nvkm_mask(device, 0x610028, 0x00010001, 0x00000000);
187}
188
189static int
190nv50_disp_core_init(struct nv50_disp_dmac *chan)
191{
192	struct nv50_disp *disp = chan->base.root->disp;
193	struct nvkm_subdev *subdev = &disp->base.engine.subdev;
194	struct nvkm_device *device = subdev->device;
195
196	/* enable error reporting */
197	nvkm_mask(device, 0x610028, 0x00010000, 0x00010000);
198
199	/* attempt to unstick channel from some unknown state */
200	if ((nvkm_rd32(device, 0x610200) & 0x009f0000) == 0x00020000)
201		nvkm_mask(device, 0x610200, 0x00800000, 0x00800000);
202	if ((nvkm_rd32(device, 0x610200) & 0x003f0000) == 0x00030000)
203		nvkm_mask(device, 0x610200, 0x00600000, 0x00600000);
204
205	/* initialise channel for dma command submission */
206	nvkm_wr32(device, 0x610204, chan->push);
207	nvkm_wr32(device, 0x610208, 0x00010000);
208	nvkm_wr32(device, 0x61020c, 0x00000000);
209	nvkm_mask(device, 0x610200, 0x00000010, 0x00000010);
210	nvkm_wr32(device, 0x640000, 0x00000000);
211	nvkm_wr32(device, 0x610200, 0x01000013);
212
213	/* wait for it to go inactive */
214	if (nvkm_msec(device, 2000,
215		if (!(nvkm_rd32(device, 0x610200) & 0x80000000))
216			break;
217	) < 0) {
218		nvkm_error(subdev, "core init: %08x\n",
219			   nvkm_rd32(device, 0x610200));
220		return -EBUSY;
221	}
222
223	return 0;
224}
225
226const struct nv50_disp_dmac_func
227nv50_disp_core_func = {
228	.init = nv50_disp_core_init,
229	.fini = nv50_disp_core_fini,
230	.bind = nv50_disp_dmac_bind,
231};
232
233const struct nv50_disp_dmac_oclass
234nv50_disp_core_oclass = {
235	.base.oclass = NV50_DISP_CORE_CHANNEL_DMA,
236	.base.minver = 0,
237	.base.maxver = 0,
238	.ctor = nv50_disp_core_new,
239	.func = &nv50_disp_core_func,
240	.mthd = &nv50_disp_core_chan_mthd,
241	.chid = 0,
242};
243