Searched refs:IO_STATE (Results 1 - 19 of 19) sorted by relevance

/linux-4.1.27/arch/cris/arch-v10/kernel/
H A Ddebugport.c51 IO_STATE(R_IRQ_MASK1_SET, ser0_data, set),
65 IO_STATE(R_IRQ_MASK1_SET, ser1_data, set),
79 IO_STATE(R_IRQ_MASK1_SET, ser2_data, set),
93 IO_STATE(R_IRQ_MASK1_SET, ser3_data, set),
147 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); start_port()
152 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); start_port()
157 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); start_port()
159 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); start_port()
160 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser2, select); start_port()
165 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); start_port()
167 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); start_port()
168 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, ser3, select); start_port()
174 IO_STATE(R_SERIAL0_XOFF, tx_stop, enable) | start_port()
175 IO_STATE(R_SERIAL0_XOFF, auto_xoff, disable) | start_port()
183 IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | start_port()
184 IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); start_port()
188 IO_STATE(R_SERIAL0_BAUD, tr_baud, c1200Hz) | start_port()
189 IO_STATE(R_SERIAL0_BAUD, rec_baud, c1200Hz); start_port()
193 IO_STATE(R_SERIAL0_BAUD, tr_baud, c2400Hz) | start_port()
194 IO_STATE(R_SERIAL0_BAUD, rec_baud, c2400Hz); start_port()
198 IO_STATE(R_SERIAL0_BAUD, tr_baud, c4800Hz) | start_port()
199 IO_STATE(R_SERIAL0_BAUD, rec_baud, c4800Hz); start_port()
203 IO_STATE(R_SERIAL0_BAUD, tr_baud, c9600Hz) | start_port()
204 IO_STATE(R_SERIAL0_BAUD, rec_baud, c9600Hz); start_port()
208 IO_STATE(R_SERIAL0_BAUD, tr_baud, c19k2Hz) | start_port()
209 IO_STATE(R_SERIAL0_BAUD, rec_baud, c19k2Hz); start_port()
213 IO_STATE(R_SERIAL0_BAUD, tr_baud, c38k4Hz) | start_port()
214 IO_STATE(R_SERIAL0_BAUD, rec_baud, c38k4Hz); start_port()
218 IO_STATE(R_SERIAL0_BAUD, tr_baud, c57k6Hz) | start_port()
219 IO_STATE(R_SERIAL0_BAUD, rec_baud, c57k6Hz); start_port()
223 IO_STATE(R_SERIAL0_BAUD, tr_baud, c115k2Hz) | start_port()
224 IO_STATE(R_SERIAL0_BAUD, rec_baud, c115k2Hz); start_port()
230 IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | start_port()
231 IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); start_port()
233 IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | start_port()
234 IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); start_port()
237 IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd) | start_port()
238 IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); start_port()
240 IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd) | start_port()
241 IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); start_port()
244 IO_STATE(R_SERIAL0_REC_CTRL, rec_par, even) | start_port()
245 IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, disable); start_port()
247 IO_STATE(R_SERIAL0_TR_CTRL, tr_par, even) | start_port()
248 IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, disable); start_port()
252 rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); start_port()
253 tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); start_port()
257 rec_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit); start_port()
258 tr_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit); start_port()
262 IO_STATE(R_SERIAL0_REC_CTRL, dma_err, stop) | start_port()
263 IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable) | start_port()
264 IO_STATE(R_SERIAL0_REC_CTRL, rts_, active) | start_port()
265 IO_STATE(R_SERIAL0_REC_CTRL, sampling, middle) | start_port()
266 IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, normal) | start_port()
271 IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable) | start_port()
272 IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, disabled) | start_port()
273 IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, one_bit) | start_port()
274 IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, normal) | start_port()
373 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); enableDebugIRQ()
375 *kgdb_port->rec_ctrl = IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); enableDebugIRQ()
H A Dhead.S17 #define START_ETHERNET_CLOCK IO_STATE(R_NETWORK_GEN_CONFIG, enable, on) |\
18 IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk)
71 move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \
72 | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \
73 | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \
74 | IO_STATE (R_MMU_CONFIG, we_excp, enable) \
75 | IO_STATE (R_MMU_CONFIG, seg_f, page) \
76 | IO_STATE (R_MMU_CONFIG, seg_e, seg) \
77 | IO_STATE (R_MMU_CONFIG, seg_d, page) \
78 | IO_STATE (R_MMU_CONFIG, seg_c, seg) \
79 | IO_STATE (R_MMU_CONFIG, seg_b, seg) \
80 | IO_STATE (R_MMU_CONFIG, seg_a, seg) \
81 | IO_STATE (R_MMU_CONFIG, seg_9, page) \
82 | IO_STATE (R_MMU_CONFIG, seg_8, page) \
83 | IO_STATE (R_MMU_CONFIG, seg_7, page) \
84 | IO_STATE (R_MMU_CONFIG, seg_6, seg) \
85 | IO_STATE (R_MMU_CONFIG, seg_5, seg) \
86 | IO_STATE (R_MMU_CONFIG, seg_4, seg) \
87 | IO_STATE (R_MMU_CONFIG, seg_3, page) \
88 | IO_STATE (R_MMU_CONFIG, seg_2, page) \
89 | IO_STATE (R_MMU_CONFIG, seg_1, page) \
90 | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0
104 move.d IO_STATE (R_MMU_CONFIG, mmu_enable, enable) \
105 | IO_STATE (R_MMU_CONFIG, inv_excp, enable) \
106 | IO_STATE (R_MMU_CONFIG, acc_excp, enable) \
107 | IO_STATE (R_MMU_CONFIG, we_excp, enable) \
108 | IO_STATE (R_MMU_CONFIG, seg_f, seg) \
109 | IO_STATE (R_MMU_CONFIG, seg_e, seg) \
110 | IO_STATE (R_MMU_CONFIG, seg_d, page) \
111 | IO_STATE (R_MMU_CONFIG, seg_c, seg) \
112 | IO_STATE (R_MMU_CONFIG, seg_b, seg) \
113 | IO_STATE (R_MMU_CONFIG, seg_a, page) \
114 | IO_STATE (R_MMU_CONFIG, seg_9, page) \
115 | IO_STATE (R_MMU_CONFIG, seg_8, page) \
116 | IO_STATE (R_MMU_CONFIG, seg_7, page) \
117 | IO_STATE (R_MMU_CONFIG, seg_6, page) \
118 | IO_STATE (R_MMU_CONFIG, seg_5, page) \
119 | IO_STATE (R_MMU_CONFIG, seg_4, seg) \
120 | IO_STATE (R_MMU_CONFIG, seg_3, page) \
121 | IO_STATE (R_MMU_CONFIG, seg_2, page) \
122 | IO_STATE (R_MMU_CONFIG, seg_1, page) \
123 | IO_STATE (R_MMU_CONFIG, seg_0, seg), $r0
383 move.d IO_STATE (R_EXT_DMA_0_CMD, cnt, enable) \
384 | IO_STATE (R_EXT_DMA_0_CMD, rqpol, ahigh) \
385 | IO_STATE (R_EXT_DMA_0_CMD, apol, ahigh) \
386 | IO_STATE (R_EXT_DMA_0_CMD, rq_ack, burst) \
387 | IO_STATE (R_EXT_DMA_0_CMD, wid, word) \
388 | IO_STATE (R_EXT_DMA_0_CMD, dir, output) \
389 | IO_STATE (R_EXT_DMA_0_CMD, run, stop) \
395 moveq IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
399 cmp.b IO_STATE (R_DMA_CH4_CMD, cmd, reset),$r0
405 moveq IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
409 cmp.b IO_STATE (R_DMA_CH5_CMD, cmd, reset),$r0
420 or.d IO_STATE (R_GEN_CONFIG, ser2, select),$r0
422 or.d IO_STATE (R_GEN_CONFIG, ser2, disable),$r0
426 or.d IO_STATE (R_GEN_CONFIG, scsi0, disable) \
427 | IO_STATE (R_GEN_CONFIG, ata, disable) \
428 | IO_STATE (R_GEN_CONFIG, par0, disable) \
429 | IO_STATE (R_GEN_CONFIG, mio, disable) \
430 | IO_STATE (R_GEN_CONFIG, scsi1, disable) \
431 | IO_STATE (R_GEN_CONFIG, scsi0w, disable) \
432 | IO_STATE (R_GEN_CONFIG, par1, disable) \
433 | IO_STATE (R_GEN_CONFIG, ser3, disable) \
434 | IO_STATE (R_GEN_CONFIG, mio_w, disable) \
435 | IO_STATE (R_GEN_CONFIG, usb1, disable) \
436 | IO_STATE (R_GEN_CONFIG, usb2, disable) \
437 | IO_STATE (R_GEN_CONFIG, par_w, disable),$r0
440 or.d IO_STATE (R_GEN_CONFIG, dma2, ata) \
441 | IO_STATE (R_GEN_CONFIG, dma3, ata) \
442 | IO_STATE (R_GEN_CONFIG, dma4, scsi1) \
443 | IO_STATE (R_GEN_CONFIG, dma5, scsi1) \
444 | IO_STATE (R_GEN_CONFIG, dma6, unused) \
445 | IO_STATE (R_GEN_CONFIG, dma7, unused) \
446 | IO_STATE (R_GEN_CONFIG, dma8, usb) \
447 | IO_STATE (R_GEN_CONFIG, dma9, usb),$r0
451 or.d IO_STATE (R_GEN_CONFIG, g0dir, out),$r0
455 or.d IO_STATE (R_GEN_CONFIG, g8_15dir, out),$r0
458 or.d IO_STATE (R_GEN_CONFIG, g16_23dir, out),$r0
462 or.d IO_STATE (R_GEN_CONFIG, g24dir, out),$r0
485 moveq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
490 cmpq IO_STATE (R_DMA_CH8_CMD, cmd, reset),$r0
495 cmpq IO_STATE (R_DMA_CH9_CMD, cmd, reset),$r0
504 or.b IO_STATE (R_PORT_PA_DIR, dir7, output),$r0
524 or.b IO_STATE (R_PORT_PB_DIR, dir5, output),$r0
563 moveq IO_STATE (R_SERIAL0_XOFF, tx_stop, enable) \
564 | IO_STATE (R_SERIAL0_XOFF, auto_xoff, disable) \
569 move.b IO_STATE (R_SERIAL0_BAUD, tr_baud, c115k2Hz) \
570 | IO_STATE (R_SERIAL0_BAUD, rec_baud, c115k2Hz),$r0
574 move.b IO_STATE (R_SERIAL0_REC_CTRL, dma_err, stop) \
575 | IO_STATE (R_SERIAL0_REC_CTRL, rec_enable, enable) \
576 | IO_STATE (R_SERIAL0_REC_CTRL, rts_, active) \
577 | IO_STATE (R_SERIAL0_REC_CTRL, sampling, middle) \
578 | IO_STATE (R_SERIAL0_REC_CTRL, rec_stick_par, normal) \
579 | IO_STATE (R_SERIAL0_REC_CTRL, rec_par, even) \
580 | IO_STATE (R_SERIAL0_REC_CTRL, rec_par_en, disable) \
581 | IO_STATE (R_SERIAL0_REC_CTRL, rec_bitnr, rec_8bit),$r0
586 | IO_STATE (R_SERIAL0_TR_CTRL, tr_enable, enable) \
587 | IO_STATE (R_SERIAL0_TR_CTRL, auto_cts, disabled) \
588 | IO_STATE (R_SERIAL0_TR_CTRL, stop_bits, one_bit) \
589 | IO_STATE (R_SERIAL0_TR_CTRL, tr_stick_par, normal) \
590 | IO_STATE (R_SERIAL0_TR_CTRL, tr_par, even) \
591 | IO_STATE (R_SERIAL0_TR_CTRL, tr_par_en, disable) \
592 | IO_STATE (R_SERIAL0_TR_CTRL, tr_bitnr, tr_8bit),$r0
597 moveq IO_STATE (R_SERIAL1_XOFF, tx_stop, enable) \
598 | IO_STATE (R_SERIAL1_XOFF, auto_xoff, disable) \
603 move.b IO_STATE (R_SERIAL1_BAUD, tr_baud, c115k2Hz) \
604 | IO_STATE (R_SERIAL1_BAUD, rec_baud, c115k2Hz),$r0
608 move.b IO_STATE (R_SERIAL1_REC_CTRL, dma_err, stop) \
609 | IO_STATE (R_SERIAL1_REC_CTRL, rec_enable, enable) \
610 | IO_STATE (R_SERIAL1_REC_CTRL, rts_, active) \
611 | IO_STATE (R_SERIAL1_REC_CTRL, sampling, middle) \
612 | IO_STATE (R_SERIAL1_REC_CTRL, rec_stick_par, normal) \
613 | IO_STATE (R_SERIAL1_REC_CTRL, rec_par, even) \
614 | IO_STATE (R_SERIAL1_REC_CTRL, rec_par_en, disable) \
615 | IO_STATE (R_SERIAL1_REC_CTRL, rec_bitnr, rec_8bit),$r0
620 | IO_STATE (R_SERIAL1_TR_CTRL, tr_enable, enable) \
621 | IO_STATE (R_SERIAL1_TR_CTRL, auto_cts, disabled) \
622 | IO_STATE (R_SERIAL1_TR_CTRL, stop_bits, one_bit) \
623 | IO_STATE (R_SERIAL1_TR_CTRL, tr_stick_par, normal) \
624 | IO_STATE (R_SERIAL1_TR_CTRL, tr_par, even) \
625 | IO_STATE (R_SERIAL1_TR_CTRL, tr_par_en, disable) \
626 | IO_STATE (R_SERIAL1_TR_CTRL, tr_bitnr, tr_8bit),$r0
632 moveq IO_STATE (R_SERIAL2_XOFF, tx_stop, enable) \
633 | IO_STATE (R_SERIAL2_XOFF, auto_xoff, disable) \
638 move.b IO_STATE (R_SERIAL2_BAUD, tr_baud, c115k2Hz) \
639 | IO_STATE (R_SERIAL2_BAUD, rec_baud, c115k2Hz),$r0
643 move.b IO_STATE (R_SERIAL2_REC_CTRL, dma_err, stop) \
644 | IO_STATE (R_SERIAL2_REC_CTRL, rec_enable, enable) \
645 | IO_STATE (R_SERIAL2_REC_CTRL, rts_, active) \
646 | IO_STATE (R_SERIAL2_REC_CTRL, sampling, middle) \
647 | IO_STATE (R_SERIAL2_REC_CTRL, rec_stick_par, normal) \
648 | IO_STATE (R_SERIAL2_REC_CTRL, rec_par, even) \
649 | IO_STATE (R_SERIAL2_REC_CTRL, rec_par_en, disable) \
650 | IO_STATE (R_SERIAL2_REC_CTRL, rec_bitnr, rec_8bit),$r0
655 | IO_STATE (R_SERIAL2_TR_CTRL, tr_enable, enable) \
656 | IO_STATE (R_SERIAL2_TR_CTRL, auto_cts, disabled) \
657 | IO_STATE (R_SERIAL2_TR_CTRL, stop_bits, one_bit) \
658 | IO_STATE (R_SERIAL2_TR_CTRL, tr_stick_par, normal) \
659 | IO_STATE (R_SERIAL2_TR_CTRL, tr_par, even) \
660 | IO_STATE (R_SERIAL2_TR_CTRL, tr_par_en, disable) \
661 | IO_STATE (R_SERIAL2_TR_CTRL, tr_bitnr, tr_8bit),$r0
668 moveq IO_STATE (R_SERIAL3_XOFF, tx_stop, enable) \
669 | IO_STATE (R_SERIAL3_XOFF, auto_xoff, disable) \
674 move.b IO_STATE (R_SERIAL3_BAUD, tr_baud, c115k2Hz) \
675 | IO_STATE (R_SERIAL3_BAUD, rec_baud, c115k2Hz),$r0
679 move.b IO_STATE (R_SERIAL3_REC_CTRL, dma_err, stop) \
680 | IO_STATE (R_SERIAL3_REC_CTRL, rec_enable, enable) \
681 | IO_STATE (R_SERIAL3_REC_CTRL, rts_, active) \
682 | IO_STATE (R_SERIAL3_REC_CTRL, sampling, middle) \
683 | IO_STATE (R_SERIAL3_REC_CTRL, rec_stick_par, normal) \
684 | IO_STATE (R_SERIAL3_REC_CTRL, rec_par, even) \
685 | IO_STATE (R_SERIAL3_REC_CTRL, rec_par_en, disable) \
686 | IO_STATE (R_SERIAL3_REC_CTRL, rec_bitnr, rec_8bit),$r0
691 | IO_STATE (R_SERIAL3_TR_CTRL, tr_enable, enable) \
692 | IO_STATE (R_SERIAL3_TR_CTRL, auto_cts, disabled) \
693 | IO_STATE (R_SERIAL3_TR_CTRL, stop_bits, one_bit) \
694 | IO_STATE (R_SERIAL3_TR_CTRL, tr_stick_par, normal) \
695 | IO_STATE (R_SERIAL3_TR_CTRL, tr_par, even) \
696 | IO_STATE (R_SERIAL3_TR_CTRL, tr_par_en, disable) \
697 | IO_STATE (R_SERIAL3_TR_CTRL, tr_bitnr, tr_8bit),$r0
H A Dtime.c117 IO_STATE(R_WATCHDOG, enable, start); reset_watchdog()
129 IO_STATE(R_WATCHDOG, enable, stop); stop_watchdog()
149 IO_STATE( R_TIMER_CTRL, i1, clr) | timer_interrupt()
150 IO_STATE( R_TIMER_CTRL, tm1, run) | timer_interrupt()
151 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | timer_interrupt()
152 IO_STATE( R_TIMER_CTRL, i0, clr) | timer_interrupt()
153 IO_STATE( R_TIMER_CTRL, tm0, run) | timer_interrupt()
154 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); timer_interrupt()
156 *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr); timer_interrupt()
204 IO_STATE( R_TIMER_CTRL, i1, nop) | time_init()
205 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) | time_init()
206 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | time_init()
207 IO_STATE( R_TIMER_CTRL, i0, nop) | time_init()
208 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) | time_init()
209 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); time_init()
214 IO_STATE( R_TIMER_CTRL, i1, nop) | time_init()
215 IO_STATE( R_TIMER_CTRL, tm1, run) | time_init()
216 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | time_init()
217 IO_STATE( R_TIMER_CTRL, i0, nop) | time_init()
218 IO_STATE( R_TIMER_CTRL, tm0, run) | time_init()
219 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); time_init()
224 IO_STATE(R_TIMER_CTRL, i1, nop) | time_init()
225 IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | time_init()
226 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | time_init()
227 IO_STATE(R_TIMER_CTRL, i0, nop) | time_init()
228 IO_STATE(R_TIMER_CTRL, tm0, stop_ld) | time_init()
229 IO_STATE(R_TIMER_CTRL, clksel0, flexible); time_init()
234 IO_STATE(R_TIMER_CTRL, i1, nop) | time_init()
235 IO_STATE(R_TIMER_CTRL, tm1, run) | time_init()
236 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | time_init()
237 IO_STATE(R_TIMER_CTRL, i0, nop) | time_init()
238 IO_STATE(R_TIMER_CTRL, tm0, run) | time_init()
239 IO_STATE(R_TIMER_CTRL, clksel0, flexible); time_init()
245 *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set); time_init()
264 *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set); time_init()
265 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set); time_init()
H A Ddma.c231 *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset); cris_free_dma()
236 *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset); cris_free_dma()
241 *R_DMA_CH2_CMD = IO_STATE(R_DMA_CH2_CMD, cmd, reset); cris_free_dma()
246 *R_DMA_CH3_CMD = IO_STATE(R_DMA_CH3_CMD, cmd, reset); cris_free_dma()
251 *R_DMA_CH4_CMD = IO_STATE(R_DMA_CH4_CMD, cmd, reset); cris_free_dma()
256 *R_DMA_CH5_CMD = IO_STATE(R_DMA_CH5_CMD, cmd, reset); cris_free_dma()
261 *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, reset); cris_free_dma()
266 *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, reset); cris_free_dma()
271 *R_DMA_CH8_CMD = IO_STATE(R_DMA_CH8_CMD, cmd, reset); cris_free_dma()
276 *R_DMA_CH9_CMD = IO_STATE(R_DMA_CH9_CMD, cmd, reset); cris_free_dma()
H A Dfasttimer.c181 *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); start_timer1()
190 IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | start_timer1()
195 IO_STATE(R_TIMER_CTRL, i1, clr); start_timer1()
200 IO_STATE(R_TIMER_CTRL, tm1, run); start_timer1()
203 *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer1, set); start_timer1()
349 *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_CLR, timer1, clr); timer1_handler()
355 IO_STATE(R_TIMER_CTRL, tm1, stop_ld); timer1_handler()
358 *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i1, clr); timer1_handler()
H A Dtraps.c110 while (*R_IRQ_MASK0_RD & IO_STATE(R_IRQ_MASK0_RD, nmi_pin, active)) handle_nmi()
H A Dirq.c153 (IO_STATE(R_VECT_MASK_RD, dma0, active) | do_multiple_IRQ()
154 IO_STATE(R_VECT_MASK_RD, dma1, active))) { do_multiple_IRQ()
H A Dprocess.c72 IO_STATE(R_WATCHDOG, enable, start); hard_reset_now()
H A Dentry.S499 | IO_STATE (R_WATCHDOG, enable, start), $r10
/linux-4.1.27/arch/cris/arch-v10/mm/
H A Dinit.c69 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* bootrom */ paging_init()
70 IO_STATE(R_MMU_KSEG, seg_e, page ) | paging_init()
71 IO_STATE(R_MMU_KSEG, seg_d, page ) | paging_init()
72 IO_STATE(R_MMU_KSEG, seg_c, page ) | paging_init()
73 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ paging_init()
75 IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* ARTPEC etc. */ paging_init()
77 IO_STATE(R_MMU_KSEG, seg_a, page ) | paging_init()
79 IO_STATE(R_MMU_KSEG, seg_9, seg ) | /* LED's on some boards */ paging_init()
80 IO_STATE(R_MMU_KSEG, seg_8, seg ) | /* CSE0/1, flash and I/O */ paging_init()
81 IO_STATE(R_MMU_KSEG, seg_7, page ) | /* kernel vmalloc area */ paging_init()
82 IO_STATE(R_MMU_KSEG, seg_6, seg ) | /* kernel DRAM area */ paging_init()
83 IO_STATE(R_MMU_KSEG, seg_5, seg ) | /* cached flash */ paging_init()
84 IO_STATE(R_MMU_KSEG, seg_4, page ) | /* user area */ paging_init()
85 IO_STATE(R_MMU_KSEG, seg_3, page ) | /* user area */ paging_init()
86 IO_STATE(R_MMU_KSEG, seg_2, page ) | /* user area */ paging_init()
87 IO_STATE(R_MMU_KSEG, seg_1, page ) | /* user area */ paging_init()
88 IO_STATE(R_MMU_KSEG, seg_0, page ) ); /* user area */ paging_init()
116 *R_MMU_KSEG = ( IO_STATE(R_MMU_KSEG, seg_f, seg ) | /* cached flash */ paging_init()
117 IO_STATE(R_MMU_KSEG, seg_e, seg ) | /* uncached flash */ paging_init()
118 IO_STATE(R_MMU_KSEG, seg_d, page ) | /* vmalloc area */ paging_init()
119 IO_STATE(R_MMU_KSEG, seg_c, seg ) | /* kernel area */ paging_init()
120 IO_STATE(R_MMU_KSEG, seg_b, seg ) | /* kernel reg area */ paging_init()
121 IO_STATE(R_MMU_KSEG, seg_a, seg ) | /* bootrom */ paging_init()
122 IO_STATE(R_MMU_KSEG, seg_9, page ) | /* user area */ paging_init()
123 IO_STATE(R_MMU_KSEG, seg_8, page ) | paging_init()
124 IO_STATE(R_MMU_KSEG, seg_7, page ) | paging_init()
125 IO_STATE(R_MMU_KSEG, seg_6, page ) | paging_init()
126 IO_STATE(R_MMU_KSEG, seg_5, page ) | paging_init()
127 IO_STATE(R_MMU_KSEG, seg_4, page ) | paging_init()
128 IO_STATE(R_MMU_KSEG, seg_3, page ) | paging_init()
129 IO_STATE(R_MMU_KSEG, seg_2, page ) | paging_init()
130 IO_STATE(R_MMU_KSEG, seg_1, page ) | paging_init()
131 IO_STATE(R_MMU_KSEG, seg_0, page ) ); paging_init()
158 *R_MMU_CTRL = ( IO_STATE(R_MMU_CTRL, inv_excp, enable ) | paging_init()
159 IO_STATE(R_MMU_CTRL, acc_excp, enable ) | paging_init()
160 IO_STATE(R_MMU_CTRL, we_excp, enable ) ); paging_init()
162 *R_MMU_ENABLE = IO_STATE(R_MMU_ENABLE, mmu_enable, enable); paging_init()
H A Dtlb.c51 *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | flush_tlb_all()
52 IO_STATE(R_TLB_LO, valid, no ) | flush_tlb_all()
53 IO_STATE(R_TLB_LO, kernel,no ) | flush_tlb_all()
54 IO_STATE(R_TLB_LO, we, no ) | flush_tlb_all()
87 *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | flush_tlb_mm()
88 IO_STATE(R_TLB_LO, valid, no ) | flush_tlb_mm()
89 IO_STATE(R_TLB_LO, kernel,no ) | flush_tlb_mm()
90 IO_STATE(R_TLB_LO, we, no ) | flush_tlb_mm()
127 *R_TLB_LO = ( IO_STATE(R_TLB_LO, global,no ) | flush_tlb_page()
128 IO_STATE(R_TLB_LO, valid, no ) | flush_tlb_page()
129 IO_STATE(R_TLB_LO, kernel,no ) | flush_tlb_page()
130 IO_STATE(R_TLB_LO, we, no ) | flush_tlb_page()
/linux-4.1.27/arch/cris/arch-v10/lib/
H A Ddmacopy.c21 IO_STATE(R_GEN_CONFIG, dma6, intdma7) | dma_memcpy()
22 IO_STATE(R_GEN_CONFIG, dma7, intdma6); dma_memcpy()
32 *R_DMA_CH6_CMD = IO_STATE(R_DMA_CH6_CMD, cmd, start); dma_memcpy()
33 *R_DMA_CH7_CMD = IO_STATE(R_DMA_CH7_CMD, cmd, start); dma_memcpy()
/linux-4.1.27/arch/cris/arch-v10/drivers/
H A Dsync_serial.c327 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | etrax_sync_serial_init()
328 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | etrax_sync_serial_init()
329 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | etrax_sync_serial_init()
330 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | etrax_sync_serial_init()
331 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | etrax_sync_serial_init()
335 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal)); etrax_sync_serial_init()
370 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) | initialize_port()
371 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) | initialize_port()
372 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) | initialize_port()
373 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) | initialize_port()
374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) | initialize_port()
375 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) | initialize_port()
376 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) | initialize_port()
377 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) | initialize_port()
378 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) | initialize_port()
379 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) | initialize_port()
380 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) | initialize_port()
381 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) | initialize_port()
382 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) | initialize_port()
383 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) | initialize_port()
384 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) | initialize_port()
385 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) | initialize_port()
386 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)| initialize_port()
387 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)| initialize_port()
388 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) | initialize_port()
389 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) | initialize_port()
390 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)| initialize_port()
391 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high); initialize_port()
394 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, initialize_port()
397 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, initialize_port()
507 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, sync_serial_open()
509 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, sync_serial_open()
512 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, sync_serial_open()
514 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, sync_serial_open()
517 IO_STATE(R_IRQ_MASK2_SET, dma8_eop, sync_serial_open()
519 IO_STATE(R_IRQ_MASK2_SET, dma9_descr, sync_serial_open()
562 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, sync_serial_open()
564 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, sync_serial_open()
567 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, sync_serial_open()
569 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, sync_serial_open()
572 IO_STATE(R_IRQ_MASK2_SET, dma4_eop, sync_serial_open()
574 IO_STATE(R_IRQ_MASK2_SET, dma5_descr, sync_serial_open()
707 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) | sync_serial_ioctl_unlocked()
708 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); sync_serial_ioctl_unlocked()
718 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) | sync_serial_ioctl_unlocked()
719 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); sync_serial_ioctl_unlocked()
1228 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); start_dma()
1261 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); start_dma_in()
1286 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) | tr_interrupt()
1287 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do); tr_interrupt()
1370 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD, rx_interrupt()
1373 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR, rx_interrupt()
1399 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): manual_interrupt()
1403 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): IO_STATE() function
1411 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1416 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1420 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
H A Di2c.c642 IO_STATE(R_PORT_PB_I2C, i2c_en, on) | i2c_init()
645 IO_STATE(R_PORT_PB_I2C, i2c_oe_, enable); i2c_init()
651 IO_STATE(R_PORT_PB_DIR, dir0, input) | i2c_init()
652 IO_STATE(R_PORT_PB_DIR, dir1, output)); i2c_init()
H A Dgpio.c770 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g0dir, out)) ioif_watcher()
772 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g8_15dir, out)) ioif_watcher()
774 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g16_23dir, out)) ioif_watcher()
776 if (genconfig_shadow & IO_STATE(R_GEN_CONFIG, g24dir, out)) ioif_watcher()
/linux-4.1.27/arch/cris/include/uapi/arch-v10/arch/
H A Dsv_addr_ag.h5 *! IO_STATE(reg,field,state)
32 /* IO_STATE returns a constant corresponding to a one of the symbolic
34 #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) macro
124 IO_STATE( R_BUS_CONFIG, CE, DISABLE )
125 IO_STATE( R_BUS_CONFIG, CE, ENABLE )
127 IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
134 == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
H A Dsvinto.h43 *R_DMA_CH##n##_CMD = IO_STATE( R_DMA_CH0_CMD, cmd, reset )
54 IO_STATE( R_DMA_CH0_CMD, cmd, hold ) )
/linux-4.1.27/drivers/net/cris/
H A Deth_v10.c468 *R_NETWORK_MGM_CTRL = IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable); e100_open()
471 IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) | e100_open()
472 IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) | e100_open()
473 IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr); e100_open()
477 IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) | e100_open()
478 IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) | e100_open()
479 IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) | e100_open()
480 IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr); e100_open()
553 IO_STATE(R_NETWORK_GEN_CONFIG, phy, mii_clk) | e100_open()
554 IO_STATE(R_NETWORK_GEN_CONFIG, enable, on); e100_open()
570 IO_STATE(R_IRQ_MASK2_SET, dma0_eop, set) | e100_open()
571 IO_STATE(R_IRQ_MASK2_SET, dma1_eop, set); e100_open()
574 IO_STATE(R_IRQ_MASK0_SET, overrun, set) | e100_open()
575 IO_STATE(R_IRQ_MASK0_SET, underrun, set) | e100_open()
576 IO_STATE(R_IRQ_MASK0_SET, excessive_col, set); e100_open()
580 *R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do); e100_open()
581 *R_DMA_CH1_CLR_INTR = IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do); e100_open()
591 *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, start); e100_open()
1000 IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable) | e100_send_mdio_bit()
1004 IO_STATE(R_NETWORK_MGM_CTRL, mdoe, enable) | e100_send_mdio_bit()
1144 if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma1_eop, active)) { e100rxtx_interrupt()
1147 *R_DMA_CH1_CLR_INTR = IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do); e100rxtx_interrupt()
1159 *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, restart); e100rxtx_interrupt()
1162 IO_STATE(R_DMA_CH1_CLR_INTR, clr_eop, do) | e100rxtx_interrupt()
1163 IO_STATE(R_DMA_CH1_CLR_INTR, clr_descr, do); e100rxtx_interrupt()
1185 if (irqbits & IO_STATE(R_IRQ_MASK2_RD, dma0_eop, active)) { e100rxtx_interrupt()
1187 *R_DMA_CH0_CLR_INTR = IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do); e100rxtx_interrupt()
1200 if (irqbits & IO_STATE(R_IRQ_MASK0_RD, underrun, active)) { e100nw_interrupt()
1209 if (irqbits & IO_STATE(R_IRQ_MASK0_RD, overrun, active)) { e100nw_interrupt()
1214 if (irqbits & IO_STATE(R_IRQ_MASK0_RD, excessive_col, active)) { e100nw_interrupt()
1337 IO_STATE(R_IRQ_MASK0_CLR, overrun, clr) | e100_close()
1338 IO_STATE(R_IRQ_MASK0_CLR, underrun, clr) | e100_close()
1339 IO_STATE(R_IRQ_MASK0_CLR, excessive_col, clr); e100_close()
1342 IO_STATE(R_IRQ_MASK2_CLR, dma0_descr, clr) | e100_close()
1343 IO_STATE(R_IRQ_MASK2_CLR, dma0_eop, clr) | e100_close()
1344 IO_STATE(R_IRQ_MASK2_CLR, dma1_descr, clr) | e100_close()
1345 IO_STATE(R_IRQ_MASK2_CLR, dma1_eop, clr); e100_close()
1663 *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, restart); e100_hardware_send_packet()
/linux-4.1.27/drivers/tty/serial/
H A Dcrisv10.c207 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
1181 IO_STATE(R_GEN_CONFIG, dma6, serial0)) { e100_disable_txdma_channel()
1183 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused); e100_disable_txdma_channel()
1187 IO_STATE(R_GEN_CONFIG, dma8, serial1)) { e100_disable_txdma_channel()
1189 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb); e100_disable_txdma_channel()
1193 IO_STATE(R_GEN_CONFIG, dma2, serial2)) { e100_disable_txdma_channel()
1195 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0); e100_disable_txdma_channel()
1199 IO_STATE(R_GEN_CONFIG, dma4, serial3)) { e100_disable_txdma_channel()
1201 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1); e100_disable_txdma_channel()
1218 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0); e100_enable_txdma_channel()
1221 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1); e100_enable_txdma_channel()
1224 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2); e100_enable_txdma_channel()
1227 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3); e100_enable_txdma_channel()
1243 IO_STATE(R_GEN_CONFIG, dma7, serial0)) { e100_disable_rxdma_channel()
1245 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused); e100_disable_rxdma_channel()
1249 IO_STATE(R_GEN_CONFIG, dma9, serial1)) { e100_disable_rxdma_channel()
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb); e100_disable_rxdma_channel()
1255 IO_STATE(R_GEN_CONFIG, dma3, serial2)) { e100_disable_rxdma_channel()
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0); e100_disable_rxdma_channel()
1261 IO_STATE(R_GEN_CONFIG, dma5, serial3)) { e100_disable_rxdma_channel()
1263 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1); e100_disable_rxdma_channel()
1279 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0); e100_enable_rxdma_channel()
1282 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1); e100_enable_rxdma_channel()
1285 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2); e100_enable_rxdma_channel()
1288 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3); e100_enable_rxdma_channel()
1456 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop); rs_stop()
1458 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); rs_stop()
1479 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); rs_start()
1481 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); rs_start()
1545 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | transmit_chars_dma()
1546 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); transmit_chars_dma()
1622 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start); transmit_chars_dma()
1815 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | receive_chars_dma()
1816 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); receive_chars_dma()
1859 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart); receive_chars_dma()
1889 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start); start_recv_dma()
1901 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); start_receive()
2413 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart); handle_ser_rx_interrupt()
2453 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue); handle_ser_tx_interrupt()
2560 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set); ser_interrupt()
2674 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); startup()
2682 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | startup()
2683 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); startup()
2691 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); startup()
2698 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) | startup()
2699 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do); startup()
2776 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); shutdown()
2785 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset); shutdown()
2852 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) | change_speed()
2853 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal); change_speed()
2863 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) | change_speed()
2864 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale); change_speed()
2877 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, extern) | change_speed()
2878 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, extern); change_speed()
2899 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) | change_speed()
2900 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal); change_speed()
2925 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit); change_speed()
2926 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit); change_speed()
2931 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits); change_speed()
2936 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable); change_speed()
2937 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable); change_speed()
2942 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick); change_speed()
2943 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick); change_speed()
2947 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd); change_speed()
2948 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd); change_speed()
2954 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active); change_speed()
2959 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable); change_speed()
2960 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable); change_speed()
2967 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable); change_speed()
2971 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable); change_speed()
3189 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold); rs_send_xchar()

Completed in 192 milliseconds