1/* 2 * linux/arch/cris/arch-v10/kernel/time.c 3 * 4 * Copyright (C) 1991, 1992, 1995 Linus Torvalds 5 * Copyright (C) 1999-2002 Axis Communications AB 6 * 7 */ 8 9#include <linux/timex.h> 10#include <linux/time.h> 11#include <linux/jiffies.h> 12#include <linux/interrupt.h> 13#include <linux/swap.h> 14#include <linux/sched.h> 15#include <linux/init.h> 16#include <linux/mm.h> 17#include <asm/types.h> 18#include <asm/signal.h> 19#include <asm/io.h> 20#include <asm/delay.h> 21#include <asm/irq_regs.h> 22 23/* define this if you need to use print_timestamp */ 24/* it will make jiffies at 96 hz instead of 100 hz though */ 25#undef USE_CASCADE_TIMERS 26 27unsigned long get_ns_in_jiffie(void) 28{ 29 unsigned char timer_count, t1; 30 unsigned short presc_count; 31 unsigned long ns; 32 unsigned long flags; 33 34 local_irq_save(flags); 35 timer_count = *R_TIMER0_DATA; 36 presc_count = *R_TIM_PRESC_STATUS; 37 /* presc_count might be wrapped */ 38 t1 = *R_TIMER0_DATA; 39 40 if (timer_count != t1){ 41 /* it wrapped, read prescaler again... */ 42 presc_count = *R_TIM_PRESC_STATUS; 43 timer_count = t1; 44 } 45 local_irq_restore(flags); 46 if (presc_count >= PRESCALE_VALUE/2 ){ 47 presc_count = PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2; 48 } else { 49 presc_count = PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2; 50 } 51 52 ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + 53 ( (presc_count) * (1000000000/PRESCALE_FREQ)); 54 return ns; 55} 56 57static u32 cris_v10_gettimeoffset(void) 58{ 59 u32 count; 60 61 /* The timer interrupt comes from Etrax timer 0. In order to get 62 * better precision, we check the current value. It might have 63 * underflowed already though. 64 */ 65 count = *R_TIMER0_DATA; 66 67 /* Convert timer value to nsec */ 68 return (TIMER0_DIV - count) * (NSEC_PER_SEC/HZ)/TIMER0_DIV; 69} 70 71/* Excerpt from the Etrax100 HSDD about the built-in watchdog: 72 * 73 * 3.10.4 Watchdog timer 74 75 * When the watchdog timer is started, it generates an NMI if the watchdog 76 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or 77 * stopped after an additional 3.3 ms, the watchdog resets the chip. 78 * The watchdog timer is stopped after reset. The watchdog timer is controlled 79 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit 80 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is 81 * described in the table below: 82 * 83 * Watchdog Value written: 84 * state: To enable: To key: Operation: 85 * -------- ---------- ------- ---------- 86 * stopped 0 X No effect. 87 * stopped 1 key_val Start watchdog with key = key_val. 88 * started 0 ~key Stop watchdog 89 * started 1 ~key Restart watchdog with key = ~key. 90 * started X new_key_val Change key to new_key_val. 91 * 92 * Note: '~' is the bitwise NOT operator. 93 * 94 */ 95 96/* right now, starting the watchdog is the same as resetting it */ 97#define start_watchdog reset_watchdog 98 99#ifdef CONFIG_ETRAX_WATCHDOG 100static int watchdog_key = 0; /* arbitrary number */ 101#endif 102 103/* number of pages to consider "out of memory". it is normal that the memory 104 * is used though, so put this really low. 105 */ 106 107#define WATCHDOG_MIN_FREE_PAGES 8 108 109void reset_watchdog(void) 110{ 111#if defined(CONFIG_ETRAX_WATCHDOG) 112 /* only keep watchdog happy as long as we have memory left! */ 113 if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) { 114 /* reset the watchdog with the inverse of the old key */ 115 watchdog_key ^= 0x7; /* invert key, which is 3 bits */ 116 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | 117 IO_STATE(R_WATCHDOG, enable, start); 118 } 119#endif 120} 121 122/* stop the watchdog - we still need the correct key */ 123 124void stop_watchdog(void) 125{ 126#ifdef CONFIG_ETRAX_WATCHDOG 127 watchdog_key ^= 0x7; /* invert key, which is 3 bits */ 128 *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) | 129 IO_STATE(R_WATCHDOG, enable, stop); 130#endif 131} 132 133 134extern void cris_do_profile(struct pt_regs *regs); 135 136/* 137 * timer_interrupt() needs to keep up the real-time clock, 138 * as well as call the "xtime_update()" routine every clocktick 139 */ 140static inline irqreturn_t timer_interrupt(int irq, void *dev_id) 141{ 142 struct pt_regs *regs = get_irq_regs(); 143 /* acknowledge the timer irq */ 144 145#ifdef USE_CASCADE_TIMERS 146 *R_TIMER_CTRL = 147 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | 148 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | 149 IO_STATE( R_TIMER_CTRL, i1, clr) | 150 IO_STATE( R_TIMER_CTRL, tm1, run) | 151 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | 152 IO_STATE( R_TIMER_CTRL, i0, clr) | 153 IO_STATE( R_TIMER_CTRL, tm0, run) | 154 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); 155#else 156 *R_TIMER_CTRL = r_timer_ctrl_shadow | IO_STATE(R_TIMER_CTRL, i0, clr); 157#endif 158 159 /* reset watchdog otherwise it resets us! */ 160 reset_watchdog(); 161 162 /* Update statistics. */ 163 update_process_times(user_mode(regs)); 164 165 /* call the real timer interrupt handler */ 166 xtime_update(1); 167 168 cris_do_profile(regs); /* Save profiling information */ 169 return IRQ_HANDLED; 170} 171 172/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain */ 173 174static struct irqaction irq2 = { 175 .handler = timer_interrupt, 176 .flags = IRQF_SHARED, 177 .name = "timer", 178}; 179 180void __init time_init(void) 181{ 182 arch_gettimeoffset = cris_v10_gettimeoffset; 183 184 /* probe for the RTC and read it if it exists 185 * Before the RTC can be probed the loops_per_usec variable needs 186 * to be initialized to make usleep work. A better value for 187 * loops_per_usec is calculated by the kernel later once the 188 * clock has started. 189 */ 190 loops_per_usec = 50; 191 192 /* Setup the etrax timers 193 * Base frequency is 25000 hz, divider 250 -> 100 HZ 194 * In normal mode, we use timer0, so timer1 is free. In cascade 195 * mode (which we sometimes use for debugging) both timers are used. 196 * Remember that linux/timex.h contains #defines that rely on the 197 * timer settings below (hz and divide factor) !!! 198 */ 199 200#ifdef USE_CASCADE_TIMERS 201 *R_TIMER_CTRL = 202 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | 203 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | 204 IO_STATE( R_TIMER_CTRL, i1, nop) | 205 IO_STATE( R_TIMER_CTRL, tm1, stop_ld) | 206 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | 207 IO_STATE( R_TIMER_CTRL, i0, nop) | 208 IO_STATE( R_TIMER_CTRL, tm0, stop_ld) | 209 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); 210 211 *R_TIMER_CTRL = r_timer_ctrl_shadow = 212 IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) | 213 IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) | 214 IO_STATE( R_TIMER_CTRL, i1, nop) | 215 IO_STATE( R_TIMER_CTRL, tm1, run) | 216 IO_STATE( R_TIMER_CTRL, clksel1, cascade0) | 217 IO_STATE( R_TIMER_CTRL, i0, nop) | 218 IO_STATE( R_TIMER_CTRL, tm0, run) | 219 IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz); 220#else 221 *R_TIMER_CTRL = 222 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | 223 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | 224 IO_STATE(R_TIMER_CTRL, i1, nop) | 225 IO_STATE(R_TIMER_CTRL, tm1, stop_ld) | 226 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | 227 IO_STATE(R_TIMER_CTRL, i0, nop) | 228 IO_STATE(R_TIMER_CTRL, tm0, stop_ld) | 229 IO_STATE(R_TIMER_CTRL, clksel0, flexible); 230 231 *R_TIMER_CTRL = r_timer_ctrl_shadow = 232 IO_FIELD(R_TIMER_CTRL, timerdiv1, 192) | 233 IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV) | 234 IO_STATE(R_TIMER_CTRL, i1, nop) | 235 IO_STATE(R_TIMER_CTRL, tm1, run) | 236 IO_STATE(R_TIMER_CTRL, clksel1, c19k2Hz) | 237 IO_STATE(R_TIMER_CTRL, i0, nop) | 238 IO_STATE(R_TIMER_CTRL, tm0, run) | 239 IO_STATE(R_TIMER_CTRL, clksel0, flexible); 240 241 *R_TIMER_PRESCALE = PRESCALE_VALUE; 242#endif 243 244 /* unmask the timer irq */ 245 *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, timer0, set); 246 247 /* now actually register the irq handler that calls timer_interrupt() */ 248 setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */ 249 250 /* enable watchdog if we should use one */ 251#if defined(CONFIG_ETRAX_WATCHDOG) 252 printk("Enabling watchdog...\n"); 253 start_watchdog(); 254 255 /* If we use the hardware watchdog, we want to trap it as an NMI 256 and dump registers before it resets us. For this to happen, we 257 must set the "m" NMI enable flag (which once set, is unset only 258 when an NMI is taken). 259 260 The same goes for the external NMI, but that doesn't have any 261 driver or infrastructure support yet. */ 262 asm ("setf m"); 263 264 *R_IRQ_MASK0_SET = IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set); 265 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, nmi, set); 266#endif 267} 268