Searched defs:i1 (Results 1 - 25 of 25) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/
H A Dc2p_core.h20 static inline void _transp(u32 d[], unsigned int i1, unsigned int i2, _transp() argument
/linux-4.4.14/drivers/connector/
H A Dcn_queue.c68 int cn_cb_equal(struct cb_id *i1, struct cb_id *i2) cn_cb_equal() argument
/linux-4.4.14/arch/arm/kernel/
H A Dinsn.c8 unsigned long s, j1, j2, i1, i2, imm10, imm11; __arm_gen_branch_thumb2() local
/linux-4.4.14/drivers/isdn/mISDN/
H A Dl1oip_codec.c324 int i1, i2, c, sample; l1oip_4bit_alloc() local
H A Ddsp_cmx.c388 int memb = 0, i, ii, i1, i2; dsp_cmx_hardware() local
/linux-4.4.14/arch/arm64/kvm/
H A Dsys_regs.h120 static inline int cmp_sys_reg(const struct sys_reg_desc *i1, cmp_sys_reg() argument
H A Dsys_regs.c1617 const struct sys_reg_desc *i1, *i2, *end1, *end2; walk_sys_regs() local
/linux-4.4.14/arch/blackfin/include/asm/
H A Dcontext.S268 i1 = [sp++]; define
338 i1 = [sp++]; define
/linux-4.4.14/arch/arm/kvm/
H A Dcoproc.h128 static inline int cmp_reg(const struct coproc_reg *i1, cmp_reg() argument
H A Dcoproc.c1135 const struct coproc_reg *i1, *i2, *end1, *end2; walk_cp15() local
/linux-4.4.14/include/sound/
H A Dpcm_params.h293 static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) snd_interval_eq() argument
/linux-4.4.14/tools/perf/util/
H A Dstring.c277 int i1 = strlen(s1); strtailcmp() local
/linux-4.4.14/fs/jffs2/
H A Dcompr_rubin.c105 long i0, i1; encode() local
/linux-4.4.14/drivers/staging/lustre/lustre/llite/
H A Dnamei.c291 void ll_i2gids(__u32 *suppgids, struct inode *i1, struct inode *i2) ll_i2gids() argument
H A Dllite_lib.c2113 ll_prep_md_op_data(struct md_op_data *op_data, struct inode *i1, struct inode *i2, const char *name, int namelen, int mode, __u32 opc, void *data) ll_prep_md_op_data() argument
/linux-4.4.14/arch/parisc/math-emu/
H A Dfpudispatch.c1129 struct { u_int i1; u_int i2; } ints; decode_06() member in struct:__anon2224::__anon2225
1268 struct { u_int i1; u_int i2; } ints; decode_26() member in struct:__anon2226::__anon2227
/linux-4.4.14/drivers/block/
H A Dumem.c194 int i, i1; dump_regs() local
/linux-4.4.14/net/decnet/
H A Ddn_dev.c909 unsigned char *i1, *i2; dn_send_router_hello() local
/linux-4.4.14/arch/blackfin/include/uapi/asm/
H A Dptrace.h67 long i1; member in struct:pt_regs
/linux-4.4.14/sound/pci/cs46xx/
H A Dcs46xx_dsp_scb_types.h1126 u32 i1; member in struct:dsp_magic_snoop_task
/linux-4.4.14/drivers/isdn/i4l/
H A Disdn_net.c2027 isdn_net_swap_usage(int i1, int i2) isdn_net_swap_usage() argument
/linux-4.4.14/fs/fat/
H A Dinode.c1806 int fat_flush_inodes(struct super_block *sb, struct inode *i1, struct inode *i2) fat_flush_inodes() argument
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4.xml.h352 static inline uint32_t REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE() argument
354 static inline uint32_t REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_OP() argument
374 static inline uint32_t REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_FG_ALPHA() argument
376 static inline uint32_t REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_BG_ALPHA() argument
378 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument
380 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument
382 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument
384 static inline uint32_t REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_OVLP(i0) + __offset_STAGE(i1); } REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument
396 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } REG_MDP4_OVLP_STAGE_CO3() argument
398 static inline uint32_t REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_OVLP(i0) + __offset_STAGE_CO3(i1); } REG_MDP4_OVLP_STAGE_CO3_SEL() argument
414 static inline uint32_t REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_MV() argument
416 static inline uint32_t REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) { return 0x00002400 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_MV_VAL() argument
418 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_BV() argument
420 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002500 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument
422 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_BV() argument
424 static inline uint32_t REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) { return 0x00002580 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_BV_VAL() argument
426 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_LV() argument
428 static inline uint32_t REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002600 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument
430 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_LV() argument
432 static inline uint32_t REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) { return 0x00002680 + __offset_OVLP(i0) + 0x4*i1; } REG_MDP4_OVLP_CSC_POST_LV_VAL() argument
438 static inline uint32_t REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } REG_MDP4_LUTN_LUT() argument
440 static inline uint32_t REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) { return 0x00094800 + 0x400*i0 + 0x4*i1; } REG_MDP4_LUTN_LUT_VAL() argument
569 static inline uint32_t REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_MV() argument
571 static inline uint32_t REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003400 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_MV_VAL() argument
573 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_BV() argument
575 static inline uint32_t REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003500 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_BV_VAL() argument
577 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_BV() argument
579 static inline uint32_t REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003580 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_BV_VAL() argument
581 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_LV() argument
583 static inline uint32_t REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003600 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_PRE_LV_VAL() argument
585 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_LV() argument
587 static inline uint32_t REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) { return 0x00003680 + __offset_DMA(i0) + 0x4*i1; } REG_MDP4_DMA_CSC_POST_LV_VAL() argument
820 static inline uint32_t REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_MV() argument
822 static inline uint32_t REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024400 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_MV_VAL() argument
824 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_BV() argument
826 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024500 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument
828 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_BV() argument
830 static inline uint32_t REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024580 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_BV_VAL() argument
832 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_LV() argument
834 static inline uint32_t REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024600 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument
836 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_LV() argument
838 static inline uint32_t REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) { return 0x00024680 + 0x10000*i0 + 0x4*i1; } REG_MDP4_PIPE_CSC_POST_LV_VAL() argument
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp5/
H A Dmdp5.xml.h270 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_W() argument
272 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_W_REG(uint32_t i0, uint32_t i1) { return 0x00000080 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_W_REG() argument
292 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_R() argument
294 static inline uint32_t REG_MDP5_MDP_SMP_ALLOC_R_REG(uint32_t i0, uint32_t i1) { return 0x00000130 + __offset_MDP(i0) + 0x4*i1; } REG_MDP5_MDP_SMP_ALLOC_R_REG() argument
324 static inline uint32_t REG_MDP5_MDP_IGC(uint32_t i0, enum mdp5_igc_type i1) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1); } REG_MDP5_MDP_IGC() argument
326 static inline uint32_t REG_MDP5_MDP_IGC_LUT(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } REG_MDP5_MDP_IGC_LUT() argument
328 static inline uint32_t REG_MDP5_MDP_IGC_LUT_REG(uint32_t i0, enum mdp5_igc_type i1, uint32_t i2) { return 0x00000000 + __offset_MDP(i0) + __offset_IGC(i1) + 0x4*i2; } REG_MDP5_MDP_IGC_LUT_REG() argument
379 static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } REG_MDP5_CTL_LAYER() argument
381 static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER(i1); } REG_MDP5_CTL_LAYER_REG() argument
514 static inline uint32_t REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } REG_MDP5_CTL_LAYER_EXT() argument
516 static inline uint32_t REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_CTL(i0) + __offset_LAYER_EXT(i1); } REG_MDP5_CTL_LAYER_EXT_REG() argument
643 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument
645 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000334 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument
659 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument
661 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000340 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument
675 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument
677 static inline uint32_t REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x0000034c + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument
685 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_BIAS() argument
687 static inline uint32_t REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) { return 0x00000358 + __offset_PIPE(i0) + 0x4*i1; } REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument
945 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT() argument
947 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000000 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT_LR() argument
973 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000004 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT_TB() argument
999 static inline uint32_t REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) { return 0x00000008 + __offset_PIPE(i0) + __offset_SW_PIX_EXT(i1); } REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument
1116 static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND() argument
1118 static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00000000 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_OP_MODE() argument
1140 static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000004 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_ALPHA() argument
1142 static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00000008 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_ALPHA() argument
1144 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000000c + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument
1146 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000010 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument
1148 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000014 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument
1150 static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000018 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument
1152 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000001c + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument
1154 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00000020 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument
1156 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00000024 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument
1158 static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00000028 + __offset_LM(i0) + __offset_BLEND(i1); } REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument
1689 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PRECLAMP() argument
1691 static inline uint32_t REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000274 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument
1705 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument
1707 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) { return 0x00000280 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument
1721 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PREBIAS() argument
1723 static inline uint32_t REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) { return 0x0000028c + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument
1731 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTBIAS() argument
1733 static inline uint32_t REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) { return 0x00000298 + __offset_WB(i0) + 0x4*i1; } REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument
/linux-4.4.14/drivers/scsi/
H A Dadvansys.c349 ASC_SCSIQ_1 i1; member in struct:asc_risc_q

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