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Searched refs:phase (Results 1 – 200 of 232) sorted by relevance

12

/linux-4.4.14/drivers/clk/sunxi/
Dclk-mod0.c192 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_get_phase() local
198 value = readl(phase->reg); in mmc_get_phase()
199 delay = (value >> phase->offset) & 0x3; in mmc_get_phase()
234 struct mmc_phase *phase = to_mmc_phase(hw); in mmc_set_phase() local
285 spin_lock_irqsave(phase->lock, flags); in mmc_set_phase()
286 value = readl(phase->reg); in mmc_set_phase()
287 value &= ~GENMASK(phase->offset + 3, phase->offset); in mmc_set_phase()
288 value |= delay << phase->offset; in mmc_set_phase()
289 writel(value, phase->reg); in mmc_set_phase()
290 spin_unlock_irqrestore(phase->lock, flags); in mmc_set_phase()
[all …]
/linux-4.4.14/drivers/char/
Dppdev.c365 pp->saved_state.phase = info->phase; in pp_do_ioctl()
367 info->phase = pp->state.phase; in pp_do_ioctl()
395 pp->state.phase = init_phase (mode); in pp_do_ioctl()
399 pp->pdev->port->ieee1284.phase = pp->state.phase; in pp_do_ioctl()
420 int phase; in pp_do_ioctl() local
421 if (copy_from_user (&phase, argp, sizeof (phase))) { in pp_do_ioctl()
425 pp->state.phase = phase; in pp_do_ioctl()
428 pp->pdev->port->ieee1284.phase = phase; in pp_do_ioctl()
435 int phase; in pp_do_ioctl() local
438 phase = pp->pdev->port->ieee1284.phase; in pp_do_ioctl()
[all …]
/linux-4.4.14/include/trace/events/
Dclk.h164 TP_PROTO(struct clk_core *core, int phase),
166 TP_ARGS(core, phase),
170 __field( int, phase )
175 __entry->phase = phase;
178 TP_printk("%s %d", __get_str(name), (int)__entry->phase)
183 TP_PROTO(struct clk_core *core, int phase),
185 TP_ARGS(core, phase)
190 TP_PROTO(struct clk_core *core, int phase),
192 TP_ARGS(core, phase)
/linux-4.4.14/scripts/
Danalyze_suspend.py271 for phase in self.phases:
272 list = self.dmesg[phase]['list']
292 for phase in self.phases:
293 list = self.dmesg[phase]['list']
306 for phase in self.phases:
307 list = self.dmesg[phase]['list']
341 for phase in self.phases:
342 p = self.dmesg[phase]
373 for phase in self.phases:
374 p = self.dmesg[phase]
[all …]
/linux-4.4.14/drivers/mmc/host/
Dsdhci-sirf.c83 int phase; in sdhci_sirf_execute_tuning() local
94 phase = 0; in sdhci_sirf_execute_tuning()
98 clock_setting | phase, in sdhci_sirf_execute_tuning()
105 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
107 start = phase; in sdhci_sirf_execute_tuning()
108 end = phase; in sdhci_sirf_execute_tuning()
110 if (phase == (SIRF_TUNING_COUNT - 1) in sdhci_sirf_execute_tuning()
115 mmc_hostname(mmc), phase); in sdhci_sirf_execute_tuning()
123 } while (++phase < SIRF_TUNING_COUNT); in sdhci_sirf_execute_tuning()
130 phase = tuning_value; in sdhci_sirf_execute_tuning()
[all …]
Dsdhci-msm.c92 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase) in msm_config_cm_dll_phase() argument
121 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT; in msm_config_cm_dll_phase()
141 mmc_hostname(mmc), phase); in msm_config_cm_dll_phase()
349 u8 phase, tuned_phases[16], tuned_phase_cnt = 0; in sdhci_msm_execute_tuning() local
369 phase = 0; in sdhci_msm_execute_tuning()
372 rc = msm_config_cm_dll_phase(host, phase); in sdhci_msm_execute_tuning()
379 tuned_phases[tuned_phase_cnt++] = phase; in sdhci_msm_execute_tuning()
381 mmc_hostname(mmc), phase); in sdhci_msm_execute_tuning()
383 } while (++phase < ARRAY_SIZE(tuned_phases)); in sdhci_msm_execute_tuning()
391 phase = rc; in sdhci_msm_execute_tuning()
[all …]
/linux-4.4.14/drivers/parport/
Dieee1284_ops.c57 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ieee1284_write_compat()
143 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_write_compat()
176 port->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_nibble()
229 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_nibble()
232 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_nibble()
267 port->physport->ieee1284.phase = IEEE1284_PH_REV_DATA; in parport_ieee1284_read_byte()
317 port->physport->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_ieee1284_read_byte()
320 port->physport->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_read_byte()
357 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in ecp_forward_to_reverse()
361 port->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; in ecp_forward_to_reverse()
[all …]
Dieee1284.c255 if (port->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { in parport_ieee1284_terminate()
274 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_terminate()
312 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ieee1284_terminate()
381 port->ieee1284.phase = IEEE1284_PH_NEGOTIATION; in parport_negotiate()
419 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_negotiate()
520 port->ieee1284.phase = IEEE1284_PH_ECP_SETUP; in parport_negotiate()
536 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_negotiate()
542 port->ieee1284.phase = IEEE1284_PH_REV_IDLE; in parport_negotiate()
545 port->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_negotiate()
568 port->ieee1284.phase = IEEE1284_PH_HBUSY_DAVAIL; in parport_ieee1284_ack_data_avail()
[all …]
Dparport_ip32.c1650 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ip32_compat_write_data()
1680 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ip32_compat_write_data()
1711 if (physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { in parport_ip32_ecp_write_data()
1720 physport->ieee1284.phase = IEEE1284_PH_ECP_DIR_UNKNOWN; in parport_ip32_ecp_write_data()
1731 physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_ip32_ecp_write_data()
1761 physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_ip32_ecp_write_data()
Dprobe.c201 if (port->physport->ieee1284.phase != IEEE1284_PH_HBUSY_DAVAIL) { in parport_read_device_id()
Dparport_pc.c731 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_pc_compat_write_block_pio()
776 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_pc_compat_write_block_pio()
799 if (port->physport->ieee1284.phase != IEEE1284_PH_FWD_IDLE) { in parport_pc_ecp_write_block_pio()
827 port->physport->ieee1284.phase = IEEE1284_PH_FWD_DATA; in parport_pc_ecp_write_block_pio()
891 port->physport->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_pc_ecp_write_block_pio()
Dshare.c463 tmp->ieee1284.phase = IEEE1284_PH_FWD_IDLE; in parport_register_port()
/linux-4.4.14/drivers/leds/trigger/
Dledtrig-heartbeat.c27 unsigned int phase; member
46 switch (heartbeat_data->phase) { in led_heartbeat_function()
59 heartbeat_data->phase++; in led_heartbeat_function()
65 heartbeat_data->phase++; in led_heartbeat_function()
71 heartbeat_data->phase++; in led_heartbeat_function()
78 heartbeat_data->phase = 0; in led_heartbeat_function()
134 heartbeat_data->phase = 0; in heartbeat_trig_activate()
/linux-4.4.14/drivers/scsi/pcmcia/
Dnsp_cs.c230 SCpnt->SCp.phase = PH_UNDETERMINED; in nsp_queuecommand_lck()
371 unsigned char phase, arbit; in nsphw_start_selection() local
375 phase = nsp_index_read(base, SCSIBUSMON); in nsphw_start_selection()
376 if(phase != BUSMON_BUS_FREE) { in nsphw_start_selection()
383 SCpnt->SCp.phase = PH_ARBSTART; in nsphw_start_selection()
403 SCpnt->SCp.phase = PH_SELSTART; in nsphw_start_selection()
550 unsigned char phase, i_src; in nsp_expect_signal() local
556 phase = nsp_index_read(base, SCSIBUSMON); in nsp_expect_signal()
557 if (phase == 0xff) { in nsp_expect_signal()
566 if ((phase & mask) != 0 && (phase & BUSMON_PHASE_MASK) == current_phase) { in nsp_expect_signal()
[all …]
Dsym53c500_cs.c409 if (curSC->SCp.phase != message_in) { /* Unexpected disconnect */ in SYM53C500_intr()
424 curSC->SCp.phase = data_out; in SYM53C500_intr()
443 curSC->SCp.phase = data_in; in SYM53C500_intr()
458 curSC->SCp.phase = command_ph; in SYM53C500_intr()
463 curSC->SCp.phase = status_ph; in SYM53C500_intr()
476 curSC->SCp.phase = message_out; in SYM53C500_intr()
483 curSC->SCp.phase = message_in; in SYM53C500_intr()
503 curSC->SCp.phase = idle; in SYM53C500_intr()
569 data->current_SC->SCp.phase = command_ph; in SYM53C500_queue_lck()
Dnsp_debug.c148 int i = SCpnt->SCp.phase; in show_phase()
Dnsp_cs.h321 static int nsp_xfer (struct scsi_cmnd *SCpnt, int phase);
/linux-4.4.14/Documentation/devicetree/bindings/mmc/
Dexynos-dw-mshc.txt30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
35 * samsung,dw-mshc-ddr-timing: Specifies the value of CUI clock phase shift value
36 in transmit mode and CIU clock phase shift value in receive mode for double
39 * samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
45 - First Cell: CIU clock phase shift value for tx mode.
46 - Second Cell: CIU clock phase shift value for rx mode.
49 - valid value for tx phase shift and rx phase shift is 0 to 7.
50 - when CIU clock divider value is set to 3, all possible 8 phase shift
53 phase shift clocks should be 0.
Drockchip-dw-mshc.txt26 * rockchip,default-sample-phase: The default phase to set ciu_sample at
/linux-4.4.14/drivers/isdn/i4l/
Disdn_ttyfax.c83 if (f->phase == ISDN_FAX_PHASE_A) in isdn_tty_fax_modem_result()
84 f->phase = ISDN_FAX_PHASE_B; in isdn_tty_fax_modem_result()
222 if (f->phase == ISDN_FAX_PHASE_C) { in isdn_tty_fax_command()
233 f->phase = ISDN_FAX_PHASE_E; in isdn_tty_fax_command()
240 f->phase = ISDN_FAX_PHASE_C; in isdn_tty_fax_command()
260 f->phase = ISDN_FAX_PHASE_D; in isdn_tty_fax_command()
266 f->phase = ISDN_FAX_PHASE_B; in isdn_tty_fax_command()
274 f->phase = ISDN_FAX_PHASE_D; in isdn_tty_fax_command()
798 ((f->phase == ISDN_FAX_PHASE_B) || (f->phase == ISDN_FAX_PHASE_D))) { in isdn_tty_cmd_FCLASS2()
807 if (f->phase == ISDN_FAX_PHASE_B) { in isdn_tty_cmd_FCLASS2()
[all …]
/linux-4.4.14/drivers/gpu/drm/i915/
Di915_gem_shrinker.c85 }, *phase; in i915_gem_shrink() local
110 for (phase = phases; phase->list; phase++) { in i915_gem_shrink()
113 if ((flags & phase->bit) == 0) in i915_gem_shrink()
117 while (count < target && !list_empty(phase->list)) { in i915_gem_shrink()
121 obj = list_first_entry(phase->list, in i915_gem_shrink()
145 list_splice(&still_in_list, phase->list); in i915_gem_shrink()
/linux-4.4.14/sound/firewire/
Damdtp-stream.c254 unsigned int phase, data_blocks; in calculate_data_blocks() local
269 phase = s->data_block_state; in calculate_data_blocks()
281 data_blocks = 5 + ((phase & 1) ^ in calculate_data_blocks()
282 (phase == 0 || phase >= 40)); in calculate_data_blocks()
285 data_blocks = 11 * (s->sfc >> 1) + (phase == 0); in calculate_data_blocks()
286 if (++phase >= (80 >> (s->sfc >> 1))) in calculate_data_blocks()
287 phase = 0; in calculate_data_blocks()
288 s->data_block_state = phase; in calculate_data_blocks()
298 unsigned int syt_offset, phase, index, syt; in calculate_syt() local
314 phase = s->syt_offset_state; in calculate_syt()
[all …]
/linux-4.4.14/drivers/staging/iio/Documentation/
Dsysfs-bus-iio-dds36 Stores phase into Y.
40 control the desired phase Y which is added to the phase
48 the desired value in rad. If shared across all phase registers
56 Specifies the active phase Y which is added to the phase
68 phase is controlled by the respective phase and frequency
/linux-4.4.14/drivers/scsi/arm/
Dfas216.c200 info->scsi.type, info->scsi.phase); in fas216_dumpinfo()
276 if (info->scsi.phase < ARRAY_SIZE(phases) && in fas216_drv_phase()
277 phases[info->scsi.phase]) in fas216_drv_phase()
278 return phases[info->scsi.phase]; in fas216_drv_phase()
565 info->scsi.phase = PHASE_MSGOUT_EXPECT; in fas216_handlesync()
606 info->scsi.phase = PHASE_MSGOUT_EXPECT; in fas216_handlesync()
635 SCp->phase -= bytes_transferred; in fas216_updateptrs()
717 total = info->scsi.SCp.phase; in fas216_cleanuptransfer()
735 if (info->scsi.phase == PHASE_DATAOUT) in fas216_cleanuptransfer()
755 info->scsi.SCp.phase); in fas216_transfer()
[all …]
Dacornscsi.c385 host->scsi.phase = PHASE_IDLE; in acornscsi_resetcard()
738 host->scsi.phase = PHASE_CONNECTING; in acornscsi_kick()
874 host->scsi.phase = PHASE_IDLE; in acornscsi_done()
1320 host->scsi.phase = PHASE_COMMAND; in acornscsi_sendcommand()
1481 if (host->scsi.phase == PHASE_RECONNECTED) { in acornscsi_message()
1491 host->scsi.phase = PHASE_MSGIN; in acornscsi_message()
1498 if (host->scsi.phase != PHASE_STATUSIN) { in acornscsi_message()
1503 host->scsi.phase = PHASE_DONE; in acornscsi_message()
1517 host->scsi.phase = PHASE_MSGIN; in acornscsi_message()
1532 host->scsi.phase = PHASE_MSGIN; in acornscsi_message()
[all …]
Dscsi.h93 SCpnt->SCp.phase = scsi_bufflen(SCpnt); in init_SCp()
117 SCpnt->SCp.phase = in init_SCp()
126 SCpnt->SCp.phase = 0; in init_SCp()
Dacornscsi.h287 phase_t phase; /* current phase */ member
Dfas216.h236 phase_t phase; /* current phase */ member
/linux-4.4.14/Documentation/isdn/
DINTERFACE.fax58 - phase
61 If the phase changes because of an AT command, the LL driver
90 switching to phase C.
93 switching to phase D.
96 switching to phase B.
99 switching to phase B.
110 1: switching to phase B (next document)
115 switching to phase D.
118 OK message, switching to phase E.
/linux-4.4.14/drivers/scsi/
Dmac53c94.c53 enum fsc_phase phase; /* what we're currently trying to do */ member
96 if (state->phase == idle) in mac53c94_queue_lck()
152 if (state->phase != idle || state->current_req != NULL) in mac53c94_start()
177 state->phase = selecting; in mac53c94_start()
212 intr, stat, seq, state->phase); in mac53c94_interrupt()
225 intr, stat, seq, state->phase); in mac53c94_interrupt()
233 intr, stat, seq, state->phase); in mac53c94_interrupt()
247 switch (state->phase) { in mac53c94_interrupt()
278 state->phase = dataing; in mac53c94_interrupt()
283 state->phase = completing; in mac53c94_interrupt()
[all …]
Datari_NCR5380.c1121 p = hostdata->connected->SCp.phase; in NCR5380_dma_complete()
1310 unsigned char tmp[3], phase; in NCR5380_select() local
1592 phase = PHASE_MSGOUT; in NCR5380_select()
1593 NCR5380_transfer_pio(instance, &phase, &len, &data); in NCR5380_select()
1635 unsigned char *phase, int *count, in NCR5380_transfer_pio() argument
1638 register unsigned char p = *phase, tmp; in NCR5380_transfer_pio()
1734 *phase = tmp & PHASE_MASK; in NCR5380_transfer_pio()
1736 *phase = PHASE_UNKNOWN; in NCR5380_transfer_pio()
1738 if (!c || (*phase == p)) in NCR5380_transfer_pio()
1755 unsigned char tmp, *msgptr, phase; in do_abort() local
[all …]
DNCR5380.c1210 unsigned char tmp[3], phase; in NCR5380_select() local
1447 phase = PHASE_MSGOUT; in NCR5380_select()
1448 NCR5380_transfer_pio(instance, &phase, &len, &data); in NCR5380_select()
1489 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsig… in NCR5380_transfer_pio() argument
1491 unsigned char p = *phase, tmp; in NCR5380_transfer_pio()
1606 *phase = tmp & PHASE_MASK; in NCR5380_transfer_pio()
1608 *phase = PHASE_UNKNOWN; in NCR5380_transfer_pio()
1610 if (!c || (*phase == p)) in NCR5380_transfer_pio()
1650 unsigned char *msgptr, phase, tmp; in do_abort() local
1688 phase = PHASE_MSGOUT; in do_abort()
[all …]
Dmesh.c95 u8 phase; member
152 enum mesh_phase phase; /* what we're currently trying to do */ member
221 tlp->phase = (ms->msgphase << 4) + ms->phase; in dlog()
252 t, lp->bs1, lp->bs0, lp->phase); in dumplog()
277 lp->bs1, lp->bs0, lp->phase, lp->tgt); in dumpslog()
322 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr); in mesh_dump_regs()
399 ms->phase = idle; in mesh_init()
427 ms->phase = arbitrating; in mesh_start_cmd()
467 if (ms->phase != arbitrating) in mesh_start_cmd()
475 ms->phase = idle; in mesh_start_cmd()
[all …]
Daha152x.c887 CURRENT_SC->SCp.phase |= 1 << 16; in setup_expected_interrupts()
889 if(CURRENT_SC->SCp.phase & selecting) { in setup_expected_interrupts()
894 SETPORT(SIMODE0, (CURRENT_SC->SCp.phase & spiordy) ? ENSPIORDY : 0); in setup_expected_interrupts()
916 int phase, void (*done)(Scsi_Cmnd *)) in aha152x_internal_queue() argument
922 SCpnt->SCp.phase = not_issued | phase; in aha152x_internal_queue()
928 if(SCpnt->SCp.phase & (resetting|check_condition)) { in aha152x_internal_queue()
951 if ((phase & resetting) || !scsi_sglist(SCpnt)) { in aha152x_internal_queue()
1090 if(SCpnt->SCp.phase & resetted) { in aha152x_device_reset()
1390 CURRENT_SC->SCp.phase &= ~syncneg; in busfree_run()
1392 if(CURRENT_SC->SCp.phase & completed) { in busfree_run()
[all …]
DNCR53c406a.c687 current_SC->SCp.phase = idle;
711 current_SC->SCp.phase = command_ph; in NCR53c406a_queue_lck()
818 current_SC->SCp.phase = idle; in NCR53c406a_intr()
826 current_SC->SCp.phase = idle; in NCR53c406a_intr()
835 current_SC->SCp.phase = idle; in NCR53c406a_intr()
843 current_SC->SCp.phase = idle; in NCR53c406a_intr()
851 if (current_SC->SCp.phase != message_in) { /* Unexpected disconnect */ in NCR53c406a_intr()
859 current_SC->SCp.phase = idle; in NCR53c406a_intr()
868 current_SC->SCp.phase = data_out; in NCR53c406a_intr()
890 current_SC->SCp.phase = data_in; in NCR53c406a_intr()
[all …]
Dsym53c416.c347 current_command->SCp.phase = idle; in sym53c416_intr_handle()
357 current_command->SCp.phase = idle; in sym53c416_intr_handle()
367 current_command->SCp.phase = idle; in sym53c416_intr_handle()
377 current_command->SCp.phase = idle; in sym53c416_intr_handle()
387 current_command->SCp.phase = idle; in sym53c416_intr_handle()
396 if(current_command->SCp.phase != message_in) in sym53c416_intr_handle()
400 current_command->SCp.phase = idle; in sym53c416_intr_handle()
414 current_command->SCp.phase = data_out; in sym53c416_intr_handle()
436 current_command->SCp.phase = data_in; in sym53c416_intr_handle()
457 current_command->SCp.phase = command_ph; in sym53c416_intr_handle()
[all …]
Dimm.c67 dev->cur_cmd->SCp.phase = 1; in got_it()
762 if (cmd->SCp.phase > 1) in imm_interrupt()
786 switch (cmd->SCp.phase) { in imm_engine()
800 cmd->SCp.phase++; in imm_engine()
808 cmd->SCp.phase++; in imm_engine()
818 cmd->SCp.phase++; in imm_engine()
832 cmd->SCp.phase++; in imm_engine()
850 cmd->SCp.phase++; in imm_engine()
866 cmd->SCp.phase++; in imm_engine()
878 cmd->SCp.phase++; in imm_engine()
[all …]
Dwd7000.c507 volatile unchar phase; /* used by interrupt handler */ member
517 volatile unchar phase; /* used by interrupt handler */ member
527 volatile unchar phase; /* used by interrupt handler */ member
538 volatile unchar phase; /* used by interrupt handler */ member
549 volatile unchar phase; /* used by interrupt handler */ member
566 volatile unchar phase; /* used by interrupt handler */ member
574 volatile unchar phase; /* used by interrupt handler */ member
1060 icb->phase = 0; in wd7000_intr()
1065 if (--(SCpnt->SCp.phase) <= 0) { /* all scbs are done */ in wd7000_intr()
1098 SCpnt->SCp.phase = 1; in wd7000_queuecommand_lck()
[all …]
DNCR5380.h206 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2) argument
333 static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsig…
335 static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsig…
Dppa.c58 dev->cur_cmd->SCp.phase = 1; in got_it()
660 if (cmd->SCp.phase > 1) in ppa_interrupt()
682 switch (cmd->SCp.phase) { in ppa_engine()
717 cmd->SCp.phase++; in ppa_engine()
725 cmd->SCp.phase++; in ppa_engine()
734 cmd->SCp.phase++; in ppa_engine()
747 cmd->SCp.phase++; in ppa_engine()
759 cmd->SCp.phase++; in ppa_engine()
798 cmd->SCp.phase = 0; /* bus free */ in ppa_queuecommand_lck()
839 switch (cmd->SCp.phase) { in ppa_abort()
[all …]
Dinitio.c1180 host->phase = host->jsstatus0 & TSS_PH_MASK; in tulip_scsi()
1338 if (host->phase == MSG_OUT) { in initio_state_1()
1418 switch (host->phase) { in initio_state_3()
1425 if (host->phase == CMD_OUT) in initio_state_3()
1489 switch (host->phase) { in initio_state_4()
1576 if ((cnt == 1) && (host->phase == DATA_OUT)) { in initio_state_5()
1636 switch (host->phase) { in initio_state_6()
1686 switch (host->phase) { in initio_state_7()
1775 if (host->phase != DATA_IN) { in initio_xpad_in()
1800 if (host->phase != DATA_OUT) { /* Disable wide CPU to allow read 16 bits */ in initio_xpad_out()
[all …]
Dqlogicfas408.c96 static int ql_pdma(struct qlogicfas408_priv *priv, int phase, char *request, int reqlen) in ql_pdma() argument
101 if (phase & 1) { /* in */ in ql_pdma()
266 unsigned int phase; /* recorded scsi phase */ in ql_pcmd() local
304 if (reqlen && !((phase = inb(qbase + 4)) & 6)) { /* data phase */ in ql_pcmd()
321 if (ql_pdma(priv, phase, buf, sg->length)) in ql_pcmd()
Dfdomain.c1158 if (current_SC->SCp.phase & aborted) { in do_fdomain_16x0_intr()
1170 if (current_SC->SCp.phase & in_arbitration) { in do_fdomain_16x0_intr()
1181 current_SC->SCp.phase = in_selection; in do_fdomain_16x0_intr()
1194 } else if (current_SC->SCp.phase & in_selection) { in do_fdomain_16x0_intr()
1214 current_SC->SCp.phase = in_other; in do_fdomain_16x0_intr()
1408 if (current_SC->SCp.phase & disconnect) { in do_fdomain_16x0_intr()
1458 current_SC->SCp.phase = in_arbitration; in fdomain_16x0_queue_lck()
1487 switch (SCpnt->SCp.phase) { in DEF_SCSI_QCMD()
1495 SCpnt->SCp.phase, in DEF_SCSI_QCMD()
1563 current_SC->SCp.phase |= aborted; in fdomain_16x0_abort()
Dscript_asm.pl167 $phase = join ('|', keys %scsi_phases);
168 print STDERR "phase regex = $phase\n" if ($debug);
322 } elsif ($conditional =~ /^($phase)\s*(.*)/i) {
470 if ($rest =~ /^FROM\s+($value)\s*,\s*(WITH|WHEN)\s+($phase)\s*$/i) {
479 } elsif ($rest =~ /^($value)\s*,\s*(PTR\s+|)($value)\s*,\s*(WITH|WHEN)\s+($phase)\s*$/i) {
Dncr53c8xx.h1238 #define WHEN(phase) (0x00030000 | (phase)) argument
1239 #define IF(phase) (0x00020000 | (phase)) argument
Din2000.c532 cmd->SCp.phase = 0; /* assume no disconnect */ in DEF_SCSI_QCMD()
546 prev->SCp.phase = 1; in DEF_SCSI_QCMD()
553 cmd->SCp.phase = 1; in DEF_SCSI_QCMD()
560 write_3393(hostdata, WD_SOURCE_ID, ((cmd->SCp.phase) ? SRCID_ER : 0)); in DEF_SCSI_QCMD()
646 if (!(cmd->SCp.phase)) { in DEF_SCSI_QCMD()
707 DB(DB_EXECUTE, printk("%s)EX-2 ", (cmd->SCp.phase) ? "d:" : "")) in DEF_SCSI_QCMD()
784 if ((hostdata->level2 >= L2_DATA) || (hostdata->level2 == L2_BASIC && cmd->SCp.phase == 0)) { in transfer_bytes()
800 if ((hostdata->level2 >= L2_DATA) || (hostdata->level2 == L2_BASIC && cmd->SCp.phase == 0)) { in transfer_bytes()
1101 if (cmd->SCp.phase) in in2000_intr()
Dwd33c93.c562 cmd->SCp.phase = 0; /* assume no disconnect */ in DEF_SCSI_QCMD()
579 prev->SCp.phase = 1; in DEF_SCSI_QCMD()
587 cmd->SCp.phase = 1; in DEF_SCSI_QCMD()
595 write_wd33c93(regs, WD_SOURCE_ID, ((cmd->SCp.phase) ? SRCID_ER : 0)); in DEF_SCSI_QCMD()
664 if ((cmd->SCp.phase == 0) && (hostdata->no_dma == 0)) { in DEF_SCSI_QCMD()
691 printk("%s)EX-2 ", (cmd->SCp.phase) ? "d:" : "")) in DEF_SCSI_QCMD()
790 (hostdata->level2 == L2_BASIC && cmd->SCp.phase == 0)) { in transfer_bytes()
900 if (cmd->SCp.phase) in wd33c93_intr()
Dsun3_scsi.c65 #define NCR5380_dma_xfer_len(instance, cmd, phase) \ argument
66 sun3scsi_dma_xfer_len(cmd->SCp.this_residual, cmd, !((phase) & SR_IO))
Dnsp32.c461 unsigned char phase; in nsp32_selection_autopara() local
471 phase = nsp32_read1(base, SCSI_BUS_MONITOR); in nsp32_selection_autopara()
472 if (phase != BUSMON_BUS_FREE) { in nsp32_selection_autopara()
474 show_busphase(phase & BUSMON_PHASE_MASK); in nsp32_selection_autopara()
591 unsigned char phase; in nsp32_selection_autoscsi() local
608 phase = nsp32_read1(base, SCSI_BUS_MONITOR); in nsp32_selection_autoscsi()
609 if(((phase & BUSMON_BSY) == 1) || (phase & BUSMON_SEL) == 1) { in nsp32_selection_autoscsi()
Datari_scsi.c110 #define NCR5380_dma_xfer_len(instance, cmd, phase) \ argument
111 atari_dma_xfer_len(cmd->SCp.this_residual, cmd, !((phase) & SR_IO))
Desp_scsi.c1391 u32 fflags, phase; in esp_data_bytes_sent() local
1405 phase = esp->sreg & ESP_STAT_PMASK; in esp_data_bytes_sent()
1408 if ((phase == ESP_DOP && in esp_data_bytes_sent()
1410 (phase == ESP_DIP && in esp_data_bytes_sent()
2113 u8 phase; in __esp_interrupt() local
2145 phase = (esp->sreg & ESP_STAT_PMASK); in __esp_interrupt()
2147 if (((phase != ESP_DIP && phase != ESP_DOP) && in __esp_interrupt()
Dinitio.h512 u8 phase; /* 0F */ member
Dgdth.c2073 if (nscp_cmndinfo->phase == -1) { in gdth_next()
2074 nscp_cmndinfo->phase = CACHESERVICE; /* default: cache svc. */ in gdth_next()
2088 nscp_cmndinfo->phase = ((ha->scan_mode & 0x10 ? 1:0) << 8) in gdth_next()
2099 nscp_cmndinfo->phase = SCSIRAWSERVICE; in gdth_next()
2117 if ((nscp_cmndinfo->phase & 0xff) == CACHESERVICE) { in gdth_next()
2121 } else if ((nscp_cmndinfo->phase & 0xff) == SCSIRAWSERVICE) { in gdth_next()
2636 cmdp->u.raw64.direction = (cmndinfo->phase >> 8); in gdth_fill_raw_cmd()
2642 cmdp->u.raw.direction = (cmndinfo->phase >> 8); in gdth_fill_raw_cmd()
3340 cmndinfo->phase = -2; /* reservation conflict */ in gdth_sync_event()
4023 cmndinfo->phase = -1; in DEF_SCSI_QCMD()
Dlibiscsi.c1359 if (task->sc->SCp.phase != conn->session->age) { in iscsi_itt_to_ctask()
1362 task->sc->SCp.phase, conn->session->age); in iscsi_itt_to_ctask()
1616 sc->SCp.phase = conn->session->age; in iscsi_alloc_task()
2156 sc->SCp.phase != session->age) { in iscsi_eh_abort()
Ddc395x.c1704 u16 phase; in dc395x_handle_interrupt() local
1757 phase = (u16)srb->scsi_phase; in dc395x_handle_interrupt()
1772 dc395x_statev = dc395x_scsi_phase0[phase]; in dc395x_handle_interrupt()
1781 phase = (u16)scsi_status & PHASEMASK; in dc395x_handle_interrupt()
1795 dc395x_statev = dc395x_scsi_phase1[phase]; in dc395x_handle_interrupt()
Dgdth.h915 int phase; /* ???? */ member
Dncr53c8xx.c525 #define __data_mapped SCp.phase
6168 int phase = -1; in ncr_int_par() local
6199 phase = (dbc >> 24) & 7; in ncr_int_par()
6200 if (phase == 7) in ncr_int_par()
6212 if (phase == 1) in ncr_int_par()
/linux-4.4.14/Documentation/networking/
Dcops.txt52 dummy -seed -phase 2 -net 2000 -addr 2000.10 -zone "1033"
53 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
56 eth0 -seed -phase 2 -net 3000 -addr 3000.20 -zone "1033"
57 lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
61 lt0 -seed -phase 1 -net 1000 -addr 1000.10 -zone "LocalTalk1"
62 lt1 -seed -phase 1 -net 2000 -addr 2000.20 -zone "LocalTalk2"
63 eth0 -seed -phase 2 -net 3000 -addr 3000.30 -zone "EtherTalk"
Dltpc.txt47 dummy -seed -phase 2 -net 2000 -addr 2000.26 -zone "1033"
48 lt0 -seed -phase 1 -net 1033 -addr 1033.27 -zone "1033"
62 lt0 -phase 1
Dswitchdev.txt380 For switchdev ops attr_set and obj_add, there is a 2 phase transaction model
381 used. First phase is to "prepare" anything needed, including various checks,
383 to fail here. The second phase is to "commit" the actual changes.
388 The object created by a driver in "prepare" phase and it is queued up by:
390 During the "commit" phase, the driver gets the object by:
393 If a transaction is aborted during "prepare" phase, switchdev code will handle
Dcan.txt379 bitrates for the arbitration phase and the payload phase of the CAN FD frame
1022 [ tq TQ prop-seg PROP_SEG phase-seg1 PHASE-SEG1
1023 phase-seg2 PHASE-SEG2 [ sjw SJW ] ]
1057 tq 125 prop-seg 6 phase-seg1 7 phase-seg2 2 sjw 1
1091 "tq 125 prop-seg 6 phase-seg1 7 phase-seg2 2 sjw 1"
1092 Shows the time quanta in ns, propagation segment, phase buffer
1121 phase-seg1 7 phase-seg2 2 sjw 1
1169 arbitration phase and the payload phase of the CAN FD frame. Therefore a
1191 has to be set. This bitrate for the data phase of the CAN FD frame has to be
1192 at least the bitrate which was configured for the arbitration phase. This
[all …]
Drxrpc.txt5 The RxRPC protocol driver provides a reliable two-phase transport on top of UDP
59 (2) A two-phase protocol. The client transmits a blob (the request) and then
126 (*) Calls are two-phase and asymmetric: the client sends its request data,
130 (*) The data blobs are of indefinite size, the end of a phase is marked with a
307 of the last data message in that phase yet), then MSG_MORE will be
/linux-4.4.14/Documentation/devicetree/bindings/leds/backlight/
Dsky81452-backlight.txt14 - skyworks,phase-shift : Enable phase shift mode
27 skyworks,phase-shift;
/linux-4.4.14/Documentation/video4linux/
Dradiotrack.txt88 0 0 : "zero" bit phase 1
89 0 1 : "zero" bit phase 2
91 1 0 : "one" bit phase 1
92 1 1 : "one" bit phase 2
138 disable, "zero" bit phase 1, tuner adjust)
140 disable, "zero" bit phase 2, tuner adjust)
143 disable, "one" bit phase 1, tuner adjust)
145 disable, "one" bit phase 2, tuner adjust)
Dhauppauge-wintv-cx88-ir.txt35 bits. (Hint: look for the 0/1and 1/0 crossings of the RC5 bi-phase data) An
50 and even a reference to how to decode a bi-phase data stream.
/linux-4.4.14/drivers/target/iscsi/
Discsi_target_parameters.c127 char *name, char *value, u8 phase, u8 scope, u8 sender, in iscsi_set_default_param() argument
151 param->phase = phase; in iscsi_set_default_param()
611 new_param->phase = param->phase; in iscsi_copy_param_list()
1234 int phase, in iscsi_check_key() argument
1271 if (!phase) in iscsi_check_key()
1274 if (!(param->phase & phase)) { in iscsi_check_key()
1277 switch (phase) { in iscsi_check_key()
1294 u8 phase, in iscsi_enforce_integrity_rules() argument
1304 if (!(param->phase & phase)) in iscsi_enforce_integrity_rules()
1321 if (!(param->phase & phase)) in iscsi_enforce_integrity_rules()
[all …]
Discsi_target_parameters.h16 u8 phase; member
205 #define IS_PHASE_SECURITY(p) ((p)->phase & PHASE_SECURITY)
206 #define IS_PHASE_OPERATIONAL(p) ((p)->phase & PHASE_OPERATIONAL)
207 #define IS_PHASE_DECLARATIVE(p) ((p)->phase & PHASE_DECLARATIVE)
208 #define IS_PHASE_FFP0(p) ((p)->phase & PHASE_FFP0)
/linux-4.4.14/Documentation/devicetree/bindings/spi/
Dspi-samsung.txt48 - samsung,spi-feedback-delay: The sampling phase shift to be applied on the
52 - 0: No phase shift.
53 - 1: 90 degree phase shift sampling.
54 - 2: 180 degree phase shift sampling.
55 - 3: 270 degree phase shift sampling.
Dspi-bus.txt53 shifted clock phase (CPHA) mode
/linux-4.4.14/drivers/usb/host/
Duhci-q.c611 static int uhci_highest_load(struct uhci_hcd *uhci, int phase, int period) in uhci_highest_load() argument
613 int highest_load = uhci->load[phase]; in uhci_highest_load()
615 for (phase += period; phase < MAX_PHASE; phase += period) in uhci_highest_load()
616 highest_load = max_t(int, highest_load, uhci->load[phase]); in uhci_highest_load()
630 if (qh->phase >= 0) in uhci_check_bandwidth()
631 minimax_load = uhci_highest_load(uhci, qh->phase, qh->period); in uhci_check_bandwidth()
633 int phase, load; in uhci_check_bandwidth() local
636 qh->phase = 0; in uhci_check_bandwidth()
637 minimax_load = uhci_highest_load(uhci, qh->phase, qh->period); in uhci_check_bandwidth()
638 for (phase = 1; phase < max_phase; ++phase) { in uhci_check_bandwidth()
[all …]
Dehci-sched.c214 ps->phase, ps->phase_uf, ps->period, in bandwidth_dbg()
228 if (qh->ps.phase == NO_FRAME) /* Bandwidth wasn't reserved */ in reserve_release_intr_bandwidth()
554 qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs); in qh_link_periodic()
560 for (i = qh->ps.phase; i < ehci->periodic_size; i += period) { in qh_link_periodic()
635 for (i = qh->ps.phase; i < ehci->periodic_size; i += period) in qh_unlink_periodic()
647 qh, qh->ps.phase, qh->ps.usecs, qh->ps.c_usecs); in qh_unlink_periodic()
871 if (qh->ps.phase != NO_FRAME) { in qh_schedule()
911 qh->ps.phase = (qh->ps.period ? ehci->random_frame & in qh_schedule()
913 qh->ps.bw_phase = qh->ps.phase & (qh->ps.bw_period - 1); in qh_schedule()
1034 stream->ps.phase = NO_FRAME; in iso_stream_alloc()
[all …]
Duhci-debug.c187 space, "", qh->period, qh->phase, qh->load, in uhci_show_qh()
191 space, "", qh->period, qh->phase, qh->load); in uhci_show_qh()
Duhci-hcd.h167 short phase; /* Between 0 and period-1 */ member
Dehci.h68 u16 phase; /* actual phase, frame part */ member
/linux-4.4.14/drivers/block/paride/
Dpd.c356 static enum action (*phase)(void); variable
397 if (!phase) { in run_fsm()
400 phase = do_pd_io_start; in run_fsm()
413 switch(res = phase()) { in run_fsm()
417 phase = NULL; in run_fsm()
448 phase = pd_special; in do_pd_io_start()
507 phase = do_pd_read_drq; in do_pd_read_start()
534 phase = do_pd_write_done; in do_pd_write_start()
553 phase = do_pd_read_start; in do_pd_read_drq()
573 phase = do_pd_write_start; in do_pd_write_done()
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Daltr_socfpga.txt26 - clk-phase : For the sdmmc_clk, contains the value of the clock phase that controls
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
Dqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
Dclock-bindings.txt102 /* phase-locked-loop device, generates a higher frequency clock
/linux-4.4.14/Documentation/power/
Ddevices.txt238 always go together, and both are multi-phase operations.
273 hibernation state ("suspend-to-disk"). Each phase involves executing callbacks
274 for every device before the next phase begins. Not all busses or classes
286 which callback to execute in the given phase:
318 1. The prepare phase is meant to prevent races by preventing new devices
323 phase the device tree is traversed top-down.
361 4. The suspend_noirq phase occurs after IRQ handlers have been disabled,
370 an error during the suspend phase by fielding a shared interrupt
400 means undoing the actions of the suspend_noirq phase. If the bus type
414 preceding suspend_late phase.
[all …]
Dsuspend-and-interrupts.txt11 suspend after the "late" phase of suspending devices (that is, after all of the
15 The rationale for doing so is that after the "late" phase of device suspend
24 of suspend_device_irqs(), along with the "noirq" phase of device suspend and
27 Device IRQs are re-enabled during system resume, right before the "early" phase
99 interrupts right after the "noirq" phase of suspending devices.
Dpci.txt422 callbacks for this purpose. They are executed in phases such that each phase
424 to the given subsystem before the next phase begins. These phases always run
457 Note that the suspend phase is carried out asynchronously for PCI devices, so
533 The resume phase is carried out asynchronously for PCI devices, like the
534 suspend phase described above, which means that if two PCI devices don't depend
560 This means that the prepare phase is exactly the same as for system suspend.
601 The complete phase it the same as for system resume.
609 where the prepare phase is exactly the same as for system suspend. The other
665 The complete phase is carried out in exactly the same way as during system
824 state in the resume_noirq phase of system resume and restores their standard
[all …]
/linux-4.4.14/Documentation/
Dmemory-hotplug.txt18 4. Physical memory hot-add phase
21 5. Logical Memory hot-add phase
59 1) Physical Memory Hotplug phase
60 2) Logical Memory Hotplug phase.
62 The First phase is to communicate hardware/firmware and make/erase
63 environment for hotplugged memory. Basically, this phase is necessary
64 for the purpose (B), but this is good phase for communication between
71 this phase is triggered automatically. ACPI can notify this event. If not,
75 Logical Memory Hotplug phase is to change memory state into
77 changed by this phase. The kernel makes all memory in it as free pages
[all …]
Dmodule-signing.txt70 modules_install phase of a build. If this is off, then the modules must
78 This presents a choice of which hash algorithm the installation phase will
/linux-4.4.14/drivers/block/
Dswim.c256 swim_write(base, phase, 0xf5); in get_swim_mode()
257 if (swim_read(base, phase) != 0xf5) in get_swim_mode()
259 swim_write(base, phase, 0xf6); in get_swim_mode()
260 if (swim_read(base, phase) != 0xf6) in get_swim_mode()
262 swim_write(base, phase, 0xf7); in get_swim_mode()
263 if (swim_read(base, phase) != 0xf7) in get_swim_mode()
274 swim_write(base, phase, RELAX); in swim_select()
278 swim_write(base, phase, sel & CA_MASK); in swim_select()
289 swim_write(base, phase, (LSTRB<<4) | LSTRB); in swim_action()
291 swim_write(base, phase, (LSTRB<<4) | ((~LSTRB) & 0x0F)); in swim_action()
/linux-4.4.14/drivers/net/irda/
Dsh_sir.c446 static void sh_sir_set_phase(struct sh_sir_self *self, int phase) in sh_sir_set_phase() argument
451 switch (phase) { in sh_sir_set_phase()
488 static void sh_sir_tx(struct sh_sir_self *self, int phase) in sh_sir_tx() argument
490 switch (phase) { in sh_sir_tx()
563 int phase = sh_sir_is_which_phase(self); in sh_sir_irq() local
565 switch (phase) { in sh_sir_irq()
568 sh_sir_tx(self, phase); in sh_sir_irq()
/linux-4.4.14/arch/mips/include/asm/octeon/
Dcvmx-smix-defs.h154 uint64_t phase:8; member
156 uint64_t phase:8;
177 uint64_t phase:8; member
179 uint64_t phase:8;
Dcvmx-led-defs.h69 uint64_t phase:7; member
71 uint64_t phase:7;
/linux-4.4.14/drivers/staging/iio/frequency/
Dad9832.c60 unsigned long addr, unsigned long phase) in ad9832_write_phase() argument
62 if (phase > BIT(AD9832_PHASE_BITS)) in ad9832_write_phase()
67 ((phase >> 8) & 0xFF)); in ad9832_write_phase()
70 (phase & 0xFF)); in ad9832_write_phase()
Dad9834.c56 unsigned long addr, unsigned long phase) in ad9834_write_phase() argument
58 if (phase > BIT(AD9834_PHASE_BITS)) in ad9834_write_phase()
60 st->data = cpu_to_be16(addr | phase); in ad9834_write_phase()
/linux-4.4.14/Documentation/devicetree/bindings/iio/frequency/
Dadf4350.txt22 - adi,phase-detector-polarity-positive-enable: Enables positive phase
82 adi,phase-detector-polarity-positive-enable;
/linux-4.4.14/arch/x86/crypto/
Dghash-clmulni-intel_asm.S70 # first phase of the reduction
83 # second phase of the reduction
Daesni-intel_avx-x86_64.S269 #first phase of the reduction
280 vpxor \T2, \GH, \GH # first phase of the reduction complete
282 #second phase of the reduction
926 #first phase of the reduction
938 vpxor \T2, \T7, \T7 # first phase of the reduction complete
952 #second phase of the reduction
1115 #first phase of the reduction
1126 vpxor \T2, \T7, \T7 # first phase of the reduction complete
1130 #second phase of the reduction
1559 #first phase of the reduction
[all …]
Daesni-intel_asm.S180 # first phase of the reduction
197 # second phase of the reduction
831 # first phase of reduction
847 # second phase of reduction
1043 # first phase of reduction
1059 # second phase of reduction
1143 # first phase of the reduction
1158 # second phase of the reduction
/linux-4.4.14/Documentation/devicetree/bindings/power/
Dbq25890.txt10 constant-voltage phase drops below this value (in uA);
12 phase (in uA);
Dbq2415x.txt26 constant-voltage phase drops below this value (in mA).
Drt9455_charger.txt14 When the current in constant-voltage phase drops
Dbq24257.txt16 constant-voltage phase drops below this value (in uA).
/linux-4.4.14/drivers/scsi/aic7xxx/
Daic79xx.seq549 * 2) In a non QAS, protocol allowed phase change,
706 * On a phase change oustside of packet boundaries,
805 * REQs in a non-packet phase.
839 * should go into the message out phase since we have ATN
847 * the bus phase.
865 * Command phase. Set up the DMA registers and let 'er rip.
904 * command phase starts. There is only one problem
905 * with this approach. If the target changes phase
907 * that can go out on the bus in a data phase. Due
913 * 800ns dead time between command phase and the REQ
[all …]
Daic7xxx.seq187 * setup the phase for receiving messages
455 * Assert BSY and setup the phase for
648 * should go into the message out phase since we have ATN
658 * the bus phase.
839 * If we re-enter the data phase after going through another
840 * phase, our transfer location has almost certainly been
848 /* We have seen a data phase for the first time */
890 * us to another phase, and then notify the host.
915 * completes or the target changes phase.
935 * The transfer has terminated either due to a phase
[all …]
Daic7xxx.reg217 * upper byte of a 16bit wide asynchronouse data phase transfer.
359 field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */
877 mask BAD_PHASE SEQINT /* unknown scsi bus phase */
883 * Returned to data phase
1501 * The last bus phase as seen by the sequencer.
Daic7xxx.h762 uint8_t phase; member
Daic79xx.h816 uint8_t phase; member
Daic7xxx_core.c1394 if (lastphase == ahc_phase_table[i].phase) in ahc_handle_seqint()
1650 if (errorphase == ahc_phase_table[i].phase) in ahc_handle_scsiint()
1940 if (lastphase == ahc_phase_table[i].phase) in ahc_handle_scsiint()
2802 ahc_lookup_phase_entry(int phase) in ahc_lookup_phase_entry() argument
2813 if (phase == entry->phase) in ahc_lookup_phase_entry()
Daic79xx.reg136 BAD_PHASE, /* unknown scsi bus phase */
142 * Returned to data phase
3694 * the current data phase is odd.
3859 * The last bus phase as seen by the sequencer.
/linux-4.4.14/Documentation/devicetree/bindings/display/
Dssd1307fb.txt25 - solomon,prechargep1: Length of deselect period (phase 1) in clock cycles.
26 - solomon,prechargep2: Length of precharge period (phase 2) in clock cycles.
/linux-4.4.14/drivers/scsi/sym53c8xx_2/
Dsym_defs.h722 #define WHEN(phase) (0x00030000 | (phase)) argument
723 #define IF(phase) (0x00020000 | (phase)) argument
Dsym_hipd.c2318 int phase = cmd & 7; local
2344 if ((cmd & 0xc0) || !(phase & 1) || !(sbcl & 0x8))
2356 np->msgout[0] = (phase == 7) ? M_PARITY : M_ID_ERROR;
2365 if (phase == 1 || phase == 5) {
2378 else if (phase == 7) /* We definitely cannot handle parity errors */
/linux-4.4.14/drivers/clk/rockchip/
DMakefile10 obj-y += clk-mmc-phase.o
/linux-4.4.14/Documentation/video4linux/cx88/
Dhauppauge-wintv-cx88-ir.txt35 bits. (Hint: look for the 0/1and 1/0 crossings of the RC5 bi-phase data) An
50 and even a reference to how to decode a bi-phase data stream.
/linux-4.4.14/drivers/input/joystick/iforce/
Diforce-ff.c69 __s16 magnitude, __s16 offset, u16 period, u16 phase) in make_period_modifier() argument
91 data[4] = HI(phase); in make_period_modifier()
288 || old->u.periodic.phase != new->u.periodic.phase); in need_period_modifier()
372 effect->u.periodic.period, effect->u.periodic.phase); in iforce_upload_periodic()
/linux-4.4.14/drivers/net/ethernet/qlogic/qed/
Dqed_init_ops.h37 int phase,
Dqed_init_ops.c415 u32 phase, in qed_init_cmd_phase() argument
421 if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase && in qed_init_cmd_phase()
431 int phase, in qed_init_run() argument
468 phase, phase_id); in qed_init_run()
/linux-4.4.14/sound/pci/ice1712/
DMakefile8 …revo.o aureon.o vt1720_mobo.o pontis.o prodigy192.o prodigy_hifi.o juli.o phase.o wtm.o se.o maya4…
/linux-4.4.14/drivers/usb/atm/
Dspeedtch.c363 int phase, const struct firmware **fw_p) in speedtch_find_firmware() argument
371 sprintf(buf, "speedtch-%d.bin.%x.%02x", phase, major_revision, minor_revision); in speedtch_find_firmware()
375 sprintf(buf, "speedtch-%d.bin.%x", phase, major_revision); in speedtch_find_firmware()
379 sprintf(buf, "speedtch-%d.bin", phase); in speedtch_find_firmware()
383 usb_err(usbatm, "%s: no stage %d firmware found!\n", __func__, phase); in speedtch_find_firmware()
389 usb_info(usbatm, "found stage %d firmware %s\n", phase, buf); in speedtch_find_firmware()
Dcxacru.c1075 char *phase, const struct firmware **fw_p) in cxacru_find_firmware() argument
1081 sprintf(buf, "cxacru-%s.bin", phase); in cxacru_find_firmware()
1085 usb_dbg(usbatm, "no stage %s firmware found\n", phase); in cxacru_find_firmware()
/linux-4.4.14/Documentation/devicetree/bindings/mfd/
Dsky81452.txt24 skyworks,phase-shift;
/linux-4.4.14/drivers/input/
Dinput-compat.h44 __u16 phase; member
Dff-core.c84 effect->u.periodic.phase = 0; in compat_effect()
/linux-4.4.14/Documentation/devicetree/bindings/mtd/
Ddavinci-nand.txt28 phase. These offset will be added to the base
34 phase. These offset will be added to the base
/linux-4.4.14/fs/f2fs/
Dgc.c674 int phase = 0; in gc_data_segment() local
695 if (phase == 0) { in gc_data_segment()
704 if (phase == 1) { in gc_data_segment()
711 if (phase == 2) { in gc_data_segment()
749 if (++phase < 4) in gc_data_segment()
/linux-4.4.14/Documentation/devicetree/bindings/eeprom/
Dat25.txt12 - spi-cpha : SPI shifted clock phase, as per spi-bus bindings.
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-bus-iio-frequency-ad952327 with their predefined phase offsets (out_altvoltageY_phase).
/linux-4.4.14/sound/usb/
Dendpoint.c154 ep->phase = (ep->phase & 0xffff) in snd_usb_endpoint_next_packet_size()
156 ret = min(ep->phase >> 16, ep->maxframesize); in snd_usb_endpoint_next_packet_size()
880 ep->phase = 0; in snd_usb_endpoint_set_params()
936 ep->phase = 0; in snd_usb_endpoint_start()
Dcard.h87 unsigned int phase; /* phase accumulator */ member
/linux-4.4.14/Documentation/cpu-freq/
Dcore.txt69 The phase is specified in the second argument to the notifier.
85 The second argument specifies the phase - CPUFREQ_PRECHANGE or
Dcpu-drivers.txt67 phase of cpu hotplug process.
70 called during CPU_DOWN_PREPARE phase of
/linux-4.4.14/Documentation/input/
Drotary-encoder.txt8 peripherals with two wires. The outputs are phase-shifted by 90 degrees
16 The phase diagram of these two outputs look like this:
Dff.txt28 initialisation phase. This happens for example with my "AVB Top Shot Pegasus".
Datarikbd.txt46 approximately 200 counts (phase changes or 'clicks') per inch of travel. The
284 In this mode, the specified number of mouse phase changes ('clicks') must
/linux-4.4.14/drivers/staging/lustre/lustre/mdc/
Dmdc_locks.c75 int it_open_error(int phase, struct lookup_intent *it) in it_open_error() argument
78 if (phase >= DISP_OPEN_LEASE) in it_open_error()
84 if (phase >= DISP_OPEN_OPEN) in it_open_error()
91 if (phase >= DISP_OPEN_CREATE) in it_open_error()
98 if (phase >= DISP_LOOKUP_EXECD) in it_open_error()
105 if (phase >= DISP_IT_EXECD) in it_open_error()
/linux-4.4.14/drivers/staging/lustre/lustre/include/
Dlustre_mdc.h175 int it_open_error(int phase, struct lookup_intent *it);
Dlustre_net.h1609 ptlrpc_phase2str(enum rq_phase phase) in ptlrpc_phase2str() argument
1611 switch (phase) { in ptlrpc_phase2str()
/linux-4.4.14/Documentation/hwmon/
Dibmpowernv16 for sensor devices during the __init phase and registers them with the 'hwmon'.
Dabituguru341 Default: 1 (the driver is still in the testing phase)
Dltc297871 LTC3880, LTC3882, LTC3886, and LTC3887 are dual output poly-phase step-down
73 LTC3883 is a single phase step-down DC/DC controller.
Dabituguru65 Default: 2 (the driver is still in the testing phase)
Ducd920025 UCD9248 are multi-rail, multi-phase synchronous buck digital PWM controllers
/linux-4.4.14/Documentation/scsi/
DChangeLog.sym53c8xx59 not requires extra cycles in DT DATA OUT phase.
162 data phase. Changes based on those made in the
318 in DATA IN phase with WIDE transfer when the byte count gets odd).
324 transfer, whatever a SWIDE is present (OVERRUN in DATA IN phase)
325 or the SODL is full (UNDERRUN in DATA out phase).
447 - Fix for big-endian in phase mismatch handling. (Michal Jaegermann)
465 - Reduce a bit the number of IO register reads for phase mismatch
472 with all features enabled including the phase mismatch handling
526 - Print out some message if phase mismatch is handled from SCRIPTS.
559 driver to safely enable hardware phase mismatch with 896 rev. 1.
[all …]
Dncr53c8xx.txt103 available since the 810A and hardware phase mismatch available with the
206 The 896 and the 895A allows handling of the phase mismatch context from
207 SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor
396 number of script interruptions (phase mismatch)
501 phase: print information on script interruptions
1217 addressing logic when the DATA IN phase is entered and so prevents the bug
1218 from being triggered for the first SCSI MOVE of the phase. This work-around
1231 when the SCSI DATA IN phase is reentered after a phase mismatch.
DChangeLog.ncr53c8xx368 - Add a check of the MSG_OUT phase after Selection with ATN.
392 context on phase mismatch.
426 phase on reselection. This should have the vertue to process
Daic7xxx.txt228 "scsi0: Data Parity Error Detected during address or write data phase"
235 phase
Dsym53c8xx_2.txt183 Newer chips (see above) allows handling of the phase mismatch context from
184 SCRIPTS (avoids the phase mismatch interrupt that stops the SCSI processor
351 phase: print information on script interruptions
/linux-4.4.14/drivers/net/ethernet/brocade/bna/
Dbfi.h247 u8 phase; member
253 u8 phase;
Dbfa_ioc.c1342 drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase && in bfa_ioc_fw_ver_compatible()
1361 if (fwhdr->fwver.phase == 0 && in fwhdr_is_ga()
1393 if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase) in bfa_ioc_fw_ver_patch_cmp()
1395 else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase) in bfa_ioc_fw_ver_patch_cmp()
/linux-4.4.14/Documentation/i2c/
Dslave-interface154 It is good behaviour to always ACK the address phase, so the master knows if a
156 state being busy is troublesome. SMBus demands to always ACK the address phase,
160 phase.
Dfault-codes85 Returned by I2C adapters to indicate that the address phase
/linux-4.4.14/drivers/scsi/be2iscsi/
Dbe_cmds.h263 u8 phase[2]; /* dword 2 */ member
285 u32 phase; member
649 __le32 phase; member
1012 u32 phase; member
/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Dapll.txt7 (reference clock and bypass clock), with analog phase locked
Ddpll.txt7 (reference clock and bypass clock), with digital phase locked
/linux-4.4.14/include/linux/
Dclk.h148 static inline long clk_set_phase(struct clk *clk, int phase) in clk_set_phase() argument
Disdnif.h255 __u8 phase; member
Dparport.h184 volatile enum ieee1284_phase phase; member
/linux-4.4.14/Documentation/devicetree/bindings/net/can/
Dsja1000.txt25 <0x0> : bi-phase output mode
/linux-4.4.14/drivers/scsi/aacraid/
Dlinit.c258 cmd->SCp.phase = AAC_OWNER_LOWLEVEL; in aac_queuecommand()
556 cmd->SCp.phase = AAC_OWNER_ERROR_HANDLER; in aac_eh_abort()
571 command->SCp.phase = AAC_OWNER_ERROR_HANDLER; in aac_eh_abort()
601 cmd->SCp.phase = AAC_OWNER_ERROR_HANDLER; in aac_eh_reset()
621 (command->SCp.phase == AAC_OWNER_FIRMWARE)) { in aac_eh_reset()
Daachba.c329 scsicmd->SCp.phase = AAC_OWNER_MIDLEVEL; in aac_valid_context()
583 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in aac_get_container_name()
701 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in _aac_probe_container1()
742 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in _aac_probe_container()
1065 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in aac_get_container_serial()
1968 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in aac_read()
2071 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in aac_write()
2148 if (cmd->SCp.phase == AAC_OWNER_FIRMWARE) { in aac_synchronize()
2239 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in aac_synchronize()
2319 scsicmd->SCp.phase = AAC_OWNER_FIRMWARE; in aac_start_stop()
[all …]
Dcommsup.c1418 if (command->SCp.phase == AAC_OWNER_FIRMWARE) { in _aac_reset_adapter()
1430 command->SCp.phase = AAC_OWNER_ERROR_HANDLER; in _aac_reset_adapter()
1475 if (command->SCp.phase == AAC_OWNER_FIRMWARE) { in aac_reset_adapter()
/linux-4.4.14/drivers/infiniband/hw/ocrdma/
Docrdma.h319 u32 phase; member
503 return (cqe_valid == cq->phase); in is_cqe_valid()
/linux-4.4.14/include/uapi/linux/
Dinput.h380 __u16 phase; member
/linux-4.4.14/Documentation/x86/
Dearly-microcode.txt5 Kernel can update microcode in early phase of boot time. Loading microcode early
/linux-4.4.14/Documentation/RCU/
DwhatisRCU.txt51 "reclamation" phases. The removal phase removes references to data items
54 The reason that it is safe to run the removal phase concurrently with
57 partially updated reference. The reclamation phase does the work of reclaiming
59 removal phase. Because reclaiming data items can disrupt any readers
60 concurrently referencing those data items, the reclamation phase must
64 updater to perform the removal phase immediately, and to defer the
65 reclamation phase until all readers active during the removal phase have
68 during the removal phase need be considered, because any reader starting
69 after the removal phase will be unable to gain a reference to the removed
70 data items, and therefore cannot be disrupted by the reclamation phase.
/linux-4.4.14/arch/arm/kvm/
Dinit.S128 @ End of init phase-1
/linux-4.4.14/include/scsi/
Dscsi_cmnd.h53 volatile int phase; member
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Didle-states.txt63 PREP: Preparation phase before committing the hardware to idle mode
67 goes back to EXEC. This phase is optional. If not abortable,
68 this should be included in the ENTRY phase instead.
93 (ie wake-up) that causes the CPU to return to the EXEC phase.
315 where the duration of PREP phase (see diagram 1,
/linux-4.4.14/Documentation/acpi/apei/
Deinj.txt107 to 1 skips the trigger phase, which *may* allow the user to cause the
111 includes in the trigger phase.
/linux-4.4.14/fs/cifs/
Dsmb2pdu.c589 __le32 phase = NtLmNegotiate; /* NTLMSSP, if needed, is multistage */ in SMB2_sess_setup() local
625 if (phase == NtLmChallenge) in SMB2_sess_setup()
626 phase = NtLmAuthenticate; /* if ntlmssp, now final phase */ in SMB2_sess_setup()
692 } else if (phase == NtLmNegotiate) { /* if not krb5 must be ntlmssp */ in SMB2_sess_setup()
717 } else if (phase == NtLmAuthenticate) { in SMB2_sess_setup()
770 if (phase != NtLmNegotiate) { in SMB2_sess_setup()
783 phase = NtLmChallenge; /* process ntlmssp challenge */ in SMB2_sess_setup()
807 if ((phase == NtLmChallenge) && (rc == 0)) in SMB2_sess_setup()
/linux-4.4.14/Documentation/filesystems/
Dsharedsubtree.txt899 1. prepare phase.
903 Prepare phase:
915 If this phase is successful, there should be 'n' new
917 source tree. Go to the commit phase
923 if any memory allocations fail, go to the abort phase.
925 Commit phase
929 Abort phase
/linux-4.4.14/drivers/scsi/aic94xx/
Daic94xx_tmf.c160 enum clear_nexus_phase phase) in asd_clear_nexus_I_T() argument
166 switch (phase) { in asd_clear_nexus_I_T()
/linux-4.4.14/drivers/regulator/
DKconfig207 The DA9210 is a multi-phase synchronous step down
218 The DA9211/DA9212/DA9213/DA9214/DA9215 is a multi-phase synchronous
379 The MAXIM MAX8973 high-efficiency. three phase, DC-DC step-down
381 phase operates at a 2MHz fixed frequency with a 120 deg shift
382 from the adjacent phase, allowing the use of small magnetic component.
/linux-4.4.14/arch/arm/boot/dts/
Drk3288-veyron-sdmmc.dtsi119 rockchip,default-sample-phase = <90>;
Drk3288-veyron.dtsi152 rockchip,default-sample-phase = <158>;
Dsocfpga.dtsi452 clk-phase = <0 135>;
/linux-4.4.14/drivers/media/pci/pt1/
Dpt1.c231 int phase; in pt1_enable_ram() local
233 phase = pt1->pdev->device == 0x211a ? 128 : 166; in pt1_enable_ram()
234 for (i = 0; i < phase; i++) { in pt1_enable_ram()
/linux-4.4.14/drivers/clk/
Dclk.c66 int phase; member
1895 clk->core->phase = degrees; in clk_set_phase()
1908 ret = core->phase; in clk_core_get_phase()
2132 (u32 *)&core->phase); in clk_debug_create_one()
2419 core->phase = core->ops->get_phase(core->hw); in __clk_init()
2421 core->phase = 0; in __clk_init()
/linux-4.4.14/Documentation/usb/
Dauthorization.txt36 devices (this is so because we need to do an authentication phase
/linux-4.4.14/Documentation/vm/
Dpage_owner.txt56 pages are investigated and marked as allocated in initialization phase.
/linux-4.4.14/drivers/net/phy/
Dmdio-octeon.c55 OCT_MDIO_BITFIELD_FIELD(u64 phase:8,
/linux-4.4.14/drivers/scsi/fnic/
Dfnic.h96 #define CMD_STATE(Cmnd) ((Cmnd)->SCp.phase)
/linux-4.4.14/drivers/scsi/bfa/
Dbfi.h339 uint8_t phase; member
345 uint8_t phase;
Dbfa_ioc.c1564 drv_fwhdr->fwver.phase == fwhdr_to_cmp->fwver.phase && in bfa_ioc_fw_ver_compatible()
1583 if (fwhdr->fwver.phase == 0 && in fwhdr_is_ga()
1621 if (fwhdr_to_cmp->fwver.phase > base_fwhdr->fwver.phase) in bfa_ioc_fw_ver_patch_cmp()
1623 else if (fwhdr_to_cmp->fwver.phase < base_fwhdr->fwver.phase) in bfa_ioc_fw_ver_patch_cmp()
/linux-4.4.14/drivers/hid/usbhid/
Dhid-pidff.c357 pidff_set(&pidff->set_periodic[PID_PHASE], effect->u.periodic.phase); in pidff_set_periodic_report()
373 effect->u.periodic.phase != old->u.periodic.phase || in pidff_needs_set_periodic()
/linux-4.4.14/Documentation/security/
DIMA-templates.txt41 It is during this phase that the advantages of the new architecture are
/linux-4.4.14/Documentation/arm/
DPorting62 boot phase, virtual address PAGE_OFFSET will be mapped to physical
Dkernel_user_helpers.txt73 startup phase of a program.
/linux-4.4.14/Documentation/frv/
Datomic-ops.txt84 Then it does the load. Note that the final phase of step (1) is done at the same time as the
/linux-4.4.14/drivers/nvme/host/
Dpci.c949 u16 head, phase; in __nvme_process_cq() local
952 phase = nvmeq->cq_phase; in __nvme_process_cq()
958 if ((le16_to_cpu(cqe.status) & 1) != phase) in __nvme_process_cq()
963 phase = !phase; in __nvme_process_cq()
977 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) in __nvme_process_cq()
983 nvmeq->cq_phase = phase; in __nvme_process_cq()
/linux-4.4.14/drivers/net/wireless/ath/ath9k/
Dar9003_calib.c894 int magnitude, phase; in ar9003_hw_tx_iq_cal_outlier_detection() local
944 phase = coeff->phs_coeff[i][im][0]; in ar9003_hw_tx_iq_cal_outlier_detection()
947 (phase & 0x7f) | ((magnitude & 0x7f) << 7); in ar9003_hw_tx_iq_cal_outlier_detection()
/linux-4.4.14/Documentation/sound/alsa/
DChannel-Mapping-API.txt128 SNDRV_CHMAP_PHASE_INVERSE indicates the channel is phase inverted,
DREADME.maya4470 phase.h
/linux-4.4.14/tools/perf/Documentation/
Dperf-stat.txt163 filter out the startup phase of the program, which is often very different.
Dperf-record.txt279 filter out the startup phase of the program, which is often very different.
/linux-4.4.14/Documentation/pcmcia/
Ddriver-changes.txt67 configuration options. During a driver's probe() phase, one doesn't need
/linux-4.4.14/Documentation/spi/
Dspidev86 (clock polarity, idle high iff this is set) or SPI_CPHA (clock phase,
/linux-4.4.14/arch/arm/mach-omap2/
Dsram242x.S67 orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
Dsram243x.S67 orr r10, r10, #0x2 @ 90 degree phase for all below 133MHz
/linux-4.4.14/drivers/scsi/pm8001/
Dpm8001_sas.h594 u32 phase;/*ret code phase*/ member
/linux-4.4.14/Documentation/DocBook/
Dkernel-api.xml.db743 API-clk-set-phase
744 API-clk-get-phase
/linux-4.4.14/drivers/media/usb/pwc/
Dphilips.txt136 and the phase of the moon (i.e. it can be random). With this option you
/linux-4.4.14/Documentation/sysctl/
Dnet.txt244 that address (or network number for phase 1 networks), and the status of the
/linux-4.4.14/drivers/net/ethernet/emulex/benet/
Dbe_cmds.h340 u8 phase[2]; /* dword 2*/ member
1114 u32 phase; member
/linux-4.4.14/Documentation/networking/dsa/
Ddsa.txt336 prepare/abort/commit phases are often simplified into a prepare phase which
338 phase which applies the changes.

12