Lines Matching refs:phase

59 	  not requires extra cycles in DT DATA OUT phase.
162 	  data phase.  Changes based on those made in the
318 	  in DATA IN phase with WIDE transfer when the byte count gets odd).
324 	  transfer, whatever a SWIDE is present (OVERRUN in DATA IN phase) 
325 	  or the SODL is full (UNDERRUN in DATA out phase).
447 	- Fix for big-endian in phase mismatch handling. (Michal Jaegermann)
465 	- Reduce a bit the number of IO register reads for phase mismatch 
472 	  with all features enabled including the phase mismatch handling 
526 	- Print out some message if phase mismatch is handled from SCRIPTS.
559 	  driver to safely enable hardware phase mismatch with 896 rev. 1.
591 	- Interrupt the SCRIPTS if a device does not go to MSG OUT phase after