Searched refs:mux (Results 1 - 200 of 603) sorted by relevance

1234

/linux-4.4.14/drivers/i2c/muxes/
H A Di2c-mux-reg.c14 #include <linux/i2c-mux.h>
19 #include <linux/platform_data/i2c-mux-reg.h>
29 static int i2c_mux_reg_set(const struct regmux *mux, unsigned int chan_id) i2c_mux_reg_set() argument
31 if (!mux->data.reg) i2c_mux_reg_set()
40 switch (mux->data.reg_size) { i2c_mux_reg_set()
42 if (mux->data.little_endian) i2c_mux_reg_set()
43 iowrite32(chan_id, mux->data.reg); i2c_mux_reg_set()
45 iowrite32be(chan_id, mux->data.reg); i2c_mux_reg_set()
46 if (!mux->data.write_only) i2c_mux_reg_set()
47 ioread32(mux->data.reg); i2c_mux_reg_set()
50 if (mux->data.little_endian) i2c_mux_reg_set()
51 iowrite16(chan_id, mux->data.reg); i2c_mux_reg_set()
53 iowrite16be(chan_id, mux->data.reg); i2c_mux_reg_set()
54 if (!mux->data.write_only) i2c_mux_reg_set()
55 ioread16(mux->data.reg); i2c_mux_reg_set()
58 iowrite8(chan_id, mux->data.reg); i2c_mux_reg_set()
59 if (!mux->data.write_only) i2c_mux_reg_set()
60 ioread8(mux->data.reg); i2c_mux_reg_set()
70 struct regmux *mux = data; i2c_mux_reg_select() local
72 return i2c_mux_reg_set(mux, chan); i2c_mux_reg_select()
78 struct regmux *mux = data; i2c_mux_reg_deselect() local
80 if (mux->data.idle_in_use) i2c_mux_reg_deselect()
81 return i2c_mux_reg_set(mux, mux->data.idle); i2c_mux_reg_deselect()
87 static int i2c_mux_reg_probe_dt(struct regmux *mux, i2c_mux_reg_probe_dt() argument
110 mux->parent = adapter; i2c_mux_reg_probe_dt()
111 mux->data.parent = i2c_adapter_id(adapter); i2c_mux_reg_probe_dt()
114 mux->data.n_values = of_get_child_count(np); i2c_mux_reg_probe_dt()
116 mux->data.little_endian = true; i2c_mux_reg_probe_dt()
118 mux->data.little_endian = false; i2c_mux_reg_probe_dt()
122 mux->data.little_endian = true; i2c_mux_reg_probe_dt()
125 mux->data.little_endian = false; i2c_mux_reg_probe_dt()
131 mux->data.write_only = true; i2c_mux_reg_probe_dt()
133 mux->data.write_only = false; i2c_mux_reg_probe_dt()
136 sizeof(*mux->data.values) * mux->data.n_values, i2c_mux_reg_probe_dt()
147 mux->data.values = values;
149 if (!of_property_read_u32(np, "idle-state", &mux->data.idle))
150 mux->data.idle_in_use = true;
154 mux->data.reg_size = resource_size(&res);
155 mux->data.reg = devm_ioremap_resource(&pdev->dev, &res);
156 if (IS_ERR(mux->data.reg))
157 return PTR_ERR(mux->data.reg);
163 static int i2c_mux_reg_probe_dt(struct regmux *mux, i2c_mux_reg_probe_dt() argument
172 struct regmux *mux; i2c_mux_reg_probe() local
179 mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); i2c_mux_reg_probe()
180 if (!mux) i2c_mux_reg_probe()
183 platform_set_drvdata(pdev, mux); i2c_mux_reg_probe()
186 memcpy(&mux->data, dev_get_platdata(&pdev->dev), i2c_mux_reg_probe()
187 sizeof(mux->data)); i2c_mux_reg_probe()
189 parent = i2c_get_adapter(mux->data.parent); i2c_mux_reg_probe()
193 mux->parent = parent; i2c_mux_reg_probe()
195 ret = i2c_mux_reg_probe_dt(mux, pdev); i2c_mux_reg_probe()
202 if (!mux->data.reg) { i2c_mux_reg_probe()
206 mux->data.reg_size = resource_size(res); i2c_mux_reg_probe()
207 mux->data.reg = devm_ioremap_resource(&pdev->dev, res); i2c_mux_reg_probe()
208 if (IS_ERR(mux->data.reg)) i2c_mux_reg_probe()
209 return PTR_ERR(mux->data.reg); i2c_mux_reg_probe()
212 if (mux->data.reg_size != 4 && mux->data.reg_size != 2 && i2c_mux_reg_probe()
213 mux->data.reg_size != 1) { i2c_mux_reg_probe()
218 mux->adap = devm_kzalloc(&pdev->dev, i2c_mux_reg_probe()
219 sizeof(*mux->adap) * mux->data.n_values, i2c_mux_reg_probe()
221 if (!mux->adap) { i2c_mux_reg_probe()
226 if (mux->data.idle_in_use) i2c_mux_reg_probe()
231 for (i = 0; i < mux->data.n_values; i++) { i2c_mux_reg_probe()
232 nr = mux->data.base_nr ? (mux->data.base_nr + i) : 0; i2c_mux_reg_probe()
233 class = mux->data.classes ? mux->data.classes[i] : 0; i2c_mux_reg_probe()
235 mux->adap[i] = i2c_add_mux_adapter(mux->parent, &pdev->dev, mux, i2c_mux_reg_probe()
236 nr, mux->data.values[i], i2c_mux_reg_probe()
239 if (!mux->adap[i]) { i2c_mux_reg_probe()
246 dev_dbg(&pdev->dev, "%d port mux on %s adapter\n", i2c_mux_reg_probe()
247 mux->data.n_values, mux->parent->name); i2c_mux_reg_probe()
253 i2c_del_mux_adapter(mux->adap[i - 1]); i2c_mux_reg_probe()
260 struct regmux *mux = platform_get_drvdata(pdev); i2c_mux_reg_remove() local
263 for (i = 0; i < mux->data.n_values; i++) i2c_mux_reg_remove()
264 i2c_del_mux_adapter(mux->adap[i]); i2c_mux_reg_remove()
266 i2c_put_adapter(mux->parent); i2c_mux_reg_remove()
272 { .compatible = "i2c-mux-reg", },
281 .name = "i2c-mux-reg",
290 MODULE_ALIAS("platform:i2c-mux-reg");
H A Di2c-mux-pinctrl.c20 #include <linux/i2c-mux.h>
23 #include <linux/i2c-mux-pinctrl.h>
41 struct i2c_mux_pinctrl *mux = data; i2c_mux_pinctrl_select() local
43 return pinctrl_select_state(mux->pinctrl, mux->states[chan]); i2c_mux_pinctrl_select()
49 struct i2c_mux_pinctrl *mux = data; i2c_mux_pinctrl_deselect() local
51 return pinctrl_select_state(mux->pinctrl, mux->state_idle); i2c_mux_pinctrl_deselect()
55 static int i2c_mux_pinctrl_parse_dt(struct i2c_mux_pinctrl *mux, i2c_mux_pinctrl_parse_dt() argument
66 mux->pdata = devm_kzalloc(&pdev->dev, sizeof(*mux->pdata), GFP_KERNEL); i2c_mux_pinctrl_parse_dt()
67 if (!mux->pdata) { i2c_mux_pinctrl_parse_dt()
68 dev_err(mux->dev, i2c_mux_pinctrl_parse_dt()
75 dev_err(mux->dev, "Cannot parse pinctrl-names: %d\n", i2c_mux_pinctrl_parse_dt()
80 mux->pdata->pinctrl_states = devm_kzalloc(&pdev->dev, i2c_mux_pinctrl_parse_dt()
81 sizeof(*mux->pdata->pinctrl_states) * num_names, i2c_mux_pinctrl_parse_dt()
83 if (!mux->pdata->pinctrl_states) { i2c_mux_pinctrl_parse_dt()
84 dev_err(mux->dev, "Cannot allocate pinctrl_states\n"); i2c_mux_pinctrl_parse_dt()
90 &mux->pdata->pinctrl_states[mux->pdata->bus_count]); i2c_mux_pinctrl_parse_dt()
92 dev_err(mux->dev, "Cannot parse pinctrl-names: %d\n", i2c_mux_pinctrl_parse_dt()
96 if (!strcmp(mux->pdata->pinctrl_states[mux->pdata->bus_count], i2c_mux_pinctrl_parse_dt()
99 dev_err(mux->dev, "idle state must be last\n"); i2c_mux_pinctrl_parse_dt()
102 mux->pdata->pinctrl_state_idle = "idle"; i2c_mux_pinctrl_parse_dt()
104 mux->pdata->bus_count++; i2c_mux_pinctrl_parse_dt()
110 dev_err(mux->dev, "Cannot parse i2c-parent\n"); i2c_mux_pinctrl_parse_dt()
116 dev_err(mux->dev, "Cannot find parent bus\n"); i2c_mux_pinctrl_parse_dt()
119 mux->pdata->parent_bus_num = i2c_adapter_id(adapter); i2c_mux_pinctrl_parse_dt()
125 static inline int i2c_mux_pinctrl_parse_dt(struct i2c_mux_pinctrl *mux, i2c_mux_pinctrl_parse_dt() argument
134 struct i2c_mux_pinctrl *mux; i2c_mux_pinctrl_probe() local
138 mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); i2c_mux_pinctrl_probe()
139 if (!mux) { i2c_mux_pinctrl_probe()
144 platform_set_drvdata(pdev, mux); i2c_mux_pinctrl_probe()
146 mux->dev = &pdev->dev; i2c_mux_pinctrl_probe()
148 mux->pdata = dev_get_platdata(&pdev->dev); i2c_mux_pinctrl_probe()
149 if (!mux->pdata) { i2c_mux_pinctrl_probe()
150 ret = i2c_mux_pinctrl_parse_dt(mux, pdev); i2c_mux_pinctrl_probe()
154 if (!mux->pdata) { i2c_mux_pinctrl_probe()
160 mux->states = devm_kzalloc(&pdev->dev, i2c_mux_pinctrl_probe()
161 sizeof(*mux->states) * mux->pdata->bus_count, i2c_mux_pinctrl_probe()
163 if (!mux->states) { i2c_mux_pinctrl_probe()
169 mux->busses = devm_kzalloc(&pdev->dev, i2c_mux_pinctrl_probe()
170 sizeof(*mux->busses) * mux->pdata->bus_count, i2c_mux_pinctrl_probe()
172 if (!mux->busses) { i2c_mux_pinctrl_probe()
178 mux->pinctrl = devm_pinctrl_get(&pdev->dev); i2c_mux_pinctrl_probe()
179 if (IS_ERR(mux->pinctrl)) { i2c_mux_pinctrl_probe()
180 ret = PTR_ERR(mux->pinctrl); i2c_mux_pinctrl_probe()
184 for (i = 0; i < mux->pdata->bus_count; i++) { i2c_mux_pinctrl_probe()
185 mux->states[i] = pinctrl_lookup_state(mux->pinctrl, i2c_mux_pinctrl_probe()
186 mux->pdata->pinctrl_states[i]); i2c_mux_pinctrl_probe()
187 if (IS_ERR(mux->states[i])) { i2c_mux_pinctrl_probe()
188 ret = PTR_ERR(mux->states[i]); i2c_mux_pinctrl_probe()
191 mux->pdata->pinctrl_states[i], ret); i2c_mux_pinctrl_probe()
195 if (mux->pdata->pinctrl_state_idle) { i2c_mux_pinctrl_probe()
196 mux->state_idle = pinctrl_lookup_state(mux->pinctrl, i2c_mux_pinctrl_probe()
197 mux->pdata->pinctrl_state_idle); i2c_mux_pinctrl_probe()
198 if (IS_ERR(mux->state_idle)) { i2c_mux_pinctrl_probe()
199 ret = PTR_ERR(mux->state_idle); i2c_mux_pinctrl_probe()
202 mux->pdata->pinctrl_state_idle, ret); i2c_mux_pinctrl_probe()
211 mux->parent = i2c_get_adapter(mux->pdata->parent_bus_num); i2c_mux_pinctrl_probe()
212 if (!mux->parent) { i2c_mux_pinctrl_probe()
214 mux->pdata->parent_bus_num); i2c_mux_pinctrl_probe()
219 for (i = 0; i < mux->pdata->bus_count; i++) { i2c_mux_pinctrl_probe()
220 u32 bus = mux->pdata->base_bus_num ? i2c_mux_pinctrl_probe()
221 (mux->pdata->base_bus_num + i) : 0; i2c_mux_pinctrl_probe()
223 mux->busses[i] = i2c_add_mux_adapter(mux->parent, &pdev->dev, i2c_mux_pinctrl_probe()
224 mux, bus, i, 0, i2c_mux_pinctrl_probe()
227 if (!mux->busses[i]) { i2c_mux_pinctrl_probe()
238 i2c_del_mux_adapter(mux->busses[i - 1]); i2c_mux_pinctrl_probe()
239 i2c_put_adapter(mux->parent); i2c_mux_pinctrl_probe()
246 struct i2c_mux_pinctrl *mux = platform_get_drvdata(pdev); i2c_mux_pinctrl_remove() local
249 for (i = 0; i < mux->pdata->bus_count; i++) i2c_mux_pinctrl_remove()
250 i2c_del_mux_adapter(mux->busses[i]); i2c_mux_pinctrl_remove()
252 i2c_put_adapter(mux->parent); i2c_mux_pinctrl_remove()
259 { .compatible = "i2c-mux-pinctrl", },
267 .name = "i2c-mux-pinctrl",
278 MODULE_ALIAS("platform:i2c-mux-pinctrl");
H A Di2c-mux-gpio.c12 #include <linux/i2c-mux.h>
13 #include <linux/i2c-mux-gpio.h>
27 static void i2c_mux_gpio_set(const struct gpiomux *mux, unsigned val) i2c_mux_gpio_set() argument
31 for (i = 0; i < mux->data.n_gpios; i++) i2c_mux_gpio_set()
32 gpio_set_value_cansleep(mux->gpio_base + mux->data.gpios[i], i2c_mux_gpio_set()
38 struct gpiomux *mux = data; i2c_mux_gpio_select() local
40 i2c_mux_gpio_set(mux, chan); i2c_mux_gpio_select()
47 struct gpiomux *mux = data; i2c_mux_gpio_deselect() local
49 i2c_mux_gpio_set(mux, mux->data.idle); i2c_mux_gpio_deselect()
61 static int i2c_mux_gpio_probe_dt(struct gpiomux *mux, i2c_mux_gpio_probe_dt() argument
83 mux->data.parent = i2c_adapter_id(adapter); i2c_mux_gpio_probe_dt()
86 mux->data.n_values = of_get_child_count(np); i2c_mux_gpio_probe_dt()
89 sizeof(*mux->data.values) * mux->data.n_values, i2c_mux_gpio_probe_dt()
100 mux->data.values = values;
102 if (of_property_read_u32(np, "idle-state", &mux->data.idle))
103 mux->data.idle = I2C_MUX_GPIO_NO_IDLE;
105 mux->data.n_gpios = of_gpio_named_count(np, "mux-gpios");
106 if (mux->data.n_gpios < 0) {
107 dev_err(&pdev->dev, "Missing mux-gpios property in the DT.\n");
112 sizeof(*mux->data.gpios) * mux->data.n_gpios, GFP_KERNEL);
118 for (i = 0; i < mux->data.n_gpios; i++) {
119 ret = of_get_named_gpio(np, "mux-gpios", i);
125 mux->data.gpios = gpios;
130 static int i2c_mux_gpio_probe_dt(struct gpiomux *mux, i2c_mux_gpio_probe_dt() argument
139 struct gpiomux *mux; i2c_mux_gpio_probe() local
145 mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL); i2c_mux_gpio_probe()
146 if (!mux) { i2c_mux_gpio_probe()
151 platform_set_drvdata(pdev, mux); i2c_mux_gpio_probe()
154 ret = i2c_mux_gpio_probe_dt(mux, pdev); i2c_mux_gpio_probe()
158 memcpy(&mux->data, dev_get_platdata(&pdev->dev), i2c_mux_gpio_probe()
159 sizeof(mux->data)); i2c_mux_gpio_probe()
166 if (mux->data.gpio_chip) { i2c_mux_gpio_probe()
169 gpio = gpiochip_find(mux->data.gpio_chip, i2c_mux_gpio_probe()
179 parent = i2c_get_adapter(mux->data.parent); i2c_mux_gpio_probe()
183 mux->parent = parent; i2c_mux_gpio_probe()
184 mux->gpio_base = gpio_base; i2c_mux_gpio_probe()
186 mux->adap = devm_kzalloc(&pdev->dev, i2c_mux_gpio_probe()
187 sizeof(*mux->adap) * mux->data.n_values, i2c_mux_gpio_probe()
189 if (!mux->adap) { i2c_mux_gpio_probe()
195 if (mux->data.idle != I2C_MUX_GPIO_NO_IDLE) { i2c_mux_gpio_probe()
196 initial_state = mux->data.idle; i2c_mux_gpio_probe()
199 initial_state = mux->data.values[0]; i2c_mux_gpio_probe()
203 for (i = 0; i < mux->data.n_gpios; i++) { i2c_mux_gpio_probe()
204 ret = gpio_request(gpio_base + mux->data.gpios[i], "i2c-mux-gpio"); i2c_mux_gpio_probe()
207 mux->data.gpios[i]); i2c_mux_gpio_probe()
211 ret = gpio_direction_output(gpio_base + mux->data.gpios[i], i2c_mux_gpio_probe()
216 mux->data.gpios[i]); i2c_mux_gpio_probe()
222 for (i = 0; i < mux->data.n_values; i++) { i2c_mux_gpio_probe()
223 u32 nr = mux->data.base_nr ? (mux->data.base_nr + i) : 0; i2c_mux_gpio_probe()
224 unsigned int class = mux->data.classes ? mux->data.classes[i] : 0; i2c_mux_gpio_probe()
226 mux->adap[i] = i2c_add_mux_adapter(parent, &pdev->dev, mux, nr, i2c_mux_gpio_probe()
227 mux->data.values[i], class, i2c_mux_gpio_probe()
229 if (!mux->adap[i]) { i2c_mux_gpio_probe()
236 dev_info(&pdev->dev, "%d port mux on %s adapter\n", i2c_mux_gpio_probe()
237 mux->data.n_values, parent->name); i2c_mux_gpio_probe()
243 i2c_del_mux_adapter(mux->adap[i - 1]); i2c_mux_gpio_probe()
244 i = mux->data.n_gpios; i2c_mux_gpio_probe()
247 gpio_free(gpio_base + mux->data.gpios[i - 1]); i2c_mux_gpio_probe()
256 struct gpiomux *mux = platform_get_drvdata(pdev); i2c_mux_gpio_remove() local
259 for (i = 0; i < mux->data.n_values; i++) i2c_mux_gpio_remove()
260 i2c_del_mux_adapter(mux->adap[i]); i2c_mux_gpio_remove()
262 for (i = 0; i < mux->data.n_gpios; i++) i2c_mux_gpio_remove()
263 gpio_free(mux->gpio_base + mux->data.gpios[i]); i2c_mux_gpio_remove()
265 i2c_put_adapter(mux->parent); i2c_mux_gpio_remove()
271 { .compatible = "i2c-mux-gpio", },
280 .name = "i2c-mux-gpio",
290 MODULE_ALIAS("platform:i2c-mux-gpio");
H A Di2c-mux-pca954x.c17 * mux can select only one sub-bus at a time; a switch can select any
41 #include <linux/i2c-mux.h>
121 /* Write to mux register. Don't use i2c_transfer()/i2c_smbus_xfer()
206 /* Get the mux out of reset if a reset GPIO is specified. */ pca954x_probe()
211 /* Write the mux register at addr to verify pca954x_probe()
212 * that the mux is in fact present. This also pca954x_probe()
213 * initializes the mux to disconnected state. pca954x_probe()
224 of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); pca954x_probe()
261 ? "mux" : "switch", client->name); pca954x_probe()
312 MODULE_DESCRIPTION("PCA954x I2C mux/switch driver");
/linux-4.4.14/drivers/clk/ti/
H A Dmux.c33 struct clk_mux *mux = to_clk_mux(hw); ti_clk_mux_get_parent() local
38 * FIXME need a mux-specific flag to determine if val is bitwise or ti_clk_mux_get_parent()
44 val = ti_clk_ll_ops->clk_readl(mux->reg) >> mux->shift; ti_clk_mux_get_parent()
45 val &= mux->mask; ti_clk_mux_get_parent()
47 if (mux->table) { ti_clk_mux_get_parent()
51 if (mux->table[i] == val) ti_clk_mux_get_parent()
56 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) ti_clk_mux_get_parent()
59 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) ti_clk_mux_get_parent()
70 struct clk_mux *mux = to_clk_mux(hw); ti_clk_mux_set_parent() local
73 if (mux->table) { ti_clk_mux_set_parent()
74 index = mux->table[index]; ti_clk_mux_set_parent()
76 if (mux->flags & CLK_MUX_INDEX_BIT) ti_clk_mux_set_parent()
79 if (mux->flags & CLK_MUX_INDEX_ONE) ti_clk_mux_set_parent()
83 if (mux->flags & CLK_MUX_HIWORD_MASK) { ti_clk_mux_set_parent()
84 val = mux->mask << (mux->shift + 16); ti_clk_mux_set_parent()
86 val = ti_clk_ll_ops->clk_readl(mux->reg); ti_clk_mux_set_parent()
87 val &= ~(mux->mask << mux->shift); ti_clk_mux_set_parent()
89 val |= index << mux->shift; ti_clk_mux_set_parent()
90 ti_clk_ll_ops->clk_writel(val, mux->reg); ti_clk_mux_set_parent()
107 struct clk_mux *mux; _register_mux() local
111 /* allocate the mux */ _register_mux()
112 mux = kzalloc(sizeof(*mux), GFP_KERNEL); _register_mux()
113 if (!mux) { _register_mux()
114 pr_err("%s: could not allocate mux clk\n", __func__); _register_mux()
125 mux->reg = reg; _register_mux()
126 mux->shift = shift; _register_mux()
127 mux->mask = mask; _register_mux()
128 mux->flags = clk_mux_flags; _register_mux()
129 mux->table = table; _register_mux()
130 mux->hw.init = &init; _register_mux()
132 clk = clk_register(dev, &mux->hw); _register_mux()
135 kfree(mux); _register_mux()
142 struct ti_clk_mux *mux; ti_clk_register_mux() local
151 mux = setup->data; ti_clk_register_mux()
154 mask = mux->num_parents; ti_clk_register_mux()
155 if (!(mux->flags & CLKF_INDEX_STARTS_AT_ONE)) ti_clk_register_mux()
159 reg_setup->index = mux->module; ti_clk_register_mux()
160 reg_setup->offset = mux->reg; ti_clk_register_mux()
162 if (mux->flags & CLKF_INDEX_STARTS_AT_ONE) ti_clk_register_mux()
165 if (mux->flags & CLKF_SET_RATE_PARENT) ti_clk_register_mux()
168 return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, ti_clk_register_mux()
169 flags, (void __iomem *)reg, mux->bit_shift, mask, ti_clk_register_mux()
174 * of_mux_clk_setup - Setup function for simple mux rate clock
192 pr_err("mux-clock %s must have parents\n", node->name); of_mux_clk_setup()
230 CLK_OF_DECLARE(mux_clk, "ti,mux-clock", of_mux_clk_setup);
234 struct clk_mux *mux; ti_clk_build_component_mux() local
241 mux = kzalloc(sizeof(*mux), GFP_KERNEL); ti_clk_build_component_mux()
242 if (!mux) ti_clk_build_component_mux()
245 reg = (struct clk_omap_reg *)&mux->reg; ti_clk_build_component_mux()
247 mux->shift = setup->bit_shift; ti_clk_build_component_mux()
253 mux->flags |= CLK_MUX_INDEX_ONE; ti_clk_build_component_mux()
257 mux->mask = num_parents - 1; ti_clk_build_component_mux()
258 mux->mask = (1 << fls(mux->mask)) - 1; ti_clk_build_component_mux()
260 return &mux->hw; ti_clk_build_component_mux()
265 struct clk_mux *mux; of_ti_composite_mux_clk_setup() local
269 mux = kzalloc(sizeof(*mux), GFP_KERNEL); of_ti_composite_mux_clk_setup()
270 if (!mux) of_ti_composite_mux_clk_setup()
273 mux->reg = ti_clk_get_reg_addr(node, 0); of_ti_composite_mux_clk_setup()
275 if (IS_ERR(mux->reg)) of_ti_composite_mux_clk_setup()
279 mux->shift = val; of_ti_composite_mux_clk_setup()
282 mux->flags |= CLK_MUX_INDEX_ONE; of_ti_composite_mux_clk_setup()
291 mux->mask = num_parents - 1; of_ti_composite_mux_clk_setup()
292 mux->mask = (1 << fls(mux->mask)) - 1; of_ti_composite_mux_clk_setup()
294 if (!ti_clk_add_component(node, &mux->hw, CLK_COMPONENT_TYPE_MUX)) of_ti_composite_mux_clk_setup()
298 kfree(mux); of_ti_composite_mux_clk_setup()
300 CLK_OF_DECLARE(ti_composite_mux_clk_setup, "ti,composite-mux-clock",
H A DMakefile3 fixed-factor.o mux.o apll.o \
H A Dcomposite.c73 "gate", "divider", "mux"
126 struct clk_hw *mux; ti_clk_register_composite() local
136 mux = ti_clk_build_component_mux(comp->mux); ti_clk_register_composite()
144 if (mux) { ti_clk_register_composite()
145 num_parents = comp->mux->num_parents; ti_clk_register_composite()
146 parent_names = comp->mux->parents; ti_clk_register_composite()
150 parent_names, num_parents, mux, ti_clk_register_composite()
/linux-4.4.14/drivers/clk/
H A Dclk-mux.c33 struct clk_mux *mux = to_clk_mux(hw); clk_mux_get_parent() local
38 * FIXME need a mux-specific flag to determine if val is bitwise or numeric clk_mux_get_parent()
44 val = clk_readl(mux->reg) >> mux->shift; clk_mux_get_parent()
45 val &= mux->mask; clk_mux_get_parent()
47 if (mux->table) { clk_mux_get_parent()
51 if (mux->table[i] == val) clk_mux_get_parent()
56 if (val && (mux->flags & CLK_MUX_INDEX_BIT)) clk_mux_get_parent()
59 if (val && (mux->flags & CLK_MUX_INDEX_ONE)) clk_mux_get_parent()
70 struct clk_mux *mux = to_clk_mux(hw); clk_mux_set_parent() local
74 if (mux->table) clk_mux_set_parent()
75 index = mux->table[index]; clk_mux_set_parent()
78 if (mux->flags & CLK_MUX_INDEX_BIT) clk_mux_set_parent()
81 if (mux->flags & CLK_MUX_INDEX_ONE) clk_mux_set_parent()
85 if (mux->lock) clk_mux_set_parent()
86 spin_lock_irqsave(mux->lock, flags); clk_mux_set_parent()
88 __acquire(mux->lock); clk_mux_set_parent()
90 if (mux->flags & CLK_MUX_HIWORD_MASK) { clk_mux_set_parent()
91 val = mux->mask << (mux->shift + 16); clk_mux_set_parent()
93 val = clk_readl(mux->reg); clk_mux_set_parent()
94 val &= ~(mux->mask << mux->shift); clk_mux_set_parent()
96 val |= index << mux->shift; clk_mux_set_parent()
97 clk_writel(val, mux->reg); clk_mux_set_parent()
99 if (mux->lock) clk_mux_set_parent()
100 spin_unlock_irqrestore(mux->lock, flags); clk_mux_set_parent()
102 __release(mux->lock); clk_mux_set_parent()
125 struct clk_mux *mux; clk_register_mux_table() local
133 pr_err("mux value exceeds LOWORD field\n"); clk_register_mux_table()
138 /* allocate the mux */ clk_register_mux_table()
139 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); clk_register_mux_table()
140 if (!mux) { clk_register_mux_table()
141 pr_err("%s: could not allocate mux clk\n", __func__); clk_register_mux_table()
155 mux->reg = reg; clk_register_mux_table()
156 mux->shift = shift; clk_register_mux_table()
157 mux->mask = mask; clk_register_mux_table()
158 mux->flags = clk_mux_flags; clk_register_mux_table()
159 mux->lock = lock; clk_register_mux_table()
160 mux->table = table; clk_register_mux_table()
161 mux->hw.init = &init; clk_register_mux_table()
163 clk = clk_register(dev, &mux->hw); clk_register_mux_table()
166 kfree(mux); clk_register_mux_table()
188 struct clk_mux *mux; clk_unregister_mux() local
195 mux = to_clk_mux(hw); clk_unregister_mux()
198 kfree(mux); clk_unregister_mux()
H A Dclk-cdce706.c78 unsigned mux; member in struct:cdce706_hw_data
174 "%s, pll: %d, mux: %d, mul: %u, div: %u\n", cdce706_pll_recalc_rate()
175 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); cdce706_pll_recalc_rate()
177 if (!hwd->mux) { cdce706_pll_recalc_rate()
524 unsigned mux; cdce706_register_plls() local
526 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux); cdce706_register_plls()
545 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); cdce706_register_plls()
547 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i, cdce706_register_plls()
548 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux); cdce706_register_plls()
H A Dclk-axm5516.c5 * the Axxia device: PLL clock, a clock divider and a clock mux.
107 * struct axxia_clkmux - Axxia clock mux
127 struct axxia_clkmux *mux = to_axxia_clkmux(aclk); axxia_clkmux_get_parent() local
130 regmap_read(aclk->regmap, mux->reg, &ctrl); axxia_clkmux_get_parent()
131 parent = (ctrl >> mux->shift) & ((1 << mux->width) - 1); axxia_clkmux_get_parent()
H A Dclk-gpio.c181 * clk_register_gpio_mux - register a gpio clock mux with the clock framework
195 pr_err("mux-clock %s must have 2 parents\n", name); clk_register_gpio_mux()
325 CLK_OF_DECLARE(gpio_mux_clk, "gpio-mux-clock", of_gpio_mux_clk_setup);
/linux-4.4.14/drivers/clk/imx/
H A Dclk-fixup-mux.c22 * @mux: the parent class
30 struct clk_mux mux; member in struct:clk_fixup_mux
37 struct clk_mux *mux = to_clk_mux(hw); to_clk_fixup_mux() local
39 return container_of(mux, struct clk_fixup_mux, mux); to_clk_fixup_mux()
46 return fixup_mux->ops->get_parent(&fixup_mux->mux.hw); clk_fixup_mux_get_parent()
52 struct clk_mux *mux = to_clk_mux(hw); clk_fixup_mux_set_parent() local
56 spin_lock_irqsave(mux->lock, flags); clk_fixup_mux_set_parent()
58 val = readl(mux->reg); clk_fixup_mux_set_parent()
59 val &= ~(mux->mask << mux->shift); clk_fixup_mux_set_parent()
60 val |= index << mux->shift; clk_fixup_mux_set_parent()
62 writel(val, mux->reg); clk_fixup_mux_set_parent()
64 spin_unlock_irqrestore(mux->lock, flags); clk_fixup_mux_set_parent()
95 fixup_mux->mux.reg = reg; imx_clk_fixup_mux()
96 fixup_mux->mux.shift = shift; imx_clk_fixup_mux()
97 fixup_mux->mux.mask = BIT(width) - 1; imx_clk_fixup_mux()
98 fixup_mux->mux.lock = &imx_ccm_lock; imx_clk_fixup_mux()
99 fixup_mux->mux.hw.init = &init; imx_clk_fixup_mux()
103 clk = clk_register(NULL, &fixup_mux->mux.hw); imx_clk_fixup_mux()
H A Dclk-cpu.c20 struct clk *mux; member in struct:clk_cpu
53 ret = clk_set_parent(cpu->mux, cpu->step); clk_cpu_set_rate()
60 clk_set_parent(cpu->mux, cpu->pll); clk_cpu_set_rate()
64 clk_set_parent(cpu->mux, cpu->pll); clk_cpu_set_rate()
79 struct clk *div, struct clk *mux, struct clk *pll, imx_clk_cpu()
91 cpu->mux = mux; imx_clk_cpu()
78 imx_clk_cpu(const char *name, const char *parent_name, struct clk *div, struct clk *mux, struct clk *pll, struct clk *step) imx_clk_cpu() argument
H A Dclk-busy.c118 struct clk_mux mux; member in struct:clk_busy_mux
126 struct clk_mux *mux = container_of(hw, struct clk_mux, hw); to_clk_busy_mux() local
128 return container_of(mux, struct clk_busy_mux, mux); to_clk_busy_mux()
135 return busy->mux_ops->get_parent(&busy->mux.hw); clk_busy_mux_get_parent()
143 ret = busy->mux_ops->set_parent(&busy->mux.hw, index); clk_busy_mux_set_parent()
170 busy->mux.reg = reg; imx_clk_busy_mux()
171 busy->mux.shift = shift; imx_clk_busy_mux()
172 busy->mux.mask = BIT(width) - 1; imx_clk_busy_mux()
173 busy->mux.lock = &imx_ccm_lock; imx_clk_busy_mux()
182 busy->mux.hw.init = &init; imx_clk_busy_mux()
184 clk = clk_register(NULL, &busy->mux.hw); imx_clk_busy_mux()
/linux-4.4.14/drivers/clk/qcom/
H A Dclk-regmap-mux.c19 #include "clk-regmap-mux.h"
28 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); mux_get_parent() local
30 unsigned int mask = GENMASK(mux->width - 1, 0); mux_get_parent()
33 regmap_read(clkr->regmap, mux->reg, &val); mux_get_parent()
35 val >>= mux->shift; mux_get_parent()
43 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); mux_set_parent() local
45 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); mux_set_parent()
49 val <<= mux->shift; mux_set_parent()
51 return regmap_update_bits(clkr->regmap, mux->reg, mask, val); mux_set_parent()
H A Dclk-rcg.h117 * struct clk_dyn_rcg - root clock generator with glitch free mux
119 * @mux_sel_bit: bit to switch glitch free mux
122 * @bank_reg: register to XOR @mux_sel_bit into to switch glitch free mux
/linux-4.4.14/drivers/clk/tegra/
H A Dclk-super.c44 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); clk_super_get_parent() local
48 val = readl_relaxed(mux->reg); clk_super_get_parent()
55 super_state_to_src_shift(mux, SUPER_STATE_IDLE) : clk_super_get_parent()
56 super_state_to_src_shift(mux, SUPER_STATE_RUN); clk_super_get_parent()
58 source = (val >> shift) & super_state_to_src_mask(mux); clk_super_get_parent()
64 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && clk_super_get_parent()
65 (source == mux->pllx_index)) clk_super_get_parent()
66 source = mux->div2_index; clk_super_get_parent()
73 struct tegra_clk_super_mux *mux = to_clk_super_mux(hw); clk_super_set_parent() local
79 if (mux->lock) clk_super_set_parent()
80 spin_lock_irqsave(mux->lock, flags); clk_super_set_parent()
82 val = readl_relaxed(mux->reg); clk_super_set_parent()
87 super_state_to_src_shift(mux, SUPER_STATE_IDLE) : clk_super_set_parent()
88 super_state_to_src_shift(mux, SUPER_STATE_RUN); clk_super_set_parent()
95 if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) || clk_super_set_parent()
96 (index == mux->pllx_index))) { clk_super_set_parent()
98 if ((parent_index == mux->div2_index) || clk_super_set_parent()
99 (parent_index == mux->pllx_index)) { clk_super_set_parent()
105 writel_relaxed(val, mux->reg); clk_super_set_parent()
108 if (index == mux->div2_index) clk_super_set_parent()
109 index = mux->pllx_index; clk_super_set_parent()
111 val &= ~((super_state_to_src_mask(mux)) << shift); clk_super_set_parent()
112 val |= (index & (super_state_to_src_mask(mux))) << shift; clk_super_set_parent()
114 writel_relaxed(val, mux->reg); clk_super_set_parent()
118 if (mux->lock) clk_super_set_parent()
119 spin_unlock_irqrestore(mux->lock, flags); clk_super_set_parent()
H A Dclk-periph.c28 struct clk_hw *mux_hw = &periph->mux.hw; clk_periph_get_parent()
39 struct clk_hw *mux_hw = &periph->mux.hw; clk_periph_set_parent()
171 periph->mux.reg = clk_base + offset; _tegra_clk_register_periph()
181 periph->mux.hw.clk = clk; _tegra_clk_register_periph()
/linux-4.4.14/drivers/clk/sunxi/
H A Dclk-a10-mod1.c32 struct clk_mux *mux; sun4i_mod1_clk_setup() local
43 mux = kzalloc(sizeof(*mux), GFP_KERNEL); sun4i_mod1_clk_setup()
44 if (!mux) sun4i_mod1_clk_setup()
57 mux->reg = reg; sun4i_mod1_clk_setup()
58 mux->shift = SUN4I_MOD1_MUX; sun4i_mod1_clk_setup()
59 mux->mask = BIT(SUN4I_MOD1_MUX_WIDTH) - 1; sun4i_mod1_clk_setup()
60 mux->lock = &mod1_lock; sun4i_mod1_clk_setup()
63 &mux->hw, &clk_mux_ops, sun4i_mod1_clk_setup()
76 kfree(mux); sun4i_mod1_clk_setup()
H A Dclk-a20-gmac.c64 struct clk_mux *mux; sun7i_a20_gmac_clk_setup() local
73 /* allocate mux and gate clock structs */ sun7i_a20_gmac_clk_setup()
74 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); sun7i_a20_gmac_clk_setup()
75 if (!mux) sun7i_a20_gmac_clk_setup()
94 mux->reg = reg; sun7i_a20_gmac_clk_setup()
95 mux->mask = SUN7I_A20_GMAC_MASK; sun7i_a20_gmac_clk_setup()
96 mux->table = sun7i_a20_gmac_mux_table; sun7i_a20_gmac_clk_setup()
97 mux->lock = &gmac_lock; sun7i_a20_gmac_clk_setup()
101 &mux->hw, &clk_mux_ops, sun7i_a20_gmac_clk_setup()
119 kfree(mux); sun7i_a20_gmac_clk_setup()
H A Dclk-factors.c170 struct clk_mux *mux = NULL; sunxi_factors_register() local
177 /* if we have a mux, we will have >1 parents */ sunxi_factors_register()
214 /* Add a mux if this factor clock can be muxed */ sunxi_factors_register()
215 if (data->mux) { sunxi_factors_register()
216 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); sunxi_factors_register()
217 if (!mux) { sunxi_factors_register()
224 mux->reg = reg; sunxi_factors_register()
225 mux->shift = data->mux; sunxi_factors_register()
226 mux->mask = data->muxmask; sunxi_factors_register()
227 mux->lock = factors->lock; sunxi_factors_register()
228 mux_hw = &mux->hw; sunxi_factors_register()
H A Dclk-factors.h24 int mux; member in struct:factors_data
H A Dclk-sun8i-mbus.c62 .mux = 24,
H A Dclk-sun9i-core.c143 .mux = 24,
208 .mux = 24,
234 .mux = 24,
300 .mux = 24,
H A Dclk-sunxi.c196 struct clk_mux *mux; sun6i_ahb1_clk_setup() local
206 /* we have a mux, we will have >1 parents */ sun6i_ahb1_clk_setup()
214 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL); sun6i_ahb1_clk_setup()
215 if (!mux) { sun6i_ahb1_clk_setup()
221 mux->reg = reg; sun6i_ahb1_clk_setup()
222 mux->shift = SUN6I_AHB1_MUX_SHIFT; sun6i_ahb1_clk_setup()
223 mux->mask = SUN6I_AHB1_MUX_MASK; sun6i_ahb1_clk_setup()
224 mux->lock = &clk_lock; sun6i_ahb1_clk_setup()
228 &mux->hw, &clk_mux_ops, sun6i_ahb1_clk_setup()
725 .mux = 6,
732 .mux = 24,
740 .mux = 24,
1129 /* Matches for mux clocks */
1132 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
1164 /* Register mux clocks */ sunxi_init_clocks()
/linux-4.4.14/drivers/dma/
H A Dlpc18xx-dmamux.c24 /* CREG register offset and macros for mux manipulation */
47 struct lpc18xx_dmamux *mux = route_data; lpc18xx_dmamux_free() local
51 mux->busy = false; lpc18xx_dmamux_free()
61 unsigned mux; lpc18xx_dmamux_reserve() local
64 dev_err(&pdev->dev, "invalid number of dma mux args\n"); lpc18xx_dmamux_reserve()
68 mux = dma_spec->args[0]; lpc18xx_dmamux_reserve()
69 if (mux >= dmamux->dma_master_requests) { lpc18xx_dmamux_reserve()
70 dev_err(&pdev->dev, "invalid mux number: %d\n", lpc18xx_dmamux_reserve()
76 dev_err(&pdev->dev, "invalid dma mux value: %d\n", lpc18xx_dmamux_reserve()
89 if (dmamux->muxes[mux].busy) { lpc18xx_dmamux_reserve()
92 mux, mux, dmamux->muxes[mux].value); lpc18xx_dmamux_reserve()
97 dmamux->muxes[mux].busy = true; lpc18xx_dmamux_reserve()
98 dmamux->muxes[mux].value = dma_spec->args[1]; lpc18xx_dmamux_reserve()
101 LPC18XX_DMAMUX_MASK(mux), lpc18xx_dmamux_reserve()
102 LPC18XX_DMAMUX_VAL(dmamux->muxes[mux].value, mux)); lpc18xx_dmamux_reserve()
108 dev_dbg(&pdev->dev, "mapping dmamux %u.%u to dma request %u\n", mux, lpc18xx_dmamux_reserve()
109 dmamux->muxes[mux].value, mux); lpc18xx_dmamux_reserve()
111 return &dmamux->muxes[mux]; lpc18xx_dmamux_reserve()
/linux-4.4.14/arch/arm/mach-omap2/
H A Dmux.h14 /* 34xx mux mode options for each pin. See TRM for options */
24 /* 24xx/34xx mux bit defines */
29 /* omap3/4/5 specific mux bit defines */
106 * @gpio: gpio mux mode
125 * struct omap_mux - data for omap mux register offset and it's value
126 * @reg_offset: mux register offset from the mux base
144 * @reg_offset: mux register offset from the mux base
153 * struct omap_board_mux - data for initializing mux registers
154 * @reg_offset: mux register offset from the mux base
155 * @mux_value: desired mux value to set
174 * @partition: mux partition
175 * @mux: mux register
184 struct omap_mux *mux; member in struct:omap_device_pad
200 * @val: Options for the mux register value
207 * @val: Options for the mux register value
212 * omap_hwmod_mux_init - initialize hwmod specific mux data
264 * omap_mux_get_gpio() - get mux register value based on GPIO number
271 * omap_mux_set_gpio() - set mux register value based on GPIO number
272 * @val: New mux register value
279 * omap_mux_get() - get a mux partition by name
280 * @name: Name of the mux partition
286 * omap_mux_read() - read mux register
288 * @mux_offset: Offset of the mux register
294 * omap_mux_write() - write mux register
296 * @val: New mux register value
297 * @mux_offset: Offset of the mux register
304 * omap_mux_write_array() - write an array of mux registers
306 * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR
314 * omap2420_mux_init() - initialize mux system with board specific set
315 * @board_mux: Board specific mux table
321 * omap2430_mux_init() - initialize mux system with board specific set
322 * @board_mux: Board specific mux table
328 * omap3_mux_init() - initialize mux system with board specific set
329 * @board_mux: Board specific mux table
335 * omap4_mux_init() - initialize mux system with board specific set
336 * @board_subset: Board specific mux table
337 * @board_wkup_subset: Board specific mux table for wakeup instance
344 * omap_mux_init - private mux init function, do not call
H A Dmux.c2 * linux/arch/arm/mach-omap2/mux.c
43 #include "mux.h"
51 struct omap_mux mux; member in struct:omap_mux_entry
118 struct omap_mux *m = &e->mux; list_for_each_entry()
164 struct omap_mux *mux = NULL; _omap_mux_get_by_name() local
182 mux = &e->mux; list_for_each_entry()
183 m0_entry = mux->muxnames[0]; list_for_each_entry()
193 char *mode_cur = mux->muxnames[i]; list_for_each_entry()
199 *found_mux = mux; list_for_each_entry()
226 struct omap_mux *mux = NULL; omap_mux_get_by_name() local
227 int mux_mode = _omap_mux_get_by_name(partition, muxname, &mux); omap_mux_get_by_name()
232 *found_mux = mux; omap_mux_get_by_name()
245 struct omap_mux *mux = NULL; omap_mux_init_signal() local
249 mux_mode = omap_mux_get_by_name(muxname, &partition, &mux); omap_mux_init_signal()
250 if (mux_mode < 0 || !mux) omap_mux_init_signal()
253 old_mode = omap_mux_read(partition, mux->reg_offset); omap_mux_init_signal()
257 omap_mux_write(partition, mux_mode, mux->reg_offset); omap_mux_init_signal()
285 struct omap_mux *mux; omap_hwmod_mux_init() local
288 mux_mode = omap_mux_get_by_name(bpad->name, &partition, &mux); omap_hwmod_mux_init()
293 if (!pad->mux) omap_hwmod_mux_init()
294 pad->mux = mux; omap_hwmod_mux_init()
353 pr_err("%s: Could not allocate device mux entry\n", __func__); omap_hwmod_mux_init()
364 * array is defined for this mux, the parser will call the registered
367 * pending and non-served wakeup event for the mux, otherwise false.
383 val = omap_mux_read(pad->partition, pad->mux->reg_offset); omap_hwmod_mux_scan_wakeups()
411 if (!oh->mux || !oh->mux->enabled) _omap_hwmod_mux_handle_irq()
413 if (omap_hwmod_mux_scan_wakeups(oh->mux, oh->mpu_irqs)) _omap_hwmod_mux_handle_irq()
443 pad->mux->reg_offset); omap_hwmod_mux()
458 pad->mux->reg_offset); omap_hwmod_mux()
493 pad->mux->reg_offset); omap_hwmod_mux()
513 /* REVISIT: Add checking for non-optimal mux settings */ omap_mux_decode()
577 struct omap_mux *m = &e->mux; omap_mux_dbg_board_show()
623 static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux) omap_mux_get_partition() argument
632 struct omap_mux *m = &e->mux; list_for_each_entry()
634 if (m == mux) list_for_each_entry()
732 struct omap_mux *m = &e->mux; omap_mux_dbg_create_entry()
790 struct omap_mux *m = &e->mux; omap_mux_late_init()
817 pr_warn("mux: Failed to setup hwmod io irq %d\n", ret); omap_mux_late_init()
970 struct omap_mux *m = &e->mux; omap_mux_get_by_gpio()
1027 m = &entry->mux; omap_mux_list_add()
1028 entry->mux = *src; omap_mux_list_add()
1046 * the GPIO to mux offset mapping that is needed for dynamic muxing
1134 pr_err("%s: Could not ioremap mux partition at 0x%08x\n", omap_mux_init()
H A Dboard-rx51-video.c26 #include "mux.h"
H A Dboard-rx51.c33 #include "mux.h"
118 /* Ensure SDRC pins are mux'd for self-refresh */ rx51_init()
H A Dmsdi.c33 #include "mux.h"
H A Dusb-musb.c30 #include "mux.h"
H A Dserial.c42 #include "mux.h"
155 * Check if uart is used in default tx/rx mode i.e. in mux mode0 omap_serial_check_wakeup()
280 oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt); omap_serial_init_port()
/linux-4.4.14/drivers/net/phy/
H A Dmdio-mux-mmioreg.c19 #include <linux/mdio-mux.h>
30 * This function is called by the mdio-mux layer when it thinks the mdio bus
33 * 'current_child' is the current value of the mux register (masked via
41 * If current_child == desired_child, then the mux is already set to the
96 iprop = of_get_property(np, "mux-mask", &len); mdio_mux_mmioreg_probe()
98 dev_err(&pdev->dev, "missing or invalid mux-mask property\n"); mdio_mux_mmioreg_probe()
114 dev_err(&pdev->dev, "mdio-mux child node %s is " for_each_available_child_of_node()
120 dev_err(&pdev->dev, "mdio-mux child node %s has " for_each_available_child_of_node()
131 dev_err(&pdev->dev, "failed to register mdio-mux bus %s\n",
152 .compatible = "mdio-mux-mmioreg",
160 .name = "mdio-mux-mmioreg",
H A DMakefile37 obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
38 obj-$(CONFIG_MDIO_BUS_MUX_GPIO) += mdio-mux-gpio.o
39 obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
H A Dmdio-mux-gpio.c14 #include <linux/mdio-mux.h>
79 .compatible = "mdio-mux-gpio",
83 .compatible = "cavium,mdio-mux-sn74cbtlv3253",
91 .name = "mdio-mux-gpio",
/linux-4.4.14/drivers/clk/pistachio/
H A Dclk.c77 struct pistachio_mux *mux, pistachio_clk_register_mux()
84 clk = clk_register_mux(NULL, mux[i].name, mux[i].parents, pistachio_clk_register_mux()
85 mux[i].num_parents, pistachio_clk_register_mux()
87 p->base + mux[i].reg, mux[i].shift, pistachio_clk_register_mux()
88 get_count_order(mux[i].num_parents), pistachio_clk_register_mux()
90 p->clk_data.clks[mux[i].id] = clk; pistachio_clk_register_mux()
76 pistachio_clk_register_mux(struct pistachio_clk_provider *p, struct pistachio_mux *mux, unsigned int num) pistachio_clk_register_mux() argument
/linux-4.4.14/drivers/pinctrl/
H A Dpinctrl-adi2.h24 const unsigned short *mux; member in struct:adi_pin_group
32 .mux = m, \
36 * struct adi_pmx_func - describes function mux setting of pin groups
37 * @name: the name of this function mux setting
40 * @mux: the function mux setting array, end by zero
H A Dpinctrl-tz1090.c66 * struct tz1090_function - TZ1090 pinctrl mux function
78 * struct tz1090_muxdesc - TZ1090 individual mux description
79 * @funcs: Function for each mux value.
99 * @mux: Top level mux.
105 * @func_count: Number of pins using current mux function.
109 * configured. The most common is mux function selection.
115 struct tz1090_muxdesc mux; member in struct:tz1090_pingroup
543 /* individual pins not part of a pin mux group */
664 /* Mux functions that can be used by a mux */
669 /* magic per-non-muxing-GPIO-pin peripheral mode mux */
671 /* SDH/SDIO mux */
678 /* AFE mux */
681 /* EXT_DAC mux */
685 /* TFT mux */
693 #define FUNCTION(mux, fname, group) \
694 [(TZ1090_MUX_ ## mux)] = { \
700 #define NULL_FUNCTION(mux, fname) \
701 [(TZ1090_MUX_ ## mux)] = { \
729 * MUX() - Initialise a mux description.
736 * @mux_b: Bit number in register that the mux field begins
737 * @mux_w: Width of mux field in register
755 * @mux: Mux name (_submux is appended)
762 * @mux_b: Bit number in register that the mux field begins
763 * @mux_w: Width of mux field in register
765 * A sub mux is a nested mux that can be bound to a magic function number used
766 * by another mux description. For example value 4 of the top level mux might
768 * The outer mux can then take on any function in the top level mux or the
775 #define DEFINE_SUBMUX(mux, f0, f1, f2, f3, f4, mux_r, mux_b, mux_w) \
776 static struct tz1090_muxdesc mux ## _submux = \
791 * MUX_PG() - Initialise a pin group with mux control
799 * @mux_b: Bit number in register that the mux field begins
800 * @mux_w: Width of mux field in register
808 .mux = MUX(f0, f1, f2, f3, f4, \
848 /* name f0, f1, f2, f3, f4, mux r/b/w */
857 * These are the pin mux groups. Pin muxing can be enabled and disabled for each
858 * pin individually so these groups are internal. The mapping of pins to pin mux
863 /* pg_name, f0, f1, f2, f3, f4, mux r/b/w */
873 * This is the mapping from GPIO pins to pin mux groups in tz1090_mux_groups[].
886 * tz1090_init_mux_pins() - Initialise GPIO pin to mux group mapping.
889 * each pin mux group in tz1090_mux_groups[].
891 * It is assumed that no pin mux groups overlap (share pins).
912 * internal pin mux groups in tz1090_mux_groups[] are mirrored here with the
916 * mux group.
1065 (*map)[*num_maps].data.mux.group = group; add_map_mux()
1066 (*map)[*num_maps].data.mux.function = function; add_map_mux()
1216 * Pin mux operations
1353 * tz1090_pinctrl_enable_mux() - Switch a pin mux group to a function.
1358 * Enable a particular function on a pin mux group. Since pin mux descriptions
1367 int mux; tz1090_pinctrl_enable_mux() local
1371 /* find the mux value for this function, searching recursively */ tz1090_pinctrl_enable_mux()
1372 for (mux = 0, fit = desc->funcs; tz1090_pinctrl_enable_mux()
1373 mux < ARRAY_SIZE(desc->funcs); ++mux, ++fit) { tz1090_pinctrl_enable_mux()
1378 /* maybe it's a sub-mux */ tz1090_pinctrl_enable_mux()
1391 /* Set up the mux */ tz1090_pinctrl_enable_mux()
1397 reg |= (mux << desc->bit) & mask; tz1090_pinctrl_enable_mux()
1413 * and if it belongs to a pin mux group the mux will be switched if it isn't
1433 * All pins in the group must belong to the same mux group, tz1090_pinctrl_set_mux()
1434 * which allows us to just use the mux group of the first pin. tz1090_pinctrl_set_mux()
1445 /* no mux group, but can still be individually muxed to peripheral */ tz1090_pinctrl_set_mux()
1452 /* mux group already set to a different function? */ tz1090_pinctrl_set_mux()
1456 "%s: can't mux pin(s) to '%s', group already muxed to '%s'\n", tz1090_pinctrl_set_mux()
1465 /* if first pin in mux group to be enabled, enable the group mux */ tz1090_pinctrl_set_mux()
1468 ret = tz1090_pinctrl_enable_mux(pmx, &grp->mux, function); tz1090_pinctrl_set_mux()
1472 /* add pins to ref count and mux individually to peripheral */ tz1090_pinctrl_set_mux()
H A Dpinmux.c66 if (!map->data.mux.function) { pinmux_validate_map()
79 * name that controls its mux function, or the requested GPIO name
246 * @pin: the pin to mux in for GPIO
340 dev_err(pctldev->dev, "does not support mux function\n"); pinmux_map_to_setting()
344 ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function); pinmux_map_to_setting()
347 map->data.mux.function); pinmux_map_to_setting()
350 setting->data.mux.func = ret; pinmux_map_to_setting()
352 ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, pinmux_map_to_setting()
356 map->data.mux.function); pinmux_map_to_setting()
362 map->data.mux.function); pinmux_map_to_setting()
365 if (map->data.mux.group) { pinmux_map_to_setting()
367 group = map->data.mux.group; pinmux_map_to_setting()
377 group, map->data.mux.function); pinmux_map_to_setting()
387 map->data.mux.group); pinmux_map_to_setting()
390 setting->data.mux.group = ret; pinmux_map_to_setting()
412 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, pinmux_enable_setting()
420 setting->data.mux.group); pinmux_enable_setting()
437 setting->data.mux.group); pinmux_enable_setting()
447 /* Now that we have acquired the pins, encode the mux setting */ pinmux_enable_setting()
456 desc->mux_setting = &(setting->data.mux); pinmux_enable_setting()
459 ret = ops->set_mux(pctldev, setting->data.mux.func, pinmux_enable_setting()
460 setting->data.mux.group); pinmux_enable_setting()
492 ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, pinmux_disable_setting()
499 setting->data.mux.group); pinmux_disable_setting()
515 if (desc->mux_setting == &(setting->data.mux)) { pinmux_disable_setting()
523 setting->data.mux.group); pinmux_disable_setting()
640 /* If mux: print function+group claiming the pin */ pinmux_pins_show()
659 map->data.mux.group ? map->data.mux.group : "(default)", pinmux_show_map()
660 map->data.mux.function); pinmux_show_map()
671 pctlops->get_group_name(pctldev, setting->data.mux.group), pinmux_show_setting()
672 setting->data.mux.group, pinmux_show_setting()
673 pmxops->get_function_name(pctldev, setting->data.mux.func), pinmux_show_setting()
674 setting->data.mux.func); pinmux_show_setting()
H A Dpinctrl-lantiq.c99 (*map)->data.mux.group = group; ltq_pinctrl_dt_subnode_to_map()
100 (*map)->data.mux.function = function; ltq_pinctrl_dt_subnode_to_map()
214 static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux) match_mux() argument
218 if (mfp->func[i] == mux) match_mux()
240 unsigned mux) match_group_mux()
250 ret = match_mux(&info->mfp[pin], mux); match_group_mux()
252 dev_err(info->dev, "Can't find mux %d on pin%d\n", match_group_mux()
253 mux, pin); match_group_mux()
269 (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) { ltq_pmx_set()
281 pin_func = match_mux(&info->mfp[pin], pin_grp->mux); ltq_pmx_set()
285 "failed to apply mux %d for pin %d\n", ltq_pmx_set()
238 match_group_mux(const struct ltq_pin_group *grp, const struct ltq_pinmux_info *info, unsigned mux) match_group_mux() argument
H A Dpinctrl-tz1090-pdc.c68 * struct tz1090_pdc_function - TZ1090 PDC pinctrl mux function
84 * @func: Function enabled by the mux.
87 * @drv: Drive control supported, otherwise it's a mux.
92 * configured. The most common is mux function selection.
155 /* PDC_GPIO0 mux */
157 /* PDC_GPIO1 mux */
171 #define FUNCTION(mux, fname, group) \
172 [(TZ1090_PDC_MUX_ ## mux)] = { \
186 * MUX_PG() - Initialise a pin group with mux control
190 * @mux_b: Bit number in register of mux field
216 /* pg_name, f0, mux register, mux bit */
321 (*map)[*num_maps].data.mux.group = group; add_map_mux()
322 (*map)[*num_maps].data.mux.function = function; add_map_mux()
501 * Pin mux operations
527 * tz1090_pdc_pinctrl_mux() - update mux bit
529 * @grp: Pin mux group
538 /* select = mux && !gpio */ tz1090_pdc_pinctrl_mux()
541 /* set up the mux */ tz1090_pdc_pinctrl_mux()
562 /* is it even a mux? */ tz1090_pdc_pinctrl_set_mux()
570 /* record the pin being muxed and update mux bit */ tz1090_pdc_pinctrl_set_mux()
608 /* record the pin in GPIO use and update mux bit */ tz1090_pdc_pinctrl_gpio_request_enable()
626 /* record the pin not in GPIO use and update mux bit */ tz1090_pdc_pinctrl_gpio_disable_free()
H A Dpinctrl-at91.c101 * struct at91_pmx_pin - describes an At91 pin mux
104 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function.
110 enum at91_mux mux; member in struct:at91_pmx_pin
117 * @pins_conf: the mux mode for each pin in this group. The size of this
132 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
133 * on new IP with support for periph C and D the way to mux in
138 * @mux_A_periph: mux as periph A
139 * @mux_B_periph: mux as periph B
140 * @mux_C_periph: mux as periph C
141 * @mux_D_periph: mux as periph D
279 /* create mux map */ at91_dt_node_to_map()
286 new_map[0].data.mux.function = parent->name; at91_dt_node_to_map()
287 new_map[0].data.mux.group = np->name; at91_dt_node_to_map()
301 (*map)->data.mux.function, (*map)->data.mux.group, map_num); at91_dt_node_to_map()
644 if (pin->mux) { at91_pin_dbg()
646 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); at91_pin_dbg()
656 int mux; pin_check_config() local
677 if (!pin->mux) pin_check_config()
680 mux = pin->mux - 1; pin_check_config()
682 if (mux >= info->nmux) { pin_check_config()
684 name, index, mux, info->nmux); pin_check_config()
688 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { pin_check_config()
690 name, index, mux, pin->bank + 'A', pin->pin); pin_check_config()
741 switch (pin->mux) { at91_pmx_set()
762 if (pin->mux) at91_pmx_set()
1021 list = of_get_property(np, "atmel,mux-mask", &size); at91_pinctrl_mux_mask()
1023 dev_err(info->dev, "can not read the mux-mask of %d\n", size); at91_pinctrl_mux_mask()
1029 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); at91_pinctrl_mux_mask()
1040 ret = of_property_read_u32_array(np, "atmel,mux-mask", at91_pinctrl_mux_mask()
1043 dev_err(info->dev, "can not read the mux-mask of %d\n", size); at91_pinctrl_mux_mask()
1062 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, at91_pinctrl_parse_groups()
1085 pin->mux = be32_to_cpu(*list++); at91_pinctrl_parse_groups()
1169 dev_dbg(&pdev->dev, "mux-mask\n"); at91_pinctrl_probe_dt()
H A Dpinctrl-single.c59 * struct pcs_func_vals - mux function register offset and value pair
117 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
119 * @npins: number pins with the same mux value of gpio function
120 * @gpiofunc: mux value of gpio function
184 * @width: bits per mux register
187 * @foff: value to turn mux off
259 * generic. But at least on omaps, some mux registers are performance
858 * @np: device node of the mux entry
860 * @vals: array of mux register value pairs used by the function
861 * @nvals: number of mux register value pairs
914 * @np: device node of the mux entry
957 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", pcs_get_pin_by_offset()
1118 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
1120 * @np: device node of the mux entry
1143 const __be32 *mux; pcs_parse_one_pinctrl_entry() local
1147 mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); pcs_parse_one_pinctrl_entry()
1148 if ((!mux) || (size < sizeof(*mux) * 2)) { pcs_parse_one_pinctrl_entry()
1149 dev_err(pcs->dev, "bad data for mux %s\n", pcs_parse_one_pinctrl_entry()
1154 size /= sizeof(*mux); /* Number of elements in array */ pcs_parse_one_pinctrl_entry()
1169 offset = be32_to_cpup(mux + index++); pcs_parse_one_pinctrl_entry()
1170 val = be32_to_cpup(mux + index++); pcs_parse_one_pinctrl_entry()
1194 (*map)->data.mux.group = np->name; pcs_parse_one_pinctrl_entry()
1195 (*map)->data.mux.function = np->name; pcs_parse_one_pinctrl_entry()
1231 const __be32 *mux; pcs_parse_bits_in_pinctrl_entry() local
1236 mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); pcs_parse_bits_in_pinctrl_entry()
1238 if (!mux) { pcs_parse_bits_in_pinctrl_entry()
1243 if (size < (sizeof(*mux) * PARAMS_FOR_BITS_PER_MUX)) { pcs_parse_bits_in_pinctrl_entry()
1249 size /= sizeof(*mux); pcs_parse_bits_in_pinctrl_entry()
1270 offset = be32_to_cpup(mux + index++); pcs_parse_bits_in_pinctrl_entry()
1271 val = be32_to_cpup(mux + index++); pcs_parse_bits_in_pinctrl_entry()
1272 mask = be32_to_cpup(mux + index++); pcs_parse_bits_in_pinctrl_entry()
1323 (*map)->data.mux.group = np->name; pcs_parse_bits_in_pinctrl_entry()
1324 (*map)->data.mux.function = np->name; pcs_parse_bits_in_pinctrl_entry()
1631 * mux register. This interrupt is typically used for wake-up events.
1853 /* If mask property doesn't exist, function mux is invalid. */ pcs_probe()
1865 "pinctrl-single,bit-per-mux"); pcs_probe()
H A Dpinctrl-tegra.h68 * struct tegra_function - Tegra pinctrl mux function
84 * @funcs The mux functions which can be muxed onto this group.
86 * This register contains the mux, einput, odrain, lock,
124 * configured. The most common is mux function selection. Many others exist
172 * @functions: An array describing all mux functions the SoC supports.
H A Dpinctrl-lantiq.h54 const unsigned mux; member in struct:ltq_pin_group
105 int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
H A Dpinctrl-utils.c65 (*map)[*num_maps].data.mux.group = group; pinctrl_utils_add_map_mux()
66 (*map)[*num_maps].data.mux.function = function; pinctrl_utils_add_map_mux()
H A Dpinctrl-adi2.c82 * @mux: PORTx_MUX register
89 u32 mux; member in struct:gpio_port_saved
236 * the mux register. portmux_setup()
250 * the mux register. get_portmux()
489 port->saved_data.mux = readl(&port->regs->port_mux); adi_gpio_suspend()
505 writel(port->saved_data.mux, &port->regs->port_mux); adi_gpio_resume()
628 unsigned short *mux, pin; adi_pinmux_set() local
630 mux = (unsigned short *)pinctrl->soc->groups[group_id].mux; adi_pinmux_set()
632 while (*mux) { adi_pinmux_set()
633 pin = P_IDENT(*mux); adi_pinmux_set()
644 P_FUNCT2MUX(*mux)); adi_pinmux_set()
646 mux++; adi_pinmux_set()
H A Dcore.h112 * struct pinctrl_setting - an individual mux or config setting
126 struct pinctrl_setting_mux mux; member in union:pinctrl_setting::__anon8776
143 * @mux_setting: The most recent selected mux setting for this pin, if any.
H A Dpinctrl-rockchip.c183 * @func: the mux function number to be programmed when selected.
341 /* create mux map */ rockchip_dt_node_to_map()
348 new_map[0].data.mux.function = parent->name; rockchip_dt_node_to_map()
349 new_map[0].data.mux.group = np->name; rockchip_dt_node_to_map()
363 (*map)->data.mux.function, (*map)->data.mux.group, map_num); rockchip_dt_node_to_map()
408 /* get basic quadrupel of mux registers and the correct reg inside */ rockchip_get_mux()
427 * Set a new mux function for a pin.
437 * @mux: new mux function to set
439 static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) rockchip_set_mux() argument
458 if (mux != RK_FUNC_GPIO) { rockchip_set_mux()
460 "pin %d only supports a gpio mux\n", pin); rockchip_set_mux()
467 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", rockchip_set_mux()
468 bank->bank_num, pin, mux); rockchip_set_mux()
473 /* get basic quadrupel of mux registers and the correct reg inside */ rockchip_set_mux()
488 data |= (mux & mask) << bit; rockchip_set_mux()
1184 * the binding format is rockchip,pins = <bank pin mux CONFIG>, rockchip_pinctrl_parse_groups()
1416 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
1426 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
1949 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save rockchip_pinctrl_suspend()
/linux-4.4.14/drivers/clk/meson/
H A Dclkc.c54 struct clk_mux *mux = NULL; meson_clk_register_composite() local
63 mux = kzalloc(sizeof(*mux), GFP_KERNEL); meson_clk_register_composite()
64 if (!mux) meson_clk_register_composite()
67 mux->reg = clk_base + clk_conf->reg_off meson_clk_register_composite()
69 mux->shift = composite_conf->mux_parm.shift; meson_clk_register_composite()
70 mux->mask = BIT(composite_conf->mux_parm.width) - 1; meson_clk_register_composite()
71 mux->flags = composite_conf->mux_flags; meson_clk_register_composite()
72 mux->lock = &clk_lock; meson_clk_register_composite()
73 mux->table = composite_conf->mux_table; meson_clk_register_composite()
111 mux ? &mux->hw : NULL, mux_ops, meson_clk_register_composite()
123 kfree(mux); meson_clk_register_composite()
/linux-4.4.14/drivers/clk/mediatek/
H A Dclk-mtk.c142 struct clk_mux *mux = NULL; mtk_clk_register_composite() local
153 mux = kzalloc(sizeof(*mux), GFP_KERNEL); mtk_clk_register_composite()
154 if (!mux) mtk_clk_register_composite()
157 mux->reg = base + mc->mux_reg; mtk_clk_register_composite()
158 mux->mask = BIT(mc->mux_width) - 1; mtk_clk_register_composite()
159 mux->shift = mc->mux_shift; mtk_clk_register_composite()
160 mux->lock = lock; mtk_clk_register_composite()
162 mux_hw = &mux->hw; mtk_clk_register_composite()
213 kfree(mux); mtk_clk_register_composite()
218 kfree(mux); mtk_clk_register_composite()
/linux-4.4.14/drivers/i2c/
H A DMakefile9 obj-$(CONFIG_I2C_MUX) += i2c-mux.o
H A Di2c-mux.c10 * Supports multi-level mux'ing (mux behind a mux).
26 #include <linux/i2c-mux.h>
51 /* Switch to the right mux port and perform the transfer. */ i2c_mux_master_xfer()
71 /* Select the right mux port and perform the transfer. */ i2c_mux_smbus_xfer()
141 "i2c-%d-mux (chan_id %d)", i2c_adapter_id(parent), chan_id); i2c_add_mux_adapter()
153 "Segment %d behind mux can't share classes with ancestors\n", i2c_add_mux_adapter()
159 * Try to populate the mux adapter's of_node, expands to i2c_add_mux_adapter()
178 * Associate the mux channel with an ACPI node. i2c_add_mux_adapter()
192 "failed to add mux-adapter (error=%d)\n", i2c_add_mux_adapter()
199 "can't create symlink to mux device\n"); i2c_add_mux_adapter()
/linux-4.4.14/fs/ecryptfs/
H A Dkthread.c41 struct mutex mux; member in struct:ecryptfs_kthread_ctl
67 mutex_lock(&ecryptfs_kthread_ctl.mux); ecryptfs_threadfn()
69 mutex_unlock(&ecryptfs_kthread_ctl.mux); ecryptfs_threadfn()
81 mutex_unlock(&ecryptfs_kthread_ctl.mux); ecryptfs_threadfn()
91 mutex_init(&ecryptfs_kthread_ctl.mux); ecryptfs_init_kthread()
108 mutex_lock(&ecryptfs_kthread_ctl.mux); ecryptfs_destroy_kthread()
116 mutex_unlock(&ecryptfs_kthread_ctl.mux); ecryptfs_destroy_kthread()
156 mutex_lock(&ecryptfs_kthread_ctl.mux); ecryptfs_privileged_open()
159 mutex_unlock(&ecryptfs_kthread_ctl.mux); ecryptfs_privileged_open()
166 mutex_unlock(&ecryptfs_kthread_ctl.mux); ecryptfs_privileged_open()
H A Dmiscdev.c47 mutex_lock(&daemon->mux); ecryptfs_miscdev_poll()
58 mutex_unlock(&daemon->mux); ecryptfs_miscdev_poll()
60 mutex_lock(&daemon->mux); ecryptfs_miscdev_poll()
65 mutex_unlock(&daemon->mux); ecryptfs_miscdev_poll()
94 mutex_lock(&daemon->mux); ecryptfs_miscdev_open()
103 mutex_unlock(&daemon->mux); ecryptfs_miscdev_open()
125 mutex_lock(&daemon->mux); ecryptfs_miscdev_release()
129 mutex_unlock(&daemon->mux); ecryptfs_miscdev_release()
173 mutex_lock(&msg_ctx->mux); ecryptfs_send_miscdev()
181 mutex_unlock(&msg_ctx->mux); ecryptfs_send_miscdev()
183 mutex_lock(&daemon->mux); ecryptfs_send_miscdev()
186 mutex_unlock(&daemon->mux); ecryptfs_send_miscdev()
238 mutex_lock(&daemon->mux); ecryptfs_miscdev_read()
253 mutex_unlock(&daemon->mux); ecryptfs_miscdev_read()
256 mutex_lock(&daemon->mux); ecryptfs_miscdev_read()
275 mutex_lock(&msg_ctx->mux); ecryptfs_miscdev_read()
323 mutex_unlock(&msg_ctx->mux); ecryptfs_miscdev_read()
326 mutex_unlock(&daemon->mux); ecryptfs_miscdev_read()
H A Dmessaging.c67 if (mutex_trylock(&(*msg_ctx)->mux)) { ecryptfs_acquire_free_msg_ctx()
155 mutex_init(&(*daemon)->mux); ecryptfs_spawn_daemon()
169 * ecryptfs_daemon_hash_mux and the daemon's own mux.
176 mutex_lock(&daemon->mux); ecryptfs_exorcise_daemon()
180 mutex_unlock(&daemon->mux); ecryptfs_exorcise_daemon()
192 mutex_unlock(&daemon->mux); ecryptfs_exorcise_daemon()
236 mutex_lock(&msg_ctx->mux); ecryptfs_process_response()
261 mutex_unlock(&msg_ctx->mux); ecryptfs_process_response()
297 mutex_unlock(&(*msg_ctx)->mux); ecryptfs_send_message_locked()
350 mutex_lock(&msg_ctx->mux); ecryptfs_wait_for_response()
353 mutex_unlock(&msg_ctx->mux); ecryptfs_wait_for_response()
363 mutex_unlock(&msg_ctx->mux); ecryptfs_wait_for_response()
410 mutex_init(&ecryptfs_msg_ctx_arr[i].mux); ecryptfs_init_messaging()
411 mutex_lock(&ecryptfs_msg_ctx_arr[i].mux); ecryptfs_init_messaging()
419 mutex_unlock(&ecryptfs_msg_ctx_arr[i].mux); ecryptfs_init_messaging()
436 mutex_lock(&ecryptfs_msg_ctx_arr[i].mux); ecryptfs_release_messaging()
438 mutex_unlock(&ecryptfs_msg_ctx_arr[i].mux); ecryptfs_release_messaging()
/linux-4.4.14/drivers/clk/ingenic/
H A Djz4780-cgu.c286 .mux = { CGU_REG_CLOCKCONTROL, 30, 2 },
293 .mux = { CGU_REG_CLOCKCONTROL, 28, 2 },
312 .mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
320 .mux = { CGU_REG_CLOCKCONTROL, 24, 2 },
338 .mux = { CGU_REG_DDRCDR, 30, 2 },
346 .mux = { CGU_REG_VPUCDR, 30, 2 },
354 .mux = { CGU_REG_I2SCDR, 30, 1 },
361 .mux = { CGU_REG_I2SCDR, 31, 1 },
368 .mux = { CGU_REG_LP0CDR, 30, 2 },
376 .mux = { CGU_REG_LP1CDR, 30, 2 },
383 .mux = { CGU_REG_MSC0CDR, 30, 2 },
411 .mux = { CGU_REG_UHCCDR, 30, 2 },
419 .mux = { CGU_REG_SSICDR, 30, 1 },
426 .mux = { CGU_REG_SSICDR, 31, 1 },
432 .mux = { CGU_REG_CIMCDR, 31, 1 },
440 .mux = { CGU_REG_PCMCDR, 29, 2 },
447 .mux = { CGU_REG_PCMCDR, 31, 1 },
455 .mux = { CGU_REG_GPUCDR, 30, 2 },
464 .mux = { CGU_REG_HDMICDR, 30, 2 },
473 .mux = { CGU_REG_BCHCDR, 30, 2 },
H A Dcgu.h64 * struct ingenic_cgu_mux_info - information about a clock mux
65 * @reg: offset of the mux control register within the CGU
66 * @shift: number of bits to shift the mux value by (ie. the index of
67 * the lowest bit of the mux value within its control register)
68 * @bits: the size of the mux value in bits
131 * @mux: information valid if type includes CGU_CLK_MUX
158 struct ingenic_cgu_mux_info mux; member in struct:ingenic_cgu_clk_info::__anon3756::__anon3757
H A Djz4740-cgu.c136 .mux = { CGU_REG_CPCCR, 31, 1 },
144 .mux = { CGU_REG_SSICDR, 31, 1 },
166 .mux = { CGU_REG_CPCCR, 29, 1 },
H A Dcgu.c246 reg = readl(cgu->base + clk_info->mux.reg); ingenic_clk_get_parent()
247 hw_idx = (reg >> clk_info->mux.shift) & ingenic_clk_get_parent()
248 GENMASK(clk_info->mux.bits - 1, 0); ingenic_clk_get_parent()
282 num_poss = 1 << clk_info->mux.bits; ingenic_clk_set_parent()
294 mask = GENMASK(clk_info->mux.bits - 1, 0); ingenic_clk_set_parent()
295 mask <<= clk_info->mux.shift; ingenic_clk_set_parent()
300 reg = readl(cgu->base + clk_info->mux.reg); ingenic_clk_set_parent()
302 reg |= hw_idx << clk_info->mux.shift; ingenic_clk_set_parent()
303 writel(reg, cgu->base + clk_info->mux.reg); ingenic_clk_set_parent()
557 num_possible = 1 << clk_info->mux.bits; ingenic_register_clock()
/linux-4.4.14/arch/arm/mach-davinci/
H A Dmux.c2 * Utility to set the DAVINCI MUX register from a table in mux.h
6 * Based on linux/arch/arm/plat-omap/mux.c:
25 #include <mach/mux.h>
52 pr_err("Invalid pin mux index: %lu (%lu)\n", davinci_cfg_reg()
65 /* Update the mux register in question */ davinci_cfg_reg()
H A Dboard-dm365-evm.c35 #include <mach/mux.h>
631 u8 mux, resets; evm_init_cpld() local
657 mux = 0; evm_init_cpld()
663 /* external keypad mux */ evm_init_cpld()
664 mux |= BIT(7); evm_init_cpld()
675 /* Static video input config with SN74CBT16214 1-of-3 mux: evm_init_cpld()
676 * - port b1 == tvp7002 (mux lowbits == 1 or 6) evm_init_cpld()
677 * - port b2 == imager (mux lowbits == 2 or 7) evm_init_cpld()
678 * - port b3 == tvp5146 (mux lowbits == 5) evm_init_cpld()
684 mux |= 2; evm_init_cpld()
686 /* externally mux MMC1/ENET/AIC33 to imager */ evm_init_cpld()
687 mux |= BIT(6) | BIT(5) | BIT(3); evm_init_cpld()
704 mux |= 1; evm_init_cpld()
709 mux |= 5; evm_init_cpld()
714 __raw_writeb(mux, cpld + CPLD_MUX); evm_init_cpld()
H A DMakefile10 obj-$(CONFIG_DAVINCI_MUX) += mux.o
H A Dmux.h16 #include <mach/mux.h>
H A Dboard-da830-evm.c36 #include <mach/mux.h>
252 pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret); da830_evm_init_mmc()
409 pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret); da830_evm_init_nand()
431 pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret); da830_evm_init_lcdc()
456 /* Drive mux mode low to match the default without UI card */ da830_evm_ui_expander_setup()
601 pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret); da830_evm_init()
614 pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret); da830_evm_init()
631 pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret); da830_evm_init()
H A Dboard-sffsdr.c41 #include <mach/mux.h>
144 /* mux VLYNQ pins */ davinci_sffsdr_init()
H A Dserial.c72 * You have to mux them off in device drivers later on if not needed. davinci_serial_init()
H A Dboard-da850-evm.c45 #include <mach/mux.h>
346 pr_warn("%s: NAND mux setup failed: %d\n", da850_evm_setup_nor_nand()
351 pr_warn("%s: NOR mux setup failed: %d\n", da850_evm_setup_nor_nand()
1068 pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n", da850_evm_config_emac()
1076 pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__); da850_evm_config_emac()
1321 pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n", da850_vpif_init()
1330 pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n", da850_vpif_init()
1364 pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret); da850_evm_init()
1379 pr_warn("%s: MMCSD0 mux setup failed: %d\n", da850_evm_init()
1415 pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret); da850_evm_init()
1422 pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret); da850_evm_init()
1432 pr_warn("%s: EVM specific LCD mux setup failed: %d\n", da850_evm_init()
H A Dboard-omapl138-hawk.c24 #include <mach/mux.h>
53 pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret); omapl138_hawk_config_emac()
149 pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret); omapl138_hawk_mmc_init()
/linux-4.4.14/drivers/gpu/drm/imx/
H A Dimx-ldb.c149 static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, imx_ldb_set_clock() argument
169 /* set display clock mux to LDB input clock */ imx_ldb_set_clock()
170 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); imx_ldb_set_clock()
173 "unable to set di%d parent clock to ldb_di%d\n", mux, imx_ldb_set_clock()
218 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); imx_ldb_encoder_commit() local
229 if (mux == 0 || ldb->lvds_mux) imx_ldb_encoder_commit()
231 else if (mux == 1) imx_ldb_encoder_commit()
236 if (mux == 1 || ldb->lvds_mux) imx_ldb_encoder_commit()
238 else if (mux == 0) imx_ldb_encoder_commit()
251 mux << lvds_mux->shift); imx_ldb_encoder_commit()
268 int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder); imx_ldb_encoder_mode_set() local
281 imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); imx_ldb_encoder_mode_set()
282 imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); imx_ldb_encoder_mode_set()
285 imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, imx_ldb_encoder_mode_set()
308 int mux, ret; imx_ldb_encoder_disable() local
344 regmap_read(ldb->regmap, lvds_mux->reg, &mux); imx_ldb_encoder_disable()
345 mux &= lvds_mux->mask; imx_ldb_encoder_disable()
346 mux >>= lvds_mux->shift; imx_ldb_encoder_disable()
348 mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1; imx_ldb_encoder_disable()
351 /* set display clock mux back to original input clock */ imx_ldb_encoder_disable()
352 ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]); imx_ldb_encoder_disable()
356 mux); imx_ldb_encoder_disable()
539 * There are three different possible clock mux configurations: imx_ldb_bind()
583 * The output port is port@4 with an external 4-port mux or for_each_child_of_node()
584 * port@2 with the internal 2-port mux. for_each_child_of_node()
/linux-4.4.14/drivers/clk/st/
H A Dclkgen-mux.c2 * clkgen-mux.c: ST GEN-MUX Clock driver
44 * DOC: Clock mux with a programmable divider on each of its three inputs.
45 * The mux has an input setting which effectively gates its output.
58 /* Subclassed mux and divider structures */
59 struct clk_mux mux; member in struct:clkgena_divmux
82 static int clkgena_divmux_is_running(struct clkgena_divmux *mux) clkgena_divmux_is_running() argument
84 u32 regval = readl(mux->feedback_reg[mux->muxsel]); clkgena_divmux_is_running()
85 u32 running = regval & BIT(mux->feedback_bit_idx); clkgena_divmux_is_running()
92 struct clk_hw *mux_hw = &genamux->mux.hw; clkgena_divmux_enable()
116 struct clk_hw *mux_hw = &genamux->mux.hw; clkgena_divmux_disable()
126 struct clk_hw *mux_hw = &genamux->mux.hw; clkgena_divmux_is_enabled()
136 struct clk_hw *mux_hw = &genamux->mux.hw; clkgena_divmux_get_parent()
160 * If the mux is already enabled, call enable directly to set the clkgena_divmux_set_parent()
161 * new mux position and wait for it to start running again. Otherwise clkgena_divmux_set_parent()
243 genamux->mux.lock = &clkgena_divmux_lock; clk_register_genamux()
244 genamux->mux.mask = BIT(mux_width) - 1; clk_register_genamux()
245 genamux->mux.shift = muxdata->mux_start_bit + (idx * mux_width); clk_register_genamux()
246 if (genamux->mux.shift > 31) { clk_register_genamux()
248 * We have spilled into the second mux register so clk_register_genamux()
251 genamux->mux.reg = reg + muxdata->mux_offset2; clk_register_genamux()
252 genamux->mux.shift -= 32; clk_register_genamux()
254 genamux->mux.reg = reg + muxdata->mux_offset; clk_register_genamux()
616 .compatible = "st,stih415-clkgen-a9-mux",
620 .compatible = "st,stih416-clkgen-a9-mux",
624 .compatible = "st,stih407-clkgen-a9-mux",
682 CLK_OF_DECLARE(clkgen_mux, "st,clkgen-mux", st_of_clkgen_mux_setup);
747 struct clk_mux *mux; st_of_clkgen_vcc_setup() local
769 mux = kzalloc(sizeof(*mux), GFP_KERNEL); st_of_clkgen_vcc_setup()
770 if (!mux) { st_of_clkgen_vcc_setup()
787 mux->reg = reg + VCC_MUX_OFFSET; st_of_clkgen_vcc_setup()
788 mux->shift = 2 * i; st_of_clkgen_vcc_setup()
789 mux->mask = 0x3; st_of_clkgen_vcc_setup()
793 &mux->hw, &clk_mux_ops, st_of_clkgen_vcc_setup()
801 kfree(mux); st_of_clkgen_vcc_setup()
H A Dclk-flexgen.c22 struct clk_mux mux; member in struct:flexgen
81 struct clk_hw *mux_hw = &flexgen->mux.hw; flexgen_get_parent()
91 struct clk_hw *mux_hw = &flexgen->mux.hw; flexgen_set_parent()
203 fgxbar->mux.lock = lock; clk_register_flexgen()
204 fgxbar->mux.mask = BIT(6) - 1; clk_register_flexgen()
205 fgxbar->mux.reg = xbar_reg; clk_register_flexgen()
206 fgxbar->mux.shift = xbar_shift; clk_register_flexgen()
207 fgxbar->mux.table = NULL; clk_register_flexgen()
/linux-4.4.14/drivers/clk/samsung/
H A Dclk-exynos-clkout.c30 struct clk_mux mux; member in struct:exynos_clkout
98 clkout->mux.reg = clkout->reg + EXYNOS_PMU_DEBUG_REG; exynos_clkout_init()
99 clkout->mux.mask = mux_mask; exynos_clkout_init()
100 clkout->mux.shift = EXYNOS_CLKOUT_MUX_SHIFT; exynos_clkout_init()
101 clkout->mux.lock = &clkout->slock; exynos_clkout_init()
104 parent_names, parent_count, &clkout->mux.hw, exynos_clkout_init()
H A Dclk.h34 * struct samsung_clock_alias: information about mux clock
108 * struct samsung_mux_clock: information about mux clock
111 * @name: name of this mux clock.
115 * @offset: offset of the register for configuring the mux.
116 * @shift: starting bit location of the mux control bit-field in @reg.
117 * @width: width of the mux control bit-field in @reg.
118 * @mux_flags: flags for mux-type clock.
335 /* list of mux clocks and respective count */
H A Dclk-cpu.c15 * blocks which includes mux and divider blocks. There are a number of other
80 * Helper function to wait until mux has stabilized after the mux selection
96 pr_err("%s: re-parenting mux timed-out\n", __func__); wait_until_mux_stable()
/linux-4.4.14/drivers/tty/serial/
H A Ddz.c74 struct dz_mux *mux; member in struct:dz_port
181 static inline void dz_receive_chars(struct dz_mux *mux) dz_receive_chars() argument
184 struct dz_port *dport = &mux->dport[0]; dz_receive_chars()
192 dport = &mux->dport[LINE(status)]; dz_receive_chars()
245 tty_flip_buffer_push(&mux->dport[i].port.state->port); dz_receive_chars()
255 static inline void dz_transmit_chars(struct dz_mux *mux) dz_transmit_chars() argument
257 struct dz_port *dport = &mux->dport[0]; dz_transmit_chars()
263 dport = &mux->dport[LINE(status)]; dz_transmit_chars()
338 struct dz_mux *mux = dev_id; dz_interrupt() local
339 struct dz_port *dport = &mux->dport[0]; dz_interrupt()
346 dz_receive_chars(mux); dz_interrupt()
349 dz_transmit_chars(mux); dz_interrupt()
404 struct dz_mux *mux = dport->mux; dz_startup() local
410 irq_guard = atomic_add_return(1, &mux->irq_guard); dz_startup()
415 IRQF_SHARED, "dz", mux); dz_startup()
417 atomic_add(-1, &mux->irq_guard); dz_startup()
445 struct dz_mux *mux = dport->mux; dz_shutdown() local
454 irq_guard = atomic_add_return(-1, &mux->irq_guard); dz_shutdown()
461 free_irq(dport->port.irq, mux); dz_shutdown()
549 struct dz_mux *mux = dport->mux; dz_reset() local
551 if (mux->initialised) dz_reset()
561 mux->initialised = 1; dz_reset()
665 struct dz_mux *mux = to_dport(uport)->mux; dz_release_port() local
671 map_guard = atomic_add_return(-1, &mux->map_guard); dz_release_port()
690 struct dz_mux *mux = to_dport(uport)->mux; dz_request_port() local
694 map_guard = atomic_add_return(1, &mux->map_guard); dz_request_port()
698 atomic_add(-1, &mux->map_guard); dz_request_port()
706 map_guard = atomic_add_return(-1, &mux->map_guard); dz_request_port()
780 dport->mux = &dz_mux; dz_init_ports()
H A Dmux.c2 ** mux.c:
183 * mux_write - Write chars to the mux fifo.
187 * the mux fifo.
227 * mux_read - Read chars from the mux fifo.
230 * This reads all available data from the mux's fifo and pushes
271 * mux timer.
460 printk(KERN_INFO "Serial mux driver (%d ports) Revision: 0.6\n", port_count); mux_probe()
471 printk(KERN_ERR "Serial mux: Unable to register driver.\n"); mux_probe()
533 * want the builtin mux to be detected before addin mux cards, so we
534 * specifically probe for the builtin mux cards first.
536 * This table only contains the parisc_device_id of known builtin mux
537 * devices. All other mux cards will be detected by the generic mux_tbl.
/linux-4.4.14/drivers/gpio/
H A Dgpio-lp3943.c77 const struct lp3943_reg_cfg *mux = lp3943->mux_cfg; lp3943_gpio_set_mode() local
79 return lp3943_update_bits(lp3943, mux[offset].reg, mux[offset].mask, lp3943_gpio_set_mode()
80 val << mux[offset].shift); lp3943_gpio_set_mode()
121 const struct lp3943_reg_cfg *mux = lp3943->mux_cfg; lp3943_get_gpio_out_status() local
125 err = lp3943_read_byte(lp3943, mux[offset].reg, &read); lp3943_get_gpio_out_status()
129 read = (read & mux[offset].mask) >> mux[offset].shift; lp3943_get_gpio_out_status()
/linux-4.4.14/sound/soc/fsl/
H A Dimx-es8328.c88 ret = of_property_read_u32(np, "mux-int-port", &int_port); imx_es8328_probe()
90 dev_err(dev, "mux-int-port missing or invalid\n"); imx_es8328_probe()
94 dev_err(dev, "mux-int-port: hardware only has %d mux ports\n", imx_es8328_probe()
99 ret = of_property_read_u32(np, "mux-ext-port", &ext_port); imx_es8328_probe()
101 dev_err(dev, "mux-ext-port missing or invalid\n"); imx_es8328_probe()
105 dev_err(dev, "mux-ext-port: hardware only has %d mux ports\n", imx_es8328_probe()
H A Deukrea-tlv320.c118 ret = of_property_read_u32(np, "fsl,mux-int-port", &int_port); eukrea_tlv320_probe()
121 "fsl,mux-int-port node missing or invalid.\n"); eukrea_tlv320_probe()
124 ret = of_property_read_u32(np, "fsl,mux-ext-port", &ext_port); eukrea_tlv320_probe()
127 "fsl,mux-ext-port node missing or invalid.\n"); eukrea_tlv320_probe()
H A Dimx-sgtl5000.c68 ret = of_property_read_u32(np, "mux-int-port", &int_port); imx_sgtl5000_probe()
70 dev_err(&pdev->dev, "mux-int-port missing or invalid\n"); imx_sgtl5000_probe()
73 ret = of_property_read_u32(np, "mux-ext-port", &ext_port); imx_sgtl5000_probe()
75 dev_err(&pdev->dev, "mux-ext-port missing or invalid\n"); imx_sgtl5000_probe()
H A Dimx-wm8962.c165 ret = of_property_read_u32(np, "mux-int-port", &int_port); imx_wm8962_probe()
167 dev_err(&pdev->dev, "mux-int-port missing or invalid\n"); imx_wm8962_probe()
170 ret = of_property_read_u32(np, "mux-ext-port", &ext_port); imx_wm8962_probe()
172 dev_err(&pdev->dev, "mux-ext-port missing or invalid\n"); imx_wm8962_probe()
/linux-4.4.14/drivers/platform/x86/
H A Dmxm-wmi.c54 printk("calling mux switch %d\n", adapter); mxm_wmi_call_mxds()
62 printk("mux switched %d\n", status); mxm_wmi_call_mxds()
79 printk("calling mux switch %d\n", adapter); mxm_wmi_call_mxmx()
87 printk("mux mutex set switched %d\n", status); mxm_wmi_call_mxmx()
/linux-4.4.14/include/linux/
H A Di2c-mux.h3 * i2c-mux.h - functions for the i2c-bus mux support
34 * mux control.
H A Di2c-mux-gpio.h2 * i2c-mux-gpio interface to platform code
18 * struct i2c_mux_gpio_platform_data - Platform-dependent data for i2c-mux-gpio
H A Di2c-mux-pinctrl.h2 * i2c-mux-pinctrl platform data
23 * struct i2c_mux_pinctrl_platform_data - Platform data for i2c-mux-pinctrl
/linux-4.4.14/drivers/pinctrl/bcm/
H A Dpinctrl-cygnus-mux.c39 * @offset: register offset for mux configuration of a group
40 * @shift: bit shift for mux configuration of a group
53 * @is_configured: flag to indicate whether a mux setting has already been
57 struct cygnus_mux mux; member in struct:cygnus_mux_log
67 * @mux: Cygnus group based IOMUX configuration
73 struct cygnus_mux mux; member in struct:cygnus_pin_group
77 * Cygnus mux function and supported pin groups
100 * @mux_log: pointer to the array of mux logs
123 * @is_supported: flag to indicate GPIO mux is supported for this pin
124 * @offset: register offset for GPIO mux override of a pin
125 * @shift: bit shift for GPIO mux override of a pin
485 .mux = { \
776 const struct cygnus_mux *mux = &grp->mux; cygnus_pinmux_set() local
782 if (mux->offset != mux_log[i].mux.offset || cygnus_pinmux_set()
783 mux->shift != mux_log[i].mux.shift) cygnus_pinmux_set()
796 if (mux_log[i].mux.alt != mux->alt) { cygnus_pinmux_set()
811 mux_log[i].mux.alt = mux->alt; cygnus_pinmux_set()
816 val = readl(pinctrl->base0 + grp->mux.offset); cygnus_pinmux_set()
817 val &= ~(mask << grp->mux.shift); cygnus_pinmux_set()
818 val |= grp->mux.alt << grp->mux.shift; cygnus_pinmux_set()
819 writel(val, pinctrl->base0 + grp->mux.offset); cygnus_pinmux_set()
838 grp->mux.offset, grp->mux.shift, grp->mux.alt); cygnus_pinmux_set_mux()
848 const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data; cygnus_gpio_request_enable() local
853 if (!mux->is_supported) cygnus_gpio_request_enable()
858 val = readl(pinctrl->base1 + mux->offset); cygnus_gpio_request_enable()
859 val |= 0x3 << mux->shift; cygnus_gpio_request_enable()
860 writel(val, pinctrl->base1 + mux->offset); cygnus_gpio_request_enable()
866 pin, mux->offset, mux->shift); cygnus_gpio_request_enable()
876 struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data; cygnus_gpio_disable_free() local
880 if (!mux->is_supported) cygnus_gpio_disable_free()
885 val = readl(pinctrl->base1 + mux->offset); cygnus_gpio_disable_free()
886 val &= ~(0x3 << mux->shift); cygnus_gpio_disable_free()
887 writel(val, pinctrl->base1 + mux->offset); cygnus_gpio_disable_free()
893 pin, mux->offset, mux->shift); cygnus_gpio_disable_free()
927 log->mux.offset = i * 4; cygnus_mux_log_init()
928 log->mux.shift = j * 4; cygnus_mux_log_init()
929 log->mux.alt = 0; cygnus_mux_log_init()
/linux-4.4.14/drivers/gpu/drm/sti/
H A Dsti_awg_utils.c30 u32 mux = (mux_sel << 8) & 0x1ff; awg_generate_instr() local
66 mux = 0; awg_generate_instr()
77 mux = 0; awg_generate_instr()
82 mux = 0; awg_generate_instr()
103 arg = ((arg + mux) + data_enable); awg_generate_instr()
/linux-4.4.14/drivers/mfd/
H A Dpcf50633-adc.c30 int mux; member in struct:pcf50633_adc_request
81 adc_setup(pcf, adc->queue[head]->mux, adc->queue[head]->avg); trigger_next_adc_job_if_any()
120 int pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg) pcf50633_adc_sync_read() argument
127 ret = pcf50633_adc_async_read(pcf, mux, avg, pcf50633_adc_sync_read()
138 int pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg, pcf50633_adc_async_read() argument
149 req->mux = mux; pcf50633_adc_async_read()
/linux-4.4.14/drivers/clk/rockchip/
H A Dclk.c50 struct clk_mux *mux = NULL; rockchip_clk_register_branch() local
57 mux = kzalloc(sizeof(*mux), GFP_KERNEL); rockchip_clk_register_branch()
58 if (!mux) rockchip_clk_register_branch()
61 mux->reg = base + muxdiv_offset; rockchip_clk_register_branch()
62 mux->shift = mux_shift; rockchip_clk_register_branch()
63 mux->mask = BIT(mux_width) - 1; rockchip_clk_register_branch()
64 mux->flags = mux_flags; rockchip_clk_register_branch()
65 mux->lock = lock; rockchip_clk_register_branch()
99 mux ? &mux->hw : NULL, mux_ops, rockchip_clk_register_branch()
108 kfree(mux); rockchip_clk_register_branch()
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/pinctrl/
H A Domap.h11 /* 34xx mux mode options for each pin. See TRM for options */
21 /* 24xx/34xx mux bit defines */
26 /* omap3/4/5 specific mux bit defines */
H A Dam33xx.h10 /* am33xx specific mux bit defines */
H A Ddra.h15 /* DRA7 mux mode options for each pin. See TRM for options */
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_atpx_handler.c58 u16 mux; member in struct:atpx_mux
171 /* if separate mux flag is set, mux controls are required */ radeon_atpx_validate()
176 /* if any outputs are muxed, mux controls are required */ radeon_atpx_validate()
263 * radeon_atpx_switch_disp_mux - switch display mux
266 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
269 * switch the display mux between the discrete GPU and integrated GPU
281 input.mux = mux_id; radeon_atpx_switch_disp_mux()
295 * radeon_atpx_switch_i2c_mux - switch i2c/hpd mux
298 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
301 * switch the i2c/hpd mux between the discrete GPU and integrated GPU
313 input.mux = mux_id; radeon_atpx_switch_i2c_mux()
330 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
345 input.mux = mux_id; radeon_atpx_switch_start()
362 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
377 input.mux = mux_id; radeon_atpx_switch_end()
/linux-4.4.14/drivers/clk/nxp/
H A Dclk-lpc18xx-cgu.c167 struct clk_mux mux; member in struct:lpc18xx_cgu_src_clk_div
179 .mux = { \
201 struct clk_mux mux; member in struct:lpc18xx_cgu_base_clk
209 .mux = { \
265 struct clk_mux mux; member in struct:lpc18xx_cgu_pll_clk
276 .mux = { \
541 clk->mux.reg = reg; lpc18xx_cgu_register_div()
544 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); lpc18xx_cgu_register_div()
547 &clk->mux.hw, &clk_mux_ops, lpc18xx_cgu_register_div()
563 clk->mux.reg = reg; lpc18xx_register_base_clk()
566 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); lpc18xx_register_base_clk()
571 &clk->mux.hw, &clk_mux_ops, lpc18xx_register_base_clk()
575 &clk->mux.hw, &clk_mux_ops, lpc18xx_register_base_clk()
588 clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET; lpc18xx_cgu_register_pll()
591 lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents); lpc18xx_cgu_register_pll()
594 &clk->mux.hw, &clk_mux_ops, lpc18xx_cgu_register_pll()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_atpx_handler.c59 u16 mux; member in struct:atpx_mux
172 /* if separate mux flag is set, mux controls are required */ amdgpu_atpx_validate()
177 /* if any outputs are muxed, mux controls are required */ amdgpu_atpx_validate()
264 * amdgpu_atpx_switch_disp_mux - switch display mux
267 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
270 * switch the display mux between the discrete GPU and integrated GPU
282 input.mux = mux_id; amdgpu_atpx_switch_disp_mux()
296 * amdgpu_atpx_switch_i2c_mux - switch i2c/hpd mux
299 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
302 * switch the i2c/hpd mux between the discrete GPU and integrated GPU
314 input.mux = mux_id; amdgpu_atpx_switch_i2c_mux()
331 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
346 input.mux = mux_id; amdgpu_atpx_switch_start()
363 * @mux_id: mux state (0 = integrated GPU, 1 = discrete GPU)
378 input.mux = mux_id; amdgpu_atpx_switch_end()
/linux-4.4.14/include/linux/platform_data/
H A Di2c-mux-reg.h17 * struct i2c_mux_reg_platform_data - Platform-dependent data for i2c-mux-reg
25 * @idle: Value to write to mux when idle
H A Dasoc-s3c.h38 * @cfg_gpio: Callback function to setup mux'ed pins in I2S/PCM/AC97 mode
/linux-4.4.14/arch/powerpc/sysdev/qe_lib/
H A Dusb.c25 struct qe_mux __iomem *mux = &qe_immr->qmx; qe_usb_clock_set() local
50 clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val); qe_usb_clock_set()
/linux-4.4.14/arch/arm/mach-omap1/
H A Dboard-generic.c25 #include <mach/mux.h>
58 /* mux pins for uarts */ omap_generic_init()
H A Dmux.c2 * linux/arch/arm/mach-omap1/mux.c
32 #include <mach/mux.h>
87 * description mux mode mux pull pull pull pu_pd pu dbg
354 /* Check the mux register in question */ omap1_cfg_reg()
361 /* The mux registers always seem to be 3 bits long */ omap1_cfg_reg()
477 printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n", omap_cfg_reg()
484 printk(KERN_ERR "Pin mux table not initialized\n"); omap_cfg_reg()
489 printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n", omap_cfg_reg()
H A DMakefile6 obj-y := io.o id.o sram-init.o sram.o time.o irq.o mux.o flash.o \
H A Dboard-palmte.c38 #include <mach/mux.h>
213 /* mux pins for uarts */ omap_palmte_init()
H A Dboard-palmtt.c38 #include <mach/mux.h>
259 /* mux pins for uarts */ omap_palmtt_init()
H A Dboard-palmz71.c40 #include <mach/mux.h>
271 /* mux pins for uarts */ omap_palmz71_init()
H A Di2c.c23 #include <mach/mux.h>
/linux-4.4.14/include/linux/mfd/pcf50633/
H A Dadc.h67 pcf50633_adc_async_read(struct pcf50633 *pcf, int mux, int avg,
71 pcf50633_adc_sync_read(struct pcf50633 *pcf, int mux, int avg);
/linux-4.4.14/net/caif/
H A Dcfcnfg.c58 struct cflayer *mux; member in struct:cfcnfg
83 this->mux = cfmuxl_create(); cfcnfg_create()
84 if (!this->mux) cfcnfg_create()
102 cfmuxl_set_uplayer(this->mux, this->ctrl, 0); cfcnfg_create()
103 layer_set_dn(this->ctrl, this->mux); cfcnfg_create()
111 kfree(this->mux); cfcnfg_create()
123 kfree(cfg->mux); cfcnfg_remove()
189 servl = cfmuxl_remove_uplayer(cfg->mux, channel_id); caif_disconnect_client()
445 layer_set_dn(servicel, cnfg->mux); cfcnfg_linkup_rsp()
446 cfmuxl_set_uplayer(cnfg->mux, servicel, channel_id); cfcnfg_linkup_rsp()
503 layer_set_up(frml, cnfg->mux); cfcnfg_add_phy_layer()
547 cfmuxl_set_dnlayer(cnfg->mux, phyinfo->frm_layer, cfcnfg_set_phy_state()
550 cfmuxl_remove_dnlayer(cnfg->mux, phy_layer->id); cfcnfg_set_phy_state()
/linux-4.4.14/include/net/
H A Dbond_3ad.h70 /* mux machine states(43.4.13 in the 802.3ad standard) */
73 AD_MUX_DETACHED, /* mux machine */
74 AD_MUX_WAITING, /* mux machine */
75 AD_MUX_ATTACHED, /* mux machine */
76 AD_MUX_COLLECTING_DISTRIBUTING /* mux machine */
235 mux_states_t sm_mux_state; /* state machine mux state */
236 u16 sm_mux_timer_counter; /* state machine mux timer counter */
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_acpi.c102 DRM_DEBUG_DRIVER(" display mux info: %s\n", intel_dsm_platform_mux_info()
104 DRM_DEBUG_DRIVER(" aux/dc mux info: %s\n", intel_dsm_platform_mux_info()
106 DRM_DEBUG_DRIVER(" hpd mux info: %s\n", intel_dsm_platform_mux_info()
/linux-4.4.14/drivers/tty/
H A Dn_gsm.c28 * Review the locking/move to refcounts more (mux now moved to an
33 * Do we need a 'which mux are you' ioctl to correlate mux and tty sets
122 * complexity right now these are only ever freed up when the mux is
125 * At the moment we don't free DLCI objects until the mux is torn down
185 * Each GSM mux we have is represented by this structure. If we are
188 * to the gsm mux array. For now we don't free DLCI objects that
189 * have been instantiated until the mux itself is terminated.
191 * To consider further: tty open versus mux shutdown.
234 int (*output)(struct gsm_mux *mux, u8 *data, int len);
240 int dead; /* Has the mux been shut down */
273 * relevant mux and DLCI.
560 * @gsm: our GSM mux
612 * @gsm: our GSM mux
626 * @gsm: our GSM mux
644 * @gsm: GSM mux
728 * out of the mux tty if not already doing so. The Caller must hold
779 * out of the mux tty if not already doing so. Take the
793 * @gsm: mux
797 * is data. Keep to the MRU of the mux. This path handles the usual tty
800 * Caller must hold the tx_lock of the mux.
846 * @gsm: mux
850 * is data. Keep to the MRU of the mux. This path handles framed data
853 * Caller must hold the tx_lock of the mux.
919 * @gsm: the GSM mux
921 * Sweep the GSM mux channels in priority order looking for ones with
1037 5.4.6.3.7 of the 27.010 mux spec. */ gsm_process_modem()
1084 * the GSM mux protocol to pass virtual modem line status and optionally
1194 * @gsm: our GSM mux
1265 * @gsm: our GSM mux
1302 * @gsm: gsm mux
1392 * @gsm: GSM mux
1631 * @gsm: GSM mux
1634 * Allocate and install a new DLCI object into the GSM mux.
1707 * mux is closed or tty is closed - whichever is last.
1734 * @gsm: pointer to our gsm mux
2024 * @gsm: our mux
2026 * Clean up the bits of the mux which are the same for all framing
2027 * protocols. Remove the mux from the mux table, stop all the timers
2081 * @gsm: our mux
2083 * Set up the bits of the mux which are the same for all framing
2084 * protocols. Add the mux to the mux table so it can be opened and
2124 * gsm_free_mux - free up a mux
2125 * @mux: mux to free
2127 * Dispose of allocated resources for a dead mux
2137 * gsm_free_muxr - free up a mux
2138 * @mux: mux to free
2140 * Dispose of allocated resources for a dead mux
2159 * gsm_alloc_mux - allocate a mux
2161 * Creates a new mux ready for activation.
2200 * @gsm: our mux
2204 * Write a block of data from the GSM mux to the data channel. This
2224 * @gsm: our mux
2252 * gsmld_detach_gsm - stop doing 0710 mux
2253 * @tty: tty attached to the mux
2254 * @gsm: mux
2569 and removing from the mux array */ gsmld_config()
2906 unsigned int mux = line >> 6; gsmtty_install() local
2912 if (mux >= MAX_MUX) gsmtty_install()
2915 if (gsm_mux[mux] == NULL) gsmtty_install()
2919 gsm = gsm_mux[mux]; gsmtty_install()
/linux-4.4.14/drivers/media/dvb-frontends/
H A Drtl2830_priv.h24 #include <linux/i2c-mux.h>
H A Dsi2168_priv.h23 #include <linux/i2c-mux.h>
H A Drtl2832.h26 #include <linux/i2c-mux.h>
/linux-4.4.14/include/linux/pinctrl/
H A Dmachine.h29 * @group: the name of the group whose mux function is to be configured. This
32 * @function: the mux function to select for the group
74 struct pinctrl_map_mux mux; member in union:pinctrl_map::__anon13086
94 .data.mux = { \
H A Dpinmux.h28 * before selecting any actual mux setting across a function. The driver
35 * called by the core to figure out which mux setting it shall map a
49 * Implement this only if you can mux every pin individually as GPIO. The
/linux-4.4.14/arch/mips/include/asm/mach-loongson32/
H A Dloongson1.h46 #include <regs-mux.h>
/linux-4.4.14/sound/soc/codecs/
H A Dwm9713.c98 SOC_ENUM_SINGLE(AC97_VIDEO, 14, 4, wm9713_rec_mux), /* record mux hp 1 */
99 SOC_ENUM_SINGLE(AC97_VIDEO, 9, 4, wm9713_rec_mux), /* record mux mono 2 */
100 SOC_ENUM_SINGLE(AC97_VIDEO, 3, 8, wm9713_rec_src), /* record mux left 3 */
101 SOC_ENUM_SINGLE(AC97_VIDEO, 0, 8, wm9713_rec_src), /* record mux right 4*/
345 /* headphone capture mux */
349 /* headphone mic mux */
375 /* mono mic mux */
379 /* mono output mux */
383 /* speaker left output mux */
387 /* speaker right output mux */
391 /* headphone left output mux */
395 /* headphone right output mux */
399 /* Out3 mux */
403 /* Out4 mux */
407 /* DAC inv mux 1 */
411 /* DAC inv mux 2 */
567 /* DAC inv mux 1 */
574 /* DAC inv mux 2 */
581 /* headphone left mux */
584 /* headphone right mux */
587 /* speaker left mux */
592 /* speaker right mux */
597 /* mono mux */
601 /* out 3 mux */
604 /* out 4 mux */
/linux-4.4.14/drivers/pinctrl/freescale/
H A Dpinctrl-imx.h23 * @mux_mode: the mux mode for this pin.
66 * @mux_reg: mux register offset
H A Dpinctrl-imx1-core.c257 /* create mux map */ imx1_dt_node_to_map()
264 new_map[0].data.mux.function = parent->name; imx1_dt_node_to_map()
265 new_map[0].data.mux.group = np->name; imx1_dt_node_to_map()
280 (*map)->data.mux.function, (*map)->data.mux.group, map_num); imx1_dt_node_to_map()
311 * Configure the mux mode for each pin in the group for a specific imx1_pmx_set()
323 unsigned int mux = pins[i].mux_id; imx1_pmx_set() local
325 unsigned int afunction = MX1_MUX_FUNCTION(mux); imx1_pmx_set()
326 unsigned int gpio_in_use = MX1_MUX_GPIO(mux); imx1_pmx_set()
327 unsigned int direction = MX1_MUX_DIR(mux); imx1_pmx_set()
328 unsigned int gpio_oconf = MX1_MUX_OCONF(mux); imx1_pmx_set()
329 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux); imx1_pmx_set()
330 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux); imx1_pmx_set()
H A Dpinctrl-imx.c138 /* create mux map */ imx_dt_node_to_map()
145 new_map[0].data.mux.function = parent->name; imx_dt_node_to_map()
146 new_map[0].data.mux.group = np->name; imx_dt_node_to_map()
163 (*map)->data.mux.function, (*map)->data.mux.group, map_num); imx_dt_node_to_map()
195 * Configure the mux mode for each pin in the group for a specific imx_pmx_set()
210 dev_err(ipctl->dev, "Pin(%s) does not support mux function\n", imx_pmx_set()
315 /* Currently implementation only for shared mux/conf register */ imx_pmx_gpio_request_enable()
323 /* Find the pinctrl config with GPIO mux mode for the requested pin */ imx_pmx_gpio_request_enable()
354 * They are part of the shared mux/conf register. imx_pmx_gpio_set_direction()
573 /* SION bit is in mux register */ imx_pinctrl_parse_groups()
H A Dpinctrl-imx1.h23 * @mux_id: ID of the mux setup.
/linux-4.4.14/drivers/pinctrl/samsung/
H A Dpinctrl-exynos.h96 * @nr_banks: count of banks being part of the mux
97 * @banks: array of banks being part of the mux
/linux-4.4.14/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8505.c101 * mux in one group at a time by selecting the same altfunction for them
248 * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
250 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
252 * designers didn't apply the same logic on how to select mux in the
255 * As this pins supports at least ALT_B mux, default mux is
265 * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
266 * register is used to select the mux. As this pins doesn't support at
267 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
H A Dpinctrl-ab8500.c137 * mux in one group at a time by selecting the same altfunction for them
366 * means that pin AB8500_PIN_W17 (pin 13) supports 4 mux (default/ALT_A,
368 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
370 * designers didn't apply the same logic on how to select mux in the
373 * As this pins supports at least ALT_B mux, default mux is
383 * means that pin AB8500_PIN_W18 (pin 8) supports 2 mux, so only GPIOSEL
384 * register is used to select the mux. As this pins doesn't support at
385 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
H A Dpinctrl-ab9540.c132 * mux in one group at a time by selecting the same altfunction for them
356 * means that pin AB9540_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
358 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
360 * designers didn't apply the same logic on how to select mux in the
363 * As this pins supports at least ALT_B mux, default mux is
373 * means that pin AB9540_PIN_R4 (pin 1) supports 2 mux, so only GPIOSEL
374 * register is used to select the mux. As this pins doesn't support at
375 * least ALT_B mux, default mux is by writing 0 in GPIOSEL bit :
/linux-4.4.14/drivers/leds/
H A Dleds-lp5523.c117 #define LED_ACTIVE(mux, led) (!!(mux & (0x0001 << led)))
453 static int lp5523_mux_parse(const char *buf, u16 *mux, size_t len) lp5523_mux_parse() argument
474 *mux = tmp_mux; lp5523_mux_parse()
494 char mux[LP5523_MAX_LEDS + 1]; show_engine_leds() local
496 lp5523_mux_to_array(chip->engines[nr - 1].led_mux, mux); show_engine_leds()
498 return sprintf(buf, "%s\n", mux); show_engine_leds()
504 static int lp5523_load_mux(struct lp55xx_chip *chip, u16 mux, int nr) lp5523_load_mux() argument
520 ret = lp55xx_write(chip, LP5523_REG_PROG_MEM , (u8)(mux >> 8)); lp5523_load_mux()
524 ret = lp55xx_write(chip, LP5523_REG_PROG_MEM + 1, (u8)(mux)); lp5523_load_mux()
528 engine->led_mux = mux; lp5523_load_mux()
539 u16 mux = 0; store_engine_leds() local
542 if (lp5523_mux_parse(buf, &mux, len)) store_engine_leds()
553 if (lp5523_load_mux(chip, mux, nr)) store_engine_leds()
/linux-4.4.14/drivers/clk/mmp/
H A Dclk-mix.c2 * mmp mix(div and mux) clock operation source file
20 * The mix clock is a clock combined mux and div type clock.
21 * Because the div field and mux field need to be set at same
102 static unsigned int _get_mux_val(struct mmp_clk_mix *mix, unsigned int mux) _get_mux_val() argument
105 return mix->mux_table[mux]; _get_mux_val()
107 return mux; _get_mux_val()
484 pr_err("%s:%s: could not allocate mmp mix mux-table\n", mmp_clk_register_mix()
H A Dclk-of-pxa910.c150 /* The gate clocks has mux parent. */
161 /* The gate clocks has mux parent. */
211 /* The gate clocks has mux parent. */
/linux-4.4.14/net/9p/
H A Dtrans_fd.c103 * struct p9_conn - fd mux connection state information
104 * @mux_list: list link for mux to manage multiple connections (?)
192 * @m: mux data
203 p9_debug(P9_DEBUG_ERROR, "mux %p err %d\n", m, err); p9_conn_cancel()
308 p9_debug(P9_DEBUG_TRANS, "start mux %p pos %d\n", m, m->rpos); p9_read_work()
317 p9_debug(P9_DEBUG_TRANS, "read mux %p pos %d size: %d = %d\n", p9_read_work()
321 p9_debug(P9_DEBUG_TRANS, "mux %p got %d bytes\n", m, err); p9_read_work()
345 "mux %p pkt: size: %d bytes tag: %d\n", m, n, tag); p9_read_work()
478 p9_debug(P9_DEBUG_TRANS, "mux %p pos %d size %d\n", p9_write_work()
482 p9_debug(P9_DEBUG_TRANS, "mux %p sent %d bytes\n", m, err); p9_write_work()
572 * p9_conn_create - initialize the per-session mux data
598 p9_debug(P9_DEBUG_TRANS, "mux %p can read\n", m); p9_conn_create()
603 p9_debug(P9_DEBUG_TRANS, "mux %p can write\n", m); p9_conn_create()
609 * p9_poll_mux - polls a mux and schedules read or write works if necessary
623 p9_debug(P9_DEBUG_TRANS, "error mux %p err %d\n", m, n); p9_poll_mux()
631 p9_debug(P9_DEBUG_TRANS, "mux %p can read\n", m); p9_poll_mux()
640 p9_debug(P9_DEBUG_TRANS, "mux %p can write\n", m); p9_poll_mux()
666 p9_debug(P9_DEBUG_TRANS, "mux %p task %p tcall %p id %d\n", p9_fd_request()
841 * p9_mux_destroy - cancels all pending requests of mux
842 * @m: mux to destroy
848 p9_debug(P9_DEBUG_TRANS, "mux %p prev %p next %p\n", p9_conn_destroy()
/linux-4.4.14/arch/arm/mach-pxa/
H A Dmfp-pxa2xx.c4 * PXA2xx pin mux configuration support
47 unsigned int mux_mask; /* bit mask of muxed gpio bits, 0 if no mux */
294 #define INIT_GPIO_DESC_MUXED(mux, gpio) \
297 gpio_desc[(gpio)].mask = PWER_ ## mux ## _GPIO ##gpio; \
298 gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \
/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dhi6220-clock.h97 /* mux clocks */
144 /* mux clocks */
H A Dhix5hd2-clock.h45 /* mux clocks */
/linux-4.4.14/drivers/pwm/
H A Dpwm-lp3943.c141 const struct lp3943_reg_cfg *mux = lp3943->mux_cfg; lp3943_pwm_set_mode() local
146 err = lp3943_update_bits(lp3943, mux[index].reg, lp3943_pwm_set_mode()
147 mux[index].mask, lp3943_pwm_set_mode()
148 val << mux[index].shift); lp3943_pwm_set_mode()
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Ddas08.h48 /* bits for do/mux register on boards without separate do register */
H A Dpcl711.c225 unsigned int mux = 0; pcl711_set_changain() local
233 mux |= PCL711_MUX_DIFF; pcl711_set_changain()
236 mux |= PCL711_MUX_CS0; pcl711_set_changain()
238 mux |= PCL711_MUX_CS1; pcl711_set_changain()
241 outb(mux | PCL711_MUX_CHAN(chan), dev->iobase + PCL711_MUX_REG); pcl711_set_changain()
H A Ddas08.c60 #define DAS08_CONTROL_MUX(x) ((x) & DAS08_CONTROL_MUX_MASK) /* mux channel */
67 * + bits 3..0 (R/W) show/set the gain for the current AI mux channel
68 * + bits 6..4 (R) show the current AI mux channel
277 /* prevent race with setting of analog input mux */ das08_do_insn_bits()
/linux-4.4.14/drivers/gpu/drm/rockchip/
H A Ddw_hdmi-rockchip.c202 int mux; dw_hdmi_rockchip_encoder_commit() local
204 mux = rockchip_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder); dw_hdmi_rockchip_encoder_commit()
205 if (mux) dw_hdmi_rockchip_encoder_commit()
212 (mux) ? "LIT" : "BIG"); dw_hdmi_rockchip_encoder_commit()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/engine/pm/
H A Dpriv.h32 const struct nvkm_specmux *mux; member in struct:nvkm_specsrc
/linux-4.4.14/drivers/pinctrl/spear/
H A Dpinctrl-spear3xx.h17 /* pad mux declarations */
H A Dpinctrl-spear.h41 * struct spear_muxreg - SPEAr mux reg configuration
91 * struct spear_modemux - SPEAr mode mux configuration
122 * struct spear_function - SPEAr pinctrl mux function
140 * @functions: An array describing all mux functions the SoC supports.
171 * struct spear_pmx - SPEAr pinctrl mux
/linux-4.4.14/drivers/dma/sh/
H A Dshdma-of.c62 { .compatible = "renesas,shdma-mux", },
/linux-4.4.14/drivers/clk/berlin/
H A Dberlin2-div.c43 * (A) input pll clock mux controlled by <PllSelect[1:n]>
44 * (B) input pll bypass mux controlled by <PllSwitch>
48 * (F) constant div-by-3 clock mux controlled by <D3Switch>
56 * Also, clock gate and pll mux is not available on every div cell, so
/linux-4.4.14/arch/c6x/platforms/
H A Dmegamod-pic.c55 /* hw mux mapping */
155 /* four mappings per mux register */ set_megamod_mux()
186 map = of_get_property(np, "ti,c64x+megamod-pic-mux", &maplen); parse_priority_map()
293 pr_debug("%s: setting mux %d to priority %d\n", init_megamod_pic()
/linux-4.4.14/arch/cris/include/arch-v10/arch/
H A Dio_interface_mux.h1 /* IO interface mux allocator for ETRAX100LX.
/linux-4.4.14/arch/powerpc/platforms/52xx/
H A Dmpc52xx_common.c283 u32 mux; mpc5200_psc_ac97_gpio_reset() local
313 mux = in_be32(&simple_gpio->port_config); mpc5200_psc_ac97_gpio_reset()
314 out_be32(&simple_gpio->port_config, mux & (~gpio)); mpc5200_psc_ac97_gpio_reset()
338 out_be32(&simple_gpio->port_config, mux); mpc5200_psc_ac97_gpio_reset()
/linux-4.4.14/arch/powerpc/platforms/83xx/
H A Dmpc837x_rdb.c37 * so we can safely mux them away from the USB block. mpc837x_rdb_sd_cfg()
H A Dusb.c140 /* Configure pin mux for ULPI. There is no pin mux for UTMI */ mpc831x_usb_cfg()
245 /* Configure pin mux for ULPI/serial */ mpc837x_usb_cfg()
/linux-4.4.14/arch/sh/boards/mach-sdk7780/
H A Dsetup.c87 /* Setup pin mux'ing for PCIC */ sdk7780_setup()
/linux-4.4.14/arch/sh/drivers/pci/
H A Dfixups-sdk7786.c2 * SDK7786 FPGA PCIe mux handling
/linux-4.4.14/include/linux/i2c/
H A Dpca954x.h42 /* Per mux/switch data, used with i2c_register_board_info */
/linux-4.4.14/drivers/pinctrl/sirf/
H A Dpinctrl-sirf.c111 (*map)[index].data.mux.group = group; for_each_child_of_node()
112 (*map)[index].data.mux.function = function; for_each_child_of_node()
144 const struct sirfsoc_padmux *mux = sirfsoc_pinmux_endisable() local
146 const struct sirfsoc_muxmask *mask = mux->muxmask; sirfsoc_pinmux_endisable()
148 for (i = 0; i < mux->muxmask_counts; i++) { sirfsoc_pinmux_endisable()
160 if (mux->funcmask && enable) { sirfsoc_pinmux_endisable()
164 readl(spmx->rsc_virtbase + mux->ctrlreg); sirfsoc_pinmux_endisable()
166 (func_en_val & ~mux->funcmask) | (mux->funcval); sirfsoc_pinmux_endisable()
167 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg); sirfsoc_pinmux_endisable()
/linux-4.4.14/drivers/memory/
H A Domap-gpmc.c511 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data"); gpmc_cs_show_timings()
566 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns"); gpmc_cs_show_timings()
1262 bool mux) gpmc_calc_sync_read_timings()
1268 /* XXX: mux check required ? */ gpmc_calc_sync_read_timings()
1269 if (mux) { gpmc_calc_sync_read_timings()
1281 if (mux) { gpmc_calc_sync_read_timings()
1317 bool mux) gpmc_calc_sync_write_timings()
1323 if (mux) { gpmc_calc_sync_write_timings()
1333 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, gpmc_calc_sync_write_timings()
1336 if (mux) { gpmc_calc_sync_write_timings()
1379 bool mux) gpmc_calc_async_read_timings()
1385 if (mux) gpmc_calc_async_read_timings()
1391 if (mux) gpmc_calc_async_read_timings()
1419 bool mux) gpmc_calc_async_write_timings()
1425 if (mux) gpmc_calc_async_write_timings()
1431 if (mux) { gpmc_calc_async_write_timings()
1543 bool mux = false, sync = false; gpmc_calc_timings() local
1546 mux = gpmc_s->mux_add_data ? true : false; gpmc_calc_timings()
1555 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux); gpmc_calc_timings()
1557 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux); gpmc_calc_timings()
1560 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux); gpmc_calc_timings()
1562 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux); gpmc_calc_timings()
1681 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data); gpmc_read_settings_dt()
1751 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns", gpmc_read_timings_dt()
1260 gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, struct gpmc_device_timings *dev_t, bool mux) gpmc_calc_sync_read_timings() argument
1315 gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, struct gpmc_device_timings *dev_t, bool mux) gpmc_calc_sync_write_timings() argument
1377 gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, struct gpmc_device_timings *dev_t, bool mux) gpmc_calc_async_read_timings() argument
1417 gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, struct gpmc_device_timings *dev_t, bool mux) gpmc_calc_async_write_timings() argument
/linux-4.4.14/drivers/net/usb/
H A Dhso.c552 /* converts mux value to a port spec value */ hso_mux_to_port()
553 static u32 hso_mux_to_port(int mux) hso_mux_to_port() argument
557 switch (mux) { hso_mux_to_port()
579 /* converts port spec value to a mux value */ hso_port_to_mux()
608 int mux) get_serial_by_shared_int_and_type()
612 port = hso_mux_to_port(mux); get_serial_by_shared_int_and_type()
1847 "ERROR: mux'd reads with multiple buffers " hso_mux_serial_read()
2602 /* Frees an AT channel ( goes for both mux and non-mux ) */ hso_free_serial_device()
2711 struct hso_shared_int *mux) hso_create_mux_serial_device()
2742 serial->shared_int = mux; hso_create_mux_serial_device()
2766 static void hso_free_shared_int(struct hso_shared_int *mux) hso_free_shared_int() argument
2768 usb_free_urb(mux->shared_intr_urb); hso_free_shared_int()
2769 kfree(mux->shared_intr_buf); hso_free_shared_int()
2770 mutex_unlock(&mux->shared_int_lock); hso_free_shared_int()
2771 kfree(mux); hso_free_shared_int()
2777 struct hso_shared_int *mux = kzalloc(sizeof(*mux), GFP_KERNEL); hso_create_shared_int() local
2779 if (!mux) hso_create_shared_int()
2782 mux->intr_endp = hso_get_ep(interface, USB_ENDPOINT_XFER_INT, hso_create_shared_int()
2784 if (!mux->intr_endp) { hso_create_shared_int()
2789 mux->shared_intr_urb = usb_alloc_urb(0, GFP_KERNEL); hso_create_shared_int()
2790 if (!mux->shared_intr_urb) { hso_create_shared_int()
2794 mux->shared_intr_buf = hso_create_shared_int()
2795 kzalloc(le16_to_cpu(mux->intr_endp->wMaxPacketSize), hso_create_shared_int()
2797 if (!mux->shared_intr_buf) hso_create_shared_int()
2800 mutex_init(&mux->shared_int_lock); hso_create_shared_int()
2802 return mux; hso_create_shared_int()
2805 kfree(mux->shared_intr_buf); hso_create_shared_int()
2806 usb_free_urb(mux->shared_intr_urb); hso_create_shared_int()
2807 kfree(mux); hso_create_shared_int()
2883 int mux, i, if_num, port_spec; hso_probe() local
2931 for (i = 1, mux = 0; i < 0x100; i = i << 1, mux++) { hso_probe()
606 get_serial_by_shared_int_and_type( struct hso_shared_int *shared_int, int mux) get_serial_by_shared_int_and_type() argument
2709 hso_create_mux_serial_device(struct usb_interface *interface, int port, struct hso_shared_int *mux) hso_create_mux_serial_device() argument
/linux-4.4.14/drivers/media/pci/dt3155/
H A Ddt3155.h166 * @mux: mutex to protect the instance
186 struct mutex mux; member in struct:dt3155_priv
/linux-4.4.14/drivers/media/usb/tm6000/
H A Dtm6000-core.c751 enum tm6000_mux mux; tm6000_tvaudio_set_mute() local
754 mux = dev->rinput.amux; tm6000_tvaudio_set_mute()
756 mux = dev->vinput[dev->input].amux; tm6000_tvaudio_set_mute()
758 switch (mux) { tm6000_tvaudio_set_mute()
811 enum tm6000_mux mux; tm6000_set_volume() local
814 mux = dev->rinput.amux; tm6000_set_volume()
817 mux = dev->vinput[dev->input].amux; tm6000_set_volume()
819 switch (mux) { tm6000_set_volume()
/linux-4.4.14/drivers/pinctrl/meson/
H A Dpinctrl-meson.h26 * @reg: register offset for the group in the domain mux registers
117 * @reg_mux: registers for mux settings
/linux-4.4.14/include/linux/amba/
H A Dpl08x.h48 * @muxval: a number usually used to poke into some mux regiser to
49 * mux in the signal to this channel
/linux-4.4.14/arch/arm/mach-vt8500/
H A Dvt8500.c106 pr_err("%s: Could not remap GPIO mux\n", __func__); vt8500_init()
138 pr_err("%s: Could not remap GPIO mux\n", __func__); vt8500_init()
/linux-4.4.14/drivers/video/fbdev/omap/
H A Dlcd_osk.c29 #include <mach/mux.h>
/linux-4.4.14/drivers/media/pci/cx18/
H A Dcx18-audio.c58 /* FIXME - this internal mux should be abstracted to a subdev */ cx18_audio_set_io()
/linux-4.4.14/include/uapi/linux/
H A Datmbr2684.h38 #define BR2684_ENCAPS_VC (0) /* VC-mux */
/linux-4.4.14/arch/avr32/mach-at32ap/include/mach/
H A Dboard.h64 /* mask says which PWM channels to mux */
/linux-4.4.14/sound/oss/
H A Dwaveartist.h70 * Definitions for left/right recording input mux
/linux-4.4.14/drivers/input/touchscreen/
H A Dcolibri-vf50-ts.c96 * Let the platform mux to idle state in order to enable vf50_ts_enable_touch_detection()
118 /* Let the platform mux to default state in order to mux as ADC */ vf50_ts_irq_bh()
/linux-4.4.14/drivers/clk/keystone/
H A Dpll.c293 * of_pll_mux_clk_init - PLL mux setup function
333 pr_err("%s: error registering mux %s\n", __func__, clk_name); of_pll_mux_clk_init()
335 CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);
/linux-4.4.14/arch/hexagon/include/asm/
H A Dbitops.h55 " {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n" test_and_clear_bit()
79 " {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n" test_and_set_bit()
105 " {if !P1 jump 1b; %0 = mux(P0,#1,#0);}\n" test_and_change_bit()
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
H A Dmux.h2 * arch/arm/plat-omap/include/mach/mux.h
101 * OMAP730/850 has a slightly different config for the pin mux.
105 * as mux config
/linux-4.4.14/sound/soc/intel/atom/
H A Dsst-atom-controls.c167 unsigned int val, mux; sst_slot_get() local
173 for (mux = e->max; mux > 0; mux--) sst_slot_get()
174 if (map[mux - 1] & val) sst_slot_get()
177 ucontrol->value.enumerated.item[0] = mux; sst_slot_get()
182 e->texts[mux], mux ? map[mux - 1] : -1); sst_slot_get()
227 unsigned int val, mux; sst_slot_put() local
233 mux = ucontrol->value.enumerated.item[0]; sst_slot_put()
234 if (mux > e->max - 1) sst_slot_put()
242 if (mux == 0) { sst_slot_put()
251 slot_channel_no = mux - 1; sst_slot_put()
256 e->texts[mux], map[slot_channel_no]); sst_slot_put()

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